CN117295342A - Transistor and electronic device - Google Patents
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- CN117295342A CN117295342A CN202210686434.6A CN202210686434A CN117295342A CN 117295342 A CN117295342 A CN 117295342A CN 202210686434 A CN202210686434 A CN 202210686434A CN 117295342 A CN117295342 A CN 117295342A
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- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000002071 nanotube Substances 0.000 claims abstract description 36
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 30
- 239000002041 carbon nanotube Substances 0.000 claims description 29
- 229910021393 carbon nanotube Inorganic materials 0.000 claims description 29
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052710 silicon Inorganic materials 0.000 claims description 26
- 239000010703 silicon Substances 0.000 claims description 26
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 229910052763 palladium Inorganic materials 0.000 claims description 10
- 239000007769 metal material Substances 0.000 claims description 6
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052706 scandium Inorganic materials 0.000 claims description 4
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium atom Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 claims description 4
- 230000006866 deterioration Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 239000010408 film Substances 0.000 description 44
- 238000000034 method Methods 0.000 description 25
- 230000008569 process Effects 0.000 description 23
- 239000002135 nanosheet Substances 0.000 description 19
- 238000010586 diagram Methods 0.000 description 17
- 238000004519 manufacturing process Methods 0.000 description 13
- 239000000463 material Substances 0.000 description 10
- 230000005669 field effect Effects 0.000 description 9
- 235000012431 wafers Nutrition 0.000 description 8
- 239000012535 impurity Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 239000000969 carrier Substances 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000000313 electron-beam-induced deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000001994 activation Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000008186 active pharmaceutical agent Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000001963 growth medium Substances 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002609 medium Substances 0.000 description 1
- -1 palladium Metal Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Abstract
The embodiment of the application provides a transistor and electronic equipment, relates to the technical field of semiconductors, and can improve the problem of SS parameter deterioration of a nanotube transistor when the gate length is shortened to a certain size. The transistor includes: a substrate; source, drain and gate structures located on the surface of the substrate; the gate structure comprises a gate dielectric and a gate surrounding the gate dielectric; the channel is a disordered reticular film of the nano tube; two ends of the channel are respectively connected with the source electrode and the drain electrode; a gate dielectric surrounding the channel, the gate dielectric being located between the gate and the channel; the gate length of the transistor is less than or equal to 5nm, and the gate length is the channel length covered by the gate.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a transistor and an electronic device.
Background
As moore's law gradually goes to end, silicon-based transistors face problems of short channel effects, increased power consumption, etc., and it becomes increasingly difficult to continue to shrink device dimensions, so that for lower-made transistors, nanotube transistors with planar structures have emerged that use other nanotube materials, such as carbon nanotubes, as the transistor channel material. However, it was found from experimental results on planar-structured carbon nanotube transistors that sub-threshold swing (Subthreshold Swing, SS) parameter degradation occurs when the gate length of the carbon nanotube transistor is shortened to a certain size.
Disclosure of Invention
A transistor and an electronic device can improve the problem of SS parameter deterioration when the gate length of a nanotube transistor is shortened to a certain size.
In a first aspect, there is provided a transistor comprising: a substrate; source, drain and gate structures located on the surface of the substrate; the gate structure comprises a gate dielectric and a gate surrounding the gate dielectric; the channel is a disordered reticular film of the nano tube; two ends of the channel are respectively connected with the source electrode and the drain electrode; a gate dielectric surrounding the channel, the gate dielectric being located between the gate and the channel; the gate length of the transistor is less than or equal to 5nm, and the gate length is the channel length covered by the gate.
The grid surrounds the channel to form a ring grid structure, on one hand, the grid surrounding the channel can realize control of the channel on each side surface of the channel, namely, the grid control capability is improved, so that the short channel effect of the transistor below a 5nm process is improved, and the problem of deterioration of SS parameters is solved; on the other hand, the nanotubes in the disordered network film are arranged in a network, and can be directly placed by taking a source, drain and grid structure as support in the manufacturing process of the transistor, so that the preparation is simple; moreover, when the unordered reticular film of the nanotubes is matched with the ring grid structure, each nanotube has better grid control capability.
In one possible embodiment, the nanotube disordered mesh film is a carbon nanotube disordered mesh film. Complex and high-cost multilayer epitaxial growth and selective etching processes are not needed, and the process complexity and cost are reduced.
In one possible embodiment, the transistor includes a multilayer channel in a stacked arrangement; any two adjacent layers of channels are separated by a gate. By stacking multiple layers of channels in the vertical direction, the current density of the device is further increased, namely the on-state performance of the device is improved; meanwhile, each layer of channel forms a ring gate structure, so that the gate control capability of each layer of channel can be improved, and the off-state performance of the device can be improved.
In one possible implementation, the gate dielectric is a high-k dielectric. No additional grown buffer layer is required, so the structure and process are simpler.
In one possible embodiment, the source and drain electrodes are made of a metallic material. The energy band degeneracy is realized without source-drain impurity implantation, so that ion implantation and high-temperature impurity activation processes are not required, a lightly doped drain (Lightly Doped Drain, LDD) ion implantation process is not required, and additional processes are not required for manufacturing the side wall and the inner side wall.
In one possible embodiment, the source and drain electrodes are made of palladium metal or scandium metal.
In one possible embodiment, the transistor includes a multilayer channel in a stacked arrangement; any two adjacent layers of channels are separated by a grid electrode; the difference between the height of the end of the source electrode far away from the substrate and the height of the end of the multilayer channel far away from the substrate is less than or equal to 15nm; the difference between the height of the end of the drain electrode far away from the substrate and the height of the end of the multilayer channel far away from the substrate is less than or equal to 15nm; the height of the end of the source electrode far away from the substrate is the distance between the end of the source electrode far away from the substrate and the surface of the substrate in the direction perpendicular to the surface of the substrate; the height of the end of the multilayer channel away from the substrate is the distance between the end of the multilayer channel away from the substrate and the substrate surface in a direction perpendicular to the substrate surface. The source drain and the channel have good electrical contact to obtain larger current, the height of the source drain is not required to be increased, and the self-aligned silicide is not required, so that the source drain has lower resistance.
In one possible implementation, the gate electrode can be directly made of palladium metal material, and the manufacturing process is simpler.
In one possible implementation, the substrate comprises a silicon wafer and an insulating dielectric layer arranged on the surface of the silicon wafer, so that the process steps are reduced, and the probability of source-drain through leakage is reduced.
In one possible embodiment, the disordered network of nanotubes thin film is parallel to the substrate surface.
In one possible embodiment, the gate dielectric is hafnium oxide.
In a second aspect, an electronic device is provided, including the transistor described above.
Drawings
FIG. 1 is a graph showing the transfer characteristics of a planar structure carbon nanotube transistor according to the prior art;
fig. 2 is a schematic structural diagram of a transistor according to an embodiment of the present application;
FIG. 3 is a schematic cross-sectional view of FIG. 2;
FIG. 4 is a schematic diagram of a disordered network film of nanotubes according to an embodiment of the application;
FIG. 5 is a schematic diagram showing a carbon nanotube disordered mesh film before and after transfer in accordance with an embodiment of the present application;
FIG. 6 is a schematic diagram showing the mobility and saturation velocity of carriers in a disordered mesh film of carbon nanotubes after transfer according to an embodiment of the present application;
FIG. 7 is a schematic diagram showing a carbon nanotube disordered network film before and after dry etching;
fig. 8 is a schematic structural diagram of another transistor according to an embodiment of the present application;
FIG. 9 is a schematic cross-sectional view of the structure of FIG. 8;
FIG. 10 is a schematic diagram of a prior art transistor;
fig. 11 is a schematic diagram illustrating a process for manufacturing a transistor according to an embodiment of the present application;
FIG. 12 is a schematic diagram of a scanning electron microscope of a transistor according to an embodiment of the present application;
FIG. 13 is a schematic illustration of a disordered network film of nanotubes of FIG. 12;
FIG. 14 is a schematic diagram showing a transfer characteristic of a transistor actually fabricated according to an embodiment of the present application;
FIG. 15 is a schematic diagram showing a transfer characteristic of a transistor according to the prior art;
fig. 16 is a schematic diagram of SS parameters of a prior art fork-type sheet (fork-type) transistor and a silicon-based nano-sheet (Nanosheet) field effect transistor.
Detailed Description
The terminology used in the description section of the present application is for the purpose of describing particular embodiments of the present application only and is not intended to be limiting of the present application.
Before describing the embodiments of the present application, the technical context of the present application will be described first, and the selection of the silicon-based transistor is compared with the silicon-based transistorTransistors such as carbon nanotubes as channels have faster speeds, smaller power consumption-delay product, however, as shown in FIG. 1, where V gs Is the gate-source voltage, V t For threshold voltage, I ds Is channel current, L g As for the gate length, the experimental result of the carbon nanotube transistor of the planar structure shows that the device starts to generate a short channel effect when the gate length is reduced to 5nm, resulting in deterioration of SS parameters, which is because in the planar structure, the voltage applied to the gate can induce carriers in only one side surface of the channel, i.e., the gate can control the potential on only one side surface of the channel, i.e., the gate control capability is insufficient. In order to solve the above-described problems, the present application provides the following examples, which are described below.
As shown in fig. 2 and 3, an embodiment of the present application provides a transistor, including: a substrate 1; a source electrode 21, a drain electrode 22 and a gate structure 3 which are positioned on the surface of the substrate 1; the gate structure 3 includes a gate dielectric 31 and a gate 32 surrounding the gate dielectric 31; the channel 4 is a disordered reticular film of the nano tube; both ends of the channel 4 are respectively connected to a source electrode 21 and a drain electrode 22; gate dielectric 31 surrounds channel 4 and gate dielectric 31 is located between gate 32 and channel 4; gate length L of transistor g Less than or equal to 5nm, gate length L g The length of the channel 4 covered by the gate 32, i.e. the gate length L g The length of the channel 4 in its conduction path, which is covered by the gate 32.
Specifically, it should be noted that the channels 4 illustrated in fig. 2 and 3 are only for illustrating the relative positional relationship between the whole channel 4 and other structures, and are not for illustrating the specific structure of the disordered network film of nanotubes, and fig. 4 illustrates the specific structure of the disordered network film of nanotubes.
According to the transistor, the grid electrode surrounds the channel to form the gate-all-around structure, on one hand, the grid electrode surrounding the channel can control the channel on each side surface of the channel, namely, the gate control capability is improved, so that the short channel effect of the transistor below a 5nm process is improved, and the problem of deterioration of SS parameters is solved; on the other hand, the nanotubes in the disordered network film are arranged in a network, and can be directly placed by taking a source, drain and grid structure as support in the manufacturing process of the transistor, so that the preparation is simple; moreover, when the unordered reticular film of the nanotubes is matched with the ring grid structure, each nanotube has better grid control capability.
In one possible embodiment, the nanotube disordered mesh film is a carbon nanotube disordered mesh film.
Specifically, in the prior art, the channel of a silicon-based nano-sheet (Nanosheet) field effect transistor is formed by growing alternating layers of silicon germanium through a superlattice, then selectively etching by HCl to leave a silicon channel, the channel has a certain thickness of about 5nm, and the number of layers of the silicon-based nano-sheet has a certain limit and is about 4 layers due to the influence of an epitaxial process and the stability of a fin structure. In the embodiment of the application, the disordered network film of the carbon nano tube is used as a channel, the carbon nano tube is a typical nano tube, in the disordered network film of the carbon nano tube, the length of the carbon nano tube can be between 1.5 mu m and 3 mu m, the thickness of the disordered network film of the carbon nano tube can be about 1nm, the stacking layer number is not limited, and the substrate immunity of the carbon nano tube is added, so that the stacking of a plurality of layers of channels can be realized through the deposition or the transfer of the carbon nano tube, and the complex and high-cost multilayer epitaxial growth and selective etching process are not needed. The following examples are given by taking a carbon nanotube disordered network film as an example of a nanotube disordered network film.
In addition, in the prior art, a shallow trench isolation technology is adopted in a silicon-based nano-sheet (Nanosheet) field effect transistor, and the corresponding process is to perform high-density plasma chemical vapor deposition (High Density Plasma Chemical Vapor Deposition, HDP CVD) growth medium at a high temperature of 900 ℃, and then combine chemical mechanical polishing (Chemical Mechanical Polishing, CMP) planarization, so that the process is complex, and the situation that adjacent devices are electrically conducted and parasitic MOS still may exist under high voltage. As shown in fig. 7, the disordered carbon nanotube mesh film in the embodiment of the present application may directly remove the channel material at the irrelevant position by, for example, dry etching, so as to thoroughly block the current channel, improve the integration density of the device, and has a simple process, wherein the left side of the arrow in fig. 7 is the disordered carbon nanotube mesh film before dry etching, and the right side of the arrow is the disordered carbon nanotube mesh film after dry etching.
In addition, in the carbon nanotube disordered mesh film according to the embodiment of the present application, carbon nanotubes on various substrates can be obtained by transfer and deposition, as shown in fig. 8 and 9, fig. 8 is a schematic diagram showing a comparison of before and after transfer of the carbon nanotube disordered mesh film, an upper part is before transfer, a lower part is after transfer, and fig. 9 is a schematic diagram showing mobility and saturation velocity of carriers in the carbon nanotube disordered mesh film after transfer, the mobility of carriers in the carbon nanotube disordered mesh film after transfer is 1580cm 2 V -1 s -1 Saturated speed of 3.10 7 cm·s -1 Therefore, the embodiment of the application does not need to adopt complex film growth and selective etching processes, and can obtain a multilayer channel only through a simpler process of transfer or deposition.
In one possible embodiment, as shown in fig. 8 and 9, the transistor includes a multilayer channel 4 arranged in a stack; any two adjacent layers of channels 4 are separated by the grid electrode 32, namely, each layer of channels 4 is surrounded by the grid electrode medium 31 and the grid electrode 32, each layer of channels 4 forms a ring grid structure, and the current density of the device is further increased by stacking multiple layers of channels 4 in the vertical direction, namely, the on-state performance of the device is improved; meanwhile, as each layer of channel 4 forms a ring gate structure, the gate control capability of each layer of channel 4 can be improved, and the off-state performance of the device can be improved.
In one possible implementation, the gate dielectric 31 is a high-k dielectric.
Specifically, in the prior art, the gate dielectric material of the silicon-based nano-sheet (Nanosheet) field effect transistor is SiO N And HfO 2 SiO is required N To reduce HfO 2 And silicon, in the present example, it was found through experimental verification that the high-k material grown by low-temperature atomic layer deposition (Atomic Layer Deposition, ALD) of the gate dielectric 31 can be in channel form with the carbon nanotubesAnd a better interface is formed, and an additionally grown buffer layer is not needed, so that the structure and the process are simpler. The high-k material is a material corresponding to SiO 2 In other words, as long as the dielectric constant is greater than SiO 2 Is generally referred to as a high-k material.
In one possible implementation, the source 21 and the drain 22 in the examples of the present application are made of a metal material.
Specifically, in the prior art, as shown in fig. 10, the gate structure of the silicon-based nano-sheet (Nanosheet) field effect transistor is composed of a sidewall, an Inner sidewall (Inner Spacer) and a high-k metal gate, since the material constituting the source-drain contact is NiPtSi 2 And heavily doped silicon, so that on one hand, an additional process is required to manufacture the side wall and the inner side wall for preventing conduction between the gate electrode and the source drain electrode, and on the other hand, a Lightly Doped Drain (LDD) ion implantation process is required to mitigate the effect of heat-carried ions, so that the side wall is required to protect the LDD structure. In the embodiment of the application, as the unordered reticular film of the nanotube is used as a channel, the working principle is a schottky device, and the alignment of metals with different work functions and conduction bands or valence bands of the nanotube is adopted, so that the potential-free injection of electrons or holes can be realized, and the energy band degeneracy is realized without the need of carrying out source-drain impurity injection, so that the particle ion injection and high-temperature impurity activation process are not required, and an LDD structure is not required, namely, the side wall and the inner side wall are not required to be manufactured by an additional process.
In one possible implementation, the source 21 and the drain 22 in the examples of the present application are made of palladium metal or scandium metal.
In particular, P-Metal-Oxide-Semiconductor (PMOS) transistors may be implemented using electron beam deposition of high work function metals, such as palladium Metal, and N-Metal-Oxide-Semiconductor (NMOS) transistors may be implemented using electron beam deposition of low work function metals, such as scandium Metal.
In one possible embodiment, as shown in fig. 8 and 9, the transistor includes a multilayer channel 4 arranged in a stack; any two adjacent layers of channels 4 are separated by a gate 32; the difference between the height h1 of the end of the source electrode 21 away from the substrate 1 and the height h2 of the end of the multilayer channel 4 away from the substrate 1 is less than or equal to 15nm; the difference in height between the end of the drain 22 remote from the substrate 1 and the end of the multilayer channel 4 remote from the substrate 1 is less than or equal to 15nm; the height of the end of the source 21 away from the substrate 1 is the distance between the end of the source 21 away from the substrate 1 and the surface of the substrate 1 in the direction perpendicular to the surface of the substrate 1; the height of the end of the multilayer channel 4 remote from the substrate 1 is the distance between the end of the multilayer channel 4 remote from the substrate 1 and the surface of the substrate 1 in a direction perpendicular to the surface of the substrate 1.
Specifically, in the prior art, as shown in fig. 10, the source/drain electrode in the silicon-based nano-sheet (Nanosheet) field effect transistor is fabricated by doping or other processes, so that a problem of high resistance is caused, and in order to solve the problem, the height of the source/drain electrode is increased, that is, the distance between the source/drain electrode and the channel is large; this problem can also be solved by salicides. As shown in fig. 5 and fig. 6, since the source and the drain in the embodiment of the present application are metal, there is good electrical contact between the source and the drain and the channel 4, so that a larger current is obtained, no increase in the height of the source and the drain is required, and no salicide is required, so that the source and the drain have a lower resistance.
In one possible implementation, the gate 32 in the examples of the present application is made of palladium metal material.
Specifically, in the prior art, as shown in fig. 10, the source and drain materials in silicon-based nano-sheet (Nanosheet) field effect transistors are TaN/Al (for PMOS) and TaAlN/Al (for NMOS), respectively; in order to prevent the high-k metal gate from degradation in the high-temperature process of annealing the precursor side wall and the source drain impurities, the dummy gate is manufactured first, then the source drain is manufactured, and finally the dummy gate is pulled out to manufacture the high-k metal gate. In the embodiment of the application, the source-drain contact does not need high-temperature impurity annealing and does not need additional manufacturing of a dummy gate; according to the embodiment of the application, multiple metals do not need to be grown to carry out threshold adjustment of NMOS and PMOS, and the threshold adjustment manufacturing process of the symmetrical carbon nanotube NMOS and PMOS can be realized by utilizing the same metal such as palladium metal. It should be further noted that in other possible embodiments, the gate electrode 32 may be made of other metals that match the energy band of the channel material, such as titanium Ti metal.
In one possible implementation, as shown in fig. 9, the substrate 1 in the example of the present application includes a silicon wafer 11 and an insulating dielectric layer 12 disposed on a surface of the silicon wafer 11.
Specifically, the insulating dielectric layer 12 may be, for example, a silicon dioxide dielectric film about 300nm thick. In the prior art, since silicon-based nano-sheet (Nanosheet) field effect transistors are fabricated using silicon wafers to obtain channels, a relatively complex process is required to achieve isolation between the substrate and the device, so as to avoid current leakage between the source and the drain at the substrate. In the embodiment of the application, as shown in fig. 8 and 9, the disordered mesh film of the nanotubes is not required to be manufactured by using a substrate silicon wafer, so that the insulating dielectric layer 12 can be directly arranged on the silicon wafer 11, and the device is manufactured on the insulating dielectric layer 12, so that the conduction path between the source and the drain can be completely blocked.
In one possible implementation, the disordered network of nanotubes film in the examples of the present application is parallel to the surface of the substrate 1.
In one possible implementation, the gate dielectric 31 in the present embodiment is hafnium oxide.
The transistor in the embodiments of the present application will be further described below by taking a method for manufacturing a transistor in the embodiments of the present application as an example.
As shown in fig. 11, the transistor manufacturing method in the embodiment of the present application includes:
step 101, forming a first layer of lower gate structure 3a on a substrate 1, wherein the first layer of lower gate structure 3a comprises a lower gate 32a and a lower gate dielectric 31a, and the lower gate 32a is positioned between the lower gate dielectric 31a and the substrate 1;
specifically, in this step, the substrate 1, for example, comprises a 300nm thick silicon dioxide dielectric film on the surface of a silicon wafer, the surface of the substrate 1 may be first cleaned with ozone plasma, then patterned with a gate structure, then palladium having a thickness of about 15nm is formed as the lower gate electrode 32a by electron beam deposition, and then high-k dielectric hafnium oxide having a thickness of about 10nm is grown as the lower gate electrode dielectric 31a at 90 degrees celsius using an ALD process.
Step 102, manufacturing a lower source electrode 21a and a lower drain electrode 22a of the first layer on a substrate comprising the lower gate structure 3a of the first layer;
specifically, the source-drain pattern is photoetched, and palladium after being subjected to electron beam deposition of 25nm is used as the lower source electrode 21a and the lower drain electrode 22a.
Step 103, forming a first layer of nanotube disordered mesh film 4 on the first layer of lower gate structure 3a, the first layer of source electrode 21a and the lower drain electrode 22a in a transfer or deposition mode;
specifically, the photoresist is removed, the first layer of nanotube disordered mesh film 4 is transferred onto the structure formed in step 102, and the useless nanotubes except the channel 4 are etched away by reactive ion etching (Reactive Ion Etching, RIE), cutting off the current leakage path.
104, forming a first upper gate structure 3b on the first layer of nano tube disordered mesh film 4, wherein the first upper gate structure 3b comprises an upper gate 32b and an upper gate dielectric 31b, the upper gate dielectric 31b is positioned between the upper gate 32b and the first layer of nano tube disordered mesh film 4, the first layer of nano tube disordered mesh film 4 is surrounded by the upper gate dielectric 31b and a lower gate dielectric 31a, and the upper gate dielectric 31b and the lower gate dielectric 31a are surrounded by the upper gate 32b and the lower gate 32 die 4 b;
in step 105, an upper source electrode 21b and an upper drain electrode 22b are formed on the first layer of the disordered mesh film 4, one end of the first layer of the disordered mesh film 4 is located between the upper source electrode 21b and the lower source electrode 21a, and the other end of the first layer of the disordered mesh film 4 is located between the upper drain electrode 22b and the lower drain electrode 22a.
Through the above steps 101 to 105, a transistor with a single channel layer can be realized. Then, a second layer of lower gate dielectric may be formed on the upper side bb of the first layer, the first layer of upper gate is used as the second layer of lower gate, and the steps 103 to 105 are repeatedly performed based on the second layer on the basis of the structure, so as to realize the fabrication of the second layer of channel, and so on, the channels with the required layer number may be fabricated according to the current density.
In addition, as shown in fig. 12 and 13, fig. 12 is a schematic view of a scanning electron microscope of a transistor according to an embodiment of the present application, and fig. 13 is a schematic view of a disordered network film of nanotubes in fig. 12. FIG. 14 is a schematic diagram showing a transfer characteristic of a transistor according to an embodiment of the present application, wherein V GS Is the gate-source voltage, I ON To conduct current, V DS The SS parameter is 60 for the source-drain voltage; as shown in fig. 15, fig. 15 is a schematic diagram of transfer characteristics of a transistor in the prior art, as shown in fig. 16, fig. 16 is a schematic diagram of SS parameters of a fork-type sheet (fork-type) transistor and a silicon-based nano-sheet (Nanosheet) field effect transistor in the prior art, and it is seen that the SS parameters of the transistor in the prior art are about 70, that is, the SS parameters of the transistor in the embodiment of the present application are superior to those in the prior art. In addition, in general, the thicker the gate thickness is, the smaller the gate capacitance is, and the larger the gate control capability is, the better the SS parameter in the prior art is 120mV/dec, and the corresponding gate oxide thickness is 6.1nm; the thickness of the gate oxide layer of the transistor in the embodiment of the application is larger and is 10nm, and the corresponding SS parameter can be reduced to 60, so that the theoretical limit is reached, namely the advantages of the transistor in the embodiment of the application are fully illustrated.
The embodiment of the present application further provides an electronic device, including the transistor in any of the above embodiments, where the specific structure and principle of the transistor are the same as those of the above embodiments, and are not described herein again. The electronic device may be any electronic device using transistors, and the electronic device may be applied to various fields such as sensing, flexibility, display, and the like, to reduce power consumption.
In the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relation of association objects, and indicates that there may be three kinds of relations, for example, a and/or B, and may indicate that a alone exists, a and B together, and B alone exists. Wherein A, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of the following" and the like means any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.
The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and variations may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims (12)
1. A transistor, comprising:
a substrate;
source, drain and gate structures on the surface of the substrate;
the gate structure includes a gate dielectric and a gate surrounding the gate dielectric;
the channel is a disordered reticular film of the nano tube;
two ends of the channel are respectively connected with the source electrode and the drain electrode;
the gate dielectric surrounds the channel and is located between the gate and the channel;
the gate length of the transistor is less than or equal to 5nm, and the gate length is the channel length covered by the gate.
2. The transistor according to claim 1, wherein,
the nano tube disordered mesh film is a carbon nano tube disordered mesh film.
3. The transistor according to claim 1, wherein,
the transistor comprises a plurality of layers of the channels which are arranged in a stacked manner;
any two adjacent layers of the channel are separated by the gate.
4. The transistor according to claim 2, wherein,
the gate dielectric is a high-k dielectric.
5. The transistor according to claim 1, wherein,
the source and the drain are made of a metal material.
6. The transistor according to claim 5, wherein,
the source and the drain are made of palladium metal or scandium metal.
7. The transistor according to claim 5, wherein,
the transistor comprises a plurality of layers of the channels which are arranged in a stacked manner;
any two adjacent layers of the channels are separated by the grid electrode;
the difference between the height of the end of the source electrode far away from the substrate and the height of the end of the multilayer channel far away from the substrate is less than or equal to 15nm;
the difference between the height of the end of the drain electrode away from the substrate and the height of the end of the multilayer channel away from the substrate is less than or equal to 15nm;
the height of the end of the source electrode far away from the substrate is the distance between the end of the source electrode far away from the substrate and the surface of the substrate in the direction perpendicular to the surface of the substrate;
the height of the end of the multilayer channel away from the substrate is the distance between the end of the multilayer channel away from the substrate and the substrate surface in a direction perpendicular to the substrate surface.
8. The transistor according to claim 1, wherein,
the gate electrode is made of a palladium metal material.
9. The transistor according to claim 1, wherein,
the substrate comprises a silicon wafer and an insulating medium layer arranged on the surface of the silicon wafer.
10. The transistor according to claim 1, wherein,
the disordered network of nanotubes film is parallel to the substrate surface.
11. The transistor according to claim 1, wherein,
the gate dielectric is hafnium oxide.
12. An electronic device comprising a transistor according to any of claims 1 to 11.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210686434.6A CN117295342A (en) | 2022-06-16 | 2022-06-16 | Transistor and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210686434.6A CN117295342A (en) | 2022-06-16 | 2022-06-16 | Transistor and electronic device |
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| CN117295342A true CN117295342A (en) | 2023-12-26 |
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| CN202210686434.6A Pending CN117295342A (en) | 2022-06-16 | 2022-06-16 | Transistor and electronic device |
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