WO2021227448A1 - 一种隧穿场效应晶体管的漏端负交叠区自对准制备方法 - Google Patents

一种隧穿场效应晶体管的漏端负交叠区自对准制备方法 Download PDF

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WO2021227448A1
WO2021227448A1 PCT/CN2020/132725 CN2020132725W WO2021227448A1 WO 2021227448 A1 WO2021227448 A1 WO 2021227448A1 CN 2020132725 W CN2020132725 W CN 2020132725W WO 2021227448 A1 WO2021227448 A1 WO 2021227448A1
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field effect
effect transistor
self
gate
overlap region
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PCT/CN2020/132725
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French (fr)
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黄芊芊
李一庆
杨勐譞
王志轩
叶乐
蔡一茂
黄如
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北京大学
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Priority to US17/636,980 priority Critical patent/US20230058216A1/en
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Definitions

  • the invention belongs to the field of field-effect transistor logic devices and circuits in CMOS ultra-large integrated circuits (ULSI), and specifically relates to the design and preparation of a negative overlap region of the drain terminal of a tunneling field-effect transistor.
  • ULSI CMOS ultra-large integrated circuits
  • the tunneling field effect transistor uses a band-band tunneling mechanism to get rid of the limitation of thermoelectric potential, can achieve ultra-steep sub-threshold slope, and can achieve high current-on-off ratio at low voltage, which is considered to be a possible replacement in the future MOSFET is a low-power device.
  • TFET is a reverse-biased P-I-N junction controlled by the gate. It has the characteristics of low off-state current, steep subthreshold slope, etc., and is compatible with traditional CMOS processes. However, considering the unique device structure and electrical characteristics of TFET, the process preparation of TFET needs to be improved on the traditional CMOS process.
  • One characteristic that has a greater impact on the electrical performance of TFET devices is the bipolar effect. It means that when a reverse biased gate voltage is applied to the device, additional tunneling occurs at the drain end of the device, introducing additional bipolar current. This may cause problems such as increased leakage current of the device and decreased switching ratio.
  • the traditional method of suppressing the bipolar effect is to shift the drain injection frame so that a part of the intrinsic region is retained between the channel and the drain, which is called the drain negative overlap region (underlap region).
  • this method causes the device doping to depend heavily on the lithography accuracy, introduces additional sources of fluctuations, is not conducive to device consistency, and affects the large-scale integrated application of TFET devices.
  • the use of this method is not conducive to the subsequent metal silicide treatment of the device, thereby affecting the contact of the device, and it is also not conducive to the use of techniques such as impurity segregation. Therefore, how to self-align the negative overlap region of the drain terminal to optimize the bipolar effect while maintaining device consistency has become an urgent problem in the design of conventional TFET devices.
  • the purpose of the present invention is to provide a self-aligned preparation method of the self-aligned drain terminal negative overlap region of a tunneling field effect transistor.
  • This method effectively utilizes the existing processes in the standard CMOS IC process, can effectively suppress the device bipolar effect and maintain device consistency, and is also conducive to the introduction and use of advanced processes such as metal silicide.
  • the grid pattern is formed by photolithography and etching
  • High-temperature annealing activates impurities, and then enters the subsequent process consistent with CMOS, including depositing a passivation layer, opening contact holes, and metallization, and then a tunneling structure with a self-aligned structure in the negative overlap region of the drain terminal can be obtained.
  • Field effect transistor
  • the semiconductor substrate material in the step (1) is selected from Si, Ge, SiGe, GaAs or other II-VI, III-V and IV-IV binary or ternary compound semiconductors, insulators On silicon or germanium on insulator.
  • the gate dielectric layer material in the step (2) is selected from SiO 2 , Si 3 N 4 and high-K gate dielectric materials.
  • the method for growing the gate dielectric layer material in the step (2) is selected from one of the following methods: conventional thermal oxidation, nitrogen-doped thermal oxidation, chemical vapor deposition and physical vapor deposition.
  • the gate material in the step (2) is selected from doped polysilicon, metal cobalt, nickel, and other metals or metal silicides.
  • the thin sidewall in the step (4) and the thick sidewall in the step (5) are made of the same or different sidewall materials.
  • the sidewall spacer material is selected from one or more laminated combinations of silicon oxide, silicon nitride, and silicon carbide.
  • the thickness of the thin sidewall in the step (4) is about 5-10 nm.
  • the thickness of the thick sidewall in the step (5) is about 40-60 nm.
  • the sidewall at the source end can be completely removed and the thin sidewall can be grown again.
  • the present invention proposes a structure in which asymmetric sidewalls are designed on both sides of the gate of the tunneling field effect transistor, wherein the side of the gate close to the source end is a thin sidewall, and the side of the gate close to the drain end is a thick sidewall.
  • the present invention reasonably utilizes the thin sidewalls and thick sidewalls existing in the standard CMOS process, the thin sidewalls at the source end are used as hard masks for the injection of the source region of the transistor, and the thick sidewalls at the drain end are used as the hard mask for the injection of the drain region of the transistor Without the introduction of special materials and special processes, it can ensure that TFETs can be mixed and integrated with standard CMOS devices to achieve more complex and diverse circuit functions.
  • the invention can effectively suppress the bipolar effect, and does not introduce new non-ideal effects due to processes such as metal silicide, and can be scaled down with advanced processes.
  • the thickness of the sidewall used in the present invention can be controlled by controlling the growth and etching time and rate of the sidewall material, without considering the over-etching deviation in the photolithography process, and between the wafers, between die and die, There is good consistency from device to device. Therefore, the use of the present invention for self-aligned source-drain injection can greatly optimize the fluctuation characteristics of the device, ensure that the device has better consistency, and is beneficial to the large-scale integrated design and application of TFET.
  • FIG. 1 is a schematic cross-sectional view of a complete structure of a tunneling field effect transistor after a subsequent process in an embodiment of the present invention
  • FIG. 2 is a schematic cross-sectional view after forming STI isolation on the semiconductor substrate in the embodiment
  • FIG. 3 is a schematic cross-sectional view after the gate dielectric and the gate material are grown and the gate patterning is completed in the embodiment;
  • Figure 5 is a schematic cross-sectional view of the embodiment after the thick side wall is grown
  • FIG. 6 is a schematic cross-sectional view of the embodiment after removing the thick side wall of the source end
  • FIG. 7 is a schematic cross-sectional view after the source-drain ion implantation is completed in the embodiment
  • a specific example of the preparation method of the present invention includes the process steps shown in FIGS. 1 to 7:
  • the doping element is phosphorus
  • the doping dose is 1e13cm -2
  • the doping energy is 340keV.
  • the initial growth of silicon dioxide on the surface is bleached, and then a gate dielectric layer 3 is thermally grown.
  • the gate dielectric layer 3 is SiO 2 with a thickness of about 1.8 nm; the gate material is deposited, and the gate material is a doped polysilicon layer with a thickness It is 100nm.
  • the gate pattern is photoetched, and the gate material and the gate dielectric layer 3 are etched to the bulk silicon substrate 1, as shown in FIG. 3.
  • the implanted ion in the source region 7 is BF 2 + , the implant dose is 2e15 cm -2 , and the implant energy is 5 keV; the implanted element in the drain region 8 is As, the implant dose is 2e15 cm -2 , and the implant energy is 5 keV.
  • the passivation layer 9 of the subsequent process and the metal 10 of the subsequent process are grown in accordance with the CMOS subsequent process to obtain the tunneling field effect transistor with the structure shown in FIG. 1.

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Abstract

一种隧穿场效应晶体管的漏端负交叠区自对准制备方法，在隧穿场效应晶体管栅两侧设计不对称侧墙的结构，其中栅靠近源端的一侧为薄侧墙，栅靠近漏端的一侧为厚侧墙；将源端薄侧墙作为晶体管源区注入的硬掩模，而漏端厚侧墙作为晶体管漏区注入的硬掩模。该方法合理利用了标准CMOS工艺中存在的薄侧墙与厚侧墙，没有引入特殊材料与特殊工艺，即实现了对隧穿场效应晶体管双极效应的抑制，同时优化了器件涨落特性。而且该方法可以保证隧穿场效应晶体管能与标准CMOS器件混片集成，实现更为复杂多元的电路功能。

Description

一种隧穿场效应晶体管的漏端负交叠区自对准制备方法 技术领域
本发明属于CMOS超大集成电路(ULSI)中的场效应晶体管逻辑器件与电路领域，具体涉及一种隧穿场效应晶体管的漏端负交叠区的设计与制备。
背景技术
随着集成电路的不断发展，器件特征尺寸不断减小，芯片功耗密度不断增加，电路功耗逐渐成为限制集成电路等比例缩小的重要因素。为了降低电路功耗，较好的方法是降低电源电压。然而MOSFET的亚阈值斜率受限于热电势，在室温下不能低于60mV/dec，在维持一定驱动能力的情况下，进一步降低电源电压会导致器件泄漏电流指数上升，带来额外的功耗代价，在器件进入纳米尺度后影响尤其严重。而隧穿场效应晶体管(TFET)利用带带隧穿机制，摆脱了热电势的限制，能实现超陡的亚阈值斜率，能在低压下实现高的电流开关比，被认为是未来有可能取代MOSFET的低功耗器件。
TFET是一个受栅控制的反偏P-I-N结，它有着低关态电流，陡亚阈值斜率等特点，且能与传统CMOS工艺兼容。然而考虑到TFET独特的器件结构与电学特性，TFET的工艺制备需要在传统CMOS工艺上加以改进。其中对TFET器件电学性能影响较大的一种特性是双极效应。它是指当器件施加反偏栅电压时器件会在漏端发生额外的隧穿，引入额外的双极电流。这有可能会带来器件的泄漏电流提升，开关比下降等问题。传统抑制双极效应的方法是将漏端注入框平移，使沟道与漏端之间保留一部分的本征区，称之为漏端负交叠区(underlap区)。然而这种方法会使器件掺杂严重依赖于光刻精度，会引入额外的涨落源，不利于器件一致性，影响TFET器件的大规模集成应用。并且使用这种方法后续不利于对器件进行金属硅化物处理，从而影响器件接触，也不利于杂质分凝等技术的使用。因此，如何自对准地实现漏端负交叠区，优化双极效应的同时维护器件一致性，成为常规TFET器件设计上一个急需解决的问题。
发明内容
本发明的目的在于提出一种隧穿场效应晶体管的自对准漏端负交叠区自对准制备方法。该方法有效利用了标准CMOS IC工艺中现有的工艺，能有效抑制器件双极效应并维持器件一致性，还有利于金属硅化物等先进工艺的引入使用。
一种隧穿场效应晶体管的漏端负交叠区自对准制备方法，其特征是，包括以下步骤：
(1)准备半导体衬底，进行有源区的隔离；
(2)生长栅介质层材料，继而生长栅材料；
(3)通过光刻与刻蚀，形成栅图形；
(4)在栅图形边缘生长薄侧墙；
(5)在栅图形边缘继续生长厚侧墙；
(6)去除靠近源端的栅厚侧墙，保留源端的栅薄侧墙；
(7)以光刻胶与漏端栅厚侧墙为掩模，离子注入形成器件的漏；
(8)以光刻胶与源端栅薄侧墙为掩模，离子注入形成器件的源；
(9)高温退火激活杂质，然后进入同CMOS一致的后道工序，包括淀积钝化层、开接触孔以及金属化，即可制得具有漏端负交叠区自对准结构的隧穿场效应晶体管。
上述制备方法中，所述步骤(1)中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI、III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅或绝缘体上的锗。
上述制备方法中，所述步骤(2)中的栅介质层材料选自SiO 2、Si 3N 4和高K栅介质材料。
上述制备方法中，所述步骤(2)中的生长栅介质层材料的方法选自下列方法之一：常规热氧化、掺氮热氧化、化学气相淀积和物理气相淀积。
上述制备方法中，所述步骤(2)中的栅材料选自掺杂多晶硅、金属钴、镍以及其他金属或金属硅化物。
上述制备方法中，所述步骤(4)中的薄侧墙与步骤(5)中的厚侧墙采用相同或不同的侧墙材料。
上述制备方法中，侧墙材料选自氧化硅、氮化硅、碳化硅中的一种或多种叠层组合。
上述制备方法中，所述步骤(4)中的薄侧墙厚度约为5-10nm。
上述制备方法中，所述步骤(5)中的厚侧墙厚度约为40-60nm。
上述制备方法中，所述步骤(6)中的厚侧墙与薄侧墙间如果没有刻蚀终止层，可完全去除源端的侧墙后再次生长薄侧墙。
与现有技术相比，本发明的技术效果：
本发明提出了在隧穿场效应晶体管栅两侧设计不对称侧墙的结构，其中栅靠近源端的一侧为薄侧墙，栅靠近漏端的一侧为厚侧墙。本发明合理利用了标准CMOS工艺中存在的薄侧墙与厚侧墙，将源端薄侧墙作为晶体管源区注入的硬掩模，而漏端厚侧墙作为晶体管漏区注 入的硬掩模，没有引入特殊材料与特殊工艺，可以保证TFET能与标准CMOS器件混片集成，实现更为复杂多元的电路功能。
本发明能有效地抑制双极效应，且不会因为金属硅化物等工艺引入新的非理想效应，可以伴随先进工艺进行等比例缩小。
本发明所使用的侧墙厚度能通过控制侧墙材料的生长与刻蚀时间与速率来控制，无需考虑光刻过程中的套刻偏差，且在片与片之间，die与die之间，器件与器件之间都有着较好的一致性。因此使用本发明进行自对准的源漏注入能极大地优化器件涨落特性，保证器件具有较好的一致性，有利于TFET的大规模集成设计应用。
附图说明
图1是本发明实施例中经过后道工序后的隧穿场效应晶体管完整结构剖面示意图；
图2是实施例中在半导体衬底上形成STI隔离后的剖面示意图；
图3是实施例中生长完栅介质与栅材料并完成栅的图形化后的剖面示意图；
图4是实施例中生长完薄侧墙后的剖面示意图；
图5是实施例中生长完厚侧墙后的剖面示意图；
图6是实施例中去除源端厚侧墙后的剖面示意图；
图7是实施例中完成源漏离子注入后的剖面示意图；
图中：
1——衬底；                     2——STI隔离；
3——栅介质层；                 4——栅；
5——薄侧墙；                   6——厚侧墙；
7——源区；                     8——漏区；
9——后道工序的钝化层；         10——后道工序的金属。
具体实施方式
下面通过实例对本发明做进一步说明。需要注意的是，公布实施例的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。
本发明制备方法的一具体实例包括图1至图7所示的工艺步骤：
1、在掺杂浓度为轻掺杂、晶向为<100>的体硅衬底1上初始热氧化一层二氧化硅，厚度约10nm，并淀积一层氮化硅，厚度约100nm，之后STI刻蚀，并淀积隔离材料填充深孔后CMP，采用浅槽隔离技术制作有源区STI隔离2，然后湿法腐蚀去除氮化硅，如图2所示。
2、进行阱注入，掺杂元素为磷，掺杂剂量为1e13cm -2，掺杂能量为340keV。
3、漂去表面初始生长的二氧化硅，然后热生长一层栅介质层3，栅介质层3为SiO 2，厚度约为1.8nm；淀积栅材料，栅材料为掺杂多晶硅层，厚度为100nm。进行多晶硅预注入，注入元素为磷，注入剂量为4e15cm -2，注入能量为6keV。光刻出栅图形，刻蚀栅材料与栅介质层3直到体硅衬底1，如图3所示。
4、各向同性淀积生长8.5nm厚的氮化硅，然后各向异性刻蚀8.5nm厚的氮化硅，形成薄侧墙5，并进行30分钟800摄氏度热退火，如图4所示。
5、各向同性淀积生长9nm厚的二氧化硅，接着各向同性淀积生长42nm厚的氮化硅。各向异性刻蚀42nm厚的氮化硅，继而各向异性刻蚀9nm厚的二氧化硅，形成厚侧墙6，如图5所示。
6、淀积15nm厚的二氧化硅，光刻暴露源区，靠近漏端的栅区和厚侧墙受到光刻胶保护。各向同性过刻蚀15nm厚未受光刻胶保护的二氧化硅。去除光刻胶。各向同性过刻蚀42nm厚的氮化硅。各向同性过刻蚀9nm厚的二氧化硅。此时已去除源区厚侧墙，如图6所示。
7、分别进行源漏注入，注入掩膜版的一条边界位于栅4的中线上。源区7注入离子为BF 2 +，注入剂量为2e15cm -2，注入能量为5keV；漏区8注入元素为As，注入剂量为2e15cm -2，注入能量为5keV。进行一次快速热退火激活杂质。如图7所示。
8、依照CMOS后道工序生长后道的钝化层9和后道工序的金属10，得到如图1所示结构的隧穿场效应晶体管。
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (10)

  1. 一种隧穿场效应晶体管的漏端负交叠区自对准制备方法，其特征是，包括以下步骤：
    (1)准备半导体衬底，进行有源区的隔离；
    (2)生长栅介质层材料，继而生长栅材料；
    (3)通过光刻与刻蚀，形成栅图形；
    (4)在栅图形边缘生长薄侧墙；
    (5)在栅图形边缘继续生长厚侧墙；
    (6)去除靠近源端的栅厚侧墙，保留源端的栅薄侧墙；
    (7)以光刻胶与漏端栅厚侧墙为掩模，离子注入形成器件的漏；
    (8)以光刻胶与源端栅薄侧墙为掩模，离子注入形成器件的源；
    (9)高温退火激活杂质，然后进入同CMOS一致的后道工序，制得具有漏端负交叠区自对准结构的隧穿场效应晶体管。
  2. 如权利要求1所述的隧穿晶体管的漏端负交叠区自对准制备方法，其特征是，所述步骤(1)中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI、III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅或绝缘体上的锗。
  3. 如权利要求1所述的隧穿场效应晶体管的漏端负交叠区自对准制备方法，其特征是，所述步骤(2)中的栅介质层材料选自SiO 2、Si 3N 4和高K栅介质材料。
  4. 如权利要求1所述的隧穿场效应晶体管的漏端负交叠区自对准制备方法，其特征是，所述步骤(2)中生长栅介质层材料的方法选自下列方法之一：常规热氧化、掺氮热氧化、化学气相淀积和物理气相淀积。
  5. 如权利要求1所述的隧穿场效应晶体管的漏端负交叠区自对准制备方法，其特征是，所述步骤(2)中的栅材料选自掺杂多晶硅、金属钴、镍以及其他金属或金属硅化物。
  6. 如权利要求1所述的隧穿场效应晶体管的漏端负交叠区自对准制备方法，其特征是，所述步骤(4)的薄侧墙与步骤(5)中的厚侧墙采用相同或不同的侧墙材料。
  7. 如权利要求6所述的隧穿场效应晶体管的漏端负交叠区自对准制备方法，其特征是，所述侧墙材料选自氧化硅、氮化硅、碳化硅中的一种或多种叠层组合。
  8. 如权利要求1所述的隧穿场效应晶体管的漏端负交叠区自对准制备方法，其特征是，所述步骤(4)中的薄侧墙厚度为5-10nm。
  9. 如权利要求1所述的隧穿场效应晶体管的漏端负交叠区自对准制备方法，其特征是， 所述步骤(5)中的厚侧墙厚度为40-60nm。
  10. 如权利要求1所述的隧穿场效应晶体管的漏端负交叠区自对准制备方法，其特征是，所述步骤(6)中当厚侧墙与薄侧墙间没有刻蚀终止层时，完全去除源端的侧墙后再次生长薄侧墙。
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