WO2018000133A1 - 一种隧穿场效应晶体管及其制作方法 - Google Patents

一种隧穿场效应晶体管及其制作方法 Download PDF

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Publication number
WO2018000133A1
WO2018000133A1 PCT/CN2016/087315 CN2016087315W WO2018000133A1 WO 2018000133 A1 WO2018000133 A1 WO 2018000133A1 CN 2016087315 W CN2016087315 W CN 2016087315W WO 2018000133 A1 WO2018000133 A1 WO 2018000133A1
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Prior art keywords
region
gate
dielectric constant
drain region
conductive layer
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PCT/CN2016/087315
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English (en)
French (fr)
Inventor
杨喜超
张臣雄
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华为技术有限公司
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Priority to CN201680055102.0A priority Critical patent/CN108140671A/zh
Priority to PCT/CN2016/087315 priority patent/WO2018000133A1/zh
Publication of WO2018000133A1 publication Critical patent/WO2018000133A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a tunneling field effect transistor and a method of fabricating the same.
  • Tunneling field effect transistor can break through the metal oxide semiconductor field effect transistor (MOSFET) device due to its unique quantum mechanical working mechanism of interband tunneling. Threshold swing limit, and can better reduce the operating voltage of the device, with better advantages of reducing power consumption.
  • FIG. 1 shows a tunneling field effect transistor structure which is commonly used at present.
  • the tunneling field effect transistor 100 includes a source region 101, a drain region 102, a gate conductive layer 103, a channel 104, and a gate.
  • the source region 101, the drain region 102, and the channel 104 are disposed on the substrate 107, and the channel 104 is disposed between the source region 101 and the drain region 102.
  • the gate dielectric layer 105 covers a portion of the source region 101 and the trench 104, and the gate conductive layer 103 is disposed on an upper surface of the gate dielectric layer.
  • the partition wall 106 is disposed in a symmetrical form on both sides of the gate dielectric layer 105 and the gate conductive layer 103.
  • the gate conductive layer 103 controls the energy band structure of the channel 104 through the gate voltage, controls the on and off of the channel 104, and forms a current in the tunneling field effect transistor device.
  • the gate conductive layer 103 applies a sufficiently large gate voltage, the energy band of the channel 104 coincides with the energy band of the source region 101, and carriers (electrons) tunnel from the source region 101 to the channel. 104, and drifting to the drain region 102 to form a current under the action of the electric field of the drain region 102.
  • source region 101 and channel 104 control the tunneling of carriers, while drain region 102 and channel 104 control the subsequent transport of carriers that tunnel into the channel.
  • the gate dielectric layer 105 and the gate conductive layer 103 are not disposed above the channel 104 near the drain region 102, so that the gate voltage cannot completely regulate the energy band structure of the channel 104, so it is called a short gate structure. .
  • the barrier affects the transport of carriers, which in turn causes the current of the device to decrease, affecting the driving capability of the tunneling field effect transistor device.
  • Embodiments of the present invention provide a tunneling field effect transistor to improve driving capability of a tunneling field effect transistor.
  • a tunneling field effect transistor having a short gate structure, and a high dielectric constant is disposed in a portion of the channel near the drain region that is not covered by the gate region
  • the barrier wall weakens the bipolar conduction characteristics of the tunneling field effect transistor and improves the current drive capability of the tunneling field effect transistor.
  • the gate region is capable of electrostatically doping the channel through the high dielectric constant isolation wall, and the high dielectric constant spacer material has a relative dielectric constant greater than 3.9.
  • the tunneling field effect transistor includes a source region, a drain region, a channel, a gate region, and a isolation wall, wherein: the source region and the drain region are disposed on both sides of the channel; A portion of the channel near the side of the drain region is not covered by the gate region, forming a short gate structure, which avoids tunneling of carriers between the drain region and the channel, thereby weakening the tunneling field effect transistor Bipolar conductivity.
  • the partition wall includes a low dielectric constant partition wall disposed on one side of the source region and a high dielectric constant partition wall disposed on one side of the drain region; the low dielectric constant partition wall covering the source a portion of the region adjacent to one side of the channel and a side surface covering the side of the gate region adjacent to the source region; the high dielectric constant isolation wall covering the side of the channel adjacent to the drain region a region covered by the gate region and covering a partial region of the drain region near a side of the channel and a side surface covering a side of the gate region adjacent to the drain region to form the high dielectric constant isolation
  • a wall is connected to the gate region and the drain region, and covers a structure in which the channel is close to a region of the drain region that is not covered by the gate region to improve a current driving capability of the tunneling field effect transistor.
  • the high dielectric constant barrier has a width greater than or equal to 2 nanometers and less than or equal to 15 nanometers.
  • the partition wall further includes a low dielectric constant partition wall disposed on one side of the drain region, and the low dielectric constant partition wall disposed on one side of the drain region is disposed on
  • the high dielectric constant isolation wall is away from a side of the gate region and covers a side surface of the high dielectric constant isolation wall away from the gate region to increase a distance between the gate region and the drain region, thereby further It is possible to avoid diffusion of impurity ions in the drain region below the gate region during the rapid annealing process during the fabrication process.
  • the partition wall may be disposed on the insulating layer to reduce stress.
  • the optional partition wall may be disposed on the gate insulating layer to simplify the manufacturing process.
  • the gate dielectric layer covers a whole area of the channel, and a partial area of the source area and the drain area near a side of the channel; the gate dielectric layer is adjacent to the a partial region on one side of the drain region is not covered by the gate conductive layer; the high dielectric constant isolation barrier covers the side of the gate dielectric layer close to the drain region and not covered by the gate conductive layer In all regions of the partial region, a structure in which only a high dielectric constant isolation wall is disposed on the drain region side is formed, the capacitance of the tunneling field effect transistor is reduced, and the tunneling speed of the tunneling field effect transistor carrier is improved.
  • the gate dielectric layer covers a whole area of the channel, and a partial area of the source area and the drain area near a side of the channel; the gate dielectric layer is close to the a partial region on one side of the drain region is not covered by the gate conductive layer; the high dielectric constant isolation barrier covers a portion of the gate dielectric layer close to the drain region and not covered by the gate conductive layer a first partial region of the partial region; the low dielectric constant isolation wall disposed on one side of the drain region covers a portion of the gate dielectric layer adjacent to the drain region and not covered by the gate conductive layer a second partial region of the partial region; the first partial region and the second partial region constituting all of the partial region of the gate dielectric layer adjacent to the drain region without being covered by the gate conductive layer
  • a structure of a high dielectric constant isolation wall and a low dielectric constant isolation wall is formed on the side of the drain region to increase the distance between the gate region and the drain region, thereby avoiding the leakage region during the
  • a method for fabricating a tunneling field effect transistor comprising: Providing a semiconductor substrate; sequentially depositing a gate dielectric layer and a gate conductive layer on the semiconductor substrate; performing photolithography and etching on the gate conductive layer to form a gate conductive layer of a desired pattern; forming a conductive layer covering the gate a high dielectric constant partition wall on one side surface of the layer; a low dielectric constant partition wall is formed on one side of the source region; and a source region is formed on a side of the gate conductive layer where the high dielectric constant partition wall is not disposed, The source region partial region is covered by the gate conductive layer; a drain region is formed on a side of the gate conductive layer where the high dielectric constant isolation wall is disposed, and the drain region portion is surrounded by the high dielectric constant isolation wall Covering; forming a channel between the source region and the drain region, a portion of the channel near a side of the source region being covered by the gate conductive layer
  • the tunneling field effect transistor fabricated by the fabrication method has a short gate structure, and a high dielectric constant spacer is disposed in a portion of the channel near the drain region that is not covered by the gate region to weaken tunneling.
  • the method further includes: performing ion implantation on the source region again by using a tilt injection method, A defect distribution which is favorable for generating BTBT is formed under the gate region, thereby increasing the tunneling current.
  • the method further includes: separating the high dielectric constant isolation wall from the gate conductive layer a side of the low dielectric constant spacer covering the side surface of the high dielectric constant isolation wall away from the side of the gate conductive layer to increase the distance between the gate region and the drain region, thereby being in the process of being fabricated To avoid diffusion of impurity ions in the drain region below the gate region during the rapid annealing process.
  • FIG. 1 is a schematic structural view of a tunneling field effect transistor in the prior art
  • FIG. 2 is a schematic structural diagram of a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 3 is another schematic structural diagram of a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of another tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 5 is a flowchart of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention
  • 6A-6I are schematic diagrams showing a manufacturing process of a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 7 is still another schematic structural diagram of a tunneling field effect transistor according to an embodiment of the present invention.
  • Embodiments of the present invention provide a tunneling field effect transistor having a short gate structure and a high dielectric constant in a portion of a region near a drain region that is not covered by the gate region.
  • the barrier wall weakens the bipolar conduction characteristics of the tunneling field effect transistor and improves the current drive capability of the tunneling field effect transistor.
  • a tunneling field effect transistor 100 includes a source region 101, a drain region 102, and a trench. Road 104, grid and barrier.
  • the source region 101 and the drain region 102 are respectively disposed on two sides of the channel 104, and the source region 101 and the drain region 102 respectively adopt different doping types, that is, the source
  • the doping profiles of the region 101 and the drain region 102 are differentiated.
  • the gate region includes a gate conductive layer 103 and a gate dielectric layer 105, and covers a partial region of the source region 101 adjacent to the channel 104, and a portion of the channel 104 near a side of the source region 101 is also The gate region covers, and a portion of the channel 104 near the side of the drain region 102 is not covered by the gate region.
  • the gate region does not fully regulate the energy band structure of the channel 104, and the tunneling field effect transistor 100 has a short gate structure.
  • a gate voltage is applied to the gate region such that the gate region can control tunneling of carriers in the tunneling field effect transistor by an electric field to form an on state and an off state of the device.
  • the channel region of the tunneling field effect transistor near the drain region 102 is not regulated by the gate voltage, the energy band of the channel region cannot be with the drain region 102 in the case of the reverse gate voltage.
  • the energy band overlaps that is, the condition of band-to-band tunneling (BTBT) is not satisfied, so that the drain region 102 and the channel 104 can be avoided.
  • the carrier between the tunnels is tunneled, which in turn can weaken the bipolar conductivity of the tunneling field effect transistor.
  • the partition wall includes a low dielectric constant partition wall 1061 disposed on one side of the source region 101 and a high dielectric constant partition wall 1062 disposed on a side of the drain region 102.
  • the low dielectric constant partition wall 1061 covers a partial region of the source region 101 near a side of the channel 104 and a side surface covering a side of the gate region near the source region.
  • the high dielectric constant isolation wall 1062 covers an area of the channel 104 that is not covered by the gate region on a side of the drain region 102, and covers a portion of the drain region 102 near a side of the channel 104. And a side surface covering the side of the gate region adjacent to the drain region.
  • the high dielectric constant isolation wall 1062 needs to be connected to the gate region and the drain region 102, and covers an area of the channel 104 near the drain region 102 that is not covered by the gate region. In order to reduce the barrier of electron migration in the channel region, the current driving capability of the tunneling field effect transistor is improved. In the embodiment of the present invention, in order to ensure that the high dielectric constant isolation wall 1062 needs to be connected to the gate region and the drain region 102, and the side of the channel 104 close to the drain region 102 is not described. The region covered by the gate region, the width of the high dielectric constant barrier wall is greater than or equal to 2 nanometers and less than or equal to 15 nanometers.
  • the tunneling field effect transistor is provided with a high dielectric constant isolation wall 1062 at a channel region position near the drain region 102 which is not regulated by the gate voltage.
  • the channel near the region and the drain region 102 can serve as two electrodes of the capacitor, and the gate region, the high dielectric constant isolation wall 1062, and the channel near the drain region 102 can constitute a capacitor, and in the case where a gate voltage is applied,
  • the gate electric field cannot directly act on the channel near the drain region, but the gate fringe field can electrostatically dope the channel through the high dielectric constant isolation wall to reduce the potential barrier on the carrier drift path.
  • the gate region is capable of electrostatically doping the channel through the high dielectric constant isolation wall 1062.
  • the relative dielectric constant of the high dielectric constant spacer material is greater than 3.9, for example, Zinc oxide (ZnO), lanthanum oxide (Ta2O5), yttrium oxide (HfO2), zirconia (ZrO2), alumina (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), and nitrogen Silicon (Si3N4) and the like.
  • the tunneling field effect transistor provided by the embodiment of the present invention is provided with a high dielectric constant isolation wall 1062 at a position of a channel region near the drain region 102 which is not regulated by the gate voltage, so that it can be in a bipolar conduction Under electrical conditions, the tunneling of the carriers is weakened, and in the case where the device is in an active state (on state), the channel region covered by the high dielectric constant isolation wall 1062, due to the doping action of the fringe field effect, the barrier It is weakened, and the efficiency of the drain region 102 to extract carriers is improved, thereby improving the current driving capability of the tunneling field effect transistor.
  • the partition wall may be disposed on the insulating layer to reduce the stress.
  • the embodiment of the present invention does not limit that the partition wall must be disposed on the insulating layer, or may be disposed on the substrate.
  • the isolation wall may be disposed on the gate dielectric layer 105.
  • the gate dielectric layer 105 covers the entire area of the channel, and a partial region of the source region 101 and the drain region 102 near the side of the channel 104, and the gate dielectric layer 105 A portion of the portion adjacent to the source region 101 and the drain region 102 has a region not covered by the gate conductive layer 103, and the isolation wall may be disposed on the gate dielectric layer 105 without the gate conductive layer The area covered by 103.
  • FIG. 3 is a schematic diagram showing another structure of a tunneling field effect transistor according to an embodiment of the present invention.
  • the isolation wall includes the low dielectric constant disposed on a side of the source region 101.
  • the low dielectric constant partition wall 1061 disposed on one side of the source region 101 covers the partial region of the gate dielectric layer 105 near the source region 101 not covered by the gate conductive layer 103. All areas.
  • the high dielectric constant isolation wall 1062 disposed on one side of the drain region 102 covers the partial region of the gate dielectric layer 105 adjacent to the drain region 102 and not covered by the gate conductive layer 103. In all the regions, in other words, in the structure shown in Fig. 3, a high dielectric constant partition wall is provided on the side of the drain region 102, and a partition wall having a low dielectric constant is not provided.
  • the isolation wall includes the low dielectric constant disposed on a side of the source region 101.
  • the partition wall 1061 and the high dielectric constant partition wall 1062 disposed on one side of the drain region 102 further include a low dielectric constant partition wall 1063 disposed on one side of the drain region 102, and the low dielectric constant partition wall 1063 disposed on a side of the drain region 102 is disposed away from the high dielectric constant partition wall 1062
  • One side of the gate region covers the side surface of the high dielectric constant isolation 1062 wall away from one side of the gate region.
  • the partial region of the gate dielectric layer 105 that is not covered by the gate conductive layer 103 near the drain region 102 includes a first partial region and a second partial region, in other words, the first partial region and the first portion
  • the two-part region constitutes the entire area of the portion of the gate dielectric layer that is not covered by the gate conductive layer on the side of the drain region.
  • the low dielectric constant partition 1061 disposed on one side of the source region 101 covers the side of the gate dielectric layer 105 near the source region 101 is not described.
  • the high dielectric constant isolation wall 1062 disposed on one side of the drain region 102 covers the partial region of the gate dielectric layer 105 adjacent to the drain region 102 and not covered by the gate conductive layer 103.
  • the low dielectric constant partition 1061 disposed on one side of the source region 101 and the high dielectric disposed on a side of the drain region 102 are not limited.
  • the constant isolation wall 1062 and the low dielectric constant isolation wall 1063 disposed on one side of the drain region 102 must be disposed on the gate dielectric layer, and FIG. 4 is only for illustrative purposes.
  • a high dielectric constant isolation wall and a low dielectric constant isolation wall are disposed on one side of the drain region, which can increase the distance between the gate region and the drain region, thereby avoiding the execution of the rapid annealing process during the manufacturing process.
  • Impurity ions in the drain region diffuse below the gate region.
  • no additional photolithography and etching processes are required during the fabrication process to remove the low dielectric constant barrier on the drain side, simplifying the fabrication process.
  • an embodiment of the present invention further provides a method for fabricating a tunneling field effect transistor.
  • FIG. 5 is a flowchart of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention. As shown in FIG. 5, the method includes:
  • a semiconductor substrate 107 is provided as shown in FIG. 6A.
  • the semiconductor substrate 107 in the embodiment of the present invention may be specifically made of a semiconductor material such as bulk silicon, silicon on silicon, germanium, germanium silicon or a group III-V compound.
  • S102 sequentially depositing a gate dielectric layer 105 and a gate conductive layer 103 on the semiconductor substrate 107, as shown in FIG. 6B.
  • the material of the gate dielectric layer 105 in the embodiment of the present invention may be an insulating material having a low dielectric constant such as silicon dioxide, or a high dielectric constant insulating material such as tantalum and aluminum oxide.
  • the material of the gate conductive layer 103 may be a conductive material having good electrical conductivity such as polysilicon, metal, metal nitride or the like.
  • S103 Photolithography and etching of the gate conductive layer 103 to define the shape and position of the gate conductive layer 103 to form a desired gate conductive layer 103, as shown in FIG. 6C.
  • S104 forming a high dielectric constant partition wall 1062 covering a side surface of the gate conductive layer 103, as shown in FIG. 6D.
  • a high dielectric constant dielectric material may be deposited on the basis of the structure shown in FIG. 6C, wherein the high dielectric constant dielectric material is an insulating material having a relative dielectric constant greater than 3.9, such as zinc oxide (ZnO). , lanthanum oxide (Ta2O5), yttrium oxide (HfO2), zirconia (ZrO2), alumina (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), and silicon nitride (Si3N4) Wait.
  • ZnO zinc oxide
  • TiO5 lanthanum oxide
  • HfO2 yttrium oxide
  • ZrO2 zirconia
  • Al2O3 alumina
  • La2O3 lanthanum oxide
  • TiO2O2O3 titanium oxide
  • TiO3 titanium oxide
  • Y2O3 yttrium oxide
  • Si3N4 silicon n
  • the high dielectric constant dielectric layer may be etched by an anisotropic etching technique to form a high dielectric constant isolation wall 1062 covering both side surfaces of the gate conductive layer 103.
  • the high dielectric constant partition wall 1062 on one side thereof may be removed to form a high dielectric constant partition wall 1062 covering one side surface of the gate conductive layer 103.
  • the width of the high dielectric constant isolation wall 1062 is several nanometers to several tens of nanometers.
  • the width of the high dielectric constant isolation wall 1062 is greater than or equal to 2 nanometers and less than or equal to 15 nanometers.
  • S105 forming a source region 101 on a side of the gate conductive layer 103 where the high dielectric constant isolation wall 1062 is not disposed, and a portion of the source region 101 is covered by the gate conductive layer 103.
  • the photoresist 108 may be disposed on the side of the drain region 102 and protected by photolithography. A region of the drain region 102 is to be formed, and ion implantation of ions of the first doping type is performed to form a source region 101 of the first doping type.
  • the first doping type ions may be implanted in a vertical implantation manner, and a heavily doped region is formed on the surface of the source region 101, as shown in FIG. 6E.
  • S106 removing the photoresist in S105, depositing a low dielectric constant dielectric material, and forming an a low dielectric constant spacer 1061 and a low dielectric constant 1062 using an anisotropic etching technique.
  • the low dielectric constant dielectric material in the embodiment of the invention may be an insulating material such as silicon nitride or silicon dioxide.
  • the low dielectric constant isolation wall of the embodiment of the present invention includes a low dielectric constant isolation wall 1061 disposed on one side of the source region 101 and a low dielectric constant isolation wall 1063 disposed on a side of the high dielectric constant isolation wall 1062. As shown in Figure 6F. Of course, the low dielectric constant spacer 1063 on the side of the high dielectric constant isolation wall 1062 can also be removed, which is not limited in the embodiment of the present invention.
  • S107 ion implantation is performed on the source region 101 by a tilt injection method, as shown in FIG. 6G.
  • a photoresist 108 may be disposed on the side of the drain region 102 to protect the drain region 102 by photolithography, and ion implantation is performed on the source region 101 again.
  • ion implantation, doping type and The doping type is the same when the source region 101 is formed in S105.
  • the only difference is that the ion implantation is performed by the oblique injection method, and the implantation energy is higher than the implantation energy in S105, and the implantation dose is also higher than the implantation dose in S105.
  • the source region 101 is ion-implanted again by using a tilt injection method to form an impurity distribution under the gate region to facilitate the generation of BTBT, thereby increasing the tunneling current.
  • step S107 is an optional step.
  • a drain region 102 is formed on a side of the high dielectric constant isolation wall 1062, and a portion of the drain region 102 is covered by the high dielectric constant isolation wall 1062.
  • the photoresist 108 disposed in S107 may be removed, and a photoresist is disposed on the source region 101 side, the source region 101 is protected by photolithography, and one of the high dielectric constant isolation walls 1062 is disposed.
  • the ion implantation of the second doping type ions is performed on the side.
  • the second doping type ion implantation adopts a vertical implantation mode, as shown in FIG. 6H.
  • a channel is formed between the source region 101 and the drain region 102, A portion of the channel near the side of the source region 101 is covered by the gate conductive layer 103, and a portion of the channel near the side of the drain region 102 is not covered by the gate conductive layer 103 but is described
  • the high dielectric constant isolation wall 1062 is covered.
  • S109 etching the gate dielectric layer 105 by an anisotropic etching technique to obtain a desired gate dielectric layer 105.
  • the gate conductive layer 103 is a self-aligned template, and only the gate dielectric layer 105 of the gate conductive layer 103 is preserved, and the gate dielectric layer 105 of the tunneling field effect transistor shown in FIG. 2 is formed.
  • the gate conductive layer 103, the high dielectric constant isolation wall 1062, and the low dielectric constant isolation wall may be self-aligned templates, and the gate conductive layer 103 is retained, and the high dielectric constant is
  • the spacer 1062 and the gate dielectric layer 105 of the low dielectric constant barrier region form a pattern of the gate dielectric layer 105 in the tunneling field effect transistor shown in FIGS. 3 and 4.
  • the insulating material 110 having a low dielectric constant can be deposited, and after exposure, a metal electrode window is formed by photolithography and etching, and a corresponding metal is formed. Electrode 109 is shown in Figure 6I.
  • the low dielectric constant partition wall in the embodiment of the present invention refers to a partition wall whose relative dielectric constant is less than 3.9.
  • the high dielectric constant barrier wall refers to a barrier wall having a material having a relative dielectric constant greater than 3.9.
  • tunneling field effect transistors involved in the above embodiments of the present invention and the accompanying drawings are merely illustrative and not limited to other tunneling field effects in the short gate structure. It is also within the scope of the present invention to structure a tunneling field effect transistor having an asymmetric isolation wall formed by a high dielectric constant spacer on one side of the drain region of the transistor, such as the tunneling field effect transistor shown in FIG. In FIG. 7, the tunneling field effect transistor has a vertical structure, that is, the source region, the channel, and the drain region are located in the vertical direction.
  • the tunneling field effect transistor having a vertical structure may be a nanowire, a FinFET-like device or the like.

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Abstract

一种隧穿场效应晶体管（100）及其制作方法，隧穿场效应晶体管包括源区（101）、漏区（102）、沟道（104）、栅区和隔离墙，其中：源区和漏区设置于沟道两侧；沟道靠近漏区一侧的部分区域未被栅区覆盖；隔离墙包括设置于源区一侧的低介电常数隔离墙（1061）和设置于漏区一侧的高介电常数隔离墙（1062）；低介电常数隔离墙，覆盖源区靠近沟道一侧的部分区域以及覆盖栅区靠近源区一侧的侧表面；高介电常数隔离墙，覆盖沟道靠近漏区一侧未被栅区覆盖的区域，并覆盖漏区靠近沟道一侧的部分区域以及覆盖栅区靠近漏区一侧的侧表面，以削弱隧穿场效应晶体管的双极导电特性，并提升隧穿场效应晶体管的电流驱动能力。

Description

一种隧穿场效应晶体管及其制作方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种隧穿场效应晶体管及其制作方法。
背景技术
隧穿场效应晶体管(tunnel field effect transistor，简称TFET)由于其独特的带间隧穿的量子力学工作机制，可以突破金属氧化物半导体场效应晶体管(metal oxide semiconductor field effect transistor，MOSFET)器件的亚阈值摆幅限制，并能够较好地降低器件工作电压，具有更好的降低功耗的优势。
图1所示为目前比较常用的一种隧穿场效应晶体管结构，如图1所示，该隧穿场效应晶体管100包括源区101、漏区102、栅导电层103、沟道104、栅介质层105、隔离墙106和衬底107。所述源区101、漏区102和沟道104设置于所述衬底107上，且所述沟道104设置于所述源区101和所述漏区102之间。所述栅介质层105覆盖所述源区101和所述沟道104的部分区域，所述栅导电层103设置于所述栅介质层的上表面。所述隔离墙106以对称形式设置于所述栅介质层105和所述栅导电层103的两侧。其中，栅导电层103通过栅电压调控沟道104的能带结构，控制沟道104的通断，在隧穿场效应晶体管器件内形成电流。以n型TFET为例，当栅导电层103施加足够大的栅电压时，沟道104的能带与源区101的能带重合，载流子(电子)从源区101隧穿到沟道104，并且在漏区102电场的作用下漂移到漏区102形成电流。整个过程，源区101和沟道104控制载流子的隧穿，而漏区102和沟道104控制隧穿进沟道的载流子的后续输运。
图1中，在接近漏区102的沟道104上方未设置所述栅介质层105和所述栅导电层103，使得栅电压不能完全调控沟道104的能带结构，故称为短栅结构。接近漏区102的沟道104区域没有栅电压调控，在能带上存在一较高 的势垒，影响载流子的输运，进而导致器件的电流减小，影响隧穿场效应晶体管器件的驱动能力。
发明内容
本发明实施例提供一种隧穿场效应晶体管，以提高隧穿场效应晶体管的驱动能力。
第一方面，提供一种隧穿场效应晶体管，该隧穿场效应晶体管具有短栅结构，并在沟道靠近漏区一侧未被所述栅区覆盖的部分区域，设置高介电常数的隔离墙，以削弱隧穿场效应晶体管的双极导电特性，并提升隧穿场效应晶体管的电流驱动能力。
其中，本发明实施例中为使栅区能够通过所述高介电常数隔离墙对所述沟道进行静电掺杂，所述高介电常数隔离墙材料的相对介电常数大于3.9。
一种可能的设计中，所述隧穿场效应晶体管包括源区、漏区、沟道、栅区和隔离墙，其中：所述源区和所述漏区设置于所述沟道两侧；所述沟道靠近漏区一侧的部分区域未被所述栅区覆盖，形成短栅结构，可避免漏区和沟道之间的载流子发生隧穿，进而可削弱隧穿场效应晶体管的双极导电性。
所述隔离墙包括设置于所述源区一侧的低介电常数隔离墙和设置于所述漏区一侧的高介电常数隔离墙；所述低介电常数隔离墙，覆盖所述源区靠近所述沟道一侧的部分区域以及覆盖所述栅区靠近所述源区一侧的侧表面；所述高介电常数隔离墙，覆盖所述沟道靠近所述漏区一侧未被所述栅区覆盖的区域，并覆盖所述漏区靠近所述沟道一侧的部分区域以及覆盖所述栅区靠近所述漏区一侧的侧表面，形成所述高介电常数隔离墙与所述栅区和所述漏区连接，并覆盖所述沟道靠近所述漏区一侧未被所述栅区覆盖的区域的结构，以提升隧穿场效应晶体管的电流驱动能力。
可选的，为保证所述高介电常数隔离墙需要与所述栅区和所述漏区连接，并覆盖所述沟道靠近所述漏区一侧未被所述栅区覆盖的区域，所述高介电常数隔离墙的宽度大于等于2纳米，并小于等于15纳米。
另一种可能的设计中，所述隔离墙还包括设置于所述漏区一侧的低介电常数隔离墙，所述设置于所述漏区一侧的低介电常数隔离墙，设置于所述高介电常数隔离墙远离所述栅区的一侧，并覆盖所述高介电常数隔离墙远离所述栅区一侧的侧表面，以增大栅区与漏区的距离，进而可在制作过程中，避免执行快速退火工艺时漏区的杂质离子扩散至栅区下面。
再一种可能的设计中，所述隔离墙可以设置于绝缘层上，以减少应力作用。
可选的所述隔离墙可以设置于栅绝缘层上，以简化制作工艺。
一种可能的实施方式中，所述栅介质层覆盖所述沟道全部区域、以及所述源区和所述漏区靠近所述沟道一侧的部分区域；所述栅介质层靠近所述漏区一侧的部分区域未被所述栅导电层所覆盖；所述高介电常数隔离墙覆盖所述栅介质层靠近所述漏区一侧未被所述栅导电层所覆盖的所述部分区域的全部区域，形成漏区一侧仅设置高介电常数隔离墙的结构，降低隧穿场效应晶体管的电容，提高隧穿场效应晶体管载流子隧穿速度。
另一种可能的实施方式中，所述栅介质层覆盖所述沟道全部区域、以及所述源区和所述漏区靠近所述沟道一侧的部分区域；所述栅介质层靠近所述漏区一侧的部分区域未被所述栅导电层所覆盖；所述高介电常数隔离墙覆盖所述栅介质层靠近所述漏区一侧未被所述栅导电层所覆盖的所述部分区域的第一部分区域；所述设置于所述漏区一侧的低介电常数的隔离墙覆盖所述栅介质层靠近所述漏区一侧未被所述栅导电层所覆盖的所述部分区域的第二部分区域；所述第一部分区域和所述第二部分区域组成所述栅介质层靠近所述漏区一侧未被所述栅导电层所覆盖的所述部分区域的全部区域，形成漏区一侧设置高介电常数隔离墙和低介电常数隔离墙的结构，以增大栅区与漏区的距离，进而可在制作过程中，避免执行快速退火工艺时漏区的杂质离子扩散至栅区下面。另外，工艺制作过程中也不需要额外的光刻移除漏区一侧的低介电常数隔离墙，简化制作工艺。
第二方面，提供一种隧穿场效应晶体管的制作方法，所述方法包括：提 供半导体衬底；在所述半导体衬底上依次沉积栅介质层和栅导电层；对所述栅导电层进行光刻和刻蚀，形成所需图形的栅导电层；形成覆盖所述栅导电层一侧侧表面的高介电常数隔离墙；在所述源区一侧，形成低介电常数隔离墙；在所述栅导电层未设置高介电常数隔离墙的一侧形成源区，所述源区部分区域被所述栅导电层所覆盖；在所述栅导电层设置高介电常数隔离墙的一侧形成漏区，所述漏区部分区域被所述高介电常数隔离墙覆盖；在所述源区和所述漏区之间形成沟道，所述沟道靠近所述源区一侧的部分区域被所述栅导电层所覆盖，所述沟道靠近漏区一侧的部分区域未被所述栅导电层所覆盖但被所述高介电常数隔离墙所覆盖；对所述栅介质层进行光刻和刻蚀，形成所需图形的栅介质层。通过该制作方法制作出的隧穿场效应晶体管具有短栅结构，并在沟道靠近漏区一侧未被所述栅区覆盖的部分区域，设置高介电常数的隔离墙，以削弱隧穿场效应晶体管的双极导电特性，并提升隧穿场效应晶体管的电流驱动能力。
一种可能的设计中，在所述栅导电层未设置高介电常数隔离墙的一侧形成源区之后，所述方法还包括：采用倾角注入方式对所述源区再次进行离子注入，以在栅区下方形成利于产生BTBT的杂质分布，进而提升隧穿电流。
又一种可能的设计中，形成覆盖所述栅导电层一侧的侧表面的高介电常数隔离墙之后，所述方法还包括：在所述高介电常数隔离墙远离所述栅导电层的一侧，形成覆盖所述高介电常数隔离墙远离所述栅导电层一侧的侧表面的低介电常数隔离墙，以增大栅区与漏区的距离，进而可在制作过程中，避免执行快速退火工艺时漏区的杂质离子扩散至栅区下面。
附图说明
图1为现有技术中隧穿场效应晶体管的结构示意图；
图2为本发明实施例提供的隧穿场效应晶体管的一种结构示意图；
图3为本发明实施例提供的隧穿场效应晶体管的另一种结构示意图；
图4为本发明实施例提供的隧穿场效应晶体管的又一种结构示意图；
图5为本发明实施例提供的隧穿场效应晶体管的制作方法流程图；
图6A至图6I为本发明实施例提供的隧穿场效应晶体管制作过程示意图；
图7为本发明实施例提供的隧穿场效应晶体管的又一种结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。
本发明实施例提供一种隧穿场效应晶体管，该隧穿场效应晶体管具有短栅结构，并在沟道靠近漏区一侧未被所述栅区覆盖的部分区域，设置高介电常数的隔离墙，以削弱隧穿场效应晶体管的双极导电特性，并提升隧穿场效应晶体管的电流驱动能力。
图2所示为本发明实施例提供的隧穿场效应晶体管的一种结构示意图，如图2所示，本发明实施例提供的隧穿场效应晶体管100包括源区101、漏区102、沟道104、栅区和隔离墙。
本发明实施例中所述源区101和所述漏区102分别设置于所述沟道104两侧，且所述源区101和所述漏区102分别采用不同的掺杂类型，即对源区101和漏区102的掺杂分布进行了差异化处理。所述栅区包括栅导电层103和栅介质层105，并覆盖所述源区101靠近所述沟道104的部分区域，所述沟道104靠近所述源区101一侧的部分区域也被所述栅区覆盖，所述沟道104靠近漏区102一侧的部分区域未被所述栅区覆盖。换言之，所述栅区并不能完全调控所述沟道104的能带结构，所述隧穿场效应晶体管100具有短栅结构。对所述栅区施加栅电压，使得所述栅区可通过电场控制所述隧穿场效应晶体管中载流子的隧穿，形成器件的开态和关态。但是由于所述隧穿场效应晶体管接近漏区102一侧的沟道区域不受所述栅电压的调控，故在反向栅电压情况下，沟道区域的能带不能与所述漏区102的能带重合，即不满足器件带间隧穿(band-to-band tunneling，BTBT)的条件，故可避免漏区102和沟道104 之间的载流子发生隧穿，进而可削弱隧穿场效应晶体管的双极导电性。
本发明实施例中，所述隔离墙包括设置于所述源区101一侧的低介电常数隔离墙1061和设置于所述漏区102一侧的高介电常数隔离墙1062。如图2所示，所述低介电常数隔离墙1061，覆盖所述源区101靠近所述沟道104一侧的部分区域以及覆盖所述栅区靠近所述源区一侧的侧表面。所述高介电常数隔离墙1062，覆盖所述沟道104靠近所述漏区102一侧未被所述栅区覆盖的区域，覆盖所述漏区102靠近所述沟道104一侧的部分区域以及覆盖所述栅区靠近所述漏区一侧的侧表面。换言之，所述高介电常数隔离墙1062需要与所述栅区和所述漏区102连接，并覆盖所述沟道104靠近所述漏区102一侧未被所述栅区覆盖的区域，以降低沟道区电子迁移的势垒，提升隧穿场效应晶体管的电流驱动能力。本发明实施例中，为保证所述高介电常数隔离墙1062需要与所述栅区和所述漏区102连接，并覆盖所述沟道104靠近所述漏区102一侧未被所述栅区覆盖的区域，所述高介电常数隔离墙的宽度大于等于2纳米，并小于等于15纳米。
结合图1和图2可知，本发明实施例中所述隧穿场效应晶体管在不受栅电压调控的漏区102附近的沟道区域位置处设置有高介电常数的隔离墙1062，故栅区和漏区102附近的沟道可以作为电容的两电极，栅区、高介电常数的隔离墙1062和漏区102附近的沟道可以构成电容，进而在施加栅极电压的情况下，虽然栅极电场不能直接作用于漏区附近的沟道，但栅极边缘场可以通过高介电常数的隔离墙对沟道进行静电掺杂，降低载流子漂移路线上的势垒。
本发明实施例中为使栅区能够通过所述高介电常数隔离墙1062对所述沟道进行静电掺杂，所述高介电常数隔离墙材料的相对介电常数大于3.9，例如可选用氧化锌(ZnO)、氧化钽(Ta2O5)、氧化铪(HfO2)、氧化锆(ZrO2)、氧化铝(Al2O3)、氧化镧(La2O3)、氧化钛(TiO2)、氧化铱(Y2O3)、以及氮化硅(Si3N4)等。
本发明实施例提供的隧穿场效应晶体管，在不受栅电压调控的漏区102附近的沟道区域位置处设置有高介电常数的隔离墙1062，故可在处于双极导 电情况下，削弱载流子的隧穿，并在器件处于工作状态(开态)情况下，使得高介电常数隔离墙1062覆盖的沟道区域，由于边缘场效应的掺杂作用，势垒被削弱，提升了漏区102抽取载流子的效率，进而提高隧穿场效应晶体管的电流驱动能力。
本发明实施例以下将结合实际应用对本发明实施例涉及的隧穿场效应晶体管的具体结构进行说明。
本发明实施例中，所述隔离墙可以设置于绝缘层上，以减少应力作用。当然，本发明实施例并不限定隔离墙一定要设置于绝缘层上，也可以设置在衬底上。
本发明实施例中为节省工艺，可将所述隔离墙设置在栅介质层105之上。本发明实施例中所述栅介质层105覆盖所述沟道全部区域、以及所述源区101和所述漏区102靠近所述沟道104一侧的部分区域，且所述栅介质层105靠近所述源区101和所述漏区102一侧的部分区域存在未被所述栅导电层103覆盖的区域，所述隔离墙可设置在所述栅介质层105未被所述栅导电层103所覆盖的区域。
图3所示为本发明实施例提供的隧穿场效应晶体管的另一种结构示意图，如图3所示，所述隔离墙包括设置于所述源区101一侧的所述低介电常数隔离墙1061和设置于所述漏区102一侧的所述高介电常数隔离墙1062。设置于所述源区101一侧的所述低介电常数隔离墙1061覆盖所述栅介质层105靠近所述源区101一侧未被所述栅导电层103所覆盖的所述部分区域的全部区域。设置于所述漏区102一侧的所述高介电常数隔离墙1062覆盖所述栅介质层105靠近所述漏区102一侧未被所述栅导电层103所覆盖的所述部分区域的全部区域，换言之，图3所示结构中，在漏区102一侧设置高介电常数隔离墙，未设置低介电常数的隔离墙。
图4所示为本发明实施例提供的隧穿场效应晶体管的又一种结构示意图，如图4所示，所述隔离墙包括设置于所述源区101一侧的所述低介电常数隔离墙1061和设置于所述漏区102一侧的所述高介电常数隔离墙1062，还包括 设置于所述漏区102一侧的低介电常数隔离墙1063，所述设置于所述漏区102一侧的低介电常数隔离墙1063，设置于所述高介电常数隔离墙1062远离所述栅区的一侧，并覆盖所述高介电常数隔离1062墙远离所述栅区一侧的侧表面。
所述栅介质层105靠近所述漏区102一侧未被所述栅导电层103所覆盖的所述部分区域包括第一部分区域和第二部分区域，换言之，所述第一部分区域和所述第二部分区域组成所述栅介质层靠近所述漏区一侧未被所述栅导电层所覆盖的所述部分区域的全部区域。
如图4所示，本发明实施例中，设置于所述源区101一侧的所述低介电常数隔离墙1061覆盖所述栅介质层105靠近所述源区101一侧未被所述栅导电层103所覆盖的所述部分区域的全部区域。设置于所述漏区102一侧的所述高介电常数隔离墙1062覆盖所述栅介质层105靠近所述漏区102一侧未被所述栅导电层103所覆盖的所述部分区域的第一部分区域；设置于所述漏区一侧的低介电常数隔离墙1063覆盖所述栅介质层靠近所述漏区一侧未被所述栅导电层所覆盖的所述部分区域的第二部分区域。
需要说明的是，本发明实施例中并不限定所述设置于所述源区101一侧的所述低介电常数隔离墙1061、设置于所述漏区102一侧的所述高介电常数隔离墙1062和设置于所述漏区102一侧的低介电常数隔离墙1063，必须设置于栅介质层之上，图4仅是进行示意性说明。
本发明实施例中，在漏区一侧设置高介电常数隔离墙和低介电常数隔离墙，可以增大栅区与漏区的距离，进而可在制作过程中，避免执行快速退火工艺时漏区的杂质离子扩散至栅区下面。另外，工艺制作过程中也不需要额外的光刻和刻蚀工艺移除漏区一侧的低介电常数隔离墙，简化制作工艺。
基于上述实施例提供的隧穿场效应晶体管，本发明实施例还提供一种隧穿场效应晶体管的制作方法。
图5所示为本发明实施例提供的隧穿场效应晶体管制作方法的流程图，如图5所示，所述方法包括：
S101：提供半导体衬底107，如图6A所示。
本发明实施例中所述半导体衬底107具体可以由体硅、绝缘体上的硅、锗、锗硅或者III-V族化合物等半导体材料制成。
S102：在所述半导体衬底107上依次沉积栅介质层105和栅导电层103，如图6B所示。
本发明实施例中所述栅介质层105的材料可以是二氧化硅等具有低介电常数的绝缘材料，也可以氧化铪和氧化铝等高介电常数绝缘材料。所述栅导电层103的材料可以是多晶硅、金属、金属氮化物等导电性能良好的导电材料。
S103：对所述栅导电层103进行光刻和刻蚀，定义栅导电层103的形状和位置，形成所需的栅导电层103，如图6C所示。
S104：形成覆盖所述栅导电层103一侧侧表面的高介电常数隔离墙1062，如图6D所示。
本发明实施例中，可在图6C所示结构基础上沉积高介电常数介质材料，其中，所述高介电常数介质材料是相对介电常数大于3.9的绝缘材料，例如氧化锌(ZnO)、氧化钽(Ta2O5)、氧化铪(HfO2)、氧化锆(ZrO2)、氧化铝(Al2O3)、氧化镧(La2O3)、氧化钛(TiO2)、氧化铱(Y2O3)、以及氮化硅(Si3N4)等。
本发明实施例中可利用各向异性刻蚀技术，对所述高介电常数介质层进行刻蚀，形成覆盖栅导电层103两侧侧表面的高介电常数隔离墙1062。本发明实施例中，可移除其中一侧的高介电常数隔离墙1062，形成覆盖所述栅导电层103一侧侧表面的高介电常数隔离墙1062。
本发明实施例中，所述高介电常数隔离墙1062的宽度为几纳米至几十纳米，例如所述高介电常数隔离墙1062的宽度大于等于2纳米，并小于等于15纳米。
S105：在所述栅导电层103未设置高介电常数隔离墙1062的一侧形成源区101，所述源区101部分区域被所述栅导电层103覆盖。
本发明实施例中，可在漏区102一侧设置光刻胶108，利用光刻技术保护 待形成漏区102的区域，并进行第一掺杂类型离子的离子注入，形成第一掺杂类型的源区101。本发明实施例中可采用竖直注入方式注入第一掺杂类型离子，在源区101表面形成重掺杂区域，如图6E所示。
S106：移除S105中的光刻胶，并沉积低介电常数介质材料，并利用各向异性的刻蚀技术形成低介电常数隔离墙1061和低介电常数1062。
本发明实施例中所述低介电常数介质材料可以是氮化硅和二氧化硅等绝缘材料。
本发明实施例中所述低介电常数隔离墙包括设置于源区101一侧的低介电常数隔离墙1061以及设置于高介电常数隔离墙1062一侧的低介电常数隔离墙1063，如图6F所示。当然，也可移除高介电常数隔离墙1062一侧的低介电常数隔离墙1063，本发明实施例不作限定。
S107：采用倾角注入方式对所述源区101进行离子注入，如图6G所示。
本发明实施例中，可在漏区102一侧设置光刻胶108，以采用光刻技术保护漏区102，对所述源区101再次进行离子注入，此次进行离子注入，掺杂类型与S105中形成源区101时的掺杂类型相同，不同之处仅在于此次进行离子注入采用倾角注入方式，注入能量高于S105中的注入能量，注入剂量也高于S105中的注入剂量。
本发明实施例中采用倾角注入方式对所述源区101再次进行离子注入，以在栅区下方形成利于产生BTBT的杂质分布，进而提升隧穿电流。
需要说明的是，S107步骤为可选步骤。
S108：在设置高介电常数隔离墙1062的一侧形成漏区102，所述漏区102部分区域被所述高介电常数隔离墙1062覆盖。
本发明实施例中可移除S107中设置的光刻胶108，并在源区101一侧设置光刻胶，利用光刻技术保护源区101，并在设置高介电常数隔离墙1062的一侧进行第二掺杂类型离子的离子注入，本发明实施例中第二掺杂类型离子注入时采用竖直注入方式，如图6H所示。
本发明实施例中，在所述源区101和所述漏区102之间形成沟道，所述 沟道靠近所述源区101一侧的部分区域被所述栅导电层103所覆盖，所述沟道靠近漏区102一侧的部分区域未被所述栅导电层103所覆盖但被所述高介电常数隔离墙1062所覆盖。
S109：采用各向异性刻蚀技术对所述栅介质层105进行刻蚀得到所需的栅介质层105。
本发明实施例中，可以所述栅导电层103为自对准模板，仅保留栅导电层103覆盖区域的栅介质层105，形成图2所示的隧穿场效应晶体管中栅介质层105的图形。本发明实施例中也可以所述栅导电层103、所述高介电常数隔离墙1062和所述低介电常数隔离墙为自对准模板，保留栅导电层103、所述高介电常数隔离墙1062和所述低介电常数隔离墙覆盖区域的栅介质层105，形成图3和图4所示隧穿场效应晶体管中栅介质层105的图形。
本发明实施例中形成所需图形的栅介质层105后，可沉积低介电常数的绝缘材料110，并在曝光后，利用光刻技术和刻蚀技术形成金属电极窗口，并形成对应的金属电极109，如图6I所示。
需要说明的是，本发明实施例中所述低介电常数隔离墙是指材料的相对介电常数小于3.9的隔离墙。所述高介电常数隔离墙是指材料的相对介电常数大于3.9的隔离墙。
进一步需要说明的是，本发明上述实施例以及附图中所涉及的隧穿场效应晶体管的具体结构仅是进行示意性说明，并不引以为限，其它在短栅结构的隧穿场效应晶体管漏区一侧设置高介电常数隔离墙形成的具有非对称隔离墙的隧穿场效应晶体管的结构也在本发明所保护的范围内，例如图7所示的隧穿场效应晶体管。图7中，隧穿场效应晶体管具有竖直结构，即源区、沟道和漏区位于竖直方向。具有竖直结构的隧穿场效应晶体管可以是纳米线，类FinFET器件等。
以上所述，仅为本发明较佳的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到的变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明 的保护范围应该以权利要求的保护范围为准。

Claims (11)

  1. 一种隧穿场效应晶体管，其特征在于，包括源区、漏区、沟道、栅区和隔离墙，其中：
    所述源区和所述漏区设置于所述沟道两侧；
    所述沟道靠近漏区一侧的部分区域未被所述栅区覆盖；
    所述隔离墙包括设置于所述源区一侧的低介电常数隔离墙和设置于所述漏区一侧的高介电常数隔离墙；
    所述低介电常数隔离墙，覆盖所述源区靠近所述沟道一侧的部分区域以及覆盖所述栅区靠近所述源区一侧的侧表面；
    所述高介电常数隔离墙，覆盖所述沟道靠近所述漏区一侧未被所述栅区覆盖的区域，并覆盖所述漏区靠近所述沟道一侧的部分区域以及覆盖所述栅区靠近所述漏区一侧的侧表面。
  2. 如权利要求1所述的隧穿场效应晶体管，其特征在于，所述隔离墙还包括设置于所述漏区一侧的低介电常数隔离墙；
    所述设置于所述漏区一侧的低介电常数隔离墙，设置于所述高介电常数隔离墙远离所述栅区的一侧，并覆盖所述高介电常数隔离墙远离所述栅区一侧的侧表面。
  3. 如权利要求1所述的隧穿场效应晶体管，其特征在于，所述栅区包括栅导电层和栅介质层；
    所述栅介质层覆盖所述沟道全部区域、以及所述源区和所述漏区靠近所述沟道一侧的部分区域；
    所述栅介质层靠近所述漏区一侧的部分区域未被所述栅导电层所覆盖；
    所述高介电常数隔离墙覆盖所述栅介质层靠近所述漏区一侧未被所述栅导电层所覆盖的所述部分区域的全部区域。
  4. 如权利要求2所述的隧穿场效应晶体管，其特征在于，所述栅区包括栅导电层和栅介质层；
    所述栅介质层覆盖所述沟道全部区域、以及所述源区和所述漏区靠近所述沟道一侧的部分区域；
    所述栅介质层靠近所述漏区一侧的部分区域未被所述栅导电层所覆盖；
    所述高介电常数隔离墙覆盖所述栅介质层靠近所述漏区一侧未被所述栅导电层所覆盖的所述部分区域的第一部分区域；
    所述设置于所述漏区一侧的低介电常数的隔离墙覆盖所述栅介质层靠近所述漏区一侧未被所述栅导电层所覆盖的所述部分区域的第二部分区域；
    所述第一部分区域和所述第二部分区域组成所述栅介质层靠近所述漏区一侧未被所述栅导电层所覆盖的所述部分区域的全部区域。
  5. 如权利要求1至4任一项所述的隧穿场效应晶体管，其特征在于，所述高介电常数隔离墙材料的相对介电常数大于3.9。
  6. 如权利要求1至5任一项所述的隧穿场效应晶体管，其特征在于，所述高介电常数隔离墙的宽度大于等于2纳米，并小于等于15纳米。
  7. 一种隧穿场效应晶体管的制作方法，其特征在于，所述方法包括：
    提供半导体衬底；
    在所述半导体衬底上依次沉积栅介质层和栅导电层；
    对所述栅导电层进行光刻和刻蚀，形成所需的栅导电层；
    形成覆盖所述栅导电层一侧侧表面的高介电常数隔离墙；
    在所述源区一侧，形成低介电常数隔离墙；
    在所述栅导电层未设置高介电常数隔离墙的一侧形成源区，所述源区部分区域被所述栅导电层所覆盖；
    在所述栅导电层设置高介电常数隔离墙的一侧形成漏区，所述漏区部分区域被所述高介电常数隔离墙覆盖；
    在所述源区和所述漏区之间形成沟道，所述沟道靠近所述源区一侧的部分区域被所述栅导电层所覆盖，所述沟道靠近漏区一侧的部分区域未被所述栅导电层所覆盖但被所述高介电常数隔离墙所覆盖；
    对所述栅介质层进行光刻和刻蚀，形成所需的栅介质层。
  8. 如权利要求7所述的方法，其特征在于，在所述栅导电层未设置高介电常数隔离墙的一侧形成源区之后，所述方法还包括：
    采用倾角注入方式对所述源区进行离子注入。
  9. 如权利要求7或8所述的方法，其特征在于，形成覆盖所述栅导电层一侧的侧表面的高介电常数隔离墙之后，所述方法还包括：
    在所述高介电常数隔离墙远离所述栅导电层的一侧，形成覆盖所述高介电常数隔离墙远离所述栅导电层一侧的侧表面的低介电常数隔离墙。
  10. 如权利要求7至9任一项所述的方法，其特征在于，所述高介电常数隔离墙材料的相对介电常数大于3.9。
  11. 如权利要求7至10任一项所述的方法，其特征在于，所述高介电常数隔离墙的宽度大于等于2纳米，并小于等于15纳米。
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CN112840448A (zh) * 2018-09-24 2021-05-25 麻省理工学院 通过工程化原子层沉积对碳纳米管的可调掺杂
CN111564498A (zh) * 2020-05-13 2020-08-21 北京大学 一种隧穿晶体管的漏端负交叠区自对准制备方法

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