WO2017079928A1 - 隧穿场效应晶体管及其制备方法 - Google Patents

隧穿场效应晶体管及其制备方法 Download PDF

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Publication number
WO2017079928A1
WO2017079928A1 PCT/CN2015/094352 CN2015094352W WO2017079928A1 WO 2017079928 A1 WO2017079928 A1 WO 2017079928A1 CN 2015094352 W CN2015094352 W CN 2015094352W WO 2017079928 A1 WO2017079928 A1 WO 2017079928A1
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region
dielectric layer
gate dielectric
gate
layer
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PCT/CN2015/094352
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English (en)
French (fr)
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杨喜超
张臣雄
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华为技术有限公司
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Priority to PCT/CN2015/094352 priority Critical patent/WO2017079928A1/zh
Priority to CN201580084538.8A priority patent/CN108352401A/zh
Publication of WO2017079928A1 publication Critical patent/WO2017079928A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors

Definitions

  • the present invention relates to the field of semiconductor technologies, and in particular, to a tunneling field effect transistor and a method of fabricating the same.
  • the key to reducing power consumption is to reduce the supply voltage of the transistor.
  • the core constraint to reduce the supply voltage is the subthreshold swing of the transistor, which is the sharpness of the transistor transition from the off state to the on state.
  • the steep sub-threshold transition allows for a greater reduction in supply voltage, resulting in a significant reduction in transistor power consumption.
  • TFET Tort Field-Effect Transistor
  • FIG. 1 it shows a schematic structural view of a prior art TFET.
  • a prior art TFET includes a heavily doped source region, a drain region, a channel region, a lightly doped pocket layer, a gate dielectric layer, and a gate region.
  • 101 denotes a source region
  • 102 denotes a channel region
  • 103 denotes a drain region
  • 104 denotes a pocket layer
  • 105 denotes a gate dielectric layer
  • 106 denotes a gate region.
  • the pocket layer overlaps with a partial region of the source region and a partial region of the channel region.
  • the pocket layer portion directly above the source region and the source region constitutes a first tunneling junction.
  • the tunneling direction is parallel to the gate electric field and is tunneled. Therefore, the tunneling junction is a wire tunneling junction.
  • a second tunneling junction is also formed between the corner of the source region and the pocket layer.
  • the stream will also tunnel, as indicated by the dashed arrow in Figure 1.
  • the tunneling direction of the tunneling mode intersects the gate electric field and is point tunneling. Therefore, the tunneling junction is a point tunneling junction.
  • the turn-on voltage of the point tunneling junction is smaller than the turn-on voltage of the line tunneling junction, the point tunneling junction is opened before the line tunneling junction, which causes the TFET subthreshold swing to degrade, which makes the TFET turn on slowly and weaken.
  • the ability of the TFET to reduce the operating voltage results in degradation of the device's power consumption. Therefore, the structure in Figure 1 makes the power consumption of the TFET relatively large.
  • embodiments of the present invention provide a TFET and a method of fabricating the same.
  • the technical solution is as follows:
  • a TFET including a source region, a drain region, a channel region, a pocket layer, a gate dielectric layer, and a gate region, wherein:
  • the source region and the drain region are separately disposed inside a semiconductor substrate, and the channel region connects the source region and the drain region;
  • the pocket layer is disposed on an upper surface of the source region and the channel region, the gate dielectric layer is disposed on an upper surface of the pocket layer, and the gate region is disposed on an upper surface of the gate dielectric layer.
  • the gate dielectric layer includes a first region and a second region, the first region is a gate dielectric layer region above the source region, and the second region is a gate dielectric layer region above the channel region The gate capacitance of the first region is greater than the gate capacitance of the second region;
  • the pocket layer and the source region constitute a tunneling junction of the tunneling field effect transistor.
  • the gate dielectric layer is composed of a first gate dielectric layer and a second gate dielectric layer; the first gate dielectric layer completely covers the pocket An upper surface of the layer, the second gate dielectric layer covering a first designated region of an upper surface of the first gate dielectric layer, wherein the first designated region is located in the upper surface of the first gate dielectric layer The area above the area;
  • the material of the first gate dielectric layer is a high dielectric material
  • the material of the second gate dielectric layer is a low dielectric material
  • the high dielectric material refers to a relative dielectric constant greater than that of silicon dioxide.
  • a dielectric constant dielectric material, the low dielectric material being a dielectric material having a relative dielectric constant that is less than the relative dielectric constant of the silicon dioxide.
  • the gate dielectric layer is composed of a third gate dielectric layer and a fourth gate dielectric layer; the third gate dielectric layer covers the pocket layer a second designated area of the upper surface, the second designated area being a region of the upper surface of the pocket layer above the channel region; the fourth gate dielectric layer completely covering the third gate dielectric layer a third designated area of the surface and the upper surface of the pocket layer, the third designated area being an area of the upper surface of the pocket layer except the second designated area;
  • the material of the third gate dielectric layer is a low dielectric material
  • the material of the fourth gate dielectric layer For a high dielectric material, the low dielectric material refers to a dielectric material having a relative dielectric constant smaller than the relative dielectric constant of silicon dioxide, and the high dielectric material refers to a relative dielectric constant greater than that of silicon dioxide. Dielectric material of dielectric constant.
  • the thickness of the first region is smaller than the thickness of the second region, and the materials of the first region and the second region are The same high dielectric material;
  • the high dielectric material refers to a dielectric material having a relative dielectric constant greater than a relative dielectric constant of silicon dioxide.
  • the gate dielectric layer is composed of a fifth gate dielectric layer and a sixth gate dielectric layer; the fifth gate dielectric layer completely covers the pocket An upper surface of the layer, the sixth gate dielectric layer completely covering an upper surface of the fifth gate dielectric layer, and the sixth gate dielectric layer includes a third region and a fourth region, the third region being located at a sixth gate dielectric layer region above the source region, the fourth region being a sixth gate dielectric layer region above the channel region;
  • the material of the fifth gate dielectric layer and the material of the third region are high dielectric materials
  • the material of the fourth region is a low dielectric material
  • the high dielectric material refers to a relative dielectric constant
  • a partition wall is prepared on the pocket layer, the gate dielectric layer and the gate region;
  • a metal source electrode, a metal gate electrode and a metal drain electrode are respectively prepared at the specified positions of the source region, the gate region and the drain region, and the isolation wall is used for isolating the metal source electrode and the metal gate An electrode and the metal drain electrode.
  • the material of the semiconductor substrate is one of bulk silicon, silicon on insulator, germanium silicon, germanium, and III-V compound semiconductor;
  • the material of the pocket layer is one of silicon, germanium silicon, germanium, and a group III-V compound semiconductor;
  • the material of the gate region is one of polysilicon, metal, and a multilayer composite structure of polysilicon and metal.
  • a method of preparing a TFET comprising:
  • a well implant is implanted on the predetermined substrate to obtain the tunneling a type-matched semiconductor substrate of a field effect transistor
  • the gate dielectric layer including a first region and a second region, the first region being a gate dielectric layer region above the source region, the second region a gate dielectric layer region above the channel region, a gate capacitance of the first region being greater than a gate capacitance of the second region;
  • a gate region is prepared on an upper surface of the gate dielectric layer.
  • the separately preparing the source and drain regions inside the semiconductor substrate comprises:
  • a rapid annealing process is performed on the structure in which ion implantation is completed, and source and drain regions are generated.
  • the lithography is used to protect a predetermined drain region in the semiconductor substrate, the semiconductor Before the first ion implantation in the predetermined source region in the substrate, the method further includes:
  • a protective layer on the semiconductor substrate Preparing a protective layer on the semiconductor substrate, the protective layer for protecting the semiconductor substrate during ion implantation of the predetermined source region and the predetermined drain region;
  • a sacrificial layer of a prescribed shape is prepared on the protective layer, the sacrificial layer being used to form the channel region in a self-aligned manner when ion implantation is performed on the predetermined source region and the predetermined drain region.
  • the preparing the gate dielectric layer on the upper surface of the pocket layer comprises:
  • a first gate dielectric layer on a surface of the pocket layer using a high dielectric material, the high dielectric material being a dielectric material having a relative dielectric constant greater than a relative dielectric constant of silicon dioxide;
  • the low dielectric material refers to a dielectric material having a relative dielectric constant smaller than a relative dielectric constant of silicon dioxide
  • the gate dielectric layer is composed of the first gate dielectric layer and the second gate dielectric layer.
  • the preparing a gate dielectric layer on an upper surface of the pocket layer includes:
  • a low dielectric material refers to a dielectric material having a relative dielectric constant that is less than a relative dielectric constant of silicon dioxide;
  • a fourth gate dielectric layer on the upper surface of the third gate dielectric layer and a third designated region of the upper surface of the pocket layer using a high dielectric material, the third designated region being the upper surface of the pocket layer a region outside the second designated region, the high dielectric material being a dielectric material having a relative dielectric constant greater than a relative dielectric constant of silicon dioxide;
  • the gate dielectric layer is composed of the third gate dielectric layer and the fourth gate dielectric layer.
  • the preparing the gate dielectric layer on the upper surface of the pocket layer comprises:
  • the preparing the gate dielectric layer on the upper surface of the pocket layer comprises:
  • the sixth gate dielectric layer Depositing a third region of the sixth gate dielectric layer in a fifth designated region of the upper surface of the fifth gate dielectric layer using a high dielectric material, using a sixth designation of a low dielectric material on the upper surface of the fifth gate dielectric layer Depositing a fourth region of the sixth gate dielectric layer, wherein the fifth designated region is a region above the source region of the upper surface of the fifth gate dielectric layer, and the sixth designated region is the fifth gate region a region of the upper surface of the dielectric layer above the channel region, the high dielectric material being a dielectric material having a relative dielectric constant greater than a relative dielectric constant of silicon dioxide, the low dielectric material being a relative dielectric a dielectric material having a dielectric constant less than a relative dielectric constant of silicon dioxide;
  • the gate dielectric layer is composed of the fifth gate dielectric layer and the sixth gate dielectric layer.
  • the method further includes:
  • the gate voltage is more capable of regulating the tunneling junction than the point tunneling under the same gate voltage.
  • the ability to regulate the knot. Therefore, the turn-on voltage required for the point tunneling junction is relatively increased, so that the opening of the point tunneling junction can be delayed or delayed, thereby ensuring that the line tunneling can dominate the opening of the entire device, ensuring that the TFEF has a steep subthreshold characteristic, The power consumption of the TFET is reduced.
  • FIG. 1 is a schematic structural view of a TFET in the prior art
  • FIG. 2 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • FIG. 6 is a flow chart of a method for fabricating a TFET according to another embodiment of the present invention.
  • FIG. 7 is a flow chart of a method for fabricating a TFET according to another embodiment of the present invention.
  • FIG. 8 is a schematic diagram of a semiconductor substrate according to another embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a protective layer and a sacrificial layer according to another embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a source region and a drain region according to another embodiment of the present invention.
  • FIG. 11 is a schematic diagram of an initial pocket layer, an initial first gate dielectric layer, and an initial second gate dielectric layer according to another embodiment of the present invention.
  • FIG. 12 is a schematic diagram of an initial second gate dielectric layer after etching according to another embodiment of the present invention.
  • FIG. 13 is a schematic diagram of an initial pocket layer, an initial first gate dielectric layer, an etched initial second gate dielectric layer, and an initial gate region according to another embodiment of the present invention
  • FIG. 14 is a schematic diagram of a partition wall according to another embodiment of the present invention.
  • FIG. 15 is a flowchart of a method for fabricating a TFET according to another embodiment of the present invention.
  • FIG. 16 is a flowchart of a method for fabricating a TFET according to another embodiment of the present invention.
  • FIG. 17 is a flow chart of a method for fabricating a TFET according to another embodiment of the present invention.
  • Embodiments of the present invention provide a TFET including a source region, a drain region, a channel region, a pocket layer, a gate dielectric layer, and a gate region, wherein:
  • the source region and the drain region are separately disposed inside the semiconductor substrate, and the channel region is connected to the source region and the drain region; the pocket layer is disposed on the upper surface of the source region and the channel region, and the gate dielectric layer is disposed on the upper surface of the pocket layer.
  • the gate region is disposed on an upper surface of the gate dielectric layer.
  • the thickness of the pocket layer, the gate dielectric layer and the gate region are not specifically limited in the embodiment of the present invention, and the thickness of the pocket layer, the gate dielectric layer and the gate region may be the same or different. In an alternative embodiment, the thickness of the pocket layer, the gate dielectric layer, and the gate region may each be set to any one of 1 nanometer to 5 nanometers.
  • the gate dielectric layer includes a first region and a second region, the first region is a gate dielectric layer region above the source region, and the second region is a gate dielectric layer region above the channel region, and the gate capacitance of the first region is greater than The gate capacitance of the second region.
  • the gate voltage tunnels through the junction of the first region control line and tunnels through the junction at the second region control point.
  • the gate capacitance refers to the capacitance of the surface of the gate dielectric layer when the capacitance is formed by the gate region, the gate dielectric layer, and the source and drain regions.
  • the pocket layer covers at least a portion of the source region and a portion of the channel region. Wherein, the doping concentration of the pocket layer is smaller than the doping concentration of the source region.
  • the pocket layer and the source region form a tunneling junction of the tunneling field effect transistor.
  • the gate region is used to determine the turn-on and turn-off of the TFET. When the gate voltage of the TFET is less than the threshold voltage, the TFET is turned off; when the gate voltage of the TFET is greater than the threshold voltage, the TFET is turned on. Under the action of the gate electric field, carriers in the pocket layer accumulate, eventually forming a tunneling junction with the source region, and carriers in the source region tunnel to the pocket layer to form an electric current.
  • the material of the semiconductor substrate may be one of bulk silicon, silicon-on-insulator (SOI), germanium silicon, germanium, and a group III-V compound semiconductor.
  • the material of the pocket layer may be one of silicon, germanium silicon, germanium, and a group III-V compound semiconductor.
  • the material of the gate area can be It is considered to be one of polysilicon, metal and multilayer composite structure of polysilicon and metal.
  • the materials of the semiconductor substrate and the pocket layer may be the same or different.
  • the channel region is a conductive path for carriers from the source region to the drain region. Since the channel region is a partial region inside the semiconductor substrate, the material of the channel region is the same as that of the semiconductor substrate.
  • the material and/or composition of the gate dielectric layer in the first region and the second region may be controlled.
  • the structure meets certain conditions to be realized.
  • the material and structure of the gate dielectric layer will be elaborated in the following various embodiments, and will not be described herein.
  • the content of the TFET according to the embodiment of the present invention is applicable to the following embodiments, and the same content will not be further described in the following embodiments.
  • the gate capacitance of the gate dielectric layer located above the source region is larger than the gate capacitance of the gate dielectric layer located above the channel region, so that the gate voltage is tunneled to the junction under the same gate voltage.
  • the regulation ability is stronger than the regulation ability of the point tunneling junction. Therefore, the turn-on voltage required for the point tunneling junction is relatively increased, so that the opening of the point tunneling junction can be delayed or delayed, thereby ensuring that the line tunneling can dominate the entire device. Turning on ensures that the TFEF has a steep subthreshold characteristic, which reduces the power consumption of the TFET.
  • FIG. 2 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • the corresponding embodiment of FIG. 2 controls the gate capacitance of the first region of the gate dielectric layer to be larger than the gate capacitance of the second region of the gate dielectric layer by controlling the composition and material of the gate dielectric layer.
  • the source region 201 and the drain region 203 are separately disposed inside the semiconductor substrate 200; the channel region 202 is connected to the source region 201 and the drain region 203.
  • the pocket layer 204 is disposed on a partial region of the upper surface of the semiconductor substrate 200, and the pocket layer 204 covers at least a portion of the source region 201 and a portion of the channel region 202.
  • the pocket layer 204 can be out of contact with the drain region 203.
  • the absence of contact of the pocket layer 204 with the drain region 203 reduces the likelihood of leakage of the TFET, thereby improving the performance of the TFET.
  • the gate dielectric layer 205 is disposed over the pocket layer 204, and the gate dielectric layer 205 is composed of a first gate dielectric layer 205.1 and a second gate dielectric layer 205.2.
  • the first gate dielectric layer 205.1 completely covers the upper surface of the pocket layer 204, and the second gate dielectric layer 205.2 covers the first designated region of the upper surface of the first gate dielectric layer 205.1.
  • the first designated region is the first gate dielectric layer 205.1.
  • the first region of the gate dielectric layer 205 is the first gate dielectric
  • the layer 205.1 is located above the source region 201
  • the second region of the gate dielectric layer 205 is a region of the first gate dielectric layer 205.1 above the channel region 202 and a second gate dielectric layer 205.2.
  • the gate dielectric layer corresponding to the region labeled "one" is the first region of the gate dielectric layer 205
  • the gate dielectric layer corresponding to the region labeled "two” is the second region of the gate dielectric layer 205.
  • the relative dielectric constant of the material of the first gate dielectric layer 205.1 is greater than the relative dielectric constant of the material of the second gate dielectric layer 205.2.
  • the material of the first gate dielectric layer 205.1 may be a high dielectric material
  • the material of the second gate dielectric layer 205.2 may be a low dielectric material.
  • a high dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon dioxide
  • a low dielectric material refers to a dielectric material having a relative dielectric constant less than the relative dielectric constant of silicon dioxide.
  • the relative dielectric constant refers to the dielectric constant of the relative vacuum
  • the dielectric constant of the silica relative to the vacuum is 3.9.
  • the first region of the gate dielectric layer 205 is a region where the first gate dielectric layer 205.1 is located above the source region 201, and the second region is the first gate dielectric layer 205.1 at the channel region 202.
  • the upper region and the second gate dielectric layer 205.2 are such that the thickness of the gate dielectric layer 205 in the first region is significantly smaller than the thickness of the second region, and the gate capacitance of the gate dielectric layer 205 is inversely proportional to the thickness of the gate dielectric layer 205, thereby The gate capacitance of the gate dielectric layer 205 in the first region is greater than the gate capacitance of the second region.
  • the material of the first gate dielectric layer 205.1 is a high dielectric material
  • the material of the second gate dielectric layer 205.2 is a low dielectric material, so that the material of the first gate dielectric layer 205.1 is relatively
  • the dielectric constant is greater than the relative dielectric constant of the second gate dielectric layer 205.2 material, such that the average relative dielectric constant of the first region of the gate dielectric layer 205 is greater than the average relative dielectric constant of the second region, and the gate dielectric layer 205 is gated.
  • the capacitance is proportional to the relative dielectric constant of the gate dielectric layer 205 material such that the gate capacitance of the first region of the gate dielectric layer 205 is greater than the gate capacitance of the second region.
  • spacer wall 207 is formed on both sides of pocket layer 204, gate dielectric layer 205, and gate region 206.
  • the material of the partition wall 207 is an insulating material such as silicon nitride, and the shape of the partition wall 207 may be a sickle shape as shown in FIG. 2 or a rectangle or the like.
  • the periphery of the gate region 206 and the periphery of the spacer 207 may be filled with a low dielectric material 208 such as silicon nitride (Si 3 N 4 ) or the like.
  • a metal source electrode 209, a metal gate electrode 211, and a metal drain electrode 210 are respectively prepared at specified positions of the source region 201, the gate region 206, and the drain region 203.
  • the "designated position" described in this embodiment is a position for preparing the metal source electrode 209, the metal gate electrode 211, and the metal drain electrode 210 which are set in advance.
  • the designated position may be any position where the upper surface of the source region 201 is not covered by the partition wall 207, any position on the upper surface of the gate region 206, and the upper surface of the drain region 203 is not covered by the partition wall 207.
  • the partition wall 207 is an insulating material, it can be used for isolating the metal source electrode 209, the metal gate electrode 211 and the metal drain electrode 210, thereby avoiding a short circuit phenomenon.
  • the mechanical properties of the partition wall 207 are relatively good, and the shapes of the gate region 206, the pocket layer 204, and the gate dielectric layer 205 can be fixed.
  • the parasitic capacitance of the TFET can be prevented from being excessive.
  • the mechanical support of the metal source electrode 209, the metal gate electrode 211, and the metal drain electrode 210 can be achieved by the low dielectric material.
  • the first region of the gate dielectric layer is a region where the first gate dielectric layer is located above the source region
  • the second region is a region where the first gate dielectric layer is located above the channel region and the second gate dielectric.
  • the layer is such that the thickness of the gate dielectric layer in the first region is obviously smaller than the thickness of the second region, and the material of the second gate dielectric layer is a low dielectric material, and the material of the second gate dielectric layer is a low dielectric material.
  • the average relative dielectric constant of the first region of the gate dielectric layer is greater than the average relative dielectric constant of the second region, and the gate capacitance of the gate dielectric layer is inversely proportional to the thickness, and is proportional to the relative dielectric constant of the material, thereby making the gate dielectric
  • the gate capacitance of the first region of the layer is greater than the gate capacitance of the second region such that the gate capacitance of the gate dielectric layer above the source region is greater than the gate capacitance of the gate dielectric layer above the channel region, such that the gate voltage is at the same gate voltage.
  • the regulation ability of the tunnel tunneling junction is stronger than that of the point tunneling junction.
  • the opening voltage required for the point tunneling junction is relatively increased, so that the opening of the tunneling junction can be delayed or delayed. This ensures that the line tunneling can dominate the turn-on of the entire device, ensuring that the TFEF has a steep sub-threshold characteristic, which reduces the power consumption of the TFET.
  • FIG. 3 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • the corresponding embodiment of FIG. 3 controls the first region of the gate dielectric layer by controlling the composition and material of the gate dielectric layer.
  • the gate capacitance is greater than the gate capacitance of the second region of the gate dielectric layer.
  • the source region 301 and the drain region 303 are separately disposed inside the semiconductor substrate 300; the channel region 302 is connected to the source region 301 and the drain region 303.
  • the pocket layer 304 is disposed on a partial region of the upper surface of the semiconductor substrate 300, and the pocket layer 304 covers at least a portion of the source region 301 and a portion of the channel region 302, and the pocket layer 304 is not in contact with the drain region 303.
  • the absence of contact of the pocket layer 304 with the drain region 303 reduces the likelihood of TFET leakage, thereby improving the performance of the TFET.
  • the gate dielectric layer 305 is disposed over the pocket layer 304, and the gate dielectric layer 305 is composed of a third gate dielectric layer 305.3 and a fourth gate dielectric layer 305.4.
  • the third gate dielectric layer 305.3 covers a second designated area of the upper surface of the pocket layer 304, the second designated area It is the area above the channel region 302 in the upper surface of the pocket layer 304.
  • the fourth gate dielectric layer 305.4 completely covers the upper surface of the third gate dielectric layer 305.3 and the third designated region of the upper surface of the pocket layer 304, the third designated region being the region of the upper surface of the pocket layer 304 other than the second designated region.
  • the first region of the gate dielectric layer 305 is a region in which the fourth gate dielectric layer 305.4 is located above the source region 301, and the second region of the gate dielectric layer 305 is a third gate dielectric layer. 305.3 and the fourth gate dielectric layer 305.4 are located above the channel region 302.
  • the gate dielectric layer corresponding to the region labeled "one" is the first region of the gate dielectric layer 305
  • the gate dielectric layer corresponding to the region labeled "two” is the second region of the gate dielectric layer 305.
  • the relative dielectric constant of the material of the third gate dielectric layer 305.3 is smaller than the relative dielectric constant of the material of the fourth gate dielectric layer 305.4.
  • the material of the third gate dielectric layer 305.3 may be a low dielectric material
  • the material of the fourth gate dielectric layer 305.4 may be a high dielectric material.
  • the first region of the gate dielectric layer 305 is a region where the fourth gate dielectric layer 305.4 is located above the source region 301, and the second region of the gate dielectric layer 305 is the third gate dielectric layer 305.3.
  • the fourth gate dielectric layer 305.4 is located above the channel region 302 such that the thickness of the gate dielectric layer 305 in the first region is obviously smaller than the thickness of the second region, and the gate capacitance of the gate dielectric layer 305 and the thickness of the gate dielectric layer 305 In inverse proportion, such that the gate capacitance of the gate dielectric layer 305 in the first region is greater than the gate capacitance of the second region.
  • the material of the third gate dielectric layer 305.4 is a low dielectric material
  • the material of the fourth gate dielectric layer 305.4 is a high dielectric material, so that the third gate dielectric layer 305.3 has a relative material.
  • the dielectric constant is less than the relative dielectric constant of the fourth gate dielectric layer 305.4 material, such that the average relative dielectric constant of the first region of the gate dielectric layer 305 is greater than the average relative dielectric constant of the second region, and the gate dielectric layer 305 is gated.
  • the capacitance is proportional to the relative dielectric constant of the gate dielectric layer 305 material such that the gate capacitance of the first region of the gate dielectric layer 305 is greater than the gate capacitance of the second region.
  • spacer layer 307 is formed on both sides of pocket layer 304, gate dielectric layer 305, and gate region 306, and the periphery of gate region 306 and the periphery of isolation barrier 307 may be filled with a low dielectric material 308 ( A low dielectric material is not shown in FIG. 3), and a metal source electrode 309, a metal gate electrode 311, and a metal drain electrode 310 are respectively prepared at specified positions of the source region 301, the gate region 306, and the drain region 303 (not shown in FIG. 3). A metal source electrode 309, a metal gate electrode 311, and a metal drain electrode 310) are formed.
  • the TFET provided by the embodiment of the invention provides a fourth gate dielectric by setting a first region of the gate dielectric layer
  • the layer is located in a region above the source region
  • the second region of the gate dielectric layer is a region of the third gate dielectric layer and the fourth gate dielectric layer above the channel region, such that the thickness of the gate dielectric layer in the first region is obviously smaller than the second region
  • the thickness, and the material of the third gate dielectric layer is a low dielectric material
  • the material of the fourth gate dielectric layer is a high dielectric material, such that the average relative dielectric constant of the first region of the gate dielectric layer is greater than that of the second region
  • the average relative dielectric constant, and the gate capacitance of the gate dielectric layer is inversely proportional to the thickness, and proportional to the relative dielectric constant of the material, such that the gate capacitance of the first region of the gate dielectric layer is greater than the gate capacitance of the second region, so that The gate capacitance of the gate dielectric layer above
  • the turn-on voltage required for the point tunneling junction is relatively increased, so that the opening of the point tunneling junction can be delayed or delayed, thereby ensuring that the line tunneling can dominate the opening of the entire device, ensuring that the TFEF has a steep subthreshold characteristic, The power consumption of the TFET is reduced.
  • FIG. 4 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • the corresponding embodiment of FIG. 4 controls the first region of the gate dielectric layer by controlling the thickness of the gate dielectric layer in different regions.
  • the gate capacitance is greater than the gate capacitance of the second region of the gate dielectric layer.
  • the source region 401 and the drain region 403 are separately disposed inside the semiconductor substrate 400; the channel region 402 is connected to the source region 401 and the drain region 403.
  • the pocket layer 404 is disposed in a partial region of the upper surface of the semiconductor substrate 400, and the pocket layer 404 covers at least a portion of the source region 401 and a portion of the channel region 402, and the pocket layer 404 is not in contact with the drain region 403.
  • the absence of contact of the pocket layer 404 with the drain region 403 reduces the likelihood of TFET leakage, thereby improving the performance of the TFET.
  • the gate dielectric layer 405 is disposed on the pocket layer 404, and the thickness of the first region of the gate dielectric layer 305 is smaller than the thickness of the second region, and the first region and the second region are The material is the same high dielectric material.
  • the first area is a region above the source region 401, and the second region is a region above the channel region 402.
  • the gate dielectric layer corresponding to the region labeled "one" is the first region of the gate dielectric layer 405, and the gate dielectric layer corresponding to the region labeled "two” is the second region of the gate dielectric layer 405.
  • the gate capacitance of the gate dielectric layer 405 is inversely proportional to the thickness of the gate dielectric layer 405, thereby causing the gate dielectric
  • the gate capacitance of layer 305 in the first region is greater than the gate capacitance of the second region.
  • the barrier layer 40 is formed on both sides of the pocket layer 404, the gate dielectric layer 405, and the gate region 406, and the periphery of the gate region 406 and the periphery of the isolation barrier 407 may be filled with a low dielectric material.
  • 408 low dielectric material is not shown in FIG. 4
  • metal source electrode 409, metal gate electrode 411, and metal drain electrode 410 are respectively prepared at specified positions of source region 401, gate region 406, and drain region 403 (FIG. 4)
  • the metal source electrode 409, the metal gate electrode 411, and the metal drain electrode 410) are not shown.
  • the thickness of the first region of the gate dielectric layer is smaller than the thickness of the second region, and the gate capacitance of the gate dielectric layer is inversely proportional to the thickness, so that the gate capacitance of the first region of the gate dielectric layer is greater than
  • the gate capacitance of the second region is such that the gate voltage is more capable of regulating the tunnel tunneling junction than the point tunneling junction under the same gate voltage.
  • the turn-on voltage required for the point tunneling junction is relatively increased, so that the opening of the point tunneling junction can be delayed or delayed, thereby ensuring that the line tunneling can dominate the opening of the entire device, ensuring that the TFEF has a steep subthreshold characteristic, The power consumption of the TFET is reduced.
  • FIG. 5 is a schematic structural diagram of a TFET according to another embodiment of the present invention.
  • the corresponding embodiment of FIG. 5 controls the gate capacitance of the first region of the gate dielectric layer by controlling the constituent materials of the gate dielectric layer. Greater than the gate capacitance of the second region of the gate dielectric layer.
  • the source region 501 and the drain region 503 are separately disposed inside the semiconductor substrate 500; the channel region 502 is connected to the source region 501 and the drain region 503.
  • the pocket layer 504 is disposed in a partial region of the upper surface of the semiconductor substrate 500, and the pocket layer 504 covers at least a portion of the source region 501 and a portion of the channel region 502, and the pocket layer 504 is not in contact with the drain region 503.
  • the absence of contact of the pocket layer 504 with the drain region 503 reduces the likelihood of leakage of the TFET, thereby enabling improved performance of the TFET.
  • the gate dielectric layer 505 is disposed over the pocket layer 504, and the gate dielectric layer 505 is composed of a fifth gate dielectric layer 505.5 and a sixth gate dielectric layer 505.6.
  • the fifth gate dielectric layer 505.5 completely covers the upper surface of the pocket layer 504
  • the sixth gate dielectric layer 505.6 completely covers the upper surface of the fifth gate dielectric layer 505.5
  • the sixth gate dielectric layer 505.6 includes the third region and the fourth region.
  • the third region is a region in which the sixth gate dielectric layer 505.6 is located above the source region 501
  • the fourth region is a region in which the sixth gate dielectric layer 505.6 is located above the channel region 502.
  • the first region of the gate dielectric layer 505 is a region in which the fifth gate dielectric layer 505.5 is located above the source region 501 and a region in which the sixth gate dielectric layer 505.6 is located above the source region 501.
  • the second region of the gate dielectric layer 505 is a region in which the fifth gate dielectric 505.5 is located above the channel region 502 and a region in which the sixth gate dielectric layer 505.6 is located above the channel region 502.
  • the mark "one" The gate dielectric layer corresponding to the region is the first region of the gate dielectric layer 505, and the gate dielectric layer corresponding to the region labeled "two" is the second region of the gate dielectric layer 505.
  • the material density of the third gate dielectric layer 505.5 material and the sixth gate dielectric layer 505.6 third region material is greater than the relative dielectric constant of the fourth region of the sixth gate dielectric layer 505.6.
  • the material of the fifth gate dielectric layer 505.5 and the material of the third region of the sixth gate dielectric layer 505.6 are high dielectric materials, and the material of the fourth region of the sixth gate dielectric layer 505.6 is a low dielectric material.
  • the material of the fifth gate dielectric layer 505.5 and the material of the third region of the sixth gate dielectric layer 505.6 are a high dielectric material, and the material of the fourth region of the sixth gate dielectric layer 505.6.
  • the low dielectric material is such that the average relative dielectric constant of the first region of the gate dielectric layer 505 is greater than the average relative dielectric constant of the second region, and the gate dielectric of the gate dielectric layer 505 and the relative dielectric constant of the gate dielectric layer 505 material.
  • the gate capacitance of the first region of the gate dielectric layer 505 is greater than the gate capacitance of the second region.
  • spacer layer 507 is formed on both sides of pocket layer 504, gate dielectric layer 505, and gate region 506, and the periphery of gate region 506 and the periphery of isolation wall 507 may be filled with a low dielectric material 508 ( A low dielectric material is not shown in FIG. 5), and a metal source electrode 509, a metal gate electrode 511, and a metal drain electrode 510 are respectively prepared at specified positions of the source region 501, the gate region 506, and the drain region 503 (not shown in FIG. 5). A metal source electrode 509, a metal gate electrode 511, and a metal drain electrode 510) are formed.
  • the material of the fifth gate dielectric layer and the material of the third region of the sixth gate dielectric layer are made of a high dielectric material, and the material of the fourth region of the sixth gate dielectric layer is a low dielectric material.
  • the average relative dielectric constant of the first region of the gate dielectric layer is greater than the average relative dielectric constant of the second region, and the gate capacitance of the gate dielectric layer is proportional to the relative dielectric constant of the material, thereby causing the first region of the gate dielectric layer
  • the gate capacitance is greater than the gate capacitance of the second region such that the gate capacitance of the gate dielectric layer above the source region is greater than the gate capacitance of the gate dielectric layer above the channel region such that gate-to-line tunneling is performed at the same gate voltage
  • the regulation ability of the knot is stronger than that of the point tunneling junction.
  • the turn-on voltage required for the point tunneling junction is relatively increased, so that the opening of the point tunneling junction can be delayed or delayed, thereby ensuring that the line tunneling can dominate the opening of the entire device, ensuring that the TFEF has a steep subthreshold characteristic, The power consumption of the TFET is reduced.
  • FIG. 6 is a flow chart of a method for fabricating a TFET according to another embodiment of the present invention. As shown in FIG. 6, the method for fabricating a TFET according to an embodiment of the present invention includes:
  • the gate dielectric layer on an upper surface of the pocket layer, wherein the gate dielectric layer includes a first region and a second region, the first region is a gate dielectric layer region above the source region, and the second region is located above the channel region
  • the gate dielectric layer region has a gate capacitance of the first region greater than a gate capacitance of the second region.
  • the method for fabricating a TFET according to an embodiment of the present invention provides a gate capacitance to a line tunnel under the same gate voltage by setting a gate capacitance of a gate dielectric layer above a source region to be larger than a gate capacitance of a gate dielectric layer above the channel region.
  • the regulation ability of the junction is stronger than the regulation of the tunneling junction. Therefore, the opening voltage required for the point tunneling is relatively increased, so that the opening of the tunneling junction can be delayed or delayed, thereby ensuring that the tunneling can dominate.
  • the turn-on of the entire device ensures that the TFEF has a steep subthreshold characteristic, which reduces the power consumption of the TFET.
  • the source and drain regions are separately fabricated within the semiconductor substrate, including:
  • a rapid annealing process is performed on the structure in which ion implantation is completed, and source and drain regions are generated.
  • the lithography is used to protect the predetermined drain region in the semiconductor substrate.
  • the method further includes:
  • a protective layer on the semiconductor substrate Preparing a protective layer on the semiconductor substrate, wherein the protective layer is used to protect the semiconductor substrate during ion implantation on the predetermined source region and the predetermined drain region;
  • a sacrificial layer of a specified shape is prepared on the protective layer, wherein the sacrificial layer is used to form a channel region in a self-aligned manner when ion implantation is performed on the predetermined source region and the predetermined drain region.
  • the gate dielectric layer is prepared on the upper surface of the pocket layer, including:
  • a first gate dielectric layer on a surface of the pocket layer using a high dielectric material, wherein the high dielectric material refers to a dielectric material having a relative dielectric constant greater than a relative dielectric constant of the silicon dioxide;
  • An electrical material refers to a dielectric material having a relative dielectric constant that is less than the relative dielectric constant of silicon dioxide;
  • the gate dielectric layer is composed of a first gate dielectric layer and a second gate dielectric layer.
  • the gate dielectric layer is prepared on the upper surface of the pocket layer, including:
  • a third gate dielectric layer in a second designated region of the upper surface of the pocket layer using a low dielectric material wherein the second designated region is a region above the channel region in the upper surface of the pocket layer, and the low dielectric material refers to a relative dielectric layer a dielectric material having a lower electrical constant than the relative dielectric constant of silicon dioxide;
  • a high dielectric material refers to a dielectric material having a relative dielectric constant greater than the relative dielectric constant of silicon dioxide
  • the gate dielectric layer is composed of a third gate dielectric layer and a fourth gate dielectric layer.
  • the gate dielectric layer is prepared on the upper surface of the pocket layer, including:
  • the fourth designated region of the initial gate dielectric layer is thinned to obtain a gate dielectric layer, wherein the fourth designated region is a region of the initial gate dielectric layer above the source region.
  • the gate dielectric layer is prepared on the upper surface of the pocket layer, including:
  • a high dielectric material refers to a dielectric material having a relative dielectric constant greater than a relative dielectric constant of silicon dioxide
  • a low dielectric material refers to a dielectric material having a relative dielectric constant less than a relative dielectric constant of silicon dioxide
  • the gate dielectric layer is composed of a fifth gate dielectric layer and a sixth gate dielectric layer.
  • the method further includes:
  • a metal source electrode, a metal gate electrode and a metal drain electrode are respectively prepared at specified positions of the source region, the gate region and the drain region, and the isolation wall is used for isolating the metal source electrode, the metal gate electrode and the metal drain electrode.
  • the method for preparing the TFET includes the following steps:
  • the preset substrate is an intrinsic semiconductor.
  • the types of tunneling field effect transistors are different, the types of impurities implanted are different when well implanting a predetermined substrate.
  • the implanted doping type is a P-type impurity, such as B (boron) or Ga (gallium), etc., to obtain a P-type well, that is, a P-type.
  • Semiconductor substrate is an intrinsic semiconductor.
  • the implanted doping type is an N-type impurity, such as P (phosphorus) or As (arsenic), to obtain an N-type well, that is, an N-type semiconductor lining. bottom.
  • FIG. 8 a schematic diagram of a semiconductor substrate is shown.
  • the material of the semiconductor substrate has been described in the above embodiments.
  • the protective layer serves to protect the semiconductor substrate when the source and drain regions are formed by ion implantation in the semiconductor substrate.
  • the sacrificial layer is used to form a channel region in a self-aligned manner when the source region and the drain region are formed by ion implantation in a semiconductor substrate.
  • the specified shape may be a rectangle or the like.
  • ions implanted into the source and drain regions diffuse into the channel region, and the length of the sacrificial layer on the protective layer is greater than the length of the predetermined channel region.
  • the length of the sacrificial layer may be 250 nm or the like.
  • FIG. 9 a schematic view of a protective layer and a sacrificial layer is shown. Referring to FIG. 9, the corresponding semiconductor region under the sacrificial layer is the region where the predetermined channel region is located.
  • a protective layer can be formed on a semiconductor substrate by deposition growth
  • a sacrificial layer can be formed on the protective layer by photolithography and etching techniques, and the shape of the sacrificial layer can be defined.
  • the material of the protective layer may be dioxide For silicon or the like
  • the material of the sacrificial layer may be ⁇ silicon or the like.
  • this step is an optional step for protecting the semiconductor substrate during subsequent ion implantation in the semiconductor substrate.
  • the manner of protecting the semiconductor substrate is described by taking only the generation of the protective layer and the sacrificial layer as an example. However, in the specific implementation, other methods may be used.
  • the types of ions respectively implanted are related to the type of the TFET.
  • the ions implanted in the source region are P-type ions
  • the ions implanted in the drain region are N-type ions
  • the ions implanted in the source region are N-type.
  • the ions, ions implanted in the drain region are P-type ions.
  • FIG. 10 shows a schematic diagram of a source region and a drain region.
  • the left half doped region of the semiconductor substrate represents the source region
  • the right half doped region represents the drain region.
  • the pocket layer and the source region form a tunneling junction of the tunneling field effect transistor.
  • the principle of forming the tunneling junction between the pocket layer and the source region has been described in the above embodiments, and will not be described herein.
  • the material relating to the pocket layer has also been described in the above various embodiments, and will not be described again here.
  • the initial pocket layer is etched, and the obtained pocket layer covers at least part of the source region and a portion of the channel region.
  • the pocket layer is not in contact with the drain region to reduce the likelihood of TFET leakage, thereby improving the performance of the TFET.
  • first gate dielectric layer on the upper surface of the pocket layer using a high dielectric material, and deposit a second gate dielectric layer on the first designated region of the upper surface of the first gate dielectric layer using a low dielectric material, by the first gate dielectric layer And a second gate dielectric layer to form a gate dielectric layer.
  • the first gate dielectric layer completely covers the upper surface of the pocket layer, and the second gate dielectric layer covers the first designated region of the upper surface of the first gate dielectric layer, wherein the first designated region is the upper surface of the first gate dielectric layer is located in the channel The area above the area.
  • a first gate dielectric layer is deposited on the surface of the pocket layer using a high dielectric material
  • a second gate dielectric layer is deposited on the first designated region of the upper surface of the first gate dielectric layer using a low dielectric material, including but not It is limited to two ways:
  • the upper surface of the initial pocket layer prepared in step 704 is deposited using a high dielectric material
  • An initial first gate dielectric layer is deposited on the surface of the initial first gate dielectric layer using a low dielectric material.
  • FIG. 11 a schematic diagram of an initial pocket layer, an initial first gate dielectric layer, and an initial second gate dielectric layer is shown. As can be seen from Figure 11, the initial pocket layer completely covers the upper surface of the semiconductor substrate, the initial first gate dielectric layer completely covers the initial pocket layer, and the initial second gate dielectric layer completely covers the initial first gate dielectric layer.
  • the initial second gate dielectric layer is etched by photolithography and etching techniques to define the shape of the second gate dielectric layer, and the region of the upper surface of the initial second gate dielectric layer above the source region is etched away.
  • An etched initial second gate dielectric layer is obtained.
  • the edge of the etched initial second gate dielectric layer is aligned or slightly overlapped with the source region, and the overlap size may be between 1 nanometer and 5 nanometers.
  • FIG. 12 a schematic diagram of an etched initial second gate dielectric layer is shown.
  • the initial pocket layer, the initial first gate dielectric layer, and the initial second after etching according to the shape of the preset pocket layer, the shape of the preset first gate dielectric layer, and the shape of the preset second gate dielectric layer After further etching the gate dielectric layer, a pocket layer, a first gate dielectric layer, and a second gate dielectric layer are obtained.
  • the pocket layer prepared in step 705 is obtained by etching the initial pocket layer in this step, that is, step 705 only needs to prepare the initial pocket layer.
  • the second way depositing a first gate dielectric layer directly on the upper surface of the pocket layer using a high dielectric material, and depositing a second gate dielectric layer using a low dielectric material on a first designated region previously disposed on the first gate dielectric layer.
  • the etching process can be saved, thereby saving process flow.
  • this way corresponds to the first mode in step 705.
  • an initial gate region is prepared on the upper surface of the initial second gate dielectric layer after etching and the upper surface of the initial first gate dielectric layer covered by the unetched initial second gate dielectric layer.
  • FIG. 13 a schematic diagram of an initial pocket layer, an initial first gate dielectric layer, an etched initial second gate dielectric layer, and an initial gate region is shown.
  • the etched initial second gate dielectric layer and the initial gate region are etched to obtain a pocket layer, a first gate dielectric layer, a second gate dielectric layer, and a gate region, respectively.
  • the lithography and anisotropic etching techniques may be combined to form an initial The pocket layer, the initial first gate dielectric layer, the etched initial second gate dielectric layer, and the initial gate region are etched.
  • the pocket layer prepared in step 705 is obtained by etching the initial pocket layer in this step, that is, step 705 only needs to prepare the initial pocket layer.
  • the first gate dielectric layer and the second gate dielectric layer are also obtained by etching the initial first gate dielectric layer and the etched initial second gate dielectric layer in this step, that is, step 706 only needs to be prepared to the initial stage.
  • the first gate dielectric layer and the etched initial second gate dielectric layer may be used.
  • this method corresponds to the second mode in step 705.
  • a gate region is directly deposited on the upper surface of the gate dielectric layer, and the gate region completely covers the upper surface of the gate dielectric layer.
  • the material of the partition wall is an insulating material such as silicon nitride.
  • the isolation wall can be prepared on both sides of the pocket layer, the gate dielectric layer, and the gate region by an anisotropic etching technique.
  • the partition wall is used to isolate the subsequently prepared metal source electrode, metal gate electrode and metal drain electrode to avoid short circuit.
  • Figure 14 a schematic view of a barrier wall is shown.
  • the low dielectric material may be silicon dioxide or silicon nitride. By filling the low dielectric material, the parasitic capacitance of the TFET can be prevented from being relatively large. In addition, through the low dielectric material, it can provide good mechanical support for the metal source electrode, the metal gate electrode and the metal drain electrode.
  • a first region of the gate dielectric layer is a region where the first gate dielectric layer is located above the source region, and a second region is a region where the first gate dielectric layer is located above the channel region and
  • the second gate dielectric layer is such that the thickness of the gate dielectric layer in the first region is obviously smaller than the thickness of the second region, and the material of the first gate dielectric layer is a high dielectric material, and the material of the second gate dielectric layer is a low dielectric material
  • the material is such that the average relative dielectric constant of the first region of the gate dielectric layer is greater than the average relative dielectric constant of the second region, and the gate capacitance of the gate dielectric layer is inversely proportional to the thickness, and is proportional to the relative dielectric constant of the material, thereby
  • the gate capacitance of the first region of the gate dielectric layer is made larger than the gate capacitance of the second region, such that the gate capacitance of the gate dielectric layer above the
  • the turn-on voltage required for the point tunneling junction is relatively increased, so that the opening of the point tunneling junction can be delayed or delayed, thereby ensuring that the line tunneling can dominate the opening of the entire device, ensuring that the TFEF has a steep subthreshold characteristic, The power consumption of the TFET is reduced.
  • the preparation method comprises the following steps:
  • the principle of the step is the same as the principle in the step 701.
  • step 702. The principle of the step is the same as that in the step 702. For details, refer to the content in step 702, and details are not described herein again.
  • step 703. The principle of the step is the same as that in the step 703. For details, refer to the content in step 703, and details are not described herein again.
  • the protective layer and the sacrificial layer are removed by an etching technique, an initial pocket layer is prepared on the upper surface of the semiconductor substrate, and the initial pocket layer is etched to obtain a pocket layer.
  • the principle of the step is the same as the principle in the step 704.
  • the gate dielectric layer is composed of a third gate dielectric layer and a fourth gate dielectric layer.
  • the third gate dielectric layer covers a second designated area of the upper surface of the pocket layer, and the second designated area is a region above the channel region in the upper surface of the pocket layer.
  • the fourth gate dielectric layer covers the third gate dielectric layer and the third designated region of the upper surface of the pocket layer that is not covered by the third gate dielectric layer, and the third designated region is a region of the upper surface of the pocket layer except the second designated region.
  • a third gate dielectric layer is deposited on the second designated region of the upper surface of the pocket layer using a low dielectric material, using a high dielectric material deposited on the upper surface of the third gate dielectric layer and the third designated region of the upper surface of the pocket layer
  • the fourth gate dielectric layer includes, but is not limited to, implemented in the following two ways:
  • the first manner depositing an initial third gate dielectric layer using a low dielectric material on the upper surface of the initial pocket layer prepared in step 1504, the initial third gate dielectric layer completely covering the initial pocket layer in step 1505; And etching an initial third gate dielectric layer to define a shape of the third gate dielectric layer, etching away an area of the initial third gate dielectric layer above the source region, and obtaining an etched A third gate dielectric layer.
  • the edge of the etched third gate dielectric layer is aligned or slightly overlapped with the source region, and the overlap size may be between 1 nanometer and 5 nanometers.
  • an initial fourth gate dielectric layer is deposited on the surface of the etched initial third gate dielectric layer and the upper surface of the pocket layer covered by the etched initial third gate dielectric layer.
  • the second way depositing a third gate dielectric layer directly on the upper surface of the pocket layer above the channel region using a low dielectric material, and using the high dielectric material on the third gate dielectric layer and the upper surface of the pocket layer is not the third medium
  • a fourth gate dielectric layer is deposited over the third designated region of the layer.
  • the etching process can be saved, thereby saving the process flow.
  • this way corresponds to the first mode in step 1105.
  • an initial gate region is prepared on the upper surface of the etched third gate dielectric layer; then, according to the shape of the preset pocket layer, the shape of the third gate dielectric layer is preset, the shape of the fourth gate dielectric layer is preset, and Forming a predetermined gate region, etching the initial pocket layer, the etched initial third gate dielectric layer, the initial fourth gate dielectric layer, and the initial gate region to obtain a pocket layer, a third gate dielectric layer, and a fourth Gate dielectric layer and gate region.
  • the lithography and anisotropic etching techniques may be combined to sequentially The pocket layer, the etched initial third gate dielectric layer, the second four gate dielectric layer, and the initial gate region are etched.
  • the pocket layer prepared in step 1105 is obtained by etching the initial pocket layer in this step, that is, step 1105 only needs to prepare the initial pocket layer.
  • the third gate dielectric layer and the fourth gate dielectric layer are also obtained by etching the etched initial third gate dielectric layer and the initial fourth gate dielectric layer respectively in this step, that is, the step 1106 only needs to be prepared to the initial
  • the first gate dielectric layer and the etched initial second gate dielectric layer may be used.
  • this method corresponds to the second mode in step 1105.
  • a gate region is directly deposited on the upper surface of the gate dielectric layer, and the gate region completely covers the upper surface of the gate dielectric layer.
  • step 707 The principle of this step is the same as the principle in step 707.
  • steps 707 For details, refer to the content in step 707, and details are not described herein again.
  • the principle of the step is the same as the principle in the step 708.
  • a first region of the gate dielectric layer is a region where the fourth gate dielectric layer is located above the source region, and a second region of the gate dielectric layer is a third gate dielectric layer and a fourth gate.
  • the dielectric layer is located in a region above the channel region such that the thickness of the gate dielectric layer in the first region is significantly smaller than the thickness of the second region, and the material of the third gate dielectric layer is a low dielectric material, and the fourth gate dielectric layer
  • the material is a high dielectric material such that the average relative dielectric constant of the first region of the gate dielectric layer is greater than the average relative dielectric constant of the second region, and the gate capacitance of the gate dielectric layer is inversely proportional to the thickness, and the relative dielectric of the material
  • the constant is proportional, so that the gate capacitance of the first region of the gate dielectric layer is greater than the gate capacitance of the second region, so that the gate voltage is more capable of regulating the tunneling junction than the point tunneling junction under the same gate voltage.
  • the turn-on voltage required for the point tunneling junction is relatively increased, so that the opening of the point tunneling junction can be delayed or delayed, thereby ensuring that the line tunneling can dominate the opening of the entire device, ensuring that the TFEF has a steep subthreshold characteristic, The power consumption of the TFET is reduced.
  • the preparation method comprises the following steps:
  • the type of tunneling field effect transistor performing a well implant on the predetermined substrate to obtain a tunnel A type-matched semiconductor substrate that passes through a field effect transistor.
  • the principle of the step is the same as the principle in the step 701.
  • step 702. The principle of the step is the same as that in the step 702. For details, refer to the content in step 702, and details are not described herein again.
  • step 703. The principle of the step is the same as that in the step 703. For details, refer to the content in step 703, and details are not described herein again.
  • the protective layer and the sacrificial layer are removed by an etching technique, an initial pocket layer is prepared on the upper surface of the semiconductor substrate, and the initial pocket layer is etched to obtain a pocket layer.
  • the principle of the step is the same as the principle in the step 704.
  • the initial gate dielectric layer completely covers the pocket layer, and the fourth designated region is a region where the initial gate dielectric layer is located above the source region. Specifically, when the fourth designated region of the initial gate dielectric layer is thinned, it can be implemented in combination with photolithography and etching techniques.
  • the upper surface of the initial pocket layer prepared in step 1604 is deposited with a high dielectric material to deposit the original gate dielectric layer; then, according to the shape of the preset pocket layer and the shape of the predetermined gate dielectric layer, the initial pocket layer Etching is performed with the original gate dielectric layer to obtain a pocket layer and an initial gate dielectric layer.
  • the second way depositing a predetermined thickness of the initial gate dielectric layer directly over the pocket layer.
  • the gate region covers the entire area of the upper surface of the gate dielectric layer.
  • step 707 The principle of this step is the same as the principle in step 707.
  • steps 707 For details, refer to the content in step 707, and details are not described herein again.
  • the principle of the step is the same as the principle in the step 708.
  • the thickness of the first region of the gate dielectric layer is smaller than the thickness of the second region, and the gate capacitance of the gate dielectric layer is inversely proportional to the thickness, so that the first region of the gate dielectric layer
  • the gate capacitance is greater than the gate capacitance of the second region such that the gate capacitance of the gate dielectric layer above the source region is greater than the gate capacitance of the gate dielectric layer above the channel region such that the gate dielectric is opposite to the source region and the channel region.
  • the preparation method comprises the following steps:
  • the principle of the step is the same as the principle in the step 701.
  • step 702. The principle of the step is the same as that in the step 702. For details, refer to the content in step 702, and details are not described herein again.
  • step 703. The principle of the step is the same as that in the step 703. For details, refer to the content in step 703, and details are not described herein again.
  • the protective layer and the sacrificial layer are removed by an etching technique, an initial pocket layer is prepared on the upper surface of the semiconductor substrate, and the initial pocket layer is etched to obtain a pocket layer.
  • step 704. The principle of the step is the same as the principle in step 704. For details, refer to the content in step 704. I will not repeat them here.
  • the fifth designated area is a region above the source region in the upper surface of the fifth gate dielectric layer
  • the sixth designated region is a region above the channel region in the upper surface of the fifth gate dielectric layer.
  • a fifth gate dielectric layer is deposited on the surface of the pocket layer using a high dielectric material
  • a third region of the sixth gate dielectric layer is deposited on the fifth designated region of the upper surface of the fifth gate dielectric layer using a high dielectric material
  • the deposition of the fourth region of the sixth gate dielectric layer in the sixth designated region of the upper surface of the fifth gate dielectric layer using a low dielectric material includes, but is not limited to, by two ways:
  • the initial surface of the initial pocket layer prepared in step 1604 uses a high dielectric material to deposit an initial fifth gate dielectric layer, and the high dielectric material is used to deposit an initial deposition in a fifth designated region of the upper surface of the initial fifth gate dielectric layer.
  • a third region of the sixth gate dielectric layer using a low dielectric material to deposit a fourth region of the initial sixth gate dielectric layer at a sixth designated region of the upper surface of the initial fifth gate dielectric layer, by the initial sixth gate dielectric layer
  • the third region and the fourth region of the initial sixth gate dielectric layer constitute an initial sixth gate dielectric layer.
  • the initial pocket layer, the initial fifth gate dielectric layer, and the initial sixth gate dielectric layer are etched by photolithography and etching techniques to obtain a pocket layer, a fifth gate dielectric layer, and a sixth gate dielectric layer.
  • the pocket layer prepared in step 1705 is obtained by etching the initial pocket layer in this step, that is, step 1705 requires only the preparation of the initial pocket layer.
  • the second method depositing a fifth gate dielectric layer directly on the upper surface of the pocket layer using a high dielectric material, and depositing a third region of the sixth gate dielectric layer on a fifth designated region on the fifth gate dielectric layer, using a low dielectric layer
  • the electrical material deposits a fourth region of the sixth gate dielectric layer in a sixth designated region of the upper surface of the initial fifth gate dielectric layer.
  • the first way corresponds to the first mode in step 1705.
  • an initial gate region is deposited on the upper surface of the initial sixth gate dielectric layer; then, the shape of the pocket layer is preset, the shape of the fifth gate dielectric layer is preset, the shape of the predetermined sixth gate dielectric layer, and the preset gate region are preset. shape, The initial pocket layer, the initial first five gate dielectric layer, the initial sixth gate dielectric layer, and the initial gate region are etched to obtain a pocket layer, a fifth gate dielectric layer, a sixth gate dielectric layer, and a gate region, respectively.
  • the initial pocket layer when etching the initial pocket layer, the initial first five-gate dielectric layer, the initial sixth gate dielectric layer, and the initial gate region, the initial pocket layer may be sequentially combined with photolithography and anisotropic etching techniques.
  • the initial first five gate dielectric layer, the initial sixth gate dielectric layer, and the initial gate region are etched.
  • the pocket layer prepared in step 1705 is obtained by etching the initial pocket layer in this step, that is, step 1705 only needs to prepare the initial pocket layer.
  • the fifth gate dielectric layer and the sixth gate dielectric layer are also obtained by etching the initial fifth gate dielectric layer and the initial sixth gate dielectric layer respectively in this step, that is, the step 1706 only needs to be prepared to the initial fifth gate dielectric.
  • the layer and the initial sixth gate dielectric layer are sufficient.
  • this method corresponds to the second mode in step 1705.
  • This method directly deposits a gate region on the surface of the sixth gate dielectric layer.
  • the fifth gate dielectric layer under the sixth gate dielectric layer as an example.
  • the fifth gate dielectric layer may also be located above the sixth gate dielectric layer.
  • step 707 The principle of this step is the same as the principle in step 707.
  • steps 707 For details, refer to the content in step 707, and details are not described herein again.
  • the principle of the step is the same as the principle in the step 708.
  • the method for fabricating the TFET according to the embodiment of the present invention is characterized in that the material of the fifth gate dielectric layer and the material of the third region of the sixth gate dielectric layer are high dielectric materials, and the material of the fourth region of the sixth gate dielectric layer is low dielectric.
  • the electrical material is such that the average relative dielectric constant of the first region of the gate dielectric layer is greater than the average relative dielectric constant of the second region, and the gate capacitance of the gate dielectric layer is proportional to the relative dielectric constant of the material, thereby causing the gate dielectric layer
  • the gate capacitance of a region is greater than the gate capacitance of the second region such that the gate capacitance of the gate dielectric layer above the source region is greater than the gate capacitance of the gate dielectric layer above the channel region such that at the same gate voltage, the gate voltage pair
  • the regulation ability of the tunnel tunneling junction is stronger than that of the point tunneling junction.
  • the turn-on voltage required for the point tunneling junction is relatively increased, thereby delaying or delaying the opening of the point tunneling junction, thereby ensuring that the line tunneling can dominate the opening of the entire device, ensuring that the TFEF has a steep subthreshold characteristic. This reduces the power consumption of the TFET.

Abstract

提供一种隧穿场效应晶体管（TFET）及其制备方法，属于半导体技术领域。通过设置位于源区上方的栅介质层的栅电容大于位于沟道区上方的栅介质层的栅电容，使得在相同栅压下，栅压对线隧穿结的调控能力强于对点隧穿结的调控能力，因此，点隧穿结所需的开启电压相对增大，因而能够延缓或者推迟点隧穿结的开启，从而保证线隧穿能够主宰整个器件的开启，确保TFET具有比较陡峭的亚阈值特性，使得TFET的功耗降低。

Description

隧穿场效应晶体管及其制备方法 技术领域
本发明涉及半导体技术领域，特别涉及一种隧穿场效应晶体管及其制备方法。
背景技术
随着半导体技术的迅速发展，芯片中晶体管的集成密度越来越高。在此种情况下，功耗成为芯片设计的关键挑战因素。降低功耗的关键在于降低晶体管的供电电压，而降低供电电压的核心制约因素为晶体管的亚阈值摆幅，即晶体管从关闭状态到开启状态转变的锐利程度。陡峭的亚阈值转变允许更大幅度供电电压的降低，从而实现晶体管功耗的大幅降低。TFET(Tunnel Field-Effect Transistor,隧穿场效应晶体管)即为一种具有陡峭的亚阈值特性的晶体管，因此，TFET在降低器件功耗方面具有非常大的发展潜力。
如图1所示，其示出了一种现有技术中的TFET的结构示意图。如图1所示，现有技术TFET中包括重掺杂的源区、漏区、沟道区、轻掺杂的口袋层、栅介质层和栅区。图1中，101表示源区，102表示沟道区，103表示漏区，104表示口袋层，105表示栅介质层，106表示栅区。其中，口袋层与源区的部分区域及沟道区的部分区域重叠。在栅电场的作用下，口袋层的载流子积累，最终与源区形成隧穿结，源区的载流子隧穿至口袋层，形成电流。图1所示的TFET中，源区与源区正上方的口袋层部分构成第一种隧穿结，在此基础上，在栅电场的作用下，载流子会沿着实线箭头隧穿，其隧穿方向与栅电场平行，为线隧穿。因此，该种隧穿结为线隧穿结。另外，结合图1，在这种结构下，由于沟道区上方的区域也同样受栅电场的调控，因此，在源区的角落与口袋层之间也会形成第二种隧穿结，载流子也会进行隧穿，如图1中的虚线箭头所示。该种隧穿方式的隧穿方向与栅电场交叉，为点隧穿。因此，该种隧穿结为点隧穿结。在实现本发明的过程中，发明人发现现有技术至少存在以下不足：
由于点隧穿结的开启电压小于线隧穿结的开启电压，因此，使得点隧穿结先于线隧穿结开启，导致TFET亚阈值摆幅退化，使得TFET开启缓慢，削弱 了TFET降低工作电压的能力，导致器件降低功耗能力退化。因此，图1中的结构使得TFET的功耗比较大。
发明内容
为了解决现有技术存在的问题，本发明实施例提供了一种TFET及其制备方法。所述技术方案如下：
第一方面，提供了一种TFET，所述TFET包括源区、漏区、沟道区、口袋层、栅介质层和栅区，其中：
所述源区和所述漏区分离地设置于半导体衬底内部，所述沟道区连接所述源区和所述漏区；
所述口袋层设置于所述源区和所述沟道区的上表面，所述栅介质层设置于所述口袋层的上表面，所述栅区设置于所述栅介质层的上表面，所述栅介质层包括第一区域和第二区域，所述第一区域为位于所述源区上方的栅介质层区域，所述第二区域为位于所述沟道区上方的栅介质层区域，所述第一区域的栅电容大于所述第二区域的栅电容；
其中，所述口袋层与所述源区组成所述隧穿场效应晶体管的隧穿结。
结合第一方面，在第一方面的第一种可能的实现方式中，所述栅介质层由第一栅介质层和第二栅介质层组成；所述第一栅介质层完全覆盖所述口袋层的上表面，所述第二栅介质层覆盖所述第一栅介质层上表面的第一指定区域，所述第一指定区域为所述第一栅介质层上表面中位于所述沟道区上方的区域；
其中，所述第一栅介质层的材料为高介电材料，所述第二栅介质层的材料为低介电材料，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料，所述低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料。
结合第一方面，在第一方面的第二种可能的实现方式中，所述栅介质层由第三栅介质层和第四栅介质层组成；所述第三栅介质层覆盖所述口袋层上表面的第二指定区域，所述第二指定区域为所述口袋层上表面中位于所述沟道区上方的区域；所述第四栅介质层完全覆盖所述第三栅介质层的上表面及所述口袋层上表面的第三指定区域，所述第三指定区域为所述口袋层上表面除所述第二指定区域外的区域；
其中，所述第三栅介质层的材料为低介电材料，所述第四栅介质层的材料 为高介电材料，所述低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料。
结合第一方面，在第一方面的第三种可能的实现方式中，所述第一区域的厚度小于所述第二区域的厚度，且所述第一区域和所述第二区域的材料为同一高介电材料；
其中，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料。
结合第一方面，在第一方面的第四种可能的实现方式中，所述栅介质层由第五栅介质层和第六栅介质层组成；所述第五栅介质层完全覆盖所述口袋层的上表面，所述第六栅介质层完全覆盖所述第五栅介质层的上表面，且所述第六栅介质层包括第三区域和第四区域，所述第三区域为位于所述源区上方的第六栅介质层区域，所述第四区域为位于所述沟道区上方的第六栅介质层区域；
其中，所述第五栅介质层的材料及所述第三区域的材料为高介电材料，所述第四区域的材料为低介电材料，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料，所述低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料。
结合第一方面，在第一方面的第五种可能的实现方式中，
所述口袋层、所述栅介质层和所述栅区两侧制备有隔离墙；
所述源区、所述栅区和所述漏区的指定位置处分别制备有金属源电极、金属栅电极和金属漏电极，所述隔离墙用于隔离所述金属源电极、所述金属栅电极及所述金属漏电极。
结合第一方面至第一方面的第五种可能的实现方式中的任一种可能的实现方式，在第一方面的第六种可能的实现方式中，
所述半导体衬底的材料为体硅、绝缘体上的硅、锗硅、锗以及III-V族化合物半导体中的一种；
所述口袋层的材料为硅、锗硅、锗以及III-V族化合物半导体中的一种；
所述栅区的材料为多晶硅、金属以及多晶硅与金属的多层复合结构中的一种。
第二方面，还提供了一种TFET的制备方法，所述制备方法包括：
根据隧穿场效应晶体管的类型，对预设衬底进行阱注入，得到与所述隧穿 场效应晶体管的类型匹配的半导体衬底；
在所述半导体衬底内部分离地制备源区和漏区，并使沟道区连接所述源区和所述漏区；
在所述源区和所述沟道区的上表面制备口袋层，所述口袋层与所述源区组成所述隧穿场效应晶体管的隧穿结；
在所述口袋层的上表面制备栅介质层，所述栅介质层包括第一区域和第二区域，所述第一区域为位于所述源区上方的栅介质层区域，所述第二区域为位于所述沟道区上方的栅介质层区域，所述第一区域的栅电容大于所述第二区域的栅电容；
在所述栅介质层的上表面制备栅区。
结合第二方面，在第二方面的第一种可能的实现方式中，所述在半导体衬底内部分离地制备源区和漏区，包括：
利用光刻技术保护所述半导体衬底中的预设漏区，对所述半导体衬底中的预设源区进行第一种离子注入；
利用光刻技术保护所述源区，对所述预设漏区进行第二种离子注入；
对完成离子注入的结构进行快速退火工艺，生成源区和漏区。
结合第二方面的第一种可能的实现方式，在第二方面的第二种可能的实现方式中，所述利用光刻技术保护所述半导体衬底中的预设漏区，对所述半导体衬底中的预设源区进行第一种离子注入之前，还包括：
在所述半导体衬底上制备保护层，所述保护层用于在对所述预设源区和所述预设漏区进行离子注入时，保护所述半导体衬底；
在所述保护层上制备指定形状的牺牲层，所述牺牲层用于在对所述预设源区和所述预设漏区进行离子注入时，自对准地形成所述沟道区。
结合第二方面，在第二方面的第三种可能的实现方式中，所述在所述口袋层的上表面制备栅介质层，包括：
使用高介电材料在所述口袋层上表面沉积第一栅介质层，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料；
使用低介电材料在所述第一栅介质层上表面的第一指定区域沉积第二栅介质层，所述第一指定区域为所述第一栅介质层上表面中位于所述沟道区上方的区域，所述低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料；
其中，所述栅介质层由所述第一栅介质层和所述第二栅介质层组成。
结合第二方面，在第二方面的第四种可能的实现方式中，所述在所述口袋层的上表面制备栅介质层，包括：
使用低介电材料在所述口袋层上表面的第二指定区域沉积第三栅介质层，所述第二指定区域为所述口袋层上表面中位于所述沟道区上方的区域，所述低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料；
使用高介电材料在所述第三栅介质层上表面及所述口袋层上表面的第三指定区域沉积第四栅介质层，所述第三指定区域为所述口袋层上表面除所述第二指定区域外的区域，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料；
其中，所述栅介质层由所述第三栅介质层和所述第四栅介质层组成。
结合第二方面，在第二方面的第五种可能的实现方式中，所述在所述口袋层的上表面制备栅介质层，包括：
使用高介电材料在所述口袋层的上表面沉积初始栅介质层；
对所述初始栅介质层的第四指定区域进行减薄，得到栅介质层，所述第四指定区域为所述初始栅介质层中位于所述源区上方的区域。
结合第二方面，在第二方面的第六种可能的实现方式中，所述在所述口袋层的上表面制备栅介质层，包括：
使用高介电材料在所述口袋层上表面沉积第五栅介质层；
使用高介电材料在所述第五栅介质层上表面的第五指定区域沉积第六栅介质层的第三区域，使用低介电材料在所述第五栅介质层上表面的第六指定区域沉积第六栅介质层的第四区域，所述第五指定区域为所述第五栅介质层上表面中位于所述源区上方的区域，所述第六指定区域为所述第五栅介质层上表面中位于所述沟道区上方的区域，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料，所述低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料；
其中，所述栅介质层由所述第五栅介质层和所述第六栅介质层组成。
结合第二方面，在第二方面的第七种可能的实现方式中，所述在所述栅介质层的上表面制备栅区之后，还包括：
在所述口袋层、所述栅介质层和所述栅区两侧制备隔离墙；
在所述隔离墙及所述栅区外侧填充低介电材料；
在所述源区、所述栅区和所述漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极，所述隔离墙用于隔离所述金属源电极、所述金属栅电极及所述金属漏电极。
本发明实施例提供的技术方案的有益效果是：
通过设置位于源区上方的栅介质层的栅电容大于位于沟道区上方的栅介质层的栅电容，使得在相同栅压下，栅压对线隧穿结的调控能力强于对点隧穿结的调控能力。因此，点隧穿结所需的开启电压相对增大，因而能够延缓或者推迟点隧穿结的开启，从而保证线隧穿能够主宰整个器件的开启，确保TFEF具有比较陡峭的亚阈值特性，使得TFET的功耗降低。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中的一种TFET的结构示意图；
图2是本发明另一实施例提供的一种TFET的结构示意图；
图3是本发明另一实施例提供的一种TFET的结构示意图；
图4是本发明另一实施例提供的一种TFET的结构示意图；
图5是本发明另一实施例提供的一种TFET的结构示意图；
图6是本发明另一实施例提供的一种TFET的制备方法流程图；
图7是本发明另一实施例提供的一种TFET的制备方法流程图；
图8是本发明另一实施例提供的一种半导体衬底的示意图；
图9是本发明另一实施例提供的一种保护层和牺牲层的示意图；
图10是本发明另一实施例提供的一种源区和漏区的示意图；
图11是本发明另一实施例提供的一种初始口袋层、初始第一栅介质层和初始第二栅介质层的示意图；
图12是本发明另一实施例提供的一种刻蚀后的初始第二栅介质层的示意图；
图13是本发明另一实施例提供的一种初始口袋层、初始第一栅介质层、刻蚀后的初始第二栅介质层和初始栅区的示意图；
图14是本发明另一实施例提供的一种隔离墙的示意图；
图15是本发明另一实施例提供的一种TFET的制备方法的流程图；
图16是本发明另一实施例提供的一种TFET的制备方法的流程图；
图17是本发明另一实施例提供的一种TFET的制备方法的流程图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
本发明实施例提供了一种TFET，该TFET包括源区、漏区、沟道区、口袋层、栅介质层和栅区，其中：
源区和漏区分离地设置于半导体衬底内部，且沟道区连接源区和漏区；口袋层设置于源区和沟道区的上表面，栅介质层设置于口袋层的上表面，栅区设置于栅介质层的上表面。
关于口袋层、栅介质层和栅区的厚度，本发明实施例不作具体限定，口袋层、栅介质层和栅区的厚度可以相同，也可以不同。在可选实施例中，口袋层、栅介质层和栅区的厚度均可以设置为1纳米至5纳米中的任一数值。
其中，栅介质层包括第一区域和第二区域，第一区域为位于源区上方的栅介质层区域，第二区域为位于沟道区上方的栅介质层区域，第一区域的栅电容大于第二区域的栅电容。栅压通过第一区域控制线隧穿结，通过第二区域控制点隧穿结。栅电容是指由栅区、栅介质层及源区和漏区构成电容时，栅介质层表面的电容大小。
口袋层至少覆盖部分源区和部分沟道区。其中，口袋层的掺杂浓度小于源区的掺杂浓度。口袋层与源区组成隧穿场效应晶体管的隧穿结。在该TFET中，栅区用于确定TFET的开启与关闭。当TFET的栅控电压小于阈值电压时，TFET处于关闭状态；当TFET的栅控电压大于阈值电压时，TFET处于开启状态。在栅电场的作用下，口袋层的载流子积累，最终与源区形成隧穿结，源区的载流子隧穿至口袋层，形成电流。
在本发明实施例中，半导体衬底的材料可以为体硅、绝缘体上的硅(SOI,Silicon-on-insulator)、锗硅、锗以及III-V族化合物半导体中的一种。口袋层的材料可以为硅、锗硅、锗以及III-V族化合物半导体中的一种。栅区的材料可 以为多晶硅、金属以及多晶硅与金属的多层复合结构中的一种。半导体衬底及口袋层的材料可以相同，也可以不同。沟道区是载流子从源区到漏区的导电通路。由于沟道区为半导体衬底内部的部分区域，因此，沟道区的材料与半导体衬底的材料相同。
在本发明实施例中，在使栅介质层第一区域的栅电容大于栅介质层第二区域的栅电容时，可以通过控制栅介质层在第一区域和第二区域的材料和/或组成结构满足一定条件来实现，关于栅介质层的材料及结构将在后续各个实施例中详细阐述，此处暂不赘述。另外，本发明实施例所述的TFET的内容适用于下述各个实施例，在后续各个实施例中将不针对相同的内容再作赘述。
本发明实施例提供的TFET，通过设置位于源区上方的栅介质层的栅电容大于位于沟道区上方的栅介质层的栅电容，使得在相同栅压下，栅压对线隧穿结的调控能力强于对点隧穿结的调控能力，因此，点隧穿结所需的开启电压相对增大，因而能够延缓或者推迟点隧穿结的开启，从而保证线隧穿能够主宰整个器件的开启，确保TFEF具有比较陡峭的亚阈值特性，使得TFET的功耗降低。
结合上述实施例的内容，图2是本发明另一实施例提供的一种TFET的结构示意图。图2所对应实施例通过控制栅介质层的组成结构和材料来使栅介质层第一区域的栅电容大于栅介质层第二区域的栅电容。
如图2所示，本发明实施例提供的TFET中，源区201和漏区203分离地设置于半导体衬底200内部；沟道区202连接源区201和漏区203。口袋层204设置于半导体衬底200上表面的部分区域，且口袋层204至少覆盖部分源区201和部分沟道区202。
其中，口袋层204可以与漏区203不接触。口袋层204不与漏区203接触能减小TFET漏电的可能性，从而能够提高TFET的性能。
在本发明实施例中，如图2所示，栅介质层205设置于口袋层204之上，且栅介质层205由第一栅介质层205.1和第二栅介质层205.2组成。其中，第一栅介质层205.1完全覆盖口袋层204的上表面，第二栅介质层205.2覆盖第一栅介质层205.1上表面的第一指定区域，该第一指定区域为第一栅介质层205.1上表面中位于沟道区202上方的区域。
由图2可得，在本发明实施例中，栅介质层205的第一区域为第一栅介质 层205.1位于源区201上方的区域，栅介质层205的第二区域为第一栅介质层205.1位于沟道区202上方的区域及第二栅介质层205.2。图2中，标记“一”的区域对应的栅介质层为栅介质层205的第一区域，标记“二”的区域对应的栅介质层为栅介质层205的第二区域。
其中，第一栅介质层205.1的材料的相对介电常数大于第二栅介质层205.2的材料的相对介电常数。例如，第一栅介质层205.1的材料可以为高介电材料，第二栅介质层205.2的材料可以为低介电材料。高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料，低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料。其中，相对介电常数是指相对真空的介电常数，二氧化硅相对真空的介电常数为3.9。
结合图2，在本发明实施例中，通过设置栅介质层205第一区域为第一栅介质层205.1位于源区201上方的区域，第二区域为第一栅介质层205.1位于沟道区202上方的区域及第二栅介质层205.2，使得栅介质层205在第一区域的厚度显然小于第二区域的厚度，而栅介质层205的栅电容与栅介质层205的厚度成反比，从而使得栅介质层205在第一区域的栅电容大于第二区域的栅电容。进一步地，在本发明实施例中，通过设置第一栅介质层205.1的材料为高介电材料，第二栅介质层205.2的材料为低介电材料，使得第一栅介质层205.1材料的相对介电常数大于第二栅介质层205.2材料的相对介电常数，进而使得栅介质层205第一区域的平均相对介电常数大于第二区域的平均相对介电常数，而栅介质层205的栅电容与栅介质层205材料的相对介电常数成正比，从而使得栅介质层205第一区域的栅电容大于第二区域的栅电容。
结合图2，在可选择的实施例中，口袋层204、栅介质层205和栅区206两侧制备有隔离墙207。隔离墙207的材料为氮化硅等绝缘材料，隔离墙207的形状可以为如图2所示镰刀状，也可以为矩形等。栅区206外围和隔离墙207外围可以填充有低介电材料208，如氮化硅(Si3N4)等。另外，源区201、栅区206和漏区203的指定位置处分别制备有金属源电极209、金属栅电极211和金属漏电极210。
需要说明的是，该实施例中所述的“指定位置”为预先设置的用于制备金属源电极209、金属栅电极211和金属漏电极210的位置。例如，指定位置可以为源区201上表面未被隔离墙207覆盖的任意位置，栅区206上表面的任意位置，漏区203上表面未被隔离墙207覆盖的任意位置。
其中，由于隔离墙207为绝缘材料，因此，其可以用于隔离金属源电极209、金属栅电极211及金属漏电极210，从而避免出现短路现象。另外，基于隔离墙207的材料，使得隔离墙207的机械性能比较好，能够固定栅区206、口袋层204和栅介质层205的形状。
通过填充低介电材料208，可以防止TFET的寄生电容过大。另外，通过低介电材料，能起到对金属源电极209、金属栅电极211和金属漏电极210的机械支撑作用。
本发明实施例提供的TFET，通过设置栅介质层第一区域为第一栅介质层位于源区上方的区域，第二区域为第一栅介质层位于沟道区上方的区域及第二栅介质层，使得栅介质层在第一区域的厚度显然小于第二区域的厚度，以及通过设置第一栅介质层的材料为高介电材料，第二栅介质层的材料为低介电材料，使得栅介质层第一区域的平均相对介电常数大于第二区域的平均相对介电常数，而栅介质层的栅电容与厚度成反比，而与其材料的相对介电常数成正比，从而使得栅介质层第一区域的栅电容大于第二区域的栅电容，使得位于源区上方的栅介质层的栅电容大于位于沟道区上方的栅介质层的栅电容，使在相同栅压下，栅压对线隧穿结的调控能力强于对点隧穿结的调控能力，因此，点隧穿结所需的开启电压相对增大，因而能够延缓或者推迟点隧穿结的开启，从而保证线隧穿能够主宰整个器件的开启，确保TFEF具有比较陡峭的亚阈值特性，使得TFET的功耗降低。
结合上述实施例的内容，图3是本发明另一实施例提供的一种TFET的结构示意图，图3所对应实施例通过控制栅介质层的组成结构和材料来使栅介质层第一区域的栅电容大于栅介质层第二区域的栅电容。
如图3所示，本发明实施例提供的TFET中，源区301和漏区303分离地设置于半导体衬底300内部；沟道区302连接源区301和漏区303。口袋层304设置于半导体衬底300上表面的部分区域，且口袋层304至少覆盖部分源区301和部分沟道区302，口袋层304与漏区303不接触。口袋层304不与漏区303接触能减小TFET漏电的可能性，从而能够提高TFET的性能。
在本发明实施例中，如图3所示，栅介质层305设置于口袋层304之上，且栅介质层305由第三栅介质层305.3和第四栅介质层305.4组成。其中，第三栅介质层305.3覆盖口袋层304的上表面的第二指定区域，该第二指定区域 为口袋层304上表面中位于沟道区302上方的区域。第四栅介质层305.4完全覆盖第三栅介质层305.3的上表面及口袋层304上表面的第三指定区域，该第三指定区域为口袋层304上表面除第二指定区域外的区域。
由图3可得，在本发明实施例中，栅介质层305的第一区域为第四栅介质层305.4位于源区301上方的区域，栅介质层305的第二区域为第三栅介质层305.3及第四栅介质层305.4位于沟道区302上方的区域。图3中，标记“一”的区域对应的栅介质层为栅介质层305的第一区域，标记“二”的区域对应的栅介质层为栅介质层305的第二区域。
其中，第三栅介质层305.3材料的相对介电常数小于第四栅介质层305.4材料的相对介电常数。例如，第三栅介质层305.3的材料可以为低介电材料，第四栅介质层305.4的材料可以为高介电材料。
结合图3，在本发明实施例中，通过设置栅介质层305第一区域为第四栅介质层305.4位于源区301上方的区域，栅介质层305的第二区域为第三栅介质层305.3及第四栅介质层305.4位于沟道区302上方的区域，使得栅介质层305在第一区域的厚度显然小于第二区域的厚度，而栅介质层305的栅电容与栅介质层305的厚度成反比，从而使得栅介质层305在第一区域的栅电容大于第二区域的栅电容。进一步地，在本发明实施例中，通过设置第三栅介质层305.3的材料为低介电材料，第四栅介质层305.4的材料为高介电材料，使得第三栅介质层305.3材料的相对介电常数小于第四栅介质层305.4材料的相对介电常数，进而使得栅介质层305第一区域的平均相对介电常数大于第二区域的平均相对介电常数，而栅介质层305的栅电容与栅介质层305材料的相对介电常数成正比，从而使得栅介质层305第一区域的栅电容大于第二区域的栅电容。
结合图3，在可选择的实施例中，口袋层304、栅介质层305和栅区306两侧制备有隔离墙307，栅区306外围和隔离墙307外围可以填充有低介电材料308(图3中未示出低介电材料)，源区301、栅区306和漏区303的指定位置处分别制备有金属源电极309、金属栅电极311和金属漏电极310(图3中未示出金属源电极309、金属栅电极311和金属漏电极310)。
关于隔离墙307、低介电材料308、金属源电极309、金属栅电极311及金属漏电极310的材料及作用等内容已在上述图2所对应实施例中进行了说明，具体内容可参见上述图2所对应实施例中的内容，此处不再赘述。
本发明实施例提供的TFET，通过设置栅介质层的第一区域为第四栅介质 层位于源区上方的区域，栅介质层的第二区域为第三栅介质层及第四栅介质层位于沟道区上方的区域，使得栅介质层在第一区域的厚度显然小于第二区域的厚度，以及通过设置第三栅介质层的材料为低介电材料，第四栅介质层的材料为高介电材料，使得栅介质层第一区域的平均相对介电常数大于第二区域的平均相对介电常数，而栅介质层的栅电容与厚度成反比，而与其材料的相对介电常数成正比，从而使得栅介质层第一区域的栅电容大于第二区域的栅电容，使得位于源区上方的栅介质层的栅电容大于位于沟道区上方的栅介质层的栅电容，使在相同栅压下，栅压对线隧穿结的调控能力强于对点隧穿结的调控能力。因此，点隧穿结所需的开启电压相对增大，因而能够延缓或者推迟点隧穿结的开启，从而保证线隧穿能够主宰整个器件的开启，确保TFEF具有比较陡峭的亚阈值特性，使得TFET的功耗降低。
结合上述实施例的内容，图4是本发明另一实施例提供的一种TFET的结构示意图，图4所对应实施例通过控制栅介质层在不同区域的厚度来使栅介质层第一区域的栅电容大于栅介质层第二区域的栅电容。
如图4所示，本发明实施例提供的TFET中，源区401和漏区403分离地设置于半导体衬底400内部；沟道区402连接源区401和漏区403。口袋层404设置于半导体衬底400上表面的部分区域，且口袋层404至少覆盖部分源区401和部分沟道区402，口袋层404与漏区403不接触。口袋层404不与漏区403接触能减小TFET漏电的可能性，从而能够提高TFET的性能。
在本发明实施例中，如图4所示，栅介质层405设置于口袋层404之上，且栅介质层305第一区域的厚度小于第二区域的厚度，且第一区域和第二区域的材料为同一高介电材料。其中，第一区域为位于源区401上方的区域，第二区域为位于沟道区402上方的区域。图4中，标记“一”的区域对应的栅介质层为栅介质层405的第一区域，标记“二”的区域对应的栅介质层为栅介质层405的第二区域。
在本发明实施例中，结合图4，由于栅介质层405第一区域的厚度小于第二区域的厚度，而栅介质层405的栅电容与栅介质层405的厚度成反比，从而使得栅介质层305在第一区域的栅电容大于第二区域的栅电容。
结合图4，在可选择的实施例中，口袋层404、栅介质层405和栅区406两侧制备有隔离墙40，栅区406外围和隔离墙407外围可以填充有低介电材料 408(图4中未示出低介电材料)，源区401、栅区406和漏区403的指定位置处分别制备有金属源电极409、金属栅电极411和金属漏电极410(图4中未示出金属源电极409、金属栅电极411和金属漏电极410)。
关于隔离墙407、低介电材料408、金属源电极409、金属栅电极411及金属漏电极410的材料及作用等内容已在上述图2所对应实施例中进行了说明，具体内容可参见上述图2所对应实施例中的内容，此处不再赘述。
本发明实施例提供的TFET，通过设置栅介质层的第一区域的厚度小于第二区域的厚度，而栅介质层的栅电容与厚度成反比，从而使得栅介质层第一区域的栅电容大于第二区域的栅电容，使得在相同栅压下，栅压对线隧穿结的调控能力强于对点隧穿结的调控能力。因此，点隧穿结所需的开启电压相对增大，因而能够延缓或者推迟点隧穿结的开启，从而保证线隧穿能够主宰整个器件的开启，确保TFEF具有比较陡峭的亚阈值特性，使得TFET的功耗降低。
结合上述实施例的内容，图5是本发明另一实施例提供的一种TFET的结构示意图，图5所对应实施例通过控制栅介质层的组成材料来使栅介质层第一区域的栅电容大于栅介质层第二区域的栅电容。
如图5所示，本发明实施例提供的TFET中，源区501和漏区503分离地设置于半导体衬底500内部；沟道区502连接源区501和漏区503。口袋层504设置于半导体衬底500上表面的部分区域，且口袋层504至少覆盖部分源区501和部分沟道区502，口袋层504与漏区503不接触。口袋层504不与漏区503接触能减小TFET漏电的可能性，从而能够提高TFET的性能。
在本发明实施例中，如图5所示，栅介质层505设置于口袋层504之上，且栅介质层505由第五栅介质层505.5和第六栅介质层505.6组成。其中，第五栅介质层505.5完全覆盖口袋层504的上表面，第六栅介质层505.6完全覆盖第五栅介质层505.5的上表面，且第六栅介质层505.6包括第三区域和第四区域，第三区域为第六栅介质层505.6位于源区501上方的区域，第四区域为第六栅介质层505.6位于沟道区502上方的区域。
结合图5可得，在本发明实施例中，栅介质层505的第一区域为第五栅介质层505.5位于源区501上方的区域和第六栅介质层505.6位于源区501上方的区域，栅介质层505的第二区域为第五栅介质505.5位于沟道区502上方的区域及第六栅介质层505.6位于沟道区502上方的区域。图5中，标记“一” 的区域对应的栅介质层为栅介质层505的第一区域，标记“二”的区域对应的栅介质层为栅介质层505的第二区域。
其中，第五栅介质层505.5材料及第六栅介质层505.6第三区域材料的相对介电常数大于第六栅介质层505.6第四区域的材料的相对介电常数。例如，第五栅介质层505.5的材料及第六栅介质层505.6第三区域的材料为高介电材料，第六栅介质层505.6第四区域的材料为低介电材料。
结合图5，在本发明实施例中，通过设置第五栅介质层505.5的材料及第六栅介质层505.6第三区域的材料为高介电材料，第六栅介质层505.6第四区域的材料为低介电材料，使得栅介质层505第一区域的平均相对介电常数大于第二区域的平均相对介电常数，而栅介质层505的栅电容与栅介质层505材料的相对介电常数成正比，从而使得栅介质层505第一区域的栅电容大于第二区域的栅电容。
结合图5，在可选择的实施例中，口袋层504、栅介质层505和栅区506两侧制备有隔离墙507，栅区506外围和隔离墙507外围可以填充有低介电材料508(图5中未示出低介电材料)，源区501、栅区506和漏区503的指定位置处分别制备有金属源电极509、金属栅电极511和金属漏电极510(图5中未示出金属源电极509、金属栅电极511和金属漏电极510)。
关于隔离墙507、低介电材料508、金属源电极509、金属栅电极511及金属漏电极510的材料及作用等内容已在上述图2所对应实施例中进行了说明，具体内容可参见上述图2所对应实施例中的内容，此处不再赘述。
本发明实施例提供的TFET，通过设置第五栅介质层的材料及第六栅介质层第三区域的材料为高介电材料，第六栅介质层第四区域的材料为低介电材料，使得栅介质层第一区域的平均相对介电常数大于第二区域的平均相对介电常数，而栅介质层的栅电容与其材料的相对介电常数成正比，从而使得栅介质层第一区域的栅电容大于第二区域的栅电容，从而使得位于源区上方的栅介质层的栅电容大于位于沟道区上方的栅介质层的栅电容，使得在相同栅压下，栅压对线隧穿结的调控能力强于对点隧穿结的调控能力。因此，点隧穿结所需的开启电压相对增大，因而能够延缓或者推迟点隧穿结的开启，从而保证线隧穿能够主宰整个器件的开启，确保TFEF具有比较陡峭的亚阈值特性，使得TFET的功耗降低。
结合上述图2至图5所对应的实施例的内容，本发明实施例还提供了一种TFET的制备方法，该制备方法可以用于制备上述图2至图5所对应实施例提供的TFET。图6是本发明另一实施例提供的一种TFET的制备方法的流程图。如图6所示，本发明实施例提供的TFET的制备方法包括：
601、根据隧穿场效应晶体管的类型，对预设衬底进行阱注入，得到与隧穿场效应晶体管的类型匹配的半导体衬底。
602、在半导体衬底内部分离地制备源区和漏区，并使沟道区连接源区和漏区。
603、在源区和沟道区的上表面制备口袋层，其中，口袋层与源区组成隧穿场效应晶体管的隧穿结。
604、在口袋层的上表面制备栅介质层，其中，栅介质层包括第一区域和第二区域，第一区域为位于源区上方的栅介质层区域，第二区域为位于沟道区上方的栅介质层区域，第一区域的栅电容大于第二区域的栅电容。
605、在栅介质层的上表面制备栅区。
本发明实施例提供的TFET的制备方法，通过设置位于源区上方的栅介质层的栅电容大于位于沟道区上方的栅介质层的栅电容，使得在相同栅压下，栅压对线隧穿结的调控能力强于对点隧穿结的调控能力，因此，点隧穿结所需的开启电压相对增大，因而能够延缓或者推迟点隧穿结的开启，从而保证线隧穿能够主宰整个器件的开启，确保TFEF具有比较陡峭的亚阈值特性，使得TFET的功耗降低。
在另一个实施例中，在半导体衬底内部分离地制备源区和漏区，包括：
利用光刻技术保护半导体衬底中的预设漏区，对半导体衬底中的预设源区进行第一种离子注入；
利用光刻技术保护源区，对预设漏区进行第二种离子注入；
对完成离子注入的结构进行快速退火工艺，生成源区和漏区。
在另一个实施例中，利用光刻技术保护半导体衬底中的预设漏区，对半导体衬底中的预设源区进行第一种离子注入之前，还包括：
在半导体衬底上制备保护层，其中，保护层用于在对预设源区和预设漏区进行离子注入时，保护半导体衬底；
在保护层上制备指定形状的牺牲层，其中，牺牲层用于在对预设源区和预设漏区进行离子注入时，自对准地形成沟道区。
在另一个实施例中，在口袋层的上表面制备栅介质层，包括：
使用高介电材料在口袋层上表面沉积第一栅介质层，其中，高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料；
使用低介电材料在第一栅介质层上表面的第一指定区域沉积第二栅介质层，其中，第一指定区域为第一栅介质层上表面中位于沟道区上方的区域，低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料；
其中，栅介质层由第一栅介质层和第二栅介质层组成。
在另一个实施例中，在口袋层的上表面制备栅介质层，包括：
使用低介电材料在口袋层上表面的第二指定区域沉积第三栅介质层，其中，第二指定区域为口袋层上表面中位于沟道区上方的区域，低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料；
使用高介电材料在第三栅介质层上表面及口袋层上表面的第三指定区域沉积第四栅介质层，其中，第三指定区域为口袋层上表面除第二指定区域外的区域，高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料；
其中，栅介质层由第三栅介质层和第四栅介质层组成。
在另一个实施例中，在口袋层的上表面制备栅介质层，包括：
使用高介电材料在口袋层的上表面沉积初始栅介质层；
对初始栅介质层的第四指定区域进行减薄，得到栅介质层，其中，第四指定区域为初始栅介质层中位于源区上方的区域。
在另一个实施例中，在口袋层的上表面制备栅介质层，包括：
使用高介电材料在口袋层上表面沉积第五栅介质层；
使用高介电材料在第五栅介质层上表面的第五指定区域沉积第六栅介质层的第三区域，使用低介电材料在第五栅介质层上表面的第六指定区域沉积第六栅介质层的第四区域，其中，第五指定区域为第五栅介质层上表面中位于源区上方的区域，第六指定区域为第五栅介质层上表面中位于沟道区上方的区域，高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料，低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料；
其中，栅介质层由第五栅介质层和第六栅介质层组成。
在另一个实施例中，在栅介质层的上表面制备栅区之后，还包括：
在口袋层、栅介质层和栅区两侧制备隔离墙；
在源区、栅区和漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极，隔离墙用于隔离金属源电极、金属栅电极及金属漏电极。
需要说明的是，上述所有可选技术方案，可以采用任意结合形成本发明的可选实施例，在此不再一一赘述。
结合上述图6所对应实施例的内容，为了便于理解，本发明实施例以制备图2所示的TFET为例，对本发明实施例提供的TFET的制备方法进行详细说明。如图7所示，该TFET的制备方法包括以下步骤：
701、根据隧穿场效应晶体管的类型，对预设衬底进行阱注入，得到与隧穿场效应晶体管的类型匹配的半导体衬底。
其中，预设衬底为本征半导体。当隧穿场效应晶体管的类型不同时，在对预设衬底进行阱注入时，注入的杂质的类型也不同。例如，如果TFET为N型，则对预设衬底进行阱注入时，注入的掺杂类型为P型杂质，如B(硼)或Ga(镓)等，以得到P型阱，即P型半导体衬底。如果TFET为P型，则对预设衬底进行阱注入时，注入的掺杂类型为N型杂质，如P(磷)或As(砷)等，以得到N型阱，即N型半导体衬底。
如图8所示，其示出了一种半导体衬底的示意图。该半导体衬底的材料已在上述各个实施例中进行了说明，具体可参见上述各个实施例中的内容，此处不再赘述。
702、在半导体衬底上制备保护层，在保护层上制备指定形状的牺牲层。
保护层用于在半导体衬底中通过离子注入的方式形成源区和漏区时，保护半导体衬底。牺牲层用于在半导体衬底中通过离子注入的方式形成源区和漏区时，自对准地形成沟道区。其中，指定形状可以为矩形等。
需要说明的是，为了防止后续离子注入时，注入源区和漏区的离子扩散至沟道区中，牺牲层在保护层上的长度大于预设沟道区的长度。例如，预设沟道区的长度为200纳米，则牺牲层的长度可以为250纳米等。如图9所示，其示出了一种保护层和牺牲层的示意图。结合图9，牺牲层下面对应的半导体区域为预设沟道区所在的区域。
具体地，关于制备保护层和牺牲层的方式，可以有很多种。例如，可以通过沉积生长的方式在半导体衬底上制备保护层，可以通过光刻和刻蚀技术在保护层上制备牺牲层，并定义牺牲层的形状。其中，保护层的材料可以为二氧化 硅等，牺牲层的材料可以为α硅等。
需要说明的是，该步骤为可选步骤，用于在后续在半导体衬底中进行离子注入时保护半导体衬底。当然，此处仅以生成保护层和牺牲层为例对保护半导体衬底的方式进行了说明，然而，在具体实施时，也可以采用其它方式实现。
703、利用光刻技术保护半导体衬底中的预设漏区，对半导体衬底中的预设源区进行第一种离子注入；利用光刻技术保护源区，对预设漏区进行第二种离子注入；对完成离子注入的结构进行快速退火工艺，生成源区和漏区。
在进行第一种离子注入和第二种离子注入时，分别注入的离子的类型与TFET的类型有关。例如，当TFET是N型时，在源区中注入的离子为P型离子，在漏区中注入的离子为N型离子；当TFET是P型时，在源区中注入的离子为N型离子，在漏区中注入的离子为P型离子。
如图10所示，其示出了一种源区和漏区的示意图。图10中，半导体衬底的左半边掺杂区域表示源区，右半边掺杂区域表示漏区。
704、通过刻蚀技术移除保护层和牺牲层，在半导体衬底上表面制备初始口袋层，并对初始口袋层进行刻蚀，得到口袋层。
口袋层与源区组成隧穿场效应晶体管的隧穿结。关于口袋层和源区组成隧穿结时的原理，已在上述实施例中进行了说明，此处不再赘述。关于口袋层的材料也已在上述各个实施例中进行了说明，此处也不再赘述。
其中，对初始口袋层进行刻蚀，得到的口袋层至少覆盖部分源区和部分沟道区。可选地，口袋层不与漏区接触，以能减小TFET漏电的可能性，从而能够提高TFET的性能。
705、使用高介电材料在口袋层上表面沉积第一栅介质层，使用低介电材料在第一栅介质层上表面的第一指定区域沉积第二栅介质层，由第一栅介质层和第二栅介质层组成栅介质层。
其中，第一栅介质层完全覆盖口袋层的上表面，第二栅介质层覆盖第一栅介质层上表面的第一指定区域，该第一指定区域为第一栅介质层上表面位于沟道区上方的区域。
具体地，在使用高介电材料在口袋层上表面沉积第一栅介质层，使用低介电材料在第一栅介质层上表面的第一指定区域沉积第二栅介质层时，包括但不限于通过如下两种方式来实现：
第一种方式：在步骤704中制备的初始口袋层上表面使用高介电材料沉积 初始第一栅介质层，使用低介电材料在初始第一栅介质层上表面沉积初始第二栅介质层。如图11所示，其示出了一种初始口袋层、初始第一栅介质层和初始第二栅介质层的示意图。由图11可得，初始口袋层完全覆盖半导体衬底的上表面，初始第一栅介质层完全覆盖初始口袋层，初始第二栅介质层完全覆盖初始第一栅介质层。然后，利用光刻和刻蚀技术对初始第二栅介质层进行刻蚀，以对第二栅介质层的形状进行定义，刻蚀掉初始第二栅介质层上表面位于源区上方的区域，得到刻蚀后的初始第二栅介质层。其中，刻蚀后的初始第二栅介质层的边缘与源区对齐或稍有重叠，该重叠尺寸可以为1纳米至5纳米之间。如图12所示，其示出了一种刻蚀后的初始第二栅介质层的示意图。最后，在根据预设口袋层的形状、预设第一栅介质层的形状和预设第二栅介质层的形状，对初始口袋层、初始第一栅介质层和刻蚀后的初始第二栅介质层进行进一步刻蚀后，可以得到口袋层、第一栅介质层和第二栅介质层。另外，在该种方式下，步骤705中制备得到的口袋层为在该步骤中通过对初始口袋层进行刻蚀得到的，即步骤705仅需制备初始口袋层即可。
第二种方式：直接在口袋层上表面使用高介电材料沉积第一栅介质层，并在第一栅介质层上预先设置的第一指定区域使用低介电材料沉积第二栅介质层。
通过该种方式制备第一栅介质层和第二栅介质层时，能够节省刻蚀工艺，从而能够节省工艺流程。
706、在栅介质层的上表面制备栅区。
关于栅区的材料已在上述实施例中进行了说明，此处不再赘述。
结合上述步骤705中制备第一栅介质层和第二栅介质层的两种方式，在栅介质层上表面制备栅区时，也可以有两种方式：
第一种方式：该种方式与步骤705中的第一种方式对应。
具体地，在刻蚀后的初始第二栅介质层上表面及未被刻蚀后的初始第二栅介质层覆盖的初始第一栅介质层上表面制备初始栅区。如图13所示，其示出了一种初始口袋层、初始第一栅介质层、刻蚀后的初始第二栅介质层和初始栅区的示意图。然后，根据预设口袋层的形状、预设第一栅介质层的形状、预设第二栅介质层的形状和预设栅区的形状，对初始口袋层、初始第一栅介质层、刻蚀后的初始第二栅介质层和初始栅区进行刻蚀，分别得到口袋层、第一栅介质层、第二栅介质层和栅区。
具体地，在对初始口袋层、初始第一栅介质层、刻蚀后的初始第二栅介质层和初始栅区进行刻蚀时，可以结合光刻和各向异性刻蚀技术，依次对初始口袋层、初始第一栅介质层、刻蚀后的初始第二栅介质层和初始栅区进行刻蚀。
另外，在该种方式下，步骤705中制备得到的口袋层为在该步骤中通过对初始口袋层进行刻蚀得到的，即步骤705仅需制备初始口袋层即可。第一栅介质层和第二栅介质层也为该步骤中通过分别对初始第一栅介质层和刻蚀后的初始第二栅介质层进行刻蚀得到的，即步骤706仅需制备到初始第一栅介质层和刻蚀后的初始第二栅介质层即可。
第二种方式：该种方式与步骤705中的第二种方式对应。
具体地，该种方式直接在栅介质层上表面沉积栅区，该栅区完全覆盖栅介质层的上表面。
707、在口袋层、栅介质层和栅区两侧制备隔离墙。
其中，隔离墙的材料为绝缘材料，如氮化硅等。具体地，可以通过各向异性刻蚀技术在口袋层、栅介质层和栅区两侧制备隔离墙。该隔离墙用于隔离后续制备的金属源电极、金属栅电极及金属漏电极，从而避免短路。如图14所示，其示出了一种隔离墙的示意图。
708、在隔离墙及栅区外侧填充低介电材料，并在源区、栅区和漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极。
其中，低介电材料可以为二氧化硅或氮化硅等。通过填充低介电材料，可以防止TFET的寄生电容比较大。另外，通过低介电材料，能对金属源电极、金属栅电极和金属漏电极起到很好的机械支撑作用。
另外，关于指定位置的内容已在上述各实施例中进行了说明，具体可参见上述实施例中的内容，此处不再赘述。
本发明实施例提供的TFET的制备方法，通过设置栅介质层第一区域为第一栅介质层位于源区上方的区域，第二区域为第一栅介质层位于沟道区上方的区域及第二栅介质层，使得栅介质层在第一区域的厚度显然小于第二区域的厚度，以及通过设置第一栅介质层的材料为高介电材料，第二栅介质层的材料为低介电材料，使得栅介质层第一区域的平均相对介电常数大于第二区域的平均相对介电常数，而栅介质层的栅电容与厚度成反比，而与其材料的相对介电常数成正比，从而使得栅介质层第一区域的栅电容大于第二区域的栅电容，从而使得位于源区上方的栅介质层的栅电容大于位于沟道区上方的栅介质层的栅 电容，使得在相同栅压下，栅压对线隧穿结的调控能力强于对点隧穿结的调控能力。因此，点隧穿结所需的开启电压相对增大，因而能够延缓或者推迟点隧穿结的开启，从而保证线隧穿能够主宰整个器件的开启，确保TFEF具有比较陡峭的亚阈值特性，使得TFET的功耗降低。
结合上述图6所对应实施例的内容，为了便于理解，本发明实施例以制备图3所示的TFET为例，对本发明实施例提供的TFET的制备方法进行详细说明。如图15所示，该制备方法包括以下步骤：
1501、根据隧穿场效应晶体管的类型，对预设衬底进行阱注入，得到与隧穿场效应晶体管的类型匹配的半导体衬底。
该步骤的原理同步骤701中的原理一致，具体可参见步骤701中的内容，此处不再赘述。
1502、在半导体衬底上制备保护层，在保护层上制备指定形状的牺牲层。
该步骤的原理同步骤702中的原理一致，具体可参见步骤702中的内容，此处不再赘述。
1503、利用光刻技术保护半导体衬底中的预设漏区，对半导体衬底中的预设源区进行第一种离子注入；利用光刻技术保护源区，对预设漏区进行第二种离子注入；对完成离子注入的结构进行快速退火工艺，生成源区和漏区。
该步骤的原理同步骤703中的原理一致，具体可参见步骤703中的内容，此处不再赘述。
1504、通过刻蚀技术移除保护层和牺牲层，在半导体衬底上表面制备初始口袋层，并对初始口袋层进行刻蚀，得到口袋层。
该步骤的原理同步骤704中的原理一致，具体可参见步骤704中的内容，此处不再赘述。
1505、使用低介电材料在口袋层上表面的第二指定区域沉积第三栅介质层，使用高介电材料在第三栅介质层上表面及口袋层上表面的第三指定区域沉积第四栅介质层，由第三栅介质层和第四栅介质层组成栅介质层。
其中，第三栅介质层覆盖口袋层上表面的第二指定区域，该第二指定区域为口袋层上表面中位于沟道区上方的区域。第四栅介质层覆盖第三栅介质层及口袋层上表面未被第三栅介质层覆盖的第三指定区域，该第三指定区域为口袋层上表面除第二指定区域外的区域。
具体地，在使用低介电材料在口袋层上表面的第二指定区域沉积第三栅介质层，使用高介电材料在第三栅介质层上表面及口袋层上表面的第三指定区域沉积第四栅介质层时，包括但不限于通过如下两种方式来实现：
第一种方式：在步骤1504中制备的初始口袋层上表面使用低介电材料沉积初始第三栅介质层，该初始第三栅介质层完全覆盖步骤1505中的初始口袋层；然后，光刻和刻蚀技术对初始第三栅介质层进行刻蚀，以对第三栅介质层的形状进行定义，刻蚀掉初始第三栅介质层上表面位于源区上方的区域，得到刻蚀后的第三栅介质层。其中，刻蚀后的第三栅介质层的边缘与源区对齐或稍有重叠，该重叠尺寸可以为1纳米至5纳米之间。接下来，在刻蚀后的初始第三栅介质层表面及未被刻蚀后的初始第三栅介质层覆盖的口袋层上表面沉积初始第四栅介质层。最后，根据预设口袋层的形状、预设第三栅介质层的形状和预设第四栅介质层的形状，对初始口袋层、刻蚀后的第三栅介质层和初始第四栅介质层进行进一步刻蚀后，得到口袋层、第三栅介质层和第四栅介质层。另外，在该种方式下，步骤1105中制备得到的口袋层为在该步骤中通过对初始口袋层进行刻蚀得到的，即步骤1105仅需制备初始口袋层即可。
第二种方式：直接在位于沟道区上方的口袋层上表面使用低介电材料沉积第三栅介质层，并使用高介材料在第三栅介质层及口袋层上表面未被第三介质层覆盖的第三指定区域沉积第四栅介质层。
通过该种方式制备第三栅介质层和第四栅介质层时，能够节省刻蚀工艺，从而能够节省工艺流程。
1506、在栅介质层的上表面制备栅区。
结合上述步骤1105中制备第三栅介质层和第四栅介质层的两种方式，在栅介质层上表面制备栅区时，也可以有两种方式：
第一种方式：该种方式与步骤1105中的第一种方式对应。
具体地，在刻蚀后的第三栅介质层上表面制备初始栅区；然后，根据预设口袋层的形状、预设第三栅介质层的形状、预设第四栅介质层的形状和预设栅区的形状，对初始口袋层、刻蚀后的初始第三栅介质层、初始第四栅介质层和初始栅区进行刻蚀，分别得到口袋层、第三栅介质层、第四栅介质层和栅区。
具体地，在对初始口袋层、刻蚀后的初始第三栅介质层、初始第四栅介质层和初始栅区进行刻蚀时，可以结合光刻和各向异性刻蚀技术，依次对初始口袋层、刻蚀后的初始第三栅介质层、第二四栅介质层和初始栅区进行刻蚀。
另外，在该种方式下，步骤1105中制备得到的口袋层为在该步骤中通过对初始口袋层进行刻蚀得到的，即步骤1105仅需制备初始口袋层即可。第三栅介质层和第四栅介质层也为该步骤中通过分别对刻蚀后的初始第三栅介质层和初始第四栅介质层进行刻蚀得到的，即步骤1106仅需制备到初始第一栅介质层和刻蚀后的初始第二栅介质层即可。
第二种方式：该种方式与步骤1105中的第二种方式对应。
具体地，该种方式直接在栅介质层上表面沉积栅区，该栅区完全覆盖栅介质层的上表面。
1507、在口袋层、栅介质层和栅区两侧制备隔离墙。
该步骤的原理同步骤707中的原理一致，具体可参见步骤707中的内容，此处不再赘述。
1508、在隔离墙及栅区外侧填充低介电材料，并在源区、栅区和漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极。
该步骤的原理同步骤708中的原理一致，具体可参见步骤708中的内容，此处不再赘述。
本发明实施例提供的TFET的制备方法，通过设置栅介质层的第一区域为第四栅介质层位于源区上方的区域，栅介质层的第二区域为第三栅介质层及第四栅介质层位于沟道区上方的区域，使得栅介质层在第一区域的厚度显然小于第二区域的厚度，以及通过设置第三栅介质层的材料为低介电材料，第四栅介质层的材料为高介电材料，使得栅介质层第一区域的平均相对介电常数大于第二区域的平均相对介电常数，而栅介质层的栅电容与厚度成反比，而与其材料的相对介电常数成正比，从而使得栅介质层第一区域的栅电容大于第二区域的栅电容，使得在相同栅压下，栅压对线隧穿结的调控能力强于对点隧穿结的调控能力。因此，点隧穿结所需的开启电压相对增大，因而能够延缓或者推迟点隧穿结的开启，从而保证线隧穿能够主宰整个器件的开启，确保TFEF具有比较陡峭的亚阈值特性，使得TFET的功耗降低。
结合上述图6所对应实施例的内容，为了便于理解，本发明实施例以制备图4所示的TFET为例，对本发明实施例提供的TFET的制备方法进行详细说明。如图16所示，该制备方法包括以下步骤：
1601、根据隧穿场效应晶体管的类型，对预设衬底进行阱注入，得到与隧 穿场效应晶体管的类型匹配的半导体衬底。
该步骤的原理同步骤701中的原理一致，具体可参见步骤701中的内容，此处不再赘述。
1602、在半导体衬底上制备保护层，在保护层上制备指定形状的牺牲层。
该步骤的原理同步骤702中的原理一致，具体可参见步骤702中的内容，此处不再赘述。
1603、利用光刻技术保护半导体衬底中的预设漏区，对半导体衬底中的预设源区进行第一种离子注入；利用光刻技术保护源区，对预设漏区进行第二种离子注入；对完成离子注入的结构进行快速退火工艺，生成源区和漏区。
该步骤的原理同步骤703中的原理一致，具体可参见步骤703中的内容，此处不再赘述。
1604、通过刻蚀技术移除保护层和牺牲层，在半导体衬底上表面制备初始口袋层，并对初始口袋层进行刻蚀，得到口袋层。
该步骤的原理同步骤704中的原理一致，具体可参见步骤704中的内容，此处不再赘述。
1605、使用高介电材料在口袋层的上表面沉积初始栅介质层，并对初始栅介质层的第四指定区域进行减薄，得到栅介质层。
其中，初始栅介质层完全覆盖口袋层，第四指定区域为初始栅介质层位于源区上方的区域。具体地，在对始栅介质层的第四指定区域进行减薄时，可以结合光刻和刻蚀技术实现。
在本发明实施例中，在使用高介电材料在口袋层的上表面沉积初始栅介质层时，可以通过如下两种方式来实现：
第一种方式：在步骤1604中制备得到的初始口袋层上表面使用高介电材料沉积原始栅介质层；接着，根据预设口袋层的形状和预设栅介质层的形状，对初始口袋层和原始栅介质层进行刻蚀，得到口袋层和初始栅介质层。
第二种方式；直接在口袋层上方沉积指定厚度的初始栅介质层。
1606、在栅介质层的上表面制备栅区。
其中，该栅区覆盖栅介质层上表面的整个区域。
1607、在口袋层、栅介质层和栅区两侧制备隔离墙。
该步骤的原理同步骤707中的原理一致，具体可参见步骤707中的内容，此处不再赘述。
1608、在隔离墙及栅区外侧填充低介电材料，并在源区、栅区和漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极。
该步骤的原理同步骤708中的原理一致，具体可参见步骤708中的内容，此处不再赘述。
本发明实施例提供的TFET的制备方法，通过设置栅介质层的第一区域的厚度小于第二区域的厚度，而栅介质层的栅电容与厚度成反比，从而使得栅介质层第一区域的栅电容大于第二区域的栅电容，从而使得位于源区上方的栅介质层的栅电容大于位于沟道区上方的栅介质层的栅电容，使得相对于源区与沟道区上的栅介质层具有相同栅电压的情况，减小了栅极对于点隧穿结的调控能力，进而增加了由源区与口袋层形成的点隧穿所需的开启电压，因而能够延缓或者推迟点隧穿的开启，使得线隧穿主宰整个器件的开启，确保TFEF具有比较陡峭的亚阈值特性，进而使得TFET的功耗比较小。
结合上述图6所对应实施例的内容，为了便于理解，本发明实施例以制备图5所示的TFET为例，对本发明实施例提供的TFET的制备方法进行详细说明。如图17所示，该制备方法包括以下步骤：
1701、根据隧穿场效应晶体管的类型，对预设衬底进行阱注入，得到与隧穿场效应晶体管的类型匹配的半导体衬底。
该步骤的原理同步骤701中的原理一致，具体可参见步骤701中的内容，此处不再赘述。
1702、在半导体衬底上制备保护层，在保护层上制备指定形状的牺牲层。
该步骤的原理同步骤702中的原理一致，具体可参见步骤702中的内容，此处不再赘述。
1703、利用光刻技术保护半导体衬底中的预设漏区，对半导体衬底中的预设源区进行第一种离子注入；利用光刻技术保护源区，对预设漏区进行第二种离子注入；对完成离子注入的结构进行快速退火工艺，生成源区和漏区。
该步骤的原理同步骤703中的原理一致，具体可参见步骤703中的内容，此处不再赘述。
1704、通过刻蚀技术移除保护层和牺牲层，在半导体衬底上表面制备初始口袋层，并对初始口袋层进行刻蚀，得到口袋层。
该步骤的原理同步骤704中的原理一致，具体可参见步骤704中的内容， 此处不再赘述。
1705、使用高介电材料在口袋层上表面沉积第五栅介质层，使用高介电材料在第五栅介质层上表面的第五指定区域沉积第六栅介质层的第三区域，使用低介电材料在第五栅介质层上表面的第六指定区域沉积第六栅介质层的第四区域，由第三区域和第四区域组成第六栅介质层，由第五栅介质层和第六栅介质层组成栅介质层。
其中，第五指定区域为第五栅介质层上表面中位于源区上方的区域，第六指定区域为第五栅介质层上表面中位于沟道区上方的区域。
具体地，在使用高介电材料在口袋层上表面沉积第五栅介质层，使用高介电材料在第五栅介质层上表面的第五指定区域沉积第六栅介质层的第三区域，使用低介电材料在第五栅介质层上表面的第六指定区域沉积第六栅介质层的第四区域时，包括但不限于通过如下两种方式来实现：
第一种方式：在步骤1604中制备的初始口袋层上表面使用高介电材料沉积初始第五栅介质层，使用高介电材料在初始第五栅介质层上表面的第五指定区域沉积初始第六栅介质层的第三区域，使用使用低介电材料在初始第五栅介质层上表面的第六指定区域沉积初始第六栅介质层的第四区域，由初始第六栅介质层的第三区域和初始第六栅介质层的第四区域组成初始第六栅介质层。然后，利用光刻和刻蚀技术对初始口袋层、初始第五栅介质层和初始第六栅介质层进行刻蚀，得到口袋层、第五栅介质层和第六栅介质层。在该种方式下，步骤1705中制备得到的口袋层为在该步骤中通过对初始口袋层进行刻蚀得到的，即步骤1705仅需制备初始口袋层即可。
第二种方式：直接在口袋层上表面使用高介电材料沉积第五栅介质层，在第五栅介质层上的第五指定区域沉积第六栅介质层的第三区域，使用使用低介电材料在初始第五栅介质层上表面的第六指定区域沉积第六栅介质层的第四区域。
1706、在栅介质层的上表面制备栅区。
结合上述步骤1705中制备第五栅介质层和第六栅介质层的两种方式，在栅介质层上表面制备栅区时，也可以有两种方式：
第一种方式：该种方式与步骤1705中的第一种方式对应。
具体地，在初始第六栅介质层上表面沉积初始栅区；然后，预设口袋层的形状、预设第五栅介质层的形状、预设第六栅介质层的形状和预设栅区的形状， 对初始口袋层、初始第一五栅介质层、初始第六栅介质层和初始栅区进行刻蚀，分别得到口袋层、第五栅介质层、第六栅介质层和栅区。
具体地，在对初始口袋层、初始第一五栅介质层、初始第六栅介质层和初始栅区进行刻蚀时，可以结合光刻和各向异性刻蚀技术，依次对初始口袋层、初始第一五栅介质层、初始第六栅介质层和初始栅区进行刻蚀。
另外，在该种方式下，步骤1705中制备得到的口袋层为在该步骤中通过对初始口袋层进行刻蚀得到的，即步骤1705仅需制备初始口袋层即可。第五栅介质层和第六栅介质层也为该步骤中通过分别对初始第五栅介质层和初始第六栅介质层进行刻蚀得到的，即步骤1706仅需制备到初始第五栅介质层和初始第六栅介质层即可。
第二种方式：该种方式与步骤1705中的第二种方式对应。
该种方式直接在第六栅介质层表面沉积栅区。
需要说明的是，该实施例仅以第五栅介质层位于第六栅介质层的下方为例进行了说明。然而，在具体实施时，第五栅介质层也可以位于第六栅介质层的上方。
1707、在口袋层、栅介质层和栅区两侧制备隔离墙。
该步骤的原理同步骤707中的原理一致，具体可参见步骤707中的内容，此处不再赘述。
1708、在隔离墙及栅区外侧填充低介电材料，并在源区、栅区和漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极。
该步骤的原理同步骤708中的原理一致，具体可参见步骤708中的内容，此处不再赘述。
本发明实施例提供的TFET的制备方法，通过设置第五栅介质层的材料及第六栅介质层第三区域的材料为高介电材料，第六栅介质层第四区域的材料为低介电材料，使得栅介质层第一区域的平均相对介电常数大于第二区域的平均相对介电常数，而栅介质层的栅电容与其材料的相对介电常数成正比，从而使得栅介质层第一区域的栅电容大于第二区域的栅电容，从而使得位于源区上方的栅介质层的栅电容大于位于沟道区上方的栅介质层的栅电容，使得在相同栅压下，栅压对线隧穿结的调控能力强于对点隧穿结的调控能力。因此，点隧穿结所需的开启电压相对增大，因而能够延缓或者推迟点隧穿结的开启，从而保证线隧穿能够主宰整个器件的开启，确保TFEF具有比较陡峭的亚阈值特性， 使得TFET的功耗降低。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (15)

  1. 一种隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管包括源区、漏区、沟道区、口袋层、栅介质层和栅区，其中：
    所述源区和所述漏区分离地设置于半导体衬底内部，所述沟道区连接所述源区和所述漏区；
    所述口袋层设置于所述源区和所述沟道区的上表面，所述栅介质层设置于所述口袋层的上表面，所述栅区设置于所述栅介质层的上表面，所述栅介质层包括第一区域和第二区域，所述第一区域为位于所述源区上方的栅介质层区域，所述第二区域为位于所述沟道区上方的栅介质层区域，所述第一区域的栅电容大于所述第二区域的栅电容；
    其中，所述口袋层与所述源区组成所述隧穿场效应晶体管的隧穿结。
  2. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，所述栅介质层由第一栅介质层和第二栅介质层组成；所述第一栅介质层完全覆盖所述口袋层的上表面，所述第二栅介质层覆盖所述第一栅介质层上表面的第一指定区域，所述第一指定区域为所述第一栅介质层上表面中位于所述沟道区上方的区域；
    其中，所述第一栅介质层的材料为高介电材料，所述第二栅介质层的材料为低介电材料，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料，所述低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料。
  3. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，所述栅介质层由第三栅介质层和第四栅介质层组成；所述第三栅介质层覆盖所述口袋层上表面的第二指定区域，所述第二指定区域为所述口袋层上表面中位于所述沟道区上方的区域；所述第四栅介质层完全覆盖所述第三栅介质层的上表面及所述口袋层上表面的第三指定区域，所述第三指定区域为所述口袋层上表面除所述第二指定区域外的区域；
    其中，所述第三栅介质层的材料为低介电材料，所述第四栅介质层的材料为高介电材料，所述低介电材料是指相对介电常数小于二氧化硅的相对介电常 数的介电材料，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料。
  4. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，所述第一区域的厚度小于所述第二区域的厚度，且所述第一区域和所述第二区域的材料为同一高介电材料；
    其中，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料。
  5. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，所述栅介质层由第五栅介质层和第六栅介质层组成；所述第五栅介质层完全覆盖所述口袋层的上表面，所述第六栅介质层完全覆盖所述第五栅介质层的上表面，且所述第六栅介质层包括第三区域和第四区域，所述第三区域为位于所述源区上方的第六栅介质层区域，所述第四区域为位于所述沟道区上方的第六栅介质层区域；
    其中，所述第五栅介质层的材料及所述第三区域的材料为高介电材料，所述第四区域的材料为低介电材料，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料，所述低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料。
  6. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，
    所述口袋层、所述栅介质层和所述栅区两侧制备有隔离墙；
    所述源区、所述栅区和所述漏区的指定位置处分别制备有金属源电极、金属栅电极和金属漏电极，所述隔离墙用于隔离所述金属源电极、所述金属栅电极及所述金属漏电极。
  7. 根据权利要求1至6中任一权利要求所述的隧穿场效应晶体管，其特征在于，
    所述半导体衬底的材料为体硅、绝缘体上的硅、锗硅、锗以及III-V族化合物半导体中的一种；
    所述口袋层的材料为硅、锗硅、锗以及III-V族化合物半导体中的一种；
    所述栅区的材料为多晶硅、金属以及多晶硅与金属的多层复合结构中的一种。
  8. 一种隧穿场效应晶体管的制备方法，其特征在于，所述制备方法包括：
    根据隧穿场效应晶体管的类型，对预设衬底进行阱注入，得到与所述隧穿场效应晶体管的类型匹配的半导体衬底；
    在所述半导体衬底内部分离地制备源区和漏区，并使沟道区连接所述源区和所述漏区；
    在所述源区和所述沟道区的上表面制备口袋层，所述口袋层与所述源区组成所述隧穿场效应晶体管的隧穿结；
    在所述口袋层的上表面制备栅介质层，所述栅介质层包括第一区域和第二区域，所述第一区域为位于所述源区上方的栅介质层区域，所述第二区域为位于所述沟道区上方的栅介质层区域，所述第一区域的栅电容大于所述第二区域的栅电容；
    在所述栅介质层的上表面制备栅区。
  9. 根据权利要求8所述的制备方法，其特征在于，所述在半导体衬底内部分离地制备源区和漏区，包括：
    利用光刻技术保护所述半导体衬底中的预设漏区，对所述半导体衬底中的预设源区进行第一种离子注入；
    利用光刻技术保护所述源区，对所述预设漏区进行第二种离子注入；
    对完成离子注入的结构进行快速退火工艺，生成源区和漏区。
  10. 根据权利要求9所述的制备方法，其特征在于，所述利用光刻技术保护所述半导体衬底中的预设漏区，对所述半导体衬底中的预设源区进行第一种离子注入之前，还包括：
    在所述半导体衬底上制备保护层，所述保护层用于在对所述预设源区和所述预设漏区进行离子注入时，保护所述半导体衬底；
    在所述保护层上制备指定形状的牺牲层，所述牺牲层用于在对所述预设源区和所述预设漏区进行离子注入时，自对准地形成所述沟道区。
  11. 根据权利要求8所述的制备方法，其特征在于，所述在所述口袋层的上表面制备栅介质层，包括：
    使用高介电材料在所述口袋层上表面沉积第一栅介质层，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料；
    使用低介电材料在所述第一栅介质层上表面的第一指定区域沉积第二栅介质层，所述第一指定区域为所述第一栅介质层上表面中位于所述沟道区上方的区域，所述低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料；
    其中，所述栅介质层由所述第一栅介质层和所述第二栅介质层组成。
  12. 根据权利要求8所述的制备方法，其特征在于，所述在所述口袋层的上表面制备栅介质层，包括：
    使用低介电材料在所述口袋层上表面的第二指定区域沉积第三栅介质层，所述第二指定区域为所述口袋层上表面中位于所述沟道区上方的区域，所述低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料；
    使用高介电材料在所述第三栅介质层上表面及所述口袋层上表面的第三指定区域沉积第四栅介质层，所述第三指定区域为所述口袋层上表面除所述第二指定区域外的区域，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料；
    其中，所述栅介质层由所述第三栅介质层和所述第四栅介质层组成。
  13. 根据权利要求8所述的制备方法，其特征在于，所述在所述口袋层的上表面制备栅介质层，包括：
    使用高介电材料在所述口袋层的上表面沉积初始栅介质层；
    对所述初始栅介质层的第四指定区域进行减薄，得到栅介质层，所述第四指定区域为所述初始栅介质层中位于所述源区上方的区域。
  14. 根据权利要求8所述的制备方法，其特征在于，所述在所述口袋层的上表面制备栅介质层，包括：
    使用高介电材料在所述口袋层上表面沉积第五栅介质层；
    使用高介电材料在所述第五栅介质层上表面的第五指定区域沉积第六栅介质层的第三区域，使用低介电材料在所述第五栅介质层上表面的第六指定区域沉积第六栅介质层的第四区域，所述第五指定区域为所述第五栅介质层上表面中位于所述源区上方的区域，所述第六指定区域为所述第五栅介质层上表面中位于所述沟道区上方的区域，所述高介电材料是指相对介电常数大于二氧化硅的相对介电常数的介电材料，所述低介电材料是指相对介电常数小于二氧化硅的相对介电常数的介电材料；
    其中，所述栅介质层由所述第五栅介质层和所述第六栅介质层组成。
  15. 根据权利要求8所述的制备方法，其特征在于，所述在所述栅介质层的上表面制备栅区之后，还包括：
    在所述口袋层、所述栅介质层和所述栅区两侧制备隔离墙；
    在所述隔离墙及所述栅区外侧填充低介电材料；
    在所述源区、所述栅区和所述漏区的指定位置处分别制备金属源电极、金属栅电极和金属漏电极，所述隔离墙用于隔离所述金属源电极、所述金属栅电极及所述金属漏电极。
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