WO2019000416A1 - 一种隧穿场效应晶体管及其制备方法 - Google Patents

一种隧穿场效应晶体管及其制备方法 Download PDF

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WO2019000416A1
WO2019000416A1 PCT/CN2017/091218 CN2017091218W WO2019000416A1 WO 2019000416 A1 WO2019000416 A1 WO 2019000416A1 CN 2017091218 W CN2017091218 W CN 2017091218W WO 2019000416 A1 WO2019000416 A1 WO 2019000416A1
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dielectric layer
sidewall
layer
region
gate
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PCT/CN2017/091218
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English (en)
French (fr)
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徐挽杰
蔡皓程
张臣雄
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华为技术有限公司
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Priority to PCT/CN2017/091218 priority Critical patent/WO2019000416A1/zh
Priority to CN201780003485.1A priority patent/CN109429526B/zh
Publication of WO2019000416A1 publication Critical patent/WO2019000416A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391—Gated diode structures
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    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region

Definitions

  • the present application relates to the field of field effect transistor technologies, and in particular, to a tunneling field effect transistor and a method for fabricating the same.
  • TFET Tunnel Field-Effect Transistor
  • MOSFET Metal-oxide-semiconductor field effect transistor
  • a structure of a TFET having a large overlap region between the gate and the source region When a certain bias voltage is applied to the gate, tunneling between the bands occurs in a direction perpendicular to the gate in the source region (referred to as Line tunneling), because of the small tunneling distance of the line tunneling, a small subthreshold swing and a large tunneling current can be achieved.
  • Line tunneling tunneling between the bands occurs in a direction perpendicular to the gate in the source region
  • the point tunneling is turned on earlier than the line tunneling, thus causing the current of the TFET to change more slowly with the gate bias, ie, the sub-threshold of the TFET The swing characteristics are deteriorated.
  • the present application provides a tunneling field effect transistor and a method of fabricating the same, in which an in-line tunneling structure suppresses point tunneling.
  • a method for fabricating a tunneling field effect transistor includes: forming an isolation structure on a substrate, defining an active region by the isolation structure; forming a first dielectric layer on the substrate on which the isolation structure is formed and a first mask structure covering the first dielectric layer; wherein the first dielectric layer covers a portion of the active region; the first mask structure includes an outer layer and an inner layer, the outer layer includes a first sidewall and a hard mask;
  • the active region is processed to form a drain region; the first filler is used for filling, and a planarization process is performed to expose the inner layer; the inner layer and the first dielectric layer covered by the inner layer are removed; and the exposed active region is exposed Performing a process to form a source region; forming a second dielectric layer on the source region, and the second dielectric layer has a thickness smaller than a thickness of the first dielectric layer; forming a second sidewall, the second sidewall contacting the first sidewall Filling with a second filler, performing a plan
  • the tunneling field effect transistor can be formed such that the thickness of the dielectric layer between the gate and the source region is smaller than the thickness of the dielectric layer between the gate and the channel region, based on which the tunneling field effect transistor can be tunneled based on the line
  • the mechanism works, and the point tunneling between the source region and the channel region can be realized under a large gate bias, thereby suppressing point tunneling, improving subthreshold swing and leakage current characteristics, thereby enabling
  • the tunneling field effect transistor of the present application has a small subthreshold swing and a large tunneling current.
  • the gate is formed in a region where the first sidewall and the second sidewall are removed. Based on the self-alignment manner, the position of the gate can be prevented from being determined by photolithography, thereby reducing process complexity.
  • the method further comprises: epitaxially growing a layer on the surface of the substrate
  • the material of the epitaxial layer is the same as that of the substrate.
  • the tunneling can be limited in the epitaxial layer to reduce the tunneling distance, which can further improve the subthreshold swing and the on-state current.
  • the materials of the first dielectric layer and the second medium are both SiO 2 ; the material of the inner layer is polysilicon; the materials of the outer layer and the second sidewall All are Si 3 N 4 ; the materials of the first filler, the second filler and the protective layer are both SiO 2 . It simplifies the process and reduces costs.
  • forming an isolation structure on the substrate includes: performing photolithography and etching processes on the substrate to form shallow trenches; and forming shallow trenches in the shallow trenches The SiO 2 is filled to form an isolation structure.
  • the method further comprises: using an ion implantation process Doping the active region.
  • the first dielectric layer and the first mask structure covering the first dielectric layer on the substrate formed with the isolation structure include: Forming a first dielectric film on the substrate of the isolation structure, and sequentially depositing an inner layer material and a hard mask material on the first dielectric film, forming an inner layer and an inner layer by photolithography and etching a hard mask; a hard mask material is deposited on the substrate forming the inner layer and the hard mask, and the first sidewall is formed by anisotropic etching; with the hard mask, the first sidewall, and the inner layer
  • the first mask structure is formed as a barrier, and the first dielectric film is etched to form a first dielectric layer.
  • the exposed active region is processed to form a drain region
  • the method includes: covering a region of the N-type tunneling field effect transistor with a first photoresist pattern, performing processing on the exposed active region, forming a drain region corresponding to the N-type tunneling field effect transistor, and removing the first photolithography a rubber pattern; covering a region of the P-type tunneling field effect transistor with a second photoresist pattern, performing processing on the exposed active region, forming a drain region corresponding to the P-type tunneling field effect transistor, and removing the second light
  • the engraved pattern in the case where the N-type and P-type tunneling field effect transistors are simultaneously prepared, the exposed active region is processed to form a source region, including: covering the N-type tunneling with a third photoresist pattern a region of the field effect transistor, performing processing on the exposed active region to form
  • the planarization process comprises a chemical mechanical polishing process.
  • the processing of the exposed active region includes: performing an exposed active region A process of performing an ion implantation process or etching and then epitaxial growth.
  • the material of the substrate is Si; and based on the second dielectric layer is formed on the source region, comprising: using a thermal oxidation method in the source region The surface forms a second dielectric layer.
  • the forming the second sidewall includes: depositing sidewall material on the substrate on which the second dielectric layer is formed, using anisotropic etching The method forms a second sidewall; wherein the material of the second sidewall is the same as the material of the first sidewall.
  • the forming the protective layer comprises: forming a protective layer film and performing chemical mechanical polishing to make the upper surface of the protective layer film flat;
  • the etching method forms a via hole exposing the drain region, the source region, and the gate electrode, so that the first electrode, the second electrode, and the third electrode respectively contact the gate, the drain region, and the source region through the via hole.
  • the gate is a multi-layer structure.
  • the gate of the multilayer structure is optimized in terms of conductivity, work function, and reliability, so that performance can be balanced.
  • a method for fabricating a tunneling field effect transistor comprising: forming an isolation structure on a substrate, defining an active region by the isolation structure; forming a first dielectric layer on the substrate on which the isolation structure is formed; a second mask structure covering the first dielectric layer; wherein the first dielectric layer covers a portion of the active region; processing the exposed active region to form a drain region; filling with the first filler, and planarizing a process of exposing the second mask structure and removing the second mask structure; forming a first sidewall in the region where the second mask structure is removed, removing the exposed first dielectric layer, and exposing after removing the first dielectric layer
  • the active region is processed to form a source region; a second dielectric layer is formed on the source region, and the thickness of the second dielectric layer is smaller than the thickness of the first dielectric layer; forming a second sidewall, the second sidewall and the first sidewall
  • the sidewall contacts and is filled with the second filler, performing a planarization process
  • the tunneling field effect transistor can be formed such that the thickness of the dielectric layer between the gate and the source region is smaller than the thickness of the dielectric layer between the gate and the channel region, based on which the tunneling field effect transistor can be tunneled based on the line
  • the mechanism works, and the point tunneling between the source region and the channel region can be realized under a large gate bias, thereby suppressing point tunneling, improving subthreshold swing and leakage current characteristics, thereby enabling
  • the tunneling field effect transistor of the present application has a small subthreshold swing and a large tunneling current.
  • the gate is formed in a region where the first sidewall and the second sidewall are removed. Based on the self-alignment manner, the position of the gate can be prevented from being determined by photolithography, thereby reducing process complexity.
  • the method further comprises: epitaxially growing an epitaxial layer on the surface of the substrate, and epitaxially
  • the material of the layer is the same as the material of the substrate.
  • the tunneling can be limited in the epitaxial layer to reduce the tunneling distance, which can further improve the subthreshold swing and the on-state current.
  • a tunneling field effect transistor comprising: a substrate having an isolation structure on the substrate, and an active region defined by the isolation structure; the active region including the drain region, the source region, and the drain region and a channel region between the source regions; a dielectric layer disposed above the active region and above the isolation structure, and a dielectric layer thickness above the channel region is greater than a dielectric layer thickness above the source region; a gate and a dummy gate, a gate arrangement Above the active region, the dummy gate is disposed above the isolation structure; the filling layer and the gate, the dummy gate The surface is on the same plane; the protective layer is disposed above the gate, the dummy gate and the filling layer; the first electrode, the second electrode and the third electrode are disposed above the protective layer, the first electrode is in contact with the gate, and the second The electrode and the third electrode are in contact with the drain region and the source region, respectively.
  • the tunneling field effect transistor can be operated based on the line tunneling mechanism, and the point tunneling between the source region and the channel region can be realized under a large gate bias, thereby suppressing point tunneling and improving the sub-channel.
  • the threshold swing and leakage current characteristics allow the tunneling field effect transistor of the present application to have a small subthreshold swing and a large tunneling current.
  • the dielectric layer includes a gate dielectric layer
  • the tunneling field effect transistor further includes an epitaxial layer disposed above the source region and located at the substrate and the gate dielectric layer between.
  • the tunneling can be limited in the epitaxial layer to reduce the tunneling distance, which can further improve the subthreshold swing and the on-state current.
  • FIG. 1 is a schematic flow chart 1 of a method for preparing a TFET according to the present application
  • FIG. 2 is a schematic view of forming an isolation structure on a substrate according to the present application.
  • FIG. 3 is a schematic view showing the formation of a first dielectric layer and a first mask structure on the basis of FIG. 2;
  • Figure 4 is a schematic area showing a drain region on the basis of Figure 3;
  • FIG. 5 is a schematic view showing the filling and planarization process of the first filler on the basis of FIG. 4;
  • Figure 6 is a schematic view showing the removal of the inner layer and the first dielectric layer covered by the inner layer on the basis of Figure 5;
  • Figure 7 is a schematic view showing the formation of a source region on the basis of Figure 6;
  • Figure 8 is a schematic view showing the formation of a second dielectric layer on the surface of the source region on the basis of Figure 7;
  • FIG. 9 is a schematic view showing a second sidewall formed on the basis of FIG. 8 and performing a filling and planarization process of the second filler;
  • Figure 10a is a schematic view of the first side wall, the second side wall and the second dielectric layer removed on the basis of Figure 9;
  • Figure 10b is a schematic view showing the formation of a gate dielectric on the basis of Figure 10a;
  • Figure 10c is a schematic view showing the formation of a gate on the basis of Figure 10b;
  • Figure 11 is a schematic structural view 1 of a TFET provided by the present application.
  • FIG. 12 is a second schematic diagram of a process for preparing a TFET according to the present application.
  • Figure 13 is a schematic view showing the formation of an epitaxial layer on the basis of Figure 10a;
  • FIG. 14 is a schematic structural view 2 of a TFET provided by the present application.
  • Figure 15a is a schematic view showing the formation of a first dielectric film on the basis of Figure 2, and depositing an inner layer material and a hard mask material;
  • Figure 15b is a schematic view showing the formation of an inner layer and a hard mask on the basis of Figure 15a;
  • Figure 15c is a schematic view showing the formation of an inner layer and an outer layer on the basis of Figure 15b;
  • Figure 16 is a schematic view of the second side wall before the filling and planarization process of the second filler on the basis of Figure 8;
  • FIG. 17 is a third schematic diagram of a process for preparing a TFET according to the present application.
  • Figure 18 is a schematic view showing the formation of a first dielectric layer and a second mask structure on the basis of Figure 2;
  • Figure 19 is a schematic area in which a drain region is formed on the basis of Figure 18;
  • FIG. 20 is a schematic view showing the second mask structure after the filling of the first filler and the planarization process are performed on the basis of FIG. 19;
  • Figure 21a is a schematic view showing the second mask structure removed on the basis of Figure 20;
  • FIG. 21b is a schematic view showing the first sidewall being formed on the basis of FIG. 21a, the first dielectric layer being etched by the first sidewall, and then the source region is formed;
  • Figure 22 is a schematic view showing the formation of a second dielectric layer on the surface of the source region on the basis of Figure 21b;
  • FIG. 23 is a schematic view showing a second sidewall formed on the basis of FIG. 22 and performing a filling and planarization process of the second filler;
  • Figure 24a is a schematic view of the first side wall, the second side wall and the second dielectric layer removed on the basis of Figure 23;
  • Figure 24b is a schematic view showing the formation of a gate dielectric and a gate on the basis of Figure 24a;
  • Figure 25 is a schematic structural view 3 of a TFET provided by the present application.
  • FIG. 26 is a schematic structural view 4 of a TFET provided by the present application.
  • FIG. 27 is a fourth schematic diagram of a process for preparing a TFET according to the present application.
  • the present application provides a method for preparing a TFET, as shown in FIG. 1, comprising the following steps:
  • an isolation structure 20 is formed on the substrate 10, and the active region 30 is defined by the isolation structure 20.
  • the material of the substrate 10 may be, for example, silicon (Si), germanium (Ge), a III-V compound semiconductor material, or the like.
  • the active region 30 can be doped (as shown in Figure 2) or undoped. The drawing in the subsequent steps is illustrated with the active region 30 being doped.
  • the doping type may be P-type shallow doping for the N-type tunneling field effect transistor, and the N-type shallow for the P-type tunneling field effect transistor. Doping.
  • N-type shallow doping refers to the incorporation of pentavalent impurity elements (such as phosphorus, arsenic) and the lower dose of impurities incorporated.
  • P-type shallow doping refers to the incorporation of trivalent impurity elements (such as boron) and the lower dose of impurities incorporated.
  • a first dielectric layer 41 and a first mask structure 50 covering the first dielectric layer 41 are formed on the substrate 10 on which the isolation structure 20 is formed; wherein the first dielectric layer 41 has a covered portion
  • the material of the first dielectric layer 41 may be, for example, silicon dioxide (SiO 2 ).
  • the material of the inner layer 52 may be, for example, polysilicon; the material of the outer layer 51 may be, for example, silicon nitride (Si 3 N 4 ).
  • the first side wall 511 is located on the side of the inner layer 52, and the hard mask 512 is located above the inner layer 52.
  • the size of the upper surface of the active region 30 not covered by the first dielectric layer 41 should be the size required for the drain region to be formed.
  • the exposed active region 30 is subjected to a process to form a drain region 31.
  • the first filler is used for filling, and a planarization process is performed to expose the inner layer 52.
  • the material of the first filler may be, for example, SiO 2 .
  • the material of the outer layer 51 and the inner layer 52 and the first dielectric layer 41 should be different to ensure that the first sidewall 511 is left unaffected when the inner layer 52 and the first dielectric layer 41 are removed by etching.
  • the exposed active region 30 is subjected to a process to form a source region 32.
  • the size of the first side wall 511 of the active region 30 the size of the channel region such that the exposed region is the region where the source region 32 is to be formed.
  • a second dielectric layer 42 is formed on the source region 32, and the thickness of the second dielectric layer 42 is smaller than the thickness of the first dielectric layer 41.
  • the material of the second dielectric layer 42 and the first dielectric layer 41 may be the same material.
  • a second sidewall 513 is formed, and the second sidewall 513 is in contact with the first sidewall 511, and is filled with a second filler to perform a planarization process.
  • the material of the second sidewall 513 may be the same as the material of the first sidewall 511.
  • the material of the second filler may be the same as the material of the first filler.
  • the size of the second sidewall 513 should be based on the size of the gate to be formed.
  • the materials of the first dielectric layer 41 and the second dielectric layer 42 are the same. After the second dielectric layer 42 is removed, the thickness of the first dielectric layer 41 is also reduced.
  • the thickness of the gate dielectric layer 43 is equal when the gate dielectric layer 43 is formed. Therefore, it is still ensured that the dielectric layer thickness between the gate electrode 70 and the source region 32 is smaller than the thickness of the dielectric layer between the gate electrode 70 and the channel region.
  • the process of forming the second sidewall 513, filling the second filler, and removing the first sidewall 511 and the second sidewall 513 is also performed. This can be avoided by affecting the second dielectric layer 42 on the source region 32, thereby affecting the performance of the TFET, by removing the second dielectric layer 42 on the source region 32 in this step.
  • the gate dielectric layer 43 and the gate electrode 70 are sequentially formed in a region where the first sidewall 511, the second sidewall 513, and the second dielectric layer 42 are removed.
  • the gate dielectric layer 43 may have a two-layer structure including a SiO 2 layer and an oxidized Ha layer, and the SiO 2 layer is formed adjacent to the substrate 10.
  • the gate 70 has a multilayer structure.
  • the gate of the multilayer structure is optimized in terms of conductivity, work function, and reliability, so that performance can be balanced.
  • a protective layer 80 is formed, and a first electrode 91, a second electrode 92, and a third electrode 92 are formed on the protective layer 80 corresponding to the active region 30; the first electrode 91 is in contact with the gate 70, and the second The electrode 92 and the third electrode 93 are in contact with the drain region 31 and the source region 32, respectively.
  • the material of the protective layer 80 may be a low dielectric constant insulating dielectric material to reduce the inductive coupling between the layers. To simplify the process, the material of the protective layer 80 can be made the same as the material of the first filler and the second filler.
  • the first electrode 91 is electrically connected to the gate 70 through a via located on the protective layer 80 to electrically connect the second electrode 91 through the via layer and the drain layer formed on the protective layer 80 and the filling layer formed by the filling.
  • the regions 31 are in contact to electrically connect the two;
  • the third electrode 93 is in contact with the drain region 31 through a via located on the protective layer 80 and the filling layer formed by filling the filler to electrically connect the two.
  • the gate 70 is also formed over the isolation structure 20, but the gate 70 does not actually play a corresponding role. Therefore, the gate above the isolation structure 20 can be disposed.
  • the pole 70 is referred to as a dummy gate. Based on this, when the electrodes are formed, since it is not necessary to supply power to the dummy gates, it is not necessary to form corresponding electrodes.
  • the drain region 31 is on the left and the source region 32 is shown on the right, but the present application is not limited thereto, and the source region 32 may be left and the drain region 31 may be right.
  • the present application provides a method for fabricating a TFET, which can form a TFET having a dielectric layer thickness between the gate 70 and the source region 32 that is smaller than a thickness of the dielectric layer between the gate 70 and the channel region.
  • the TFET operates based on the line tunneling mechanism and requires a large gate 70 bias to achieve point tunneling between the source region 32 and the channel region, thereby suppressing point tunneling and improving subthreshold swing and Leakage current characteristics allow the TFET of the present application to have a small subthreshold swing and a large tunneling current.
  • the gate electrode 70 is formed in a region where the first sidewall 511 and the second sidewall 513 are removed. According to the self-alignment manner, the position of the gate electrode 70 can be prevented from being determined by photolithography, thereby reducing the process complexity.
  • the above preparation method further includes:
  • an epitaxial layer 100 is epitaxially grown on the surface of the substrate 10.
  • the material of the epitaxial layer 100 is the same as that of the substrate 10.
  • the epitaxial layer 100 may be doped or undoped. In the case where the epitaxial layer 100 is doped, its doping type is opposite to that of the source region 32.
  • a TFET having the structure shown in FIG. 14 can be formed.
  • Embodiment 1 provides a TFET, including:
  • the substrate 10 is subjected to photolithography and etching processes to form shallow trenches; SiO 2 is filled in the shallow trenches to form an isolation structure 20, and the active region 30 is defined by the isolation structure 20.
  • the active region 30 is doped by an ion implantation process.
  • the active region 30 is subjected to P-type shallow doping; and for the P-type TFET, specifically, the active region 30 is subjected to N-type shallow doping.
  • N-type shallow doping refers to the incorporation of pentavalent impurity elements (such as phosphorus, arsenic) and the lower dose of impurities incorporated.
  • P-type shallow doping refers to the incorporation of trivalent impurity elements (such as boron) and the lower dose of impurities incorporated.
  • a first dielectric film 410 is formed on the substrate 10 on which the isolation structure 20 is formed, and an inner layer material and a hard mask are sequentially deposited on the first dielectric film 410.
  • the material is formed by photolithography and etching to form an inner layer 52 and a hard mask 512 on the inner layer 52.
  • the first dielectric film 410 can be formed by deposition (as shown in FIG. 15a).
  • the first dielectric film 410 can also be formed by thermal oxidation growth, but the first dielectric film 410 is a whole layer laid on the substrate 10 (as shown in FIG. 15a), using heat.
  • the first dielectric film 410 is located only in the active region 30.
  • the material of the first dielectric film 410 may be SiO 2 .
  • the inner layer material may be polysilicon and the hard mask material may be Si 3 N 4 .
  • the deposition may be chemical vapor deposition or atomic layer deposition.
  • a hard mask material is deposited, and the first sidewall 511 is formed by anisotropic etching.
  • Anisotropic etching etching only in the vertical direction, and etching in the horizontal direction.
  • the first side wall 511 and the hard mask 512 constitute an outer layer 51.
  • the first dielectric film 410 is etched by the first mask structure 50 composed of the hard mask 512, the first sidewall 511 and the inner layer 52 to form a first dielectric layer. 41.
  • the first dielectric layer 41 covers a portion of the active region 30.
  • a drain region 31 is formed on the exposed active region 30 by an ion implantation process or a process of etching and then epitaxial growth.
  • the first photoresist pattern may be used to cover the region except the N-type TFET, and the exposed active region 30 may be ion-implanted or etched and then epitaxially extended.
  • the growing process forms a drain region 31 corresponding to the N-type TFET and removes the first photoresist pattern.
  • the first photoresist pattern is formed by first forming a layer of photoresist, and then removing the photoresist of the N-type TFET region by photolithography, and the remaining photoresist forms a first photoresist pattern.
  • a second photoresist pattern may be used to cover the region of the P-type TFET, and the exposed active region 30 is formed by an ion implantation process or a first etching and epitaxial growth process to form a drain region 31 corresponding to the P-type TFET, and The second photoresist pattern is removed.
  • the second photoresist pattern is formed in a similar manner to the first photoresist pattern.
  • the first photoresist pattern may be used to cover the region of the P-type TFET, and the exposed active region 30 may be formed by an ion implantation process or a first etching and epitaxial growth process to form a drain region 31 corresponding to the P-type TFET. And removing the first photoresist pattern.
  • the second photoresist pattern may be used to cover the area of the N-type TFET, and the exposed active source In the region 30, a drain region 31 corresponding to the N-type TFET is formed by an ion implantation process or a process of etching and then epitaxial growth, and the second photoresist pattern is removed.
  • the drain region 31 is formed by a process of etching first and then epitaxially growing, specifically: for the exposed active region 30, a portion of the thickness is first etched, and then an epitaxial growth process is performed. The etched portion forms a drain region 31.
  • the first filler is used for filling, and a chemical mechanical polishing process is performed to expose the inner layer 52.
  • the first filler may be filled by a deposition method.
  • the material of the first filler may be SiO 2 . After the chemical mechanical polishing process, the surface of the structure formed on the substrate 10 is flat.
  • the inner layer 52 and the first dielectric layer 41 covered by the inner layer 52 are removed by an etching process.
  • the source region 32 is formed by the ion implantation process or the process of etching and then epitaxial growth on the exposed active region 30.
  • the third photoresist pattern may be used to cover the region except the N-type TFET, and the exposed active 30 region may be ion-implanted or first etched and then extended.
  • the growing process forms a source region 32 corresponding to the N-type TFET and removes the third photoresist pattern.
  • the region of the P-type TFET is covered by the fourth photoresist pattern, and the source region 32 corresponding to the P-type TFET is formed and removed by the ion implantation process or the process of etching and then epitaxially growing the exposed active region 30.
  • the fourth photoresist pattern The third photoresist pattern and the fourth photoresist pattern are formed in a similar manner to the first photoresist pattern.
  • the third photoresist pattern may be used to cover the region of the P-type TFET, and the exposed active region 30 is formed by an ion implantation process or a first etching and epitaxial growth process to form a source region 32 corresponding to the P-type TFET. And removing the third photoresist.
  • the fourth photoresist pattern is used to cover the region except the N-type TFET, and the exposed active region 30 is formed by an ion implantation process or a first etching and epitaxial growth process to form a source region 32 corresponding to the N-type TFET, and removed.
  • the fourth photoresist pattern is used to cover the region except the N-type TFET, and the exposed active region 30 is formed by an ion implantation process or a first etching and epitaxial growth process to form a source region 32 corresponding to the N-type TFET, and removed.
  • the source region 32 is formed by the process of etching and then epitaxially growing the exposed active region 30. Specifically, the exposed active region 30 is first etched away, and then the process is performed by epitaxial growth. The etched portion forms source region 32.
  • a second dielectric layer 42 is formed on the source region 32, and the thickness of the second dielectric layer 42 is smaller than the thickness of the first dielectric layer 41.
  • the second dielectric layer 42 may be formed on the surface of the source region 32 by thermal oxidation.
  • the second dielectric layer 42 and the first dielectric layer 41 are made of the same material.
  • the filling method may be used to fill the second filler.
  • the material of the second filler may be SiO 2 . After the chemical mechanical polishing process, the upper surfaces of the first filler, the second filler, the first sidewall 511, and the second sidewall 513 are flush.
  • the region where the first sidewall 511 and the second sidewall 513 are located is the region where the gate is subsequently formed, so the size of the second sidewall 513 should be the gate to be formed.
  • the size is subject to change.
  • the first sidewall 511 and the second sidewall 513 are removed by an etching process, and the exposed second dielectric layer 42 is removed.
  • the materials of the first dielectric layer 41 and the second dielectric layer 42 are the same. After the second dielectric layer 42 is removed, the thickness of the first dielectric layer 41 is also reduced.
  • the gate dielectric layer 43 and the gate electrode 70 are sequentially formed in a region where the first sidewall 511 and the second sidewall 513 are removed.
  • the gate dielectric film and the gate film can be deposited, and the gate dielectric layer 43 and the gate electrode 70 are formed by photolithography and etching.
  • the gate dielectric layer 43 may have a two-layer structure including a SiO 2 layer and an oxidized Ha layer, and the SiO 2 layer is formed adjacent to the substrate 10.
  • the gate 70 has a multilayer structure.
  • a protective layer film can be formed by a deposition method.
  • the material of the protective layer film may be SiO 2 .
  • the first electrode 91, the second electrode 92, and the third electrode 92 are formed on the protective layer 80 corresponding to the active region 30, so that the first electrode 91 is in contact with the gate 70 through the via hole.
  • the two electrodes 92 and the third electrode 93 are in contact with the drain region 31 and the source region 32 through the via holes, respectively.
  • the gate 70 is also formed over the isolation structure 20, but the gate 70 does not actually play a corresponding role. Therefore, the gate above the isolation structure 20 can be disposed.
  • the pole 70 is referred to as a dummy gate. Based on this, when the electrodes are formed, since it is not necessary to supply power to the dummy gates, it is not necessary to form corresponding electrodes.
  • the second embodiment is different from the first embodiment in that, on the basis of S30-S42, as shown in FIG. 13, an epitaxial layer 100 is epitaxially grown on the surface of the substrate 10, and the material of the epitaxial layer 100 and the material of the substrate 10. the same. Thereafter, similarly to the first embodiment, the gate dielectric layer 43, the gate electrode 70, the protective layer 80, and the first electrode 91, the second electrode 92, and the third electrode 92 (shown in FIG. 14) are formed.
  • the present application also provides a method for preparing a TFET, as shown in FIG. 17, comprising the following steps:
  • an isolation structure 20 is formed on the substrate 10, and the active region 30 is defined by the isolation structure 20.
  • the material of the substrate 10 may be, for example, a Si, Ge, III-V compound semiconductor material or the like.
  • the active region 30 can be doped (as shown in Figure 2) or undoped. The drawing in the subsequent steps is illustrated with the active region 30 being doped.
  • the doping type for the N-type tunneling field effect transistor It may be P-type shallow doping; for P-type tunneling field effect transistors, the doping type may be N-type shallow doping.
  • N-type shallow doping refers to the incorporation of pentavalent impurity elements (such as phosphorus, arsenic) and the lower dose of impurities incorporated.
  • P-type shallow doping refers to the incorporation of trivalent impurity elements (such as boron) and the lower dose of impurities incorporated.
  • a first dielectric layer 41 and a second mask structure 53 covering the first dielectric layer 41 are formed on the substrate 10 on which the isolation structure 20 is formed; wherein the first dielectric layer 41 has a covered portion Source area 30.
  • the material of the first dielectric layer 41 may be, for example, SiO 2 .
  • the material of the second mask structure 53 may be, for example, Si 3 N 4 .
  • the size of the upper surface of the active region 30 not covered by the first dielectric layer 41 should be the size required for the drain region to be formed.
  • the exposed active region 30 is subjected to a process to form a drain region 31.
  • filling is performed using the first filler, and a planarization process is performed to expose the second mask structure 53.
  • the first filler is located only in the region of the substrate 10 that is not covered by the second mask structure 53.
  • the material of the first filler may be, for example, SiO 2 .
  • the size of the first side wall 511 of the active region 30 the size of the channel region such that the exposed region is the region where the source region 32 is to be formed.
  • a second dielectric layer 42 is formed on the source region 32, and the thickness of the second dielectric layer 42 is smaller than the thickness of the first dielectric layer 41.
  • the material of the second dielectric layer 42 and the first dielectric layer 41 may be the same material.
  • the material of the second sidewall 513 may be the same as the material of the first sidewall 511.
  • the material of the second filler may be the same as the material of the first filler.
  • the size of the second sidewall 513 should be based on the size of the gate to be formed.
  • the materials of the first dielectric layer 41 and the second dielectric layer 42 are the same. After the second dielectric layer 42 is removed, the thickness of the first dielectric layer 41 is also reduced.
  • the thickness of the gate dielectric layer 43 is still formed when the gate dielectric layer 43 is formed. Equal, therefore, it is still ensured that the dielectric layer thickness between the gate 70 and the source region 32 is less than the thickness of the dielectric layer between the gate 70 and the channel region.
  • the process of forming the second sidewall 513, filling the second filler, and removing the first sidewall 511 and the second sidewall 513 is also performed. This can be avoided by affecting the second dielectric layer 42 on the source region 32, thereby affecting the performance of the TFET, by removing the second dielectric layer 42 on the source region 32 in this step.
  • the gate dielectric layer 43 and the gate electrode 70 are sequentially formed in a region where the first sidewall 511, the second sidewall 513, and the second dielectric layer 42 are removed.
  • the gate dielectric layer 43 may have a two-layer structure including a SiO 2 layer and an oxidized Ha layer, and the SiO 2 layer is formed adjacent to the substrate 10.
  • the gate 70 may have a multilayer structure.
  • a protective layer 80 is formed, and a first electrode 91, a second electrode 92, and a third electrode 92 are formed on the protective layer 80 corresponding to the active region 30; the first electrode 91 is in contact with the gate 70, The second electrode 92 and the third electrode 93 are in contact with the drain region 31 and the source region 32, respectively.
  • the material of the protective layer 80 may be a low dielectric constant insulating dielectric material to reduce the inductive coupling between the layers. To simplify the process, the material of the protective layer 80 can be made the same as the material of the first filler and the second filler.
  • the first electrode 91 is electrically connected to the gate 70 through a via located on the protective layer 80 to electrically connect the second electrode 91 through the via layer and the drain layer formed on the protective layer 80 and the filling layer formed by the filling.
  • the regions 31 are in contact to electrically connect the two;
  • the third electrode 93 is in contact with the drain region 31 through a via located on the protective layer 80 and the filling layer formed by filling the filler to electrically connect the two.
  • the gate 70 is also formed over the isolation structure 20, but the gate 70 does not actually play a corresponding role. Therefore, the gate above the isolation structure 20 can be disposed.
  • the pole 70 is referred to as a dummy gate. Based on this, when the electrodes are formed, since it is not necessary to supply power to the dummy gates, it is not necessary to form corresponding electrodes.
  • the present application provides a method for fabricating a TFET, which can form a TFET having a dielectric layer thickness between the gate 70 and the source region 32 that is smaller than a thickness of the dielectric layer between the gate 70 and the channel region.
  • the TFET operates based on the line tunneling mechanism and requires a large gate 70 bias to achieve point tunneling between the source region 32 and the channel region, thereby suppressing point tunneling and improving subthreshold swing and Leakage current characteristics allow the TFET of the present application to have a small subthreshold swing and a large tunneling current.
  • the gate electrode 70 is formed in a region where the first sidewall 511 and the second sidewall 513 are removed. According to the self-alignment manner, the position of the gate electrode 70 can be prevented from being determined by photolithography, thereby reducing the process complexity.
  • the above preparation method further includes:
  • an epitaxial layer 100 is epitaxially grown on the surface of the substrate 10.
  • the material of the epitaxial layer 100 is the same as that of the substrate 10.
  • the epitaxial layer 100 may be doped or undoped. In the case where the epitaxial layer 100 is doped, its doping type is opposite to that of the source region 32.
  • Embodiment 3 provides a TFET, including:
  • the substrate 10 is subjected to photolithography and etching processes to form shallow trenches; SiO 2 is filled in the shallow trenches to form an isolation structure 20, and the active region 30 is defined by the isolation structure 20.
  • the active region 30 is doped by an ion implantation process.
  • the active region 30 is subjected to P-type shallow doping; and for the P-type TFET, specifically, the active region 30 is subjected to N-type shallow doping.
  • N-type shallow doping refers to the incorporation of pentavalent impurity elements (such as phosphorus, arsenic) and the lower dose of impurities incorporated.
  • P-type shallow doping refers to the incorporation of trivalent impurity elements (such as boron) and the lower dose of impurities incorporated.
  • a first dielectric layer 41 and a second mask structure 53 covering the first dielectric layer 41 are formed on the substrate 10 on which the isolation structure 20 is formed; wherein the first dielectric layer 41 has a covered portion
  • the source region 30 extends from the active region 30 above the isolation structure 20 to cover a portion of the isolation structure 20.
  • the first dielectric film may be formed by thermal oxidation growth. At this time, the first dielectric film is only located in the active region 30, and the material thereof may be SiO 2 . Thereafter, a film layer may be formed on the first dielectric film by a deposition method, and the material of the film layer may be Si 3 N 4 , and the film layer is photolithographically etched to form a second mask structure 53 . On this basis, the first dielectric film is etched by using the second mask structure 53 as a barrier to form the first dielectric layer 41.
  • the first dielectric film can also be formed by a deposition method.
  • the first dielectric film is a whole layer structure, not only located in the active region 30 but also above the isolation structure 20.
  • a drain region 31 is formed on the exposed active region 30 by an ion implantation process or a process of etching and then epitaxial growth.
  • the first photoresist pattern may be used to cover the region except the N-type TFET, and the exposed active region 30 may be ion-implanted or etched and then epitaxially extended.
  • the growing process forms a drain region 31 corresponding to the N-type TFET and removes the first photoresist pattern.
  • the first photoresist pattern is formed by first forming a layer of photoresist, and then removing the photoresist of the N-type TFET region by photolithography, and the remaining photoresist forms a first photoresist pattern.
  • a second photoresist pattern may be used to cover the region of the P-type TFET, and the exposed active region 30 is formed by an ion implantation process or a first etching and epitaxial growth process to form a drain region 31 corresponding to the P-type TFET, and The second photoresist pattern is removed.
  • the second photoresist pattern is formed in a similar manner to the first photoresist pattern.
  • the first photoresist pattern may be used to cover the region of the P-type TFET, and the exposed active region 30 may be formed by an ion implantation process or a first etching and epitaxial growth process to form a drain region 31 corresponding to the P-type TFET. And removing the first photoresist pattern.
  • a second photoresist pattern may be used to cover the region of the N-type TFET, and the exposed active region 30 is formed by an ion implantation process or a first etching and epitaxial growth process to form a drain region 31 corresponding to the N-type TFET, and The second photoresist pattern is removed.
  • the drain region 31 is formed by a process of etching first and then epitaxially growing, specifically: for the exposed active region 30, a portion of the thickness is first etched, and then an epitaxial growth process is performed. The etched portion forms a drain region 31.
  • filling is performed using the first filler, and a planarization process is performed to expose the second mask structure 53.
  • the first filler may be filled by a deposition method.
  • the material of the first filler may be SiO 2 . After the chemical mechanical polishing process, the first filler and the upper surface of the second mask structure 53 are flush.
  • the second mask structure 53 is removed by an etching process.
  • the third photoresist pattern may be used to cover the region except the N-type TFET, and the exposed active 30 region may be ion-implanted or first etched and then extended.
  • the growing process forms a source region 32 corresponding to the N-type TFET and removes the third photoresist pattern.
  • the region of the P-type TFET is covered by the fourth photoresist pattern, and the source region 32 corresponding to the P-type TFET is formed and removed by the ion implantation process or the process of etching and then epitaxially growing the exposed active region 30.
  • the fourth photoresist pattern The third photoresist pattern and the fourth photoresist pattern are formed in a similar manner to the first photoresist pattern.
  • the third photoresist pattern may be used to cover the region of the P-type TFET, and the exposed active region 30 is formed by an ion implantation process or a first etching and epitaxial growth process to form a source region 32 corresponding to the P-type TFET. And removing the third photoresist.
  • the fourth photoresist pattern is used to cover the region except the N-type TFET, and the exposed active region 30 is formed by an ion implantation process or a first etching and epitaxial growth process to form a source region 32 corresponding to the N-type TFET, and removed.
  • the fourth photoresist pattern is used to cover the region except the N-type TFET, and the exposed active region 30 is formed by an ion implantation process or a first etching and epitaxial growth process to form a source region 32 corresponding to the N-type TFET, and removed.
  • the source region 32 is formed by the process of etching and then epitaxially growing the exposed active region 30. Specifically, the exposed active region 30 is first etched away, and then the process is performed by epitaxial growth. The etched portion forms source region 32.
  • a second dielectric layer 42 is formed on the source region 32, and the thickness of the second dielectric layer 42 is smaller than the thickness of the first dielectric layer 41.
  • the second dielectric layer 42 may be formed on the surface of the source region 32 by thermal oxidation.
  • the second dielectric layer 42 and the first dielectric layer 41 are made of the same material.
  • the filling method may be used to fill the second filler.
  • the material of the second filler may be SiO 2 . After the chemical mechanical polishing process, the upper surfaces of the first filler, the second filler, the first sidewall 511, and the second sidewall 513 are flush.
  • the region where the first sidewall 511 and the second sidewall 513 are located is the region where the gate 70 is subsequently formed, so the size of the second sidewall 513 should be the gate to be formed.
  • the pole size is correct.
  • the first sidewall 511 and the second sidewall 513 are removed by an etching process, and the exposed second dielectric layer 42 is removed.
  • the materials of the first dielectric layer 41 and the second dielectric layer 42 are the same. After the second dielectric layer 42 is removed, the thickness of the first dielectric layer 41 is also reduced.
  • the gate dielectric layer 43 and the gate electrode 70 are sequentially formed in a region where the first sidewall 511 and the second sidewall 513 are removed.
  • the gate dielectric layer 43 may have a two-layer structure including a SiO 2 layer and an oxidized Ha layer, and the SiO 2 layer is formed adjacent to the substrate 10.
  • the gate 70 has a multilayer structure.
  • a protective layer film can be formed by a deposition method.
  • the material of the protective layer film may be SiO 2 .
  • a first electrode 91, a second electrode 92, and a third electrode 92 are formed on the protective layer 80 corresponding to the active region 30, so that the first electrode 91 is in contact with the gate 70 through the via hole.
  • the two electrodes 92 and the third electrode 93 are in contact with the drain region 31 and the source region 32 through the via holes, respectively.
  • the gate 70 is also formed over the isolation structure 20, but the gate 70 does not actually play a corresponding role. Therefore, the gate above the isolation structure 20 can be disposed.
  • the pole 70 is referred to as a dummy gate. Based on this, when the electrodes are formed, since it is not necessary to supply power to the dummy gates, it is not necessary to form corresponding electrodes.
  • the fourth embodiment differs from the third embodiment in that, on the basis of S70-S80, as shown in FIG. 26, an epitaxial layer 100 is epitaxially grown on the surface of the substrate 10, and the material of the epitaxial layer 100 and the material of the substrate 10. the same. Thereafter, similarly to the third embodiment, the gate dielectric layer 43, the gate electrode 70, the protective layer 80, and the first electrode 91, the second electrode 92, and the third electrode 92 are formed.
  • TFET preparation method of the present application is also applicable to the preparation of a TFET of a fin structure, and the drawings of the present application are only illustrated by a planar structure TFET.
  • the present application also provides a TFET which can be prepared by the above preparation method.
  • the TFET includes a substrate 10 having an isolation structure 20 thereon and an active region 30 defined by the isolation structure 20; the active region 30 includes a drain region 31, a source region 32, and between the drain region 31 and the source region 32. a channel region; a dielectric layer disposed over the active region 30 and above the isolation structure 20, and a dielectric layer thickness above the channel region is greater than a dielectric layer thickness above the source region 32; a gate 70 and a dummy gate, a gate 70
  • the dummy gate is disposed above the isolation region 20, and the dummy gate is disposed above the isolation structure 20; the filling layer is on the same plane as the upper surface of the gate 70 and the dummy gate; and the protection layer 80 is disposed on the gate 70 and the dummy gate.
  • the first electrode 91, the second electrode 92 and the third electrode 93 are disposed above the protective layer 80, the first electrode 91 is in contact with the gate, and the second electrode 92 and the third electrode 93 are respectively connected to the drain region 31 and the source region. 32 contacts.
  • the structure of the gate 70 and the dummy gate are completely the same.
  • the gate 70 above the isolation structure 20 is referred to as a dummy gate.
  • the dielectric layer above the active region 30 may include a first dielectric layer 41, a second dielectric layer 42, and a gate dielectric layer 43; the first dielectric layer 41 is located above the channel region.
  • the second dielectric layer 42 is located above the source region 32, and has a spacing between the first dielectric layer 41 and the second dielectric layer 42; in the active region 30, the gate dielectric layer 43 covers the first dielectric layer 41 above the channel region, And covering the spacing between the first dielectric layer 41 and the second dielectric layer 42.
  • the present application provides a TFET that can form a TFET having a dielectric layer thickness between the gate 70 and the source region 32 that is less than a thickness of the dielectric layer between the gate 70 and the channel region, based on which the TFET can be based on a line.
  • the tunneling mechanism works and requires a large gate 70 bias to achieve point tunneling between the source region 32 and the channel region, thereby suppressing point tunneling and improving subthreshold swing and leakage current characteristics.
  • the TFET of the present application can have a small subthreshold swing and a large tunneling current.
  • the gate electrode 70 is formed in a region where the first sidewall 511 and the second sidewall 513 are removed, and the position of the gate 70 can be prevented from being determined by photolithography based on the self-alignment manner, thereby reducing process complexity.
  • the TFET may further include an epitaxial layer 100 disposed above the source region 32 and between the substrate 10 and the gate dielectric layer 43 .
  • the epitaxial layer 100 may be doped or undoped. In the case where the epitaxial layer 100 is doped, its doping type is opposite to that of the source region 32.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种隧穿场效应晶体管及其制备方法，涉及场效应晶体管技术领域，可在线隧穿结构中，抑制点隧穿。隧穿场效应晶体管的制备方法包括：在衬底(10)上形成隔离结构(20)，隔离结构(20)定义出有源区(30)；形成第一介质层(41)和第一掩膜结构(50)；第一掩膜结构(50)包括外层(51)和内层(52)，外层(51)包括第一侧壁(511)和硬掩膜(512)；对露出的有源区(30)进行工艺处理形成漏区(31)；使用第一填充物进行填充进行平坦化工艺，露出内层(52)，以去除内层(52)以及其覆盖的第一介质层(41)；对露出的有源区(30)进行工艺处理形成源区(32)；在源区(32)上形成第二介质层(42)，且第二介质层(42)的厚度小于第一介质层(41)的厚度；形成第二侧壁(513)，使用第二填充物进行填充进行平坦化工艺；去除第一侧壁(511)和第二侧壁(513)、露出的第二介质层(42)，以形成栅介质层(43)和栅极(70)。

Description

一种隧穿场效应晶体管及其制备方法 技术领域
本申请涉及场效应晶体管技术领域，尤其涉及一种隧穿场效应晶体管及其制备方法。
背景技术
隧穿场效应晶体管(Tunnel Field-Effect Transistor，简称TFET)中，载流子以带间隧穿的机制注入沟道中，可以实现比金属-氧化物-半导体场效应晶体管(Metal-Oxide-Semiconductor Field-Effect Transistor，简称MOSFET)更陡峭的电流随栅偏压的变化，具有低功耗、低亚阈值摆幅等特性。
一种TFET的结构，栅极和源区之间有较大的重叠区域，在栅极上施加一定的偏压时，带间隧穿发生在源区内垂直于栅极的方向(称之为线隧穿)，由于线隧穿的隧穿距离较小，可以实现较小的亚阈值摆幅和较大的隧穿电流。
然而，由于存在源区和沟道区之间的点隧穿，点隧穿比线隧穿更早开启，因而会使TFET的电流随栅偏压更缓慢的变化，即，使得TFET的亚阈值摆幅特性变差。
发明内容
本申请提供一种隧穿场效应晶体管及其制备方法，在线隧穿结构中，抑制点隧穿。
第一方面，提供一种隧穿场效应晶体管的制备方法，包括：在衬底上形成隔离结构，由隔离结构定义出有源区；在形成有隔离结构的衬底上形成第一介质层和覆盖第一介质层的第一掩膜结构；其中，第一介质层覆盖部分有源区；第一掩膜结构包括外层和内层，外层包括第一侧壁和硬掩膜；对露出的有源区进行工艺处理，形成漏区；使用第一填充物进行填充，并进行平坦化的工艺，露出内层；去除内层以及内层覆盖的第一介质层；对露出的有源区进行工艺处理，形成源区；在源区上形成第二介质层，且第二介质层的厚度小于第一介质层的厚度；形成第二侧壁，第二侧壁与第一侧壁接触，并使用第二填充物进行填充，进行平坦化的工艺；去除第一侧壁和第二侧壁，并去除露出的第二介质层，在去除第一侧壁、第二侧壁和第二介质层的区域，依次形成栅介质层和栅极；形成保护层，并在保护层上对应有源区形成第一电极、第二电极和第三电极；第一电极与栅极接触，第二电极和第三电极分别与漏区和源区接触。可使形成的隧穿场效应晶体管，其栅极与源区之间的介质层厚度小于栅极与沟道区之间介质层的厚度，基于此，可使隧穿场效应晶体管基于线隧穿机制工作，且需在较大的栅极偏压下，才能实现源区和沟道区之间的点隧穿，因而可以抑制点隧穿，改善亚阈值摆幅和泄漏电流特性，从而可使本申请的隧穿场效应晶体管具有较小的亚阈值摆幅和较大的隧穿电流。其中，栅极在去除第一侧壁和第二侧壁的区域形成，基于自对准方式，可避免栅极的位置通过光刻来决定，因而可减小工艺复杂度。
结合第一方面，在第一方面的第一种可能的实现方式中，在去除第二介质层之后，形成栅介质层之前，该方法还包括：在衬底表面外延生长一层外 延层，外延层的材料与衬底的材料相同。可将隧穿限制在外延层中，减小隧穿距离，可进一步改善亚阈值摆幅和开态电流。
结合第一方面，在第一方面的第二种可能的实现方式中，第一介质层和第二介质的材料均为SiO2；内层的材料为多晶硅；外层和第二侧壁的材料均为Si3N4；第一填充物、第二填充物和保护层的材料均为SiO2。可简化工艺，降低成本。
结合第一方面，在第一方面的第三种可能的实现方式中，在衬底上形成隔离结构，包括:对衬底进行光刻、刻蚀工艺，形成浅沟槽；在浅沟槽中填充SiO2，形成隔离结构。
结合第一方面，在第一方面的第四种可能的实现方式中，在衬底上形成隔离结构之后，形成第一介质层和第一掩膜结构之前，该方法还包括：采用离子注入工艺，对有源区进行掺杂。
结合第一方面，在第一方面的第五种可能的实现方式中，在形成有隔离结构的衬底上第一介质层和覆盖第一介质层的第一掩膜结构，包括：在形成有隔离结构的衬底上形成第一介质薄膜，并在第一介质薄膜上依次沉积一层内层材料和一层硬掩模材料，采用光刻、刻蚀方法形成内层和位于内层上的硬掩膜；在形成内层和硬掩膜的衬底上，沉积硬掩模材料，采用各向异性刻蚀的方法形成第一侧壁；以由硬掩膜、第一侧壁和内层构成的第一掩膜结构为阻挡，对第一介质薄膜进行刻蚀，形成第一介质层。
结合第一方面，在第一方面的第六种可能的实现方式中，在N型和P型隧穿场效应晶体管同时制备的情况下，对露出的有源区进行工艺处理，形成漏区，包括：采用第一光刻胶图案覆盖除N型隧穿场效应晶体管的区域，对露出的有源区进行工艺处理，形成对应N型隧穿场效应晶体管的漏区，并去除第一光刻胶图案；采用第二光刻胶图案覆盖除P型隧穿场效应晶体管的区域，对露出的有源区进行工艺处理，形成对应P型隧穿场效应晶体管的漏区，并去除第二光刻胶图案；在N型和P型隧穿场效应晶体管同时制备的情况下，对露出的有源区进行工艺处理，形成源区，包括：采用第三光刻胶图案覆盖除N型隧穿场效应晶体管的区域，对露出的有源区进行工艺处理，形成对应N型隧穿场效应晶体管的源区，并去除第三光刻胶图案；采用第四光刻胶图案覆盖除P型隧穿场效应晶体管的区域，对露出的有源区进行工艺处理，形成对应P型隧穿场效应晶体管的源区，并去除第四光刻胶图案。
结合第一方面，在第一方面的第七种可能的实现方式中，平坦化工艺，包括化学机械抛光工艺。
结合第一方面、或第一方面的第六种可能的实现方式，在第一方面的第八种可能的实现方式中，对露出的有源区进行工艺处理，包括：对露出的有源区进行离子注入工艺或者先刻蚀再外延生长的工艺。
结合第一方面，在第一方面的第九种可能的实现方式中，衬底的材料为Si；基于此，在源区上形成第二介质层，包括：采用热氧化的方法在源区的表面形成第二介质层。
结合第一方面，在第一方面的第十种可能的实现方式中，形成第二侧壁，包括：在形成有第二介质层的衬底上，沉积侧壁材料，采用各向异性刻蚀的方法形成第二侧壁；其中，第二侧壁的材料与第一侧壁的材料相同。
结合第一方面，在第一方面的第十一种可能的实现方式中，形成保护层，包括：形成保护层薄膜，并进行化学机械抛光，使保护层薄膜的上表面平坦；采用光刻、刻蚀方法，形成露出漏区、源区和栅极的过孔，以使第一电极、第二电极和第三电极分别通过过孔与栅极、漏区和源区接触。
结合第一方面，在第一方面的第十二种可能的实现方式中，栅极为多层结构。多层结构的栅极在导电性、功函数以及可靠性等方面会进行优化，做到各项性能的兼顾。
第二方面，提供一种隧穿场效应晶体管的制备方法，包括：在衬底上形成隔离结构，由隔离结构定义出有源区；在形成有隔离结构的衬底上形成第一介质层和覆盖第一介质层的第二掩膜结构；其中，第一介质层覆盖部分有源区；对露出的有源区进行工艺处理，形成漏区；使用第一填充物进行填充，并进行平坦化工艺，露出第二掩膜结构，并去除第二掩膜结构；在去除第二掩膜结构的区域，形成第一侧壁，去除露出的第一介质层，并对去除第一介质层后露出的有源区进行工艺处理，形成源区；在源区上形成第二介质层，且第二介质层的厚度小于第一介质层的厚度；形成第二侧壁，第二侧壁与第一侧壁接触，并使用第二填充物进行填充，进行平坦化工艺，暴露第一侧壁和第二侧壁；去除第一侧壁和第二侧壁，并去除露出的第二介质层，在去除第一侧壁、第二侧壁和第二介质层的区域，依次形成栅介质层和栅极；形成保护层，并在保护层上对应有源区形成第一电极、第二电极和第三电极；第一电极与栅极接触，第二电极和第三电极分别与漏区和源区接触。可使形成的隧穿场效应晶体管，其栅极与源区之间的介质层厚度小于栅极与沟道区之间介质层的厚度，基于此，可使隧穿场效应晶体管基于线隧穿机制工作，且需在较大的栅极偏压下，才能实现源区和沟道区之间的点隧穿，因而可以抑制点隧穿，改善亚阈值摆幅和泄漏电流特性，从而可使本申请的隧穿场效应晶体管具有较小的亚阈值摆幅和较大的隧穿电流。其中，栅极在去除第一侧壁和第二侧壁的区域形成，基于自对准方式，可避免栅极的位置通过光刻来决定，因而可减小工艺复杂度。
结合第二方面，在第二方面的第一种可能的实现方式中，在去除第二介质层之后，形成栅介质层之前，该方法还包括：在衬底表面外延生长一层外延层，外延层的材料与衬底的材料相同。可将隧穿限制在外延层中，减小隧穿距离，可进一步改善亚阈值摆幅和开态电流。
第三方面，提供一种隧穿场效应晶体管，包括：衬底，衬底上具有隔离结构，并由隔离结构定义出有源区；有源区包括漏区、源区、以及位于漏区和源区之间的沟道区；介质层设置于有源区上方以及隔离结构上方，且沟道区上方的介质层厚度大于源区上方的介质层厚度；栅极和伪栅极，栅极设置于有源区的上方，伪栅极设置于隔离结构上方；填充层与栅极、伪栅极的上 表面在同一平面上；保护层，设置于栅极、伪栅极和填充层上方；第一电极、第二电极和第三电极，设置于保护层上方，第一电极与栅极接触，第二电极和第三电极分别与漏区和源区接触。可使隧穿场效应晶体管基于线隧穿机制工作，且需在较大的栅极偏压下，才能实现源区和沟道区之间的点隧穿，因而可以抑制点隧穿，改善亚阈值摆幅和泄漏电流特性，从而可使本申请的隧穿场效应晶体管具有较小的亚阈值摆幅和较大的隧穿电流。
结合第三方面，在第一方面的第一种可能的实现方式中，介质层包括栅介质层；隧穿场效应晶体管还包括外延层，设置于源区上方且位于衬底与栅介质层之间。可将隧穿限制在外延层中，减小隧穿距离，可进一步改善亚阈值摆幅和开态电流。
附图说明
图1为本申请提供的一种制备TFET的流程示意图一；
图2为本申请提供的一种在衬底上形成隔离结构的示意图；
图3为在图2的基础上形成第一介质层和第一掩膜结构的示意图；
图4为在图3的基础上形成漏区的示意区；
图5为在图4的基础上进行第一填充物的填充以及平坦化工艺后的示意图；
图6为在图5的基础上去除内层以及内层覆盖的第一介质层的示意图；
图7为在图6的基础上形成源区的示意图；
图8为在图7的基础上在源区表面形成第二介质层的示意图；
图9为在图8的基础上形成第二侧壁，并进行第二填充物的填充以及平坦化工艺后的示意图；
图10a为在图9的基础上去除第一侧壁、第二侧壁以及第二介质层后的示意图；
图10b为在图10a的基础上形成栅介质的示意图；
图10c为在图10b的基础上形成栅极的示意图；
图11为本申请提供的一种TFET的结构示意图一；
图12为本申请提供的一种制备TFET的流程示意图二；
图13为在图10a的基础上形成外延层的示意图；
图14为本申请提供的一种TFET的结构示意图二；
图15a为在图2的基础上形成第一介质薄膜、并沉积一层内层材料和一层硬掩模材料后的示意图；
图15b为在图15a的基础上刻蚀形成内层和硬掩膜的示意图；
图15c为在图15b的基础上形成内层和外层的示意图；
图16为在图8的基础上在进行第二填充物的填充以及平坦化工艺之前，第二侧壁的示意图；
图17为本申请提供的一种制备TFET的流程示意图三；
图18在图2的基础上形成第一介质层和第二掩膜结构的示意图；
图19为在图18的基础上形成漏区的示意区；
图20为在图19的基础上进行第一填充物的填充以及平坦化工艺后露出第二掩膜结构的示意图；
图21a为在图20的基础上去除第二掩膜结构后的示意图；
图21b为在图21a的基础上制作第一侧壁、以第一侧壁为阻挡刻蚀第一介质层，然后形成源区的示意图；
图22为在图21b的基础上在源区表面形成第二介质层的示意图；
图23为在图22的基础上形成第二侧壁，并进行第二填充物的填充以及平坦化工艺后的示意图；
图24a为在图23的基础上去除第一侧壁、第二侧壁以及第二介质层后的示意图；
图24b为在图24a的基础上形成栅介质和栅极的示意图；
图25为本申请提供的一种TFET的结构示意图三；
图26为本申请提供的一种TFET的结构示意图四；
图27为本申请提供的一种制备TFET的流程示意图四。
附图标记：
10-衬底；20-隔离结构；30-有源区；31-漏区；32-源区；41-第一介质层；42-第二介质层；43-栅介质层；50-第一掩膜结构；51-外层；52-内层；53-第二掩膜结构；70-栅极；80-保护层；91-第一电极；92-第二电极；93-第三电极；100-外延层；511-第一侧壁；512-硬掩膜；513-第二侧壁。
具体实施方式
本申请提供一种TFET的制备方法，如图1所示，包括如下步骤：
S10、如图2所示，在衬底10上形成隔离结构20，由隔离结构20定义出有源区30。
其中，衬底10的材料例如可以为硅(Si)、锗(Ge)、III-V族化合物半导体材料等。
有源区30可以是掺杂的(如图2所示)，也可以是不掺杂的。后续步骤中的附图以有源区30是掺杂的进行示意。
在有源区30掺杂的情况下，针对N型隧穿场效应晶体管，其掺杂类型可以是P型浅掺杂；针对P型隧穿场效应晶体管，其掺杂类型可以是N型浅掺杂。
N型浅掺杂指的是掺入五价杂质元素(如磷、砷)且掺入的杂质剂量较低。P型浅掺杂指的是掺入三价杂质元素(如硼)且掺入的杂质剂量较低。
S11、如图3所示，在形成有隔离结构20的衬底10上形成第一介质层41和覆盖第一介质层41的第一掩膜结构50；其中，第一介质层41覆盖部分有源区30；第一掩膜结构50包括外层51和内层52，外层51包括第一侧壁511和硬掩膜512。
其中，第一介质层41的材料例如可以为二氧化硅(SiO2)。内层52的材料例如可以为多晶硅；外层51的材料例如可以为氮化硅(Si3N4)。
第一侧壁511位于内层52的侧面，硬掩膜512位于内层52的上方。
需要说明的是，未被第一介质层41覆盖的有源区30上表面的尺寸，应以待形成漏区所需的尺寸为准。
S12、如图4所示，对露出的有源区30进行工艺处理，形成漏区31。
S13、如图5所示，使用第一填充物进行填充，并进行平坦化的工艺，露出内层52。
使用第一填充物进行填充后，由于结构的表面不平坦，需采用平坦化的工艺方法使之平坦化。平坦化过程中会把硬掩膜512磨掉，以暴露出内层52。
其中，第一填充物的材料例如可以为SiO2。
S14、如图6所示，去除内层52以及内层52覆盖的第一介质层41。
其中，外层51与内层52和第一介质层41的材料应不相同，以保证在刻蚀去除内层52和第一介质层41时，第一侧壁511不受影响而被保留。
S15、如图7所示，对露出的有源区30进行工艺处理，形成源区32。
此处，需使位于有源区30的第一侧壁511的尺寸为沟道区的尺寸，从而使暴露出的区域为待形成源区32的区域。
S16、如图8所示，在源区32上形成第二介质层42，且第二介质层42的厚度小于第一介质层41的厚度。
其中，第二介质层42和第一介质层41的材料可以为同一种材料。
S17、如图9所示，形成第二侧壁513，第二侧壁513与第一侧壁511接触，并使用第二填充物进行填充，进行平坦化的工艺。
其中，第二侧壁513的材料可以与第一侧壁511的材料相同。第二填充物的材料可以与第一填充物的材料相同。
需要说明的是，由于第一侧壁511和第二侧壁513所在区域为后续形成栅极的区域，因此，对于第二侧壁513的尺寸应以待形成的栅极尺寸为准。
S18、如图10a所示，去除第一侧壁511和第二侧壁513，并去除露出的第二介质层42。
其中，第一介质层41和第二介质层42的材料相同，在去除第二介质层42后，第一介质层41的厚度也会降低。
由于在去除第一侧壁511和第二侧壁513的区域，去除第二介质层42后，第一介质层41仍保留部分厚度，当形成栅介质层43时，栅介质层43的厚度相等，因此，仍然可保证栅极70与源区32之间的介质层厚度小于栅极70与沟道区之间介质层的厚度。
需要说明的是，由于在形成第二介质层42之后，还经过了形成第二侧壁513、进行第二填充物的填充、以及去除第一侧壁511和第二侧壁513的工艺过程，会对源区32上的第二介质层42造成影响，从而影响TFET的性能，在该步骤中通过去除源区32上的第二介质层42，可避免此问题。
S19、如图10b和图10c所示，在去除第一侧壁511、第二侧壁513和第二介质层42的区域，依次形成栅介质层43和栅极70。
栅介质层43可以为两层结构，包括SiO2层和氧化哈层，SiO2层靠近衬底10形成。
栅极70为多层结构。多层结构的栅极在导电性、功函数以及可靠性等方面会进行优化，做到各项性能的兼顾。
S20、如图11，形成保护层80，并在保护层80上对应有源区30形成第一电极91、第二电极92和第三电极92；第一电极91与栅极70接触，第二电极92和第三电极93分别与漏区31和源区32接触。
其中，保护层80的材料可以为低介电常数的绝缘电介质材料，以减小层间的电感性耦合。为简化工艺，可使保护层80的材料与第一填充物、第二填充物的材料相同。
第一电极91通过位于保护层80上的过孔与栅极70接触从而使二者电连接；第二电极92通过位于保护层80和由填充物填充而形成的填充层上的过孔与漏区31接触从而使二者电连接；第三电极93通过位于保护层80和由填充物填充而形成的填充层上的过孔与漏区31接触从而使二者电连接。
需要说明的是，由于经过S10-S20的工艺之后，也会在隔离结构20上方形成栅极70，但是该栅极70并不实际起相应的作用，因此，可将位于隔离结构20上方的栅极70称为伪栅极。基于此，在形成电极时，由于无需向伪栅极供电，因此，也无需形成相应的电极。
此外，基于图3-图11的剖视图，以漏区31在左，源区32在右进行示意，但本申请并不限于此，也可以是源区32在左，漏区31在右。
本申请提供一种TFET的制备方法，可使形成的TFET，其栅极70与源区32之间的介质层厚度小于栅极70与沟道区之间介质层的厚度，基于此，可使TFET基于线隧穿机制工作，且需在较大的栅极70偏压下，才能实现源区32和沟道区之间的点隧穿，因而可以抑制点隧穿，改善亚阈值摆幅和泄漏电流特性，从而可使本申请的TFET具有较小的亚阈值摆幅和较大的隧穿电流。其中，栅极70在去除第一侧壁511和第二侧壁513的区域形成，基于自对准方式，可避免栅极70的位置通过光刻来决定，因而可减小工艺复杂度。
如图12所示，在去除第二介质层42之后，形成栅介质层43之前，上述制备方法还包括：
S21、如图13所示，在衬底10表面外延生长一层外延层100，外延层100的材料与衬底10的材料相同。
其中，外延层100可以是掺杂的，也可以是不掺杂的。在外延层100掺杂的情况下，其掺杂类型与源区32的掺杂类型相反。
在此基础上，在形成栅介质层43、栅极70、保护层80和第一电极91、第二电极92、第三电极92后，可形成如图14所示结构的TFET。
通过在去除第二介质层42之后，在衬底10表面外延生长一层外延层100，可将隧穿限制在外延层100中，减小隧穿距离，可进一步改善亚阈值摆幅和开态电流。
实施例一，提供一种TFET，具体包括：
S30、如图2所示，对衬底10进行光刻、刻蚀工艺，形成浅沟槽；在浅沟槽中填充SiO2，形成隔离结构20，由隔离结构20定义出有源区30。
S31、如图2所示，采用离子注入工艺，对有源区30进行掺杂。
其中，针对N型TFET，具体为对有源区30进行P型浅掺杂；针对P型TFET，具体为对有源区30进行N型浅掺杂。
N型浅掺杂指的是掺入五价杂质元素(如磷、砷)且掺入的杂质剂量较低。P型浅掺杂指的是掺入三价杂质元素(如硼)且掺入的杂质剂量较低。
S32、如图15a和图15b所示，在形成有隔离结构20的衬底10上形成第一介质薄膜410，并在第一介质薄膜410上依次沉积一层内层材料和一层硬掩模材料，采用光刻、刻蚀方法形成内层52和位于内层52上的硬掩膜512。
具体的，可采用沉积的方法形成第一介质薄膜410(如图15a所示)。当然，也可采用热氧化生长的方法形成第一介质薄膜410，但是相对采用沉积方法，第一介质薄膜410为平铺于衬底10上的一整层(如图15a所示)，采用热氧化生长的方法形成第一介质薄膜410时，第一介质薄膜410仅位于有源区30。
第一介质薄膜410的材料可以为SiO2。
内层材料可以为多晶硅，硬掩模材料可以为Si3N4。
其中，沉积可以是化学气相沉积，也可以是原子层沉积等。
S33、如图15c所示，在形成内层52和硬掩膜512的衬底10上，沉积硬掩模材料，采用各向异性刻蚀的方法形成第一侧壁511。
各向异性刻蚀，只在垂直方向刻蚀，水平方向不刻蚀。
第一侧壁511和硬掩膜512构成外层51。
S34、如图3所示，以由硬掩膜512、第一侧壁511和内层52构成的第一掩膜结构50为阻挡，对第一介质薄膜410进行刻蚀，形成第一介质层41。其中，第一介质层41覆盖部分有源区30。
S35、如图4所示，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成漏区31。
具体的，在N型和P型TFET同时制备的情况下，可先采用第一光刻胶图案覆盖除N型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应N型TFET的漏区31，并去除第一光刻胶图案。其中，第一光刻胶图案的形成方式为：先形成一层光刻胶，再采用光刻方法将N型TFET区域的光刻胶去除，剩余的光刻胶形成第一光刻胶图案。
之后，可采用第二光刻胶图案覆盖除P型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应P型TFET的漏区31，并去除第二光刻胶图案。第二光刻胶图案的形成方式与第一光刻胶图案相似。
或者，可先采用第一光刻胶图案覆盖除P型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应P型TFET的漏区31，并去除第一光刻胶图案。
之后，可采用第二光刻胶图案覆盖除N型TFET的区域，对露出的有源 区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应N型TFET的漏区31，并去除第二光刻胶图案。
其中，对露出的有源区30，利用先刻蚀再外延生长的工艺，形成漏区31，具体为：对露出的有源区30，先刻蚀掉部分厚度，然后通过外延生长的工艺，在刻蚀掉的部分形成漏区31。
S36、如图5所示，使用第一填充物进行填充，并进行化学机械抛光工艺，露出内层52。
具体的，可采用沉积方法进行第一填充物的填充。第一填充物的材料可以为SiO2。经过化学机械抛光工艺后，形成在衬底10上的结构的表面平坦。
S37、如图6所示，采用刻蚀工艺去除内层52以及内层52覆盖的第一介质层41。
S38、如图7所示，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成源区32。
具体的，在N型和P型TFET同时制备的情况下，可先采用第三光刻胶图案覆盖除N型TFET的区域，对露出的有源30区，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应N型TFET的源区32，并去除第三光刻胶图案。
之后，采用第四光刻胶图案覆盖除P型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应P型TFET的源区32，并去除第四光刻胶图案。其中，第三光刻胶图案和第四光刻胶图案的形成方式与第一光刻胶图案相似。
或者，可先采用第三光刻胶图案覆盖除P型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应P型TFET的源区32，并去除第三光刻胶。
之后，采用第四光刻胶图案覆盖除N型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应N型TFET的源区32，并去除第四光刻胶图案。
其中，对露出的有源区30，利用先刻蚀再外延生长的工艺，形成源区32，具体为：对露出的有源区30，先刻蚀掉部分厚度，然后通过外延生长的工艺，在刻蚀掉的部分形成源区32。
S39、如图8所示，在源区32上形成第二介质层42，且第二介质层42的厚度小于第一介质层41的厚度。
具体的，在衬底10的材料为Si的情况下，可采用热氧化的方法在源区32的表面形成第二介质层42。
其中，第二介质层42和第一介质层41的材料相同。
S40、如图16所示，在形成有第二介质层42的衬底上，沉积侧壁材料，采用各向异性刻蚀的方法形成第二侧壁513；第二侧壁513与第一侧壁511接触，且第二侧壁513的材料与第一侧壁511的材料相同。
S41、如图9所示，使用第二填充物进行填充，并进行化学机械抛光工艺。
具体的，可采用沉积方法进行第二填充物的填充。第二填充物的材料可以为SiO2。经过化学机械抛光工艺后，第一填充物、第二填充物、第一侧壁511以及第二侧壁513的上表面齐平。
需要说明的是，由于经过化学机械抛光后，第一侧壁511和第二侧壁513所在区域为后续形成栅极的区域，因此，对于第二侧壁513的尺寸应以待形成的栅极尺寸为准。
S42、如图10a所示，采用刻蚀工艺去除第一侧壁511和第二侧壁513，并去除露出的第二介质层42。
其中，第一介质层41和第二介质层42的材料相同，在去除第二介质层42后，第一介质层41的厚度也会降低。
S43、如图10b和图10c所示，在去除第一侧壁511和第二侧壁513的区域依次形成栅介质层43和栅极70。
具体的，可以此沉积栅介质薄膜和栅极薄膜，采用光刻、刻蚀方法，形成栅介质层43和栅极70。
栅介质层43可以为两层结构，包括SiO2层和氧化哈层，SiO2层靠近衬底10形成。栅极70为多层结构。
S44、如图11所示，形成保护层薄膜，并进行化学机械抛光，使保护层薄膜的上表面平坦；采用光刻、刻蚀方法形成包括露出漏区31、源区32和栅极70的过孔的保护层80。
具体的，可采用沉积方法形成保护层薄膜。保护层薄膜的材料可以为SiO2。
S45、如图11所示，在保护层80上对应有源区30形成第一电极91、第二电极92和第三电极92，以使第一电极91通过过孔与栅极70接触，第二电极92和第三电极93分别通过过孔与漏区31和源区32接触。
需要说明的是，由于经过S30-S45的工艺之后，也会在隔离结构20上方形成栅极70，但是该栅极70并不实际起相应的作用，因此，可将位于隔离结构20上方的栅极70称为伪栅极。基于此，在形成电极时，由于无需向伪栅极供电，因此，也无需形成相应的电极。
实施例二，与实施例一的不同在于，在S30-S42的基础上，如图13所示，在衬底10表面外延生长一层外延层100，外延层100的材料与衬底10的材料相同。之后，与实施例一类似，形成栅介质层43、栅极70、保护层80和第一电极91、第二电极92、第三电极92(如图14所示)。
本申请还提供一种TFET的制备方法，如图17所示，包括如下步骤：
S50、参考图2所示，在衬底10上形成隔离结构20，由隔离结构20定义出有源区30。
其中，衬底10的材料例如可以为Si、Ge、III-V族化合物半导体材料等。
有源区30可以是掺杂的(如图2所示)，也可以是不掺杂的。后续步骤中的附图以有源区30是掺杂的进行示意。
在有源区30掺杂的情况下，针对N型隧穿场效应晶体管，其掺杂类型 可以是P型浅掺杂；针对P型隧穿场效应晶体管，其掺杂类型可以是N型浅掺杂。
N型浅掺杂指的是掺入五价杂质元素(如磷、砷)且掺入的杂质剂量较低。P型浅掺杂指的是掺入三价杂质元素(如硼)且掺入的杂质剂量较低。
S51、如图18所示，在形成有隔离结构20的衬底10上形成第一介质层41和覆盖第一介质层41的第二掩膜结构53；其中，第一介质层41覆盖部分有源区30。
其中，第一介质层41的材料例如可以为SiO2。第二掩膜结构53的材料例如可以为Si3N4。
需要说明的是，未被第一介质层41覆盖的有源区30上表面的尺寸，应以待形成漏区所需的尺寸为准。
S52、如图19所示，对露出的有源区30进行工艺处理，形成漏区31。
S53、如图20所示，使用第一填充物进行填充，并进行平坦化工艺，露出第二掩膜结构53。
即，经过平坦化工艺后，第一填充物仅位于衬底10的未被第二掩膜结构53覆盖的区域。
其中，第一填充物的材料例如可以为SiO2。
S54、如图21a所示，去除第二掩膜结构53。
S55、如图21b所示，在去除第二掩膜结构53的区域，形成第一侧壁511，去除露出的第一介质层41，并对去除第一介质层41后露出的有源区30进行工艺处理，形成源区32。
此处，需使位于有源区30的第一侧壁511的尺寸为沟道区的尺寸，从而使暴露出的区域为待形成源区32的区域。
S56、如图22所示，在源区32上形成第二介质层42，且第二介质层42的厚度小于第一介质层41的厚度。
其中，第二介质层42和第一介质层41的材料可以为同一种材料。
S57、如图23所示，形成第二侧壁513，第二侧壁513与第一侧壁511接触，并使用第二填充物进行填充，进行平坦化的工艺，暴露第一侧壁511和第二侧壁513。
其中，第二侧壁513的材料可以与第一侧壁511的材料相同。第二填充物的材料可以与第一填充物的材料相同。
需要说明的是，由于第一侧壁511和第二侧壁513所在区域为后续形成栅极的区域，因此，对于第二侧壁513的尺寸应以待形成的栅极尺寸为准。
S58、如图24a所示，去除第一侧壁511和第二侧壁513，并去除露出的第二介质层42。
其中，第一介质层41和第二介质层42的材料相同，在去除第二介质层42后，第一介质层41的厚度也会降低。
由于在去除第一侧壁511和第二侧壁513的区域，去除第二介质层42后，第一介质层41仍保留部分厚度，当形成栅介质层43时，栅介质层43的厚度 相等，因此，仍然可保证栅极70与源区32之间的介质层厚度小于栅极70与沟道区之间介质层的厚度。
需要说明的是，由于在形成第二介质层42之后，还经过了形成第二侧壁513、进行第二填充物的填充、以及去除第一侧壁511和第二侧壁513的工艺过程，会对源区32上的第二介质层42造成影响，从而影响TFET的性能，在该步骤中通过去除源区32上的第二介质层42，可避免此问题。
S59、如图24b所示，在去除第一侧壁511、第二侧壁513和第二介质层42的区域，依次形成栅介质层43和栅极70。
栅介质层43可以为两层结构，包括SiO2层和氧化哈层，SiO2层靠近衬底10形成。栅极70可以为多层结构。
S60、如图25所示，形成保护层80，并在保护层80上对应有源区30形成第一电极91、第二电极92和第三电极92；第一电极91与栅极70接触，第二电极92和第三电极93分别与漏区31和源区32接触。
其中，保护层80的材料可以为低介电常数的绝缘电介质材料，以减小层间的电感性耦合。为简化工艺，可使保护层80的材料与第一填充物、第二填充物的材料相同。
第一电极91通过位于保护层80上的过孔与栅极70接触从而使二者电连接；第二电极92通过位于保护层80和由填充物填充而形成的填充层上的过孔与漏区31接触从而使二者电连接；第三电极93通过位于保护层80和由填充物填充而形成的填充层上的过孔与漏区31接触从而使二者电连接。
需要说明的是，由于经过S50-S60的工艺之后，也会在隔离结构20上方形成栅极70，但是该栅极70并不实际起相应的作用，因此，可将位于隔离结构20上方的栅极70称为伪栅极。基于此，在形成电极时，由于无需向伪栅极供电，因此，也无需形成相应的电极。
此外，本申请涉及的附图，以漏区31在左，源区32在右进行示意，但本申请并不限于此，也可以是源区32在左，漏区31在右。
本申请提供一种TFET的制备方法，可使形成的TFET，其栅极70与源区32之间的介质层厚度小于栅极70与沟道区之间介质层的厚度，基于此，可使TFET基于线隧穿机制工作，且需在较大的栅极70偏压下，才能实现源区32和沟道区之间的点隧穿，因而可以抑制点隧穿，改善亚阈值摆幅和泄漏电流特性，从而可使本申请的TFET具有较小的亚阈值摆幅和较大的隧穿电流。其中，栅极70在去除第一侧壁511和第二侧壁513的区域形成，基于自对准方式，可避免栅极70的位置通过光刻来决定，因而可减小工艺复杂度。
如图27所示，在去除第二介质层42之后，形成栅介质层43之前，上述制备方法还包括：
S61、如图26所示，在衬底10表面外延生长一层外延层100，外延层100的材料与衬底10的材料相同。
其中，外延层100可以是掺杂的，也可以是不掺杂的。在外延层100掺杂的情况下，其掺杂类型与源区32的掺杂类型相反。
通过在去除第二介质层42之后，在衬底10表面外延生长一层外延层100，可将隧穿限制在外延层100中，减小隧穿距离，可进一步改善亚阈值摆幅和开态电流。
实施例三，提供一种TFET，具体包括：
S70、如图2所示，对衬底10进行光刻、刻蚀工艺，形成浅沟槽；在浅沟槽中填充SiO2，形成隔离结构20，由隔离结构20定义出有源区30。
S71、如图2所示，采用离子注入工艺，对有源区30进行掺杂。
其中，针对N型TFET，具体为对有源区30进行P型浅掺杂；针对P型TFET，具体为对有源区30进行N型浅掺杂。
N型浅掺杂指的是掺入五价杂质元素(如磷、砷)且掺入的杂质剂量较低。P型浅掺杂指的是掺入三价杂质元素(如硼)且掺入的杂质剂量较低。
S72、如图18所示，在形成有隔离结构20的衬底10上形成第一介质层41和覆盖第一介质层41的第二掩膜结构53；其中，第一介质层41覆盖部分有源区30，并由有源区30延伸至隔离结构20上方，覆盖部分隔离结构20。
具体的，可先热氧化生长的方法形成第一介质薄膜，此时，第一介质薄膜仅位于有源区30，其材料可以为SiO2。之后，在第一介质薄膜上可采用沉积方法形成一层膜层，该膜层的材料可以为Si3N4，并对该膜层进行光刻、刻蚀，形成第二掩膜结构53。在此基础上，以第二掩膜结构53为阻挡，对第一介质薄膜进行刻蚀，形成第一介质层41。
当然，也可先采用沉积的方法形成第一介质薄膜，此时第一介质薄膜为一整层结构，不仅位于有源区30，还位于隔离结构20上方。
S73、如图19所示，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成漏区31。
具体的，在N型和P型TFET同时制备的情况下，可先采用第一光刻胶图案覆盖除N型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应N型TFET的漏区31，并去除第一光刻胶图案。其中，第一光刻胶图案的形成方式为：先形成一层光刻胶，再采用光刻方法将N型TFET区域的光刻胶去除，剩余的光刻胶形成第一光刻胶图案。
之后，可采用第二光刻胶图案覆盖除P型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应P型TFET的漏区31，并去除第二光刻胶图案。第二光刻胶图案的形成方式与第一光刻胶图案相似。
或者，可先采用第一光刻胶图案覆盖除P型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应P型TFET的漏区31，并去除第一光刻胶图案。
之后，可采用第二光刻胶图案覆盖除N型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应N型TFET的漏区31，并去除第二光刻胶图案。
其中，对露出的有源区30，利用先刻蚀再外延生长的工艺，形成漏区31，具体为：对露出的有源区30，先刻蚀掉部分厚度，然后通过外延生长的工艺，在刻蚀掉的部分形成漏区31。
S74、如图20所示，使用第一填充物进行填充，并进行平坦化工艺，露出第二掩膜结构53。
具体的，可采用沉积方法进行第一填充物的填充。第一填充物的材料可以为SiO2。经过化学机械抛光工艺后，第一填充物和第二掩膜结构53的上表面齐平。
S75、如图21a所示，采用刻蚀工艺去除第二掩膜结构53。
S76、如图21b所示，在去除第二掩膜结构53的区域，形成第一侧壁511，去除露出的第一介质层41，并对去除第一介质层41后露出的有源区30进行工艺处理，形成源区32。
具体的，在N型和P型TFET同时制备的情况下，可先采用第三光刻胶图案覆盖除N型TFET的区域，对露出的有源30区，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应N型TFET的源区32，并去除第三光刻胶图案。
之后，采用第四光刻胶图案覆盖除P型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应P型TFET的源区32，并去除第四光刻胶图案。其中，第三光刻胶图案和第四光刻胶图案的形成方式与第一光刻胶图案相似。
或者，可先采用第三光刻胶图案覆盖除P型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应P型TFET的源区32，并去除第三光刻胶。
之后，采用第四光刻胶图案覆盖除N型TFET的区域，对露出的有源区30，利用离子注入工艺或者先刻蚀再外延生长的工艺，形成对应N型TFET的源区32，并去除第四光刻胶图案。
其中，对露出的有源区30，利用先刻蚀再外延生长的工艺，形成源区32，具体为：对露出的有源区30，先刻蚀掉部分厚度，然后通过外延生长的工艺，在刻蚀掉的部分形成源区32。
S77、如图22所示，在源区32上形成第二介质层42，且第二介质层42的厚度小于第一介质层41的厚度。
具体的，在衬底10的材料为Si的情况下，可采用热氧化的方法在源区32的表面形成第二介质层42。
其中，第二介质层42和第一介质层41的材料相同。
S78、如图23所示，在形成有第二介质层42的衬底上，沉积侧壁材料，采用各向异性刻蚀的方法形成第二侧壁513；第二侧壁513与第一侧壁511接触，且第二侧壁513的材料与第一侧壁511的材料相同。
S79、如图23所示，使用第二填充物进行填充，并进行化学机械抛光工艺，暴露第一侧壁511和第二侧壁513。
具体的，可采用沉积方法进行第二填充物的填充。第二填充物的材料可以为SiO2。经过化学机械抛光工艺后，第一填充物、第二填充物、第一侧壁511以及第二侧壁513的上表面齐平。
需要说明的是，由于经过化学机械抛光后，第一侧壁511和第二侧壁513所在区域为后续形成栅极70的区域，因此，对于第二侧壁513的尺寸应以待形成的栅极尺寸为准。
S80、如图24a所示，采用刻蚀工艺去除第一侧壁511和第二侧壁513，并去除露出的第二介质层42。
其中，第一介质层41和第二介质层42的材料相同，在去除第二介质层42后，第一介质层41的厚度也会降低。
S81、如图24b所示，在去除第一侧壁511和第二侧壁513的区域依次形成栅介质层43和栅极70。
栅介质层43可以为两层结构，包括SiO2层和氧化哈层，SiO2层靠近衬底10形成。栅极70为多层结构。
S82、如图25所示，形成保护层薄膜，并进行化学机械抛光，使保护层薄膜的上表面平坦；采用光刻、刻蚀方法形成包括露出漏区31、源区32和栅极70的过孔的保护层80。
具体的，可采用沉积方法形成保护层薄膜。保护层薄膜的材料可以为SiO2。
S83、如图25所示，在保护层80上对应有源区30形成第一电极91、第二电极92和第三电极92，以使第一电极91通过过孔与栅极70接触，第二电极92和第三电极93分别通过过孔与漏区31和源区32接触。
需要说明的是，由于经过S70-S83的工艺之后，也会在隔离结构20上方形成栅极70，但是该栅极70并不实际起相应的作用，因此，可将位于隔离结构20上方的栅极70称为伪栅极。基于此，在形成电极时，由于无需向伪栅极供电，因此，也无需形成相应的电极。
实施例四，与实施例三的不同在于，在S70-S80的基础上，如图26所示，在衬底10表面外延生长一层外延层100，外延层100的材料与衬底10的材料相同。之后，与实施例三类似，形成栅介质层43、栅极70、保护层80和第一电极91、第二电极92、第三电极92。
需要说明的是，本申请的TFET制备方法，也适用于制备鳍形结构的TFET，本申请附图仅以平面结构的TFET进行示意。
本申请还提供一种TFET，可通过上述的制备方法制备得到。
TFET包括衬底10，衬底上具有隔离结构20，并由隔离结构20定义出有源区30；有源区30包括漏区31、源区32、以及位于漏区31和源区32之间的沟道区；介质层设置于有源区30上方以及隔离结构20上方，且沟道区上方的介质层厚度大于源区32上方的介质层厚度；栅极70和伪栅极，栅极70设置于有源区30的上方，伪栅极设置于隔离结构20上方；填充层与栅极70、伪栅极的上表面在同一平面上；保护层80，设置于栅极70、伪栅极和填充层 上方；第一电极91、第二电极92和第三电极93，设置于保护层80上方，第一电极91与栅极接触，第二电极92和第三电极93分别与漏区31和源区32接触。
其中，栅极70和伪栅极的结构完全相同，仅为描述方便，将隔离结构20上方的栅极70称为伪栅极。
具体的，如图11和图25所示，有源区30上方的介质层可包括第一介质层41、第二介质层42和栅介质层43；第一介质层41位于沟道区的上方；第二介质层42位于源区32上方，第一介质层41和第二介质层42之间具有间距；在有源区30，栅介质层43覆盖沟道区上方的第一介质层41，且覆盖第一介质层41和第二介质层42之间的间距。
本申请提供一种TFET，可使形成的TFET，其栅极70与源区32之间的介质层厚度小于栅极70与沟道区之间介质层的厚度，基于此，可使TFET基于线隧穿机制工作，且需在较大的栅极70偏压下，才能实现源区32和沟道区之间的点隧穿，因而可以抑制点隧穿，改善亚阈值摆幅和泄漏电流特性，从而可使本申请的TFET具有较小的亚阈值摆幅和较大的隧穿电流。其中，栅极70在去除第一侧壁511和第二侧壁513的区域形成，可基于自对准方式可避免栅极70的位置通过光刻来决定，因而可减小工艺复杂度。
可选的，如图14和图26所示，TFET还可以包括外延层100，设置于源区32上方且位于衬底10与栅介质层43之间。
其中，外延层100可以是掺杂的，也可以是不掺杂的。在外延层100掺杂的情况下，其掺杂类型与源区32的掺杂类型相反。
通过在去除第二介质层42之后，在衬底10表面外延生长一层外延层100，可将隧穿限制在外延层100中，减小隧穿距离，可进一步改善亚阈值摆幅和开态电流。

Claims (17)

  1. 一种隧穿场效应晶体管的制备方法，其特征在于，包括：
    在衬底上形成隔离结构，由所述隔离结构定义出有源区；
    在形成有所述隔离结构的衬底上形成第一介质层和覆盖所述第一介质层的第一掩膜结构；其中，所述第一介质层覆盖部分所述有源区；所述第一掩膜结构包括外层和内层，所述外层包括第一侧壁和硬掩膜；
    对露出的所述有源区进行工艺处理，形成漏区；
    使用第一填充物进行填充，并进行平坦化的工艺，露出所述内层；
    去除所述内层以及所述内层覆盖的所述第一介质层；
    对露出的所述有源区进行工艺处理，形成源区；
    在所述源区上形成第二介质层，且所述第二介质层的厚度小于所述第一介质层的厚度；
    形成所述第二侧壁，所述第二侧壁与所述第一侧壁接触，并使用第二填充物进行填充，进行平坦化的工艺；
    去除所述第一侧壁和所述第二侧壁，并去除露出的所述第二介质层，在去除所述第一侧壁、所述第二侧壁和所述第二介质层的区域，依次形成栅介质层和栅极；
    形成保护层，并在所述保护层上对应所述有源区形成第一电极、第二电极和第三电极；所述第一电极与所述栅极接触，所述第二电极和所述第三电极分别与所述漏区和所述源区接触。
  2. 根据权利要求1所述的制备方法，其特征在于，在去除所述第二介质层之后，形成所述栅介质层之前，所述方法还包括：
    在所述衬底表面外延生长一层外延层，所述外延层的材料与所述衬底的材料相同。
  3. 根据权利要求1所述的制备方法，其特征在于，所述第一介质层和所述第二介质的材料均为SiO2；
    所述内层的材料为多晶硅；
    所述外层和所述第二侧壁的材料均为Si3N4；
    所述第一填充物、所述第二填充物和所述保护层的材料均为SiO2。
  4. 根据权利要求1所述的制备方法，其特征在于，在衬底上形成隔离结构，包括:
    对衬底进行光刻、刻蚀工艺，形成浅沟槽；
    在所述浅沟槽中填充SiO2，形成所述隔离结构。
  5. 根据权利要求1所述的制备方法，其特征在于，在衬底上形成所述隔离结构之后，形成所述第一介质层和所述第一掩膜结构之前，所述方法还包括：
    采用离子注入工艺，对所述有源区进行掺杂。
  6. 根据权利要求1所述的制备方法，其特征在于，在形成有所述隔离结构的衬底上形成第一介质层和覆盖所述第一介质层的第一掩膜结构，包括：
    在形成有所述隔离结构的衬底上形成第一介质薄膜，并在所述第一介质薄 膜上依次沉积一层内层材料和一层硬掩模材料，采用光刻、刻蚀方法形成所述内层和位于所述内层上的所述硬掩膜；
    在形成所述内层和所述硬掩膜的衬底上，沉积所述硬掩模材料，采用各向异性刻蚀的方法形成所述第一侧壁；
    以由所述硬掩膜、所述第一侧壁和所述内层构成的所述第一掩膜结构为阻挡，对所述第一介质薄膜进行刻蚀，形成所述第一介质层。
  7. 根据权利要求1所述的制备方法，其特征在于，在N型和P型所述隧穿场效应晶体管同时制备的情况下，对露出的所述有源区进行工艺处理，形成漏区，包括：
    采用第一光刻胶图案覆盖除N型所述隧穿场效应晶体管的区域，对露出的所述有源区进行工艺处理，形成对应N型所述隧穿场效应晶体管的漏区，并去除所述第一光刻胶图案；
    采用第二光刻胶图案覆盖除P型所述隧穿场效应晶体管的区域，对露出的所述有源区进行工艺处理，形成对应P型所述隧穿场效应晶体管的漏区，并去除所述第二光刻胶图案；
    在N型和P型所述隧穿场效应晶体管同时制备的情况下，对露出的所述有源区进行工艺处理，形成源区，包括：
    采用第三光刻胶图案覆盖除N型所述隧穿场效应晶体管的区域，对露出的所述有源区进行工艺处理，形成对应N型所述隧穿场效应晶体管的源区，并去除所述第三光刻胶图案；
    采用第四光刻胶图案覆盖除P型所述隧穿场效应晶体管的区域，对露出的所述有源区进行工艺处理，形成对应P型所述隧穿场效应晶体管的源区，并去除所述第四光刻胶图案。
  8. 根据权利要求1所述的制备方法，其特征在于，平坦化工艺，包括化学机械抛光工艺。
  9. 根据权利要求1或7所述的制备方法，其特征在于，对露出的所述有源区进行工艺处理，包括：
    对露出的所述有源区进行离子注入工艺或者先刻蚀再外延生长的工艺。
  10. 根据权利要求1所述的制备方法，其特征在于，所述衬底的材料为Si；
    在所述源区上形成第二介质层，包括：
    采用热氧化的方法在所述源区的表面形成第二介质层。
  11. 根据权利要求1所述的制备方法，其特征在于，形成所述第二侧壁，包括：
    在形成有所述第二介质层的衬底上，沉积侧壁材料，采用各向异性刻蚀的方法形成所述第二侧壁；
    其中，所述第二侧壁的材料与所述第一侧壁的材料相同。
  12. 根据权利要求1所述的制备方法，其特征在于，形成所述保护层，包括：
    形成保护层薄膜，并进行化学机械抛光，使所述保护层薄膜的上表面平坦；
    采用光刻、刻蚀方法，形成露出所述漏区、所述源区和所述栅极的过孔，以使所述第一电极、所述第二电极和所述第三电极分别通过所述过孔与所述栅极、所述漏区和所述源区接触。
  13. 根据权利要求1所述的制备方法，其特征在于，所述栅极为多层结构。
  14. 一种隧穿场效应晶体管的制备方法，其特征在于，包括：
    在衬底上形成隔离结构，由所述隔离结构定义出有源区；
    在形成有所述隔离结构的衬底上形成第一介质层和覆盖所述第一介质层的第二掩膜结构；其中，所述第一介质层覆盖部分所述有源区；
    对露出的所述有源区进行工艺处理，形成漏区；
    使用第一填充物进行填充，并进行平坦化工艺，露出所述第二掩膜结构，并去除所述第二掩膜结构；
    在去除所述第二掩膜结构的区域，形成第一侧壁，去除露出的所述第一介质层，并对去除所述第一介质层后露出的所述有源区进行工艺处理，形成源区；
    在所述源区上形成第二介质层，且所述第二介质层的厚度小于所述第一介质层的厚度；
    形成所述第二侧壁，所述第二侧壁与所述第一侧壁接触，并使用第二填充物进行填充，进行平坦化工艺，暴露所述第一侧壁和所述第二侧壁；
    去除所述第一侧壁和所述第二侧壁，并去除露出的所述第二介质层，在去除所述第一侧壁、所述第二侧壁和所述第二介质层的区域，依次形成栅介质层和栅极；
    形成保护层，并所述保护层上对应所述有源区形成第一电极、第二电极和第三电极；所述第一电极与所述栅极接触，所述第二电极和所述第三电极分别与所述漏区和所述源区接触。
  15. 根据权利要求14所述的制备方法，其特征在于，在去除所述第二介质层之后，形成所述栅介质层之前，所述方法还包括：
    在所述衬底表面外延生长一层外延层，所述外延层的材料与所述衬底的材料相同。
  16. 一种隧穿场效应晶体管，其特征在于，包括：
    衬底，衬底上具有隔离结构，并由所述隔离结构定义出有源区；所述有源区包括漏区、源区、以及位于所述漏区和所述源区之间的沟道区；
    介质层设置于所述有源区上方以及所述隔离结构上方，且所述沟道区上方的介质层厚度大于所述源区上方的介质层厚度；栅极和伪栅极，所述栅极设置于所述有源区的上方，所述伪栅极设置于所述隔离结构上方；
    填充层与所述栅极、所述伪栅极的上表面在同一平面上；
    保护层，设置于所述栅极、所述伪栅极和所述填充层上方；
    第一电极、第二电极和第三电极，设置于所述保护层上方，所述第一电极与所述栅极接触，所述第二电极和所述第三电极分别与所述漏区和所述源区接触。
  17. 根据权利要求16所述的隧穿场效应晶体管，其特征在于，所述介质层包括栅介质层；
    所述隧穿场效应晶体管还包括外延层，设置于所述源区上方且位于所述衬底与所述栅介质层之间。
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