TWI576923B - 半導體裝置的形成方法 - Google Patents
半導體裝置的形成方法 Download PDFInfo
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- TWI576923B TWI576923B TW104126207A TW104126207A TWI576923B TW I576923 B TWI576923 B TW I576923B TW 104126207 A TW104126207 A TW 104126207A TW 104126207 A TW104126207 A TW 104126207A TW I576923 B TWI576923 B TW I576923B
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- 238000000034 method Methods 0.000 title claims description 150
- 239000004065 semiconductor Substances 0.000 title claims description 108
- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000000463 material Substances 0.000 claims description 116
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- 229910052749 magnesium Inorganic materials 0.000 description 1
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- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
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- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
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Description
本發明關於半導體裝置的方法,更特別關於磊晶成長後平坦化製程。
半導體產業已進階至奈米技術節點,以達更高的裝置密度、更高效能、與更低成本。為解決製作與設計問題,發展出三維設計如垂直式閘極全環繞(VGAA)電晶體。一般的GAA電晶體可藉由閘極介電層與閘極完全包覆半導體奈米線之通道區,以提升對縱向電荷載子的控制。由於通道區被閘極圍繞,因此源極/汲極區對通道區之電場效應降低,進而使GAA電晶體的短通道效應較小。
然而,目前的VGAA仍面臨某些挑戰。舉例來說,用於互補式金氧半(CMOS)裝置的製程與材料並未非特別適用於製作VGAA電晶體。如此一來,需改進製程以製作VGAA電晶體。
本發明一實施例提供之半導體裝置的形成方法,包括形成第一開口於半導體基板中,以及磊晶成長第一半導體材料於第一開口中。平坦化第一半導體材料與半導體基板。形成第二開口於第一半導體材料中,並磊晶成長第二半導體材料於第二開口中。平坦化第二半導體材料與第一半導體材料;以
及磊晶成長通道層於第一半導體材料與第二半導體材料上。
本發明另一實施例提供之半導體裝置的形成方法包括:將介電材料嵌置於半導體基板中。將第一半導體材料嵌置於半導體基板中,且此步驟至少部份採用第一磊晶成長製程。將第二半導體材料嵌置於半導體基板中,且此步驟至少部份採用第二磊晶製程,第二磊晶製程不同於第一磊晶製程,且第二半導體材料與第一半導體材料齊平。磊晶成長通道層於第一半導體材料與第二半導體材料上,其中至少部份的通道層延伸至介電材料上。
本發明又一實施例提供之半導體裝置包括:第一導電區嵌置於基板中,且第一導電區具有第一導電型態。第二導電區嵌置於基板中,第二導電區具有第二導電型態,且第二導電型態與第一導電型態相反,其中第一導電區、第二導電區、與基板彼此齊平。介電材料嵌置於基板中。第一通道區物理接觸第一導電區,且第一通道區包含第一材料。第二通道區物理接觸第二導電區,且第二通道區包含第一材料。襯墊覆蓋介電材料的第一部份,其中襯墊包含第一材料。
D1‧‧‧第一距離
D2‧‧‧第二距離
D3‧‧‧第三深度
H1‧‧‧第一高度
RD1‧‧‧第一凹陷深度
RD2‧‧‧第二凹陷深度
T1‧‧‧第一厚度
T2‧‧‧第二厚度
W1‧‧‧第一寬度
101‧‧‧基板
103‧‧‧對準標記
105‧‧‧第一硬遮罩
201‧‧‧第一開口
203‧‧‧第一掺雜區
301‧‧‧第一平坦化製程
401‧‧‧第二硬遮罩
403‧‧‧第二開口
405‧‧‧第二掺雜區
501‧‧‧第二平坦化製程
601‧‧‧通道層
603‧‧‧第三掺雜區
605‧‧‧第一通道區
607‧‧‧第二通道區
701‧‧‧第三開口
703‧‧‧第四掺雜區
705‧‧‧第三硬遮罩
801‧‧‧第三平坦化製程
901‧‧‧第一奈米線
903‧‧‧第二奈米線
905‧‧‧第四光阻
911‧‧‧虛置條
1000‧‧‧第一VGAA裝置
1001‧‧‧第二VGAA裝置
1002‧‧‧第一接觸墊
1003‧‧‧第一閘極
1004‧‧‧第二接觸墊
1005‧‧‧第一隔離區
1007‧‧‧第二閘極
1009‧‧‧第一閘極介電物
1011‧‧‧第二閘極介電物
1013‧‧‧第三隔離區
1015‧‧‧第四隔離區
1017‧‧‧第三接觸墊
1019‧‧‧第四接觸墊
1021‧‧‧第五隔離區
1023‧‧‧基板隔離區
第1圖係某些實施例中,具有對準標記之基板的示意圖。
第2圖係某些實施例中,形成第一掺雜區的示意圖。
第3圖係一實施例中,平坦化第一掺雜區的示意圖。
第4圖係一實施例中,形成第二掺雜區的示意圖。
第5圖係一實施例中,平坦化第二掺雜區的示意圖。
第6圖係一實施例中,形成通道區與第三掺雜區的示意圖。
第7圖係一實施例中,形成第四掺雜區的示意圖。
第8圖係一實施例中,平坦化第四掺雜區的示意圖。
第9圖係一實施例中,形成第一奈米線與第二奈米線的示意圖。
第10圖係一實施例中,形成第一垂直式閘極全環繞裝置與第二垂直式閘極全環繞裝置的示意圖。
下述內容提供的不同實施例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說,形成第一構件於第二構件上的敘述包含兩者直接接觸,或兩者之間隔有其他額外構件而非直接接觸。此外,本發明之多種實例將重複標號及/或符號以簡化並清楚說明。不同實施例中具有相同標號的元件並不必然具有相同的對應關係及/或排列。
此外,空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件,而非侷限於圖示方向。元件亦可轉動90°或其他角度,因此方向性用語僅用以說明圖示中的方向。
下述實施例關於用在垂直式閘極全環繞電晶體中的特定實施例。然而這些實施例亦可用於任何合適的製程或裝置。
如第1圖所示,其具有基板101、對準標記103、與第一硬遮罩105。在一實施例中,基板101包含半導體基板如矽、矽鍺、或硼化矽鍺。在其他實施例中,基板101包含絕緣層上矽(SOI)結構。在某些實施例中,基板101可包含半導體化合物如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、或銻化銦,半導體合金如矽鍺、矽鍺錫、鍺錫、磷化鎵砷、砷化鋁銦、砷化鋁鎵、砷化鎵銦、磷化鎵銦、或砷磷化鎵銦,或上述之組合。
對準標記103可形成於基板101中,以提供控制點確保基板101已對準後續製程之特定模式。在一實施例中,對準標記103可為可見材料(人眼可見或儀器可見)如氧化矽,不過任何其他合適材料亦可用於對準標記103。對準標記103之形成方法可為圖案化基板(如搭配光微影遮罩與蝕刻製程),以形成溝槽。當溝槽形成後,可將氧化矽一類的材料填滿及/或超填溝槽,並可採用平坦化製程如化學機械研磨移除超出溝槽的任何材料,使對準標記的上表面與基板101的上表面共平面。在一實施例中,對準標記103之第一寬度W1可介於約0.1μm與約1.6μm之間(比如1.1μm)。
當對準標記103形成於基板101中,可將第一硬遮罩105置於基板101與對準標記103上,以形成後續蝕刻基板101所用的遮罩。在一實施例中,第一硬遮罩105包含介電材料如氮化矽、氮化鈦、氮氧化矽、上述之組合、或類似物。第一硬遮罩105之形成方法可為化學氣相沉積、電漿增強式化學氣相沉積、原子層沉積、或類似方法。然而,任何其他合適材料與形成方法均可用於形成第一硬遮罩105。第一硬遮罩105之厚度
可介於約20Å至約3000Å之間(比如20Å)。
當第一硬遮罩105形成後,可圖案化第一硬遮罩105以露出部份的基板101其後續形成第一掺雜區203處(未圖示於第1圖但將圖示於第2圖)。在一實施例中,第一硬遮罩105的圖案化方法先將第一光阻(未個別圖示)置於第一硬遮罩105上,並以圖案化的能量源(如光)曝光第一光阻,以起始第一光阻之曝光部份的化學反應並調整其物理性質。接著可施加第一顯影液(同樣未個別圖示於第1圖中)以顯影第一光阻。藉由曝光區與未曝光區之間的物理性質差異,第一顯影液可選擇性地移除第一光阻的曝光區或未曝光區。
當第一光阻圖案化後,第一光阻可作為圖案化其下方之第一硬遮罩105的遮罩。在一實施例中,第一硬遮罩105的圖案化方法可採用以第一光阻作為遮罩的反應性離子蝕刻製程。圖案化製程可持續到露出第一硬遮罩105下方之基板101為止。
如第2圖所示,採用第一硬遮罩105圖案化基板101後,可形成第一開口201。在一實施例中,將第一硬遮罩105之圖案轉移至基板101的圖案化步驟,可為反應性離子蝕刻製程,其採用的蝕刻品可搭配第一硬遮罩105作為遮罩,並適用於蝕刻基板101的材料如矽。第一開口201之第一凹陷深度RD1介於約50nm至約90nm之間(比如約64nm)。
在第一開口201形成於基板101中之後,可填滿第一開口201以形成第一掺雜區203。在一實施例中,第一掺雜區203將用於形成第一VGAA(垂直式閘極全環繞)裝置1000(並
未圖示於第2圖中,但將圖示於第10圖中並說明如下)。在特定實施例中,第一掺雜區203用於形成第一VGAA裝置1000的源極/汲極區,因此其包含半導體材料(如矽)與掺質(使第一掺雜區203之半導體材料具有第一導電型態)。然而任何合適的半導體材料如鍺、矽鍺、上述之組合、或類似物亦可作為第一掺雜區203的半導體材料。
第一掺雜區203之形成製程可為磊晶成長,其採用基板101露出的部份作為成長起始處。舉例來說,某些實施例之第一掺雜區203之形成製程可為有機金屬CVD(MOCVD)、原子束磊晶(MBE)、液相磊晶(LPE)、氣相磊晶(VPE)、選擇磊晶成長(SEG)、類似製程、或上述之組合。由於第一掺雜區203磊晶成長於基板101的露出部份上,第一掺雜區203將形成於第一開口201中而不起始成長於第一硬遮罩105上。此外,第一掺雜區203其晶格常數,與用以形成第一掺雜區203於其上之下方的基板101其晶格常數類似。
為了作為源極/汲極區,第一掺雜區203掺有掺質,其適用於自第一掺雜區203形成之裝置的導電型態。舉例來說,一實施例需自第一掺雜區203形成NMOS裝置,則第一掺雜區203需掺有N型掺質如磷或砷。在其他實施例中,若需自第一掺雜區203形成PMOS裝置,則可採用P型掺質如硼或鎵。
在一實施例中,在成長第一掺雜區203時將掺質導入第一掺雜區203的材料如矽。舉例來說,在磊晶成長製程時可將所需掺質的前驅物,搭配用於形成第一掺雜區203之前驅反應物一起臨場置入反應容器中。如此一來,掺質將導入第一
掺雜區203的材料,並整合至第一掺雜區203之材料中,使第一掺雜區203具有所需的導電型態。
在其他實施例中,可在第一掺雜區203如矽成長後,再將掺質導入第一掺雜區203中。在此實施例中,第一掺雜區203在成長時未搭配掺質,而導入掺質的製程如佈植製程或擴散製程之後將掺質導入第一掺雜區203中。在掺質導入後,可進行回火以活化第一掺雜區203中的掺質。
磊晶成長製程至少可持續至第一掺雜區203的材料填滿第一開口201。此外,為確保完全填滿第一開口201,成長製程可持續至超出第一開口201。這些超出第一開口201的材料將導致第一掺雜區203橫向(平行於第一基板101的表面)延伸,且部份延伸至部份的第一硬遮罩105上。
如第3圖所示,第一平坦化製程301(如第3圖所示之圓盤)可平坦化第一掺雜區203,並移除第一硬遮罩105。在一實施例中,平坦化製程301可為一或多道的化學機械研磨製程,其施加蝕刻劑與研磨劑至第一掺雜區203與第一硬遮罩105,並以圓盤研磨第一掺雜區203與第一硬遮罩105以平坦化並移除位於基板101之表面上的多餘第一掺雜區203與第一硬遮罩105。
然而本技術領域中具有通常知識者應理解,上述化學機械研磨製程僅用以說明而非侷限實施例。任何合適的平坦化製程如物理研磨製程或一系列的一或多道蝕刻,亦可用於第一平坦化製程301。這些製程均包含於實施例之範疇中。
如第4圖所示,沉積第二硬遮罩401於基板101、對
準標記103、與第一掺雜區203上。在一實施例中,第二硬遮罩401包含介電材料如氮化矽、氮化鈦、氮氧化矽、上述之組合、或類似物。第二硬遮罩401之形成製程可為化學氣相沉積、電漿增強式化學氣相沉積、原子層沉積、或類似製程。然而,任何其他合適材料與形成方法亦可用於形成第二硬遮罩401。第二硬遮罩401之厚度可介於約20Å至約3000Å之間(比如約20Å)。
當第二硬遮罩401形成後,可圖案化第二硬遮罩401以露出部份第一掺雜區203(用於形成第二掺雜區405)。在一實施例中,第二硬遮罩401的圖案化方法係將第二光阻(未個別圖示於第4圖中)先置於第二硬遮罩401上,並以圖案化能量源(如光)曝光第二光阻,以起始第二光阻之曝光部份的化學反應並調整其物理性質。接著可施加第二顯影液(同樣未個別圖示於第4圖中)以顯影第二光阻。藉由曝光區與未曝光區之間的物理性質差異,第二顯影液可選擇性地移除第二光阻的曝光區或未曝光區。
當第二光阻圖案化後,第二光阻可作為圖案化其下方之第二硬遮罩401的遮罩。在一實施例中,第二硬遮罩401的圖案化方法可採用以第二光阻作為遮罩的反應性離子蝕刻製程。圖案化製程可持續到露出第二硬遮罩401下方之第一掺雜區203為止。
在形成並圖案化第二硬遮罩401後,可採用第二硬遮罩401作為遮罩並移除部份的第一掺雜區203,以形成第二開口403。在一實施例中,將第二硬遮罩401之圖案轉移至第二掺雜區203以形成第二開口403的步驟,可為反應性離子蝕刻製
程,其採用的蝕刻品可搭配第二硬遮罩401作為遮罩,並適用於蝕刻第二掺雜區203的材料如矽。第二開口403可形成以露出下方的基板101,且第二開口403之第二凹陷深度RD2介於約60nm至約90nm之間(比如約75nm)。
在形成第二開口403於第一掺雜區203與基板101中後,可填滿第二開口403以形成第二掺雜區405。在一實施例中,第二掺雜區405將用於形成第二VGAA裝置1001(並未圖示於第4圖中,但將圖示於第10圖中並說明如下)。第二VGAA裝置1001不同於第一VGAA裝置1000,比如兩者的導電型態不同。在特定實施例中,第二掺雜區403用於形成第二VGAA裝置1001的源極/汲極區。舉例來說,若第一VGAA裝置1000為NMOS裝置,則第二VGAA裝置1001為PMOS裝置。
第二掺雜區405之形成製程可為磊晶成長,其採用基板101露出的部份作為成長起始處。舉例來說,某些實施例之第二掺雜區405可由半導體材料如矽所形成,且其形成製程為磊晶成長。舉例來說,某些實施例之第二掺雜區405之形成製程可為有機金屬CVD(MOCVD)、原子束磊晶(MBE)、液相磊晶(LPE)、氣相磊晶(VPE)、選擇磊晶成長(SEG)、類似製程、或上述之組合。然而,任何合適的半導體材料如鍺、矽鍺、上述之組合、或類似物亦可用於形成第二掺雜區405。
由於第二掺雜區405磊晶成長於基板101的露出部份上,第二掺雜區405將形成於第二開口403中而不起始成長於第二硬遮罩401上。此外,第二掺雜區405其晶格常數,與用以形成第二掺雜區405於其上之下方的基板101其晶格常數類似。
在一實施例中,第二掺雜區405掺雜的掺質其導電型態與第一掺雜區203相反。舉例來說,當第一掺雜區203需用於NMOS裝置,則第二掺雜區405將用於PMOS裝置,且第二掺雜區405可掺有P型掺質如硼或鎵。在另一實施例中,若第二掺雜區405需用於NMOS裝置,則可採用N型掺質如磷或砷。
在一實施例中,在成長第二掺雜區405時將掺質導入第二掺雜區405的材料如矽。舉例來說,在磊晶成長製程時可將所需掺質的前驅物,搭配用於形成第二掺雜區405之前驅反應物一起臨場置入反應容器中。如此一來,掺質將導入第二掺雜區405的材料,並整合至第二掺雜區405之材料中,使第二掺雜區405具有所需的導電型態。
在其他實施例中,可在第二掺雜區405如矽成長後,再將掺質導入第二掺雜區405中。在此實施例中,第二掺雜區405在成長時未搭配掺質,而導入掺質的製程如佈植製程或擴散製程之後將掺質導入第二掺雜區405中。在掺質導入後,可進行回火以活化第二掺雜區405中的掺質。
磊晶成長製程至少可持續至第二掺雜區405的材料填滿第二開口403。此外,為確保完全填滿第二開口403,成長製程可持續至超出第二開口403。這些超出第二開口403的材料將導致第二掺雜區405部份延伸至第二硬遮罩401上。
如第5圖所示,第二平坦化製程501(如第5圖所示之圓盤)可平坦化第二掺雜區405,並移除第二硬遮罩401。在一實施例中,平坦化製程501可為一或多道的化學機械研磨製程,其施加蝕刻劑與研磨劑至第二掺雜區405與第二硬遮罩
401,並以圓盤研磨第二掺雜區405與第二硬遮罩401,以平坦化並移除位於基板101與第一掺雜區203以外的多餘第二掺雜區405與第二硬遮罩401。
然而本技術領域中具有通常知識者應理解,上述化學機械研磨製程僅用以說明而非侷限實施例。任何合適的平坦化製程如物理研磨製程或一系列的一或多道蝕刻,亦可用於第二平坦化製程501。這些製程均包含於實施例之範疇中。
如第6圖所示,形成通道層601及其上之第三掺雜區603。在一實施例中,通道層601可為半導體材料如矽,其形成製程可採用磊晶製程。舉例來說,某些實施例之通道層601的形成製程可為有機金屬CVD(MOCVD)、分子束磊晶(MBE)、液相磊晶(LPE)、氣相磊晶(VPE)、選擇磊晶成長(SEG)、類似製程、或上述之組合。然而,任合合適的半導體材料如鍺、矽鍺、上述之組合、或類似物亦可用於形成通道層601。
由於通道層601之形成方法採用磊晶成長製程,通道層601係成長於第一掺雜區203、第二掺雜區405、與露出的部份基板101上。然而,通道層601並未成長於對準標記103之頂部上,雖然橫向成長(平行於基板101之主要表面)可能會讓部份的通道層601延伸至對準標記103上。在一實施例中,通道層601可具有第一厚度T1,其介於約15nm至約40nm之間(比如約30nm)。通道層601延伸至對準標記103上的邊緣與對準標記103之邊緣之間的第一距離D1介於約15nm至約40nm之間(比如約30nm)。
在一實施例中,通道層601在成長時未掺雜任何掺
質(不論n型或p型)。如此一來,用於第一VGAA裝置之第一通道區605的材料可位於第一掺雜區203上的通道層601中。此外,第二通道區607可位於第二掺雜區405上的通道層601中。第一通道區605與第二通道區607在形成時均可未掺雜任何掺質。
在其他實施例中,可依需要採用遮罩與佈植製程掺雜通道層601。舉例來說,可將遮罩如光阻置於第一掺雜區203上的部份通道層601上,並將與第二掺雜區405相反導電型態的掺質佈植第二掺雜區405上的通道層601中。接著可移除遮罩,再將另一遮罩置於第二掺雜區405上的部份通道層601上,並以佈植製程將掺質佈植至第一掺雜區203上的通道層601中。任何合適製程均可用以掺雜通道層601。
此外,在磊晶成長通道層601時,基板101、第一掺雜區203、與第二掺雜區405的材料可部份延伸至基板101的某些材料上,且第一掺雜區203與第二掺雜區405在磊晶成長時向上擴散。如此一來,在成長通道層601前,基板101、第一掺雜區203、第二掺雜區405可視作少許成長。矽凹陷與表面清潔製程會消耗部份對準標記,造成對準標記103的表面少許凹陷至低於基板101的表面,且通道層601將襯墊部份凹陷。
當通道層601形成後,形成第三掺雜區603於通道層601上。在一實施例中,第三掺雜區603與第一掺雜區203互補,即第三掺雜區603與第一掺雜區203可作為第一VGAA裝置1000的源極/汲極區。如此一來,第三掺雜區603與第一掺雜區203的導電型態相同。舉例來說,一實施例之第一掺雜區203掺
有N型掺質,則第三掺雜區603亦應掺有N型掺質。同樣地,若第一掺雜區203掺有P型掺質,則第三掺雜區603亦應掺有P型掺質。
第三掺雜區603之形成製程可為磊晶製程,其採用通道層601的露出區域作為成長起始區。舉例來說,某些實施例之第三掺雜區603其材料為半導體材料如矽,其形成製程可為有機金屬CVD(MOCVD)、原子束磊晶(MBE)、液相磊晶(LPE)、氣相磊晶(VPE)、選擇磊晶成長(SEG)、類似製程、或上述之組合。然而,任何合適的半導體材料如鍺、矽鍺、上述之組合、或類似物均可用於形成第三掺雜區603。
由於第三掺雜區603之形成方法為磊晶成長,第三掺雜區603將成長於露出的通道層601上,而不成長於對準標記103上。然而,成長於通道層601上的部份材料可能延伸至對準標記103上,即第三掺雜區603部份延伸至對準標記103上及對準標記103上的凹陷中。此外,第三掺雜區603其晶格常數,可與用以形成第三掺雜區603於其上之下方的通道層601其晶格常數類似。第三掺雜區603之第二厚度T2可介於約30nm至約60nm之間(比如約45.5nm)。第三掺雜區603延伸至通道層601上的部份邊緣與通道層601之邊緣之間的第二距離D2,可介於約30nm至約60nm之間(比如約45.5nm)。
在一實施例中,在成長第三掺雜區603(如矽)時,將掺質導入第三掺雜區603。舉例來說,在磊晶成長製程時可將所需掺質的前驅物,搭配用於形成第三掺雜區603之前驅反應物一起臨場置入反應容器中。如此一來,掺質將導入第三掺
雜區603的材料,並整合至第三掺雜區603之材料中,使第三掺雜區603具有所需的導電型態。
在其他實施例中,可在第三掺雜區603如矽成長後,再將掺質導入第三掺雜區603中。在此實施例中,第三掺雜區603在成長時未搭配掺質,而導入掺質的製程如佈植製程或擴散製程之後將掺質導入第三掺雜區603中。在掺質導入後,可進行回火以活化第三掺雜區603中的掺質。
如第7圖所示,放置第三硬遮罩705、圖案化第三掺雜區603以形成第三開口701、以及形成第四掺雜區703。在一實施例中,第三硬遮罩705包含介電材料如氮化矽、氮化鈦、氮氧化矽、上述之組合、或類似物。第三硬遮罩705之形成製程可為化學氣相沉積、電漿增強式化學氣相沉積、原子層沉積、或類似製程。然而任何其他合適材料與形成方法亦可用於形成第三硬遮罩705。第三硬遮罩705之厚度可介於約20Å至約3000Å之間(比如約20Å)。
當第三硬遮罩705形成後,可圖案化第三硬遮罩705以露出部份的第三掺雜區603(用於形成第四掺雜區703處)。在一實施例中,第三硬遮罩705的圖案化方法係將第三光阻(未個別圖示於第7圖中)先置於第三硬遮罩705上,並以圖案化能量源(如光)曝光第三光阻,以起始第三光阻之曝光部份的化學反應並調整其物理性質。接著可施加第三顯影液(同樣未個別圖示於第7圖中)以顯影第三光阻。藉由曝光區與未曝光區之間的物理性質差異,第三顯影液可選擇性地移除第三光阻的曝光區或未曝光區。
當第三光阻圖案化後,第三光阻可作為圖案化其下方之第三硬遮罩705的遮罩。在一實施例中,第三硬遮罩705的圖案化方法可採用以第三光阻作為遮罩的反應性離子蝕刻製程。圖案化製程可持續到露出第三硬遮罩705下方之第三掺雜區603為止。
在形成並圖案化第三硬遮罩705後,可採用第三硬遮罩705作為遮罩並移除部份的第三掺雜區603,以形成第三開口701。在一實施例中,將第三硬遮罩705之圖案轉移至第三掺雜區603以形成第三開口701的步驟,可為反應性離子蝕刻製程,其採用的蝕刻品可搭配第三硬遮罩705作為遮罩,並適用於蝕刻第三掺雜區603的材料如矽。第三開口701可形成以露出下方的部份通道層601。
在形成第三開口701後,形成第四掺雜區703於通道層601上的第三開口701中。在一實施例中,第四掺雜區703與第二掺雜區405互補,即第四掺雜區703與第二掺雜區405可作為第二VGAA裝置1001的源極/汲極區。如此一來,第四掺雜區703與第二掺雜區405的導電型態相同。舉例來說,一實施例之第二掺雜區405掺有P型掺質,則第四掺雜區703亦應掺有P型掺質。同樣地,若第二掺雜區405掺有N型掺質,則第四掺雜區703亦應掺有N型掺質。
第四掺雜區703之形成製程可為磊晶製程,其採用第三開口701中通道層601的露出區域作為成長起始區。舉例來說,某些實施例之第四掺雜區703其材料為半導體材料如矽,其形成製程可為有機金屬CVD(MOCVD)、原子束磊晶(MBE)、
液相磊晶(LPE)、氣相磊晶(VPE)、選擇磊晶成長(SEG)、類似製程、或上述之組合。然而,任何合適的半導體材料如鍺、矽鍺、上述之組合、或類似物均可用於形成第四掺雜區703。
由於第四掺雜區703之形成方法為磊晶成長,第四掺雜區703將成長於露出的通道層601上,而不起始成長於第三硬遮罩705上。此外,第四掺雜區703其晶格常數,可與用以形成第四掺雜區703於其上之下方的通道層601其晶格常數類似。
用於第四掺雜區703的磊晶成長製程,至少可持續至第四掺雜區703的材料填滿第三開口701。此外,為確保完全填滿第三開口701,第四掺雜區703的成長製程可持續至超出第三開口701。這些超出第三開口701的材料將導致第四掺雜區703部份延伸至第三硬遮罩705上。
在一實施例中,在成長第四掺雜區703(如矽)時,將掺質導入第四掺雜區703。舉例來說,在磊晶成長製程時可將所需掺質的前驅物,搭配用於形成第四掺雜區703之前驅反應物一起臨場置入反應容器中。如此一來,掺質將導入第四掺雜區703的材料,並整合至第四掺雜區703之材料中,使第四掺雜區703具有所需的導電型態。
在其他實施例中,可在第四掺雜區703如矽成長後,再將掺質導入第四掺雜區703中。在此實施例中,第四掺雜區703在成長時未搭配掺質,而導入掺質的製程如佈植製程或擴散製程之後將掺質導入第四掺雜區703中。在掺質導入後,可進行回火以活化第四掺雜區703中的掺質。
如第8圖所示,第三平坦化製程801(如第8圖所示之
圓盤)可平坦化第四掺雜區703,並移除第三硬遮罩705。在一實施例中,平坦化製程801可為一或多道的化學機械研磨製程,其施加蝕刻劑與研磨劑至第四掺雜區703與第三硬遮罩705,並以圓盤研磨第四掺雜區703與第三硬遮罩705,以平坦化並移除多餘的第四掺雜區703與第三硬遮罩705。
然而本技術領域中具有通常知識者應理解,上述化學機械研磨製程僅用以說明而非侷限實施例。任何合適的平坦化製程如物理研磨製程或一系列的一或多道蝕刻,亦可用於第三平坦化製程801。這些製程均包含於實施例之範疇中。
上述的成長製程與平坦化製程,在形成通道於基板凹陷中時可避免常見變數。在特定實施例中,因為非順應性的晶面缺陷靠近圖案邊界,使通道層無法平面地延著圖案邊界形成的問題,可藉由平坦化製程解決:先確定下方的表面平坦,再開始形成後續的層狀物。如此一來,因為上述缺陷減少,而可減少避免裝置失效所需的整體面積,並降低採用奈米線(如採用垂直裝置之SRAM單元,其具有重N/P掺雜的源極/汲極區與垂直通道)之裝置的總體密度。
如第9圖所示,將通道層601、第三掺雜區603、與第四掺雜區703圖案化成第一奈米線901(由通道層601、第三掺雜區603、與第一掺雜區203所形成)與第二奈米線903(由第四掺雜區703、通道層601、與第二掺雜區405所形成)。在一實施例中,通道層601、第一掺雜區203、第二掺雜區405、第三掺雜區603、與第四掺雜區703之圖案化方法,可為先施加第四光阻905至第三掺雜區603與第四掺雜區703,再以圖案化能量源
(如光)曝光第四光阻905,以起始第四光阻905之曝光部份的化學反應並調整其物理性質。接著可施加第四顯影液(未個別圖示於第9圖中)以顯影第四光阻。藉由曝光區與未曝光區之間的物理性質差異,第四顯影液可選擇性地移除第四光阻905的曝光區或未曝光區。
當第四光阻905圖案化後,第四光阻905可作為將其下方之第四掺雜區703、第三掺雜區603、通道層601、第二掺雜區405、與第一掺雜區203圖案化至第一奈米線901(由第一掺雜區203、通道層601中的第一通道區605、與第三掺雜區603所形成)與第二奈米線903(由第二掺雜區405、通道層601中的第二通道區607、與第四掺雜區703所形成)的遮罩。在一實施例中,第四掺雜區703、第三掺雜區603、通道層601、第二掺雜區405、與第一掺雜區203的圖案化方法可採用以第四光阻905作為遮罩的反應性離子蝕刻製程。圖案化製程可持續到露出通道層601下方之第一掺雜區203與第二掺雜區405為止。第一奈米線901與第二奈米線903之寬度可介於約5nm至約10nm之間(比如約6nm)。
此外,上述圖案化製程可依需要持續至第一掺雜區203與第二掺雜區405中。在一實施例中,圖案化製程持續至第一掺雜區203與第二掺雜區405被移除的第三深度D3介於約5nm至約10nm之間(比如約7.5nm)。如此一來,第一奈米線901與第二奈米線903之第一高度H1可介於約50nm至約100nm之間(比如約72nm)。
在某些實施例中,亦可沿著第一奈米線901與第二
奈米線903形成虛置條,比如使通道層601與第三掺雜區603圖案化成一虛置條911。虛置條911可用以平均奈米線的密度,使製程變數不會過度影響最終產品。在一實施例中,虛置條911之尺寸可與第一奈米線901及第二奈米線903之尺寸相同。舉例來說,虛置條911之寬度可介於約5nm至約10nm之間(比如6nm),不過亦可具有任何其他合適尺寸。
在形成第一奈米線901與第二奈米線903後,可採用灰化製程移除第四光阻905,即增加第四光阻905之溫度直到其熱分解。接著可進行清潔製程以移除第一奈米線901與第二奈米線903的原生氧化物。上述清潔製程可採用稀釋的氫氟酸(DHF)。
如第10圖所示,在形成第一奈米線901與第二奈米線903後,可由第一奈米線901與第二奈米線903形成第一VGAA裝置1000與第二VGAA裝置1001。形成上述裝置的製程可先形成基板隔離區1023圍繞第一掺雜區203與第二掺雜區405,使這些區域彼此隔離。在一實施例中,基板隔離區1023包含介電材料如氧化矽。基板隔離區1023亦可包含其他合適的介電材料如氮化矽、氮氧化矽、掺雜碳的氧化矽、掺雜碳的氮化矽、或掺雜碳的氮氧化矽。在某些實施例中,介電材料層的沉積方法包括化學氣相沉積(CVD)、物理氣相沉積(PVD)、或旋轉塗佈法。進行CMP製程以移除高於第一奈米線901與第二奈米線903的部份介電材料,再回蝕刻介電材料至所需高度以幫助定義基板隔離區1023。
在形成基板隔離區1023後,形成第一接觸墊1002
以提供電性連接至第一掺雜區203,並形成第二接觸墊1004以提供電性連接至第二掺雜區405。在一實施例中,第一接觸墊1002與第二接觸墊1004之組成為導電材料如鋁,但亦可採用其他合適材料如銅、鎢、或類似物。第一接觸墊1002與第二接觸墊1004的形成製程可為CVD或PVD,但其他合適材料或方法亦可用於形成第一接觸墊1002與第二接觸墊1004。在沉積用於第一接觸墊1002與第二接觸墊1004的材料後,可採用一或多道光微影遮罩與蝕刻製程使其成型為第一接觸墊1002與第二接觸墊1004。
在形成第一接觸墊1002與第二接觸墊1004後,可形成第一隔離區1005,使第一掺雜區203與第二掺雜區405得以與後續形成之第一閘極1003與第二閘極1007隔離。在一實施例中,第一隔離區1005形成於第一接觸墊1002、第二接觸墊1004、第一掺雜區203、與第二掺雜區405上,以提供隔離功能並適當的設置第一VGAA裝置1000與第二VGAA裝置1001之多種結構。在一實施例中,第一隔離區1005包含介電材料如氧化矽。第一隔離區亦可包含其他合適介電材料如氮化矽、氮氧化矽、掺雜碳的氧化矽、掺雜碳的氮化矽、或掺雜碳的氮氧化矽。在某些實施例中,介電材料層的沉積方法包含化學氣相沉積(CVD)、物理氣相沉積(PVD)、或旋轉塗佈法。進行CMP製程以移除高於第一奈米線901與第二奈米線903的部份介電材料,再回蝕刻介電材料至所需高度以幫助定義第一隔離區1005。
在形成第一隔離區1005後,可形成第一閘極介電
物1009與第一閘極1003圍繞第一奈米線901中的第一通道區605,並形成第二閘極介電物1011與第二閘極1007圍繞第二奈米線903中的第二通道區607。在某些實施例中,第一閘極介電物1009與第二閘極介電物1011可包含氧化矽、氮化矽、氮氧化矽、或高介電常數介電物如金屬氧化物。舉例來說,可用於高介電常數介電物的金屬氧化物包含鋰、鈹、鎂、鈣、鍶、鈧、釔、鋯、鉿、鋁、鑭、鈰、鐠、釹、釤、銪、釓、鋱、鏑、鈥、鉺、銩、鐿、鎦、或上述之混合物的氧化物。在此實施例中,第一閘極介電物1009與第二閘極介電物1011為厚度介於約5Å至30Å之間的高介電常數介電層。第一閘極介電物1009與第二閘極介電物1011的形成方法可為合適製程如原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、熱氧化物法、紫外線-臭氧氧化物、或上述之組合。第一閘極介電物1009與第二閘極介電物1011亦可包含界面層(未圖示)以減少第一奈米線901與第二奈米線903中第一閘極介電物1009、第二閘極介電物1011、與通道層601之間的損傷。界面層可包含氧化矽。
在形成第一閘極介電物1009與第二閘極介電物1011後,可形成第一閘極1003與第二閘極1007。在一實施例中,第一閘極1003與第二閘極1007的形成方法可先形成金屬層(未個別圖示於第10圖中)於第一閘極介電物1009與第二閘極介電物1011上。在某些實施例中,金屬層可包含單層或多層結構。在此實施例中,金屬層可包含金屬如鋁、銅、鎢、鈦、鉭、氮化鈦、鈦鋁、氮化鈦鋁、氮化鉭、鎳矽、鈷矽、功函數與基板材料相容的其他導電材料、或上述之組合。在此實施例中,
閘極層包含一致的厚度,其介於約1nm至約20nm之間。金屬層的形成方法可為合適製程如ALD、CVD、PVD、電鍍、或上述之組合。
在形成金屬層後,可選擇性蝕刻金屬層,使其圖案化成分隔的第一閘極1003與第二閘極1007。在一實施例中,使金屬層圖案化成第一閘極1003與第二閘極1007之步驟,係先施加第五光阻(未個別圖示於第10圖中),再圖案化第五光阻以露出欲移除的部份金屬層,並覆蓋欲保留的部份金屬層。
在圖案化第五光阻以露出部份金屬層後,採用第五光阻作為遮罩並蝕刻移除露出的部份金屬層。在某些實施例中,移除露出部份的金屬層之方法可採用反應性離子蝕刻製程。在金屬層圖案化成第一閘極1003與第二閘極1007後,可採用灰化製程移除第五光阻。
在形成第一閘極1003與第二閘極1007後,可形成第三隔離區1013,使第一奈米線901中的第三掺雜區603及第二奈米線903中的第四掺雜區703得以與第一閘極1003及第二閘極1007隔離。在一實施例中,第三隔離區1013包含介電材料如氧化矽。第三隔離區1013亦可包含其他合適介電材料如氮化矽、氮氧化矽、掺雜碳的氧化矽、掺雜碳的氮化矽、或掺雜碳的氮氧化矽。在某些實施例中,介電材料層的沉積方法包含CVD或PVD。接著可採用蝕刻製程,自第一奈米線901與第二奈米線903的頂部移除第三隔離區1013的材料。
接著可形成第四隔離區1015於第三隔離區1013上,以提供第一奈米線901與第二奈米線903周圍的第一閘極
1003與第二閘極1007額外的隔離,亦可提供比第三隔離區1013更平坦的表面以利後續製程。在一實施例中,第四隔離區1015可包含介電材料,其形成方法可為旋轉塗佈法,並填入第三隔離區907之間的空間。
在形成第三隔離區1013與第四隔離區1015後,可形成第三接觸墊1017以電性連接第一奈米線901,並形成第四接觸墊1019以電性連接第二奈米線903。在一實施例中,第三接觸墊1017用以提供第一奈米線901中的第三掺雜區603與接點(未各別圖示於第10圖中)之間的電性連接,而第四接觸墊1019用以提供第二奈米線903中的第四掺雜區703與接點之間的電性連接。在一實施例中,第三接觸墊1017與第四接觸墊1019之組成為導電材料如鋁,但亦可為其他合適材料如銅、鎢、或類似物。第三接觸墊1017與第四接觸墊1019之形成製程可為CVD或PVD,但其他合適材料與方法亦可用以形成第三接觸墊1017與第四接觸墊1019。在沉積第三接觸墊1017與第四接觸墊1019的材料後,可採用光微影遮罩與蝕刻製程使材料成型為第三接觸墊1017與第四接觸墊1019。
在形成第三接觸墊1017與第四接觸墊1019後,可形成第五隔離區1021以幫助隔離第三接觸墊1017與第四接觸墊1019。在一實施例中,第五隔離區1021包含介電材料如氧化矽。第五隔離區1021亦可包含其他合適介電材料如氮化矽、氮氧化矽、掺雜碳的氧化矽、掺雜碳的氮化矽、或掺雜碳的氮氧化矽。在某些實施例中,介電材料層的沉積方法包含CVD、PVD、或旋轉塗佈製程。可依需要進行CMP製程,以平坦化第
五隔離區1021。
在一實施例中,半導體裝置的形成方法,包括形成第一開口於半導體基板中,以及磊晶成長第一半導體材料於第一開口中。平坦化第一半導體材料與半導體基板。形成第二開口於第一半導體材料中,並磊晶成長第二半導體材料於第二開口中。平坦化第二半導體材料與第一半導體材料;以及磊晶成長通道層於第一半導體材料與第二半導體材料上。
在另一實施例中,半導體裝置的形成方法包括:將介電材料嵌置於半導體基板中。將第一半導體材料嵌置於半導體基板中,且此步驟至少部份採用第一磊晶成長製程。將第二半導體材料嵌置於半導體基板中,且此步驟至少部份採用第二磊晶製程,第二磊晶製程不同於第一磊晶製程,且第二半導體材料與第一半導體材料齊平。磊晶成長通道層於第一半導體材料與第二半導體材料上,其中至少部份的通道層延伸至介電材料上。
在又一實施例中,半導體裝置包括:第一導電區嵌置於基板中,且第一導電區具有第一導電型態。第二導電區嵌置於基板中,第二導電區具有第二導電型態,且第二導電型態與第一導電型態相反,其中第一導電區、第二導電區、與基板彼此齊平。介電材料嵌置於基板中。第一通道區物理接觸第一導電區,且第一通道區包含第一材料。第二通道區物理接觸第二導電區,且第二通道區包含第一材料。襯墊覆蓋介電材料的第一部份,其中襯墊包含第一材料。
上述實施例之特徵有利於本技術領域中具有通常
知識者理解本發明。本技術領域中具有通常知識者應理解可採用本申請案作為基礎,設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解,這些等效置換並未脫離本發明之精神與範疇,並可在未脫離本發明之精神與範疇的前提下進行改變、替換、或更動。
D3‧‧‧第三深度
H1‧‧‧第一高度
101‧‧‧基板
103‧‧‧對準標記
201‧‧‧第一開口
203‧‧‧第一掺雜區
403‧‧‧第二開口
405‧‧‧第二掺雜區
601‧‧‧通道層
603‧‧‧第三掺雜區
605‧‧‧第一通道區
607‧‧‧第二通道區
703‧‧‧第四掺雜區
901‧‧‧第一奈米線
903‧‧‧第二奈米線
905‧‧‧第四光阻
911‧‧‧虛置條
Claims (7)
- 一種半導體裝置的形成方法,包括:形成一第一開口於一半導體基板中;磊晶成長一第一半導體材料於該第一開口中;平坦化該第一半導體材料與該半導體基板;形成一第二開口於該第一半導體材料中;磊晶成長一第二半導體材料於該第二開口中;平坦化該第二半導體材料與該第一半導體材料;以及磊晶成長一通道層於該第一半導體材料與該第二半導體材料上。
- 如申請專利範圍第1項所述之半導體裝置的形成方法,更包括在磊晶成長該通道層前,先形成一介電材料於該半導體基板中,其中磊晶成長該通道層之步驟形成至少部份的該通道層延伸至該介電材料上,其中該介電材料係一對準標記。
- 如申請專利範圍第2項所述之半導體裝置的形成方法,更包括:磊晶成長一第三半導體材料於該通道層上;自該第一半導體材料、該第三半導體材料、與該通道層形成一第一奈米線;形成一第三開口於該第三半導體材料中;磊晶成長一第四半導體材料於該第三開口中,其中該第四半導體材料與該第二半導體材料具有相同的導電型態;以及 自該第二半導體材料、該第四半導體材料、與該通道層形成一第二奈米線。
- 一種半導體裝置的形成方法,包括:將一介電材料嵌置於一半導體基板中;將一第一半導體材料嵌置於該半導體基板中,且此步驟至少部份採用一第一磊晶成長製程;將一第二半導體材料嵌置於該半導體基板中,且此步驟至少部份採用一第二磊晶製程,該第二磊晶製程不同於該第一磊晶製程,且該第二半導體材料與該第一半導體材料齊平;以及磊晶成長一通道層於該第一半導體材料與該第二半導體材料上,其中至少部份的該通道層延伸至該介電材料上。
- 如申請專利範圍第4項所述之半導體裝置的形成方法,更包括磊晶成長一第三半導體材料於該通道層上,其中至少部份該第三半導體材料延伸至該介電材料上;形成一開口於該第三半導體材料中,以露出該通道層;磊晶成長一第四半導體材料於該開口中;以及使該第一半導體材料、該第三半導體材料、與該通道層圖案化成一第一奈米線,以及使該第二半導體材料、該第四半導體材料、與該通道層圖案化成一第二奈米線。
- 如申請專利範圍第5項所述之半導體裝置的形成方法,更包括使該通道層與該第三半導體層圖案化成一虛置條。
- 如申請專利範圍第5項所述之半導體裝置的形成方法,更包括自該第一奈米線形成一第一垂直式閘極全環繞裝置,以 及自該第二奈米線形成一第二垂直式閘極全環繞裝置。
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US10811413B2 (en) * | 2018-08-13 | 2020-10-20 | International Business Machines Corporation | Multi-threshold vertical FETs with common gates |
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