TWI780187B - 半導體裝置的形成方法與包含ｐ型場效電晶體結構的半導體裝置 - Google Patents

半導體裝置的形成方法與包含ｐ型場效電晶體結構的半導體裝置 Download PDF

Info

Publication number
TWI780187B
TWI780187B TW107125499A TW107125499A TWI780187B TW I780187 B TWI780187 B TW I780187B TW 107125499 A TW107125499 A TW 107125499A TW 107125499 A TW107125499 A TW 107125499A TW I780187 B TWI780187 B TW I780187B
Authority
TW
Taiwan
Prior art keywords
fin
recess
forming
semiconductor device
region
Prior art date
Application number
TW107125499A
Other languages
English (en)
Other versions
TW201944538A (zh
Inventor
林俊豪
林育樟
聶俊峰
張惠政
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201944538A publication Critical patent/TW201944538A/zh
Application granted granted Critical
Publication of TWI780187B publication Critical patent/TWI780187B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/105—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with vertical doping variation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

一實施例為半導體裝置的形成方法。方法包括形成鰭狀物於基板上。形成閘極結構於鰭狀物上。形成凹陷於與閘極結構相鄰的鰭狀物中。以p型摻質形成組成漸變摻雜區於鰭狀物中。組成漸變摻雜區自凹陷的下表面延伸至垂直深度，且垂直深度低於鰭狀物中的凹陷。形成源極/汲極區於凹陷中與組成漸變摻雜區上。

Description

半導體裝置的形成方法與包含p型場效電晶體結構 的半導體裝置
本發明實施例關於半導體裝置，更特別關於源極/汲極區下的組成漸變摻雜區。
隨著半導體產業進展至奈米製程節點以求更高裝置密度、更高效能、與更低成本，製程與設計所面臨的挑戰導致三維設計如鰭狀場效電晶體的發展。一般製作半導體裝置的方法為蝕刻至基板中，以形成自基板凸起的鰭狀結構。鰭狀場效電晶體的通道形成於垂直的鰭狀物中。閘極結構位於鰭狀結構上以包覆鰭狀結構。在通道區上的閘極結構有利於閘極控制其圍繞的通道。鰭狀場效電晶體裝置具有多種優點，比如減少短通道效應及增加電流。
隨著裝置尺寸持續縮小，可採用金屬閘極取代一般的多晶矽閘極以改善鰭狀場效電晶體裝置效能。形成金屬閘極的製程之一為置換閘極製程(亦稱作閘極後製製程)，其最後才製作最終的閘極堆疊。然而在進階製程節點中，實施此積體電路製程仍具有挑戰。
本發明一實施例提供之半導體裝置的形成方法，包括：形成鰭狀物於基板上；形成閘極結構於鰭狀物上；形成凹陷於與閘極結構相鄰的鰭狀物中；以p型摻質形成組成漸變摻雜區於鰭狀物中，組成漸變摻雜區自凹陷的下表面延伸至垂直深度，且垂直深度低於鰭狀物中的凹陷；以及形成源極/汲極區於凹陷中與組成漸變摻雜區上。
GND:接地
VDD:正極電源電壓
10、200:方法
20、30、40、50、60、202、204、206、208、210、212、214、216、218、220:步驟
100:半導體結構
102:基板
103A、103B:鰭狀結構
105:絕緣材料
108:n型井區
109:p型井區
110:磊晶材料
120、120A、120B:虛置閘極結構
122:介電層
124:虛置層
126:硬遮罩層
130:閘極間隔物
140、142:遮罩
150、150A、150B:凹陷
150D、160DB、160DM、160DT:深度
150W:寬度
160:組成漸變摻雜區
170:源極/汲極區
180:接點蝕刻停止層
182:第一層間介電層
184:第二層間介電層
186:接點
190:置換閘極結構
192:閘極介電層
194:金屬襯墊層
195:功函數調整層
196:導電閘極充填物
300:互補式金氧半裝置
310:p型場效電晶體裝置
320:n型場效電晶體裝置
第1圖係一些實施例中，形成半導體裝置的方法之流程圖。
第2、3B與3C、4、5A與5B、6A與6B、及7圖係一些實施例中，半導體裝置於形成半導體裝置的中間階段之中間結構的剖視圖。
第3A圖係一些實施例中，具有兩個閘極結構形成於第一組的兩個鰭狀結構與第二組的兩個鰭狀結構上之基板的剖視圖。
第8圖係一些實施例中，形成半導體裝置如鰭狀場效電晶體結構於基板上之另一方法的流程圖。
第9、10、11、12、13、與14圖係一些實施例中，半導體裝置於形成半導體裝置的中間階段之中間結構的剖視圖。
第15圖係一些實施例中，互補式金氧半裝置的示意圖。
下述內容提供的不同實施例可實施本發明的不同結構。特定構件與排列的實施例係用以簡化而非侷限本發明實施例。舉例來說，形成第一構件於第二構件上的敘述包含兩者直 接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明之多種例子中可重複標號，但這些重複僅用以簡化與清楚說明，不代表不同實施例及/或設置之間具有相同標號之單元之間具有相同的對應關係。
此外，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
此處揭露的實施例一般關於形成組成漸變摻雜區於鰭狀結構的方法，比如沿著凹陷的表面(如下表面)形成p型應變通道裝置的源極/汲極結構。在這些實施例中，組成漸變摻雜區有助於降低p型應變通道裝置的通道電阻與寄生電阻。在這些實施例中，較低的通道電阻及/或較低的寄生電阻有助於減少或避免互補式金氧半裝置的閂鎖(latch-up)問題。
第1圖係一些實施例中，形成半導體裝置(如鰭狀場效電晶體結構)於基板上之方法10的流程圖。在一些實施例中，方法10的細節將搭配第2至7圖說明，其為形成半導體結構100(如鰭狀場效電晶體半導體裝置)於基板102上之多種階段的圖式。
第2圖係基板102的剖視圖。基板102可為半導體晶圓如矽晶圓。基板102可改為或額外包含半導體元素材料、半導體化合物材料、及/或半導體合金材料。半導體元素材料的例 子可包含但不限於矽或鍺。在這些實施例中，基板102為本質矽基板，其可適當地摻雜n型摻質以形成n型井區，並摻雜p型摻質以形成p型井區。在這些實施例中，基板102為p型基板，其含有p型摻質以形成p型井區109，並摻雜n型摻質以形成n型井區108。在這些實施例中，基板102為n型基板，其含有n型摻質以形成n型井區108，並摻雜p型摻質以形成p型井區109。
在方法10的步驟20中，形成一或多個鰭狀結構103A於n型井區108的基板102上。一或多個鰭狀結構103B亦可形成於p型井區上。鰭狀結構103A與鰭狀結構103B可同時形成或分開形成。在這些實施例中，圖案化基板102以形成鰭狀結構103A與103B。進行圖案化製程以形成凹陷(未圖示)於基板102中，以定義基板102中的鰭狀結構103A與103B。凹陷具有絕緣材料105形成其中。可採用任何合適方法圖案化鰭狀結構103A與103B。舉例來說，鰭狀結構103A與103B的圖案化方法可採用一或多道光微影製程，包括雙重圖案化製程或多重圖案化製程。一般而言，雙重圖案化或多重圖案化製程結合光微影與自對準製程，其產生的圖案間距小於單一的直接光微影製程所得之圖案間距。舉例來說，一實施例可形成犧牲層於基板上，並採用光微影製程圖案化犧牲層。採用自對準製程，以沿著圖案化的犧牲層形成間隔物。接著移除犧牲層，而保留的間隔物接著可用於圖案化鰭狀結構103A與103B。
如第2圖所示，基板亦可包含磊晶材料110形成於基板102上，以形成鰭狀結構103A。舉例來說，磊晶材料110可沉積於基板102的n型井區108上。磊晶材料110形成鰭狀結構 103A，其可為矽鍺(SixGe1-x，其中x介於近似0與1之間)。舉例來說，SixGe1-x的鰭狀結構103A中，x介於約0.05至約0.50之間時，其可用於形成應變通道於p型場效電晶體裝置中。在其他實施例中，磊晶材料110形成的鰭狀結構103A可為鍺、III-V族半導體化合物、II-VI族半導體化合物、或類似物。舉例來說，用以形成III-V族半導體化合物的材料包括砷化銦、砷化鋁、砷化鎵、磷化銦、氮化鎵、砷化銦鎵、砷化銦鋁、銻化鎵、銻化鋁、磷化鋁、磷化鎵、或類似物。磊晶材料110的沉積方法可為化學氣相沉積、低壓化學氣相沉積、原子層化學氣相沉積、超真空化學氣相沉積、遠端電漿增強化學氣相沉積、氣相磊晶、分子束磊晶、任何其他合適的沉積製程、或任何上述的組合。
在第2圖所示的實施例中，圖案化以蝕刻基板102及其上的磊晶材料110，可形成鰭狀結構103A(如矽鍺鰭狀結構)。圖案化與蝕刻基板102(不具磊晶材料110或具有矽磊晶材料於其上)可形成矽的鰭狀結構103B。在其他實施例中，n型井區108上的鰭狀結構103A亦可包含矽的鰭狀結構(不具有磊晶材料110)。
在一些實施例中，定義鰭狀結構103A與103B的凹陷可填有絕緣材料105。絕緣材料105可形成淺溝槽隔離結構。絕緣材料105可為或包含氧化矽、氮化矽、氮氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃、其他介電層、或上述之多層。絕緣材料105的沉積方法可為任何可接受的沉積製程。使絕緣材料105凹陷，可使鰭狀結構103A與103B凸起 高於絕緣材料105。
在其他實施例中，可形成介電層於半導體的基板102之上表面上、蝕刻穿過介電層以形成溝槽、磊晶成長磊晶結構(如單質磊晶或異質磊晶結構)於溝槽中、以及使介電層凹陷以讓磊晶結構自介電層凸起形成鰭狀物。這些製程形成的鰭狀物，一般可具有與第2圖所示者類似的結構。
在方法10的步驟30中，形成閘極結構(如虛置閘極結構120)於鰭狀結構103A與103B上，如第3A至3C圖所示。第3A圖係一些實施例中，第2圖的基板102之透視圖，其具有兩個虛置閘極結構120形成於兩個鰭狀結構103A(如矽鍺鰭狀物或矽鰭狀物)與兩個鰭狀結構103B(如矽鰭狀物)上。第3B圖係基板102在第3A圖的平面Y中的剖視圖，其縱向地沿著虛置閘極結構120之一。第3A與3B圖的半導體結構100顯示形成互補式金氧半裝置的階段之一。形成於n型井區108上的鰭狀結構103A上的閘極結構，可形成p型場效電晶體裝置。形成於p型井區109上的鰭狀結構103B上的閘極結構，可形成n型場效電晶體裝置。第3C圖係基板102在第3A圖中的X平面之剖視圖，其穿過n型井區108的鰭狀結構103A。
虛置閘極結構120可包含介電層122、一或多個虛置層124、與硬遮罩層126。介電層122可為氧化矽、氮氧化矽、其他介電層、或上述之多層。虛置層124可為多晶矽層或其他合適材料。硬遮罩層126可為任何合適材料，比如氮化矽、氮氧化矽、或碳氮化矽，其可圖案化基板上的虛置閘極結構120至具有所需結構與尺寸。介電層122、虛置層124、與硬遮罩層 126的沉積方法可為一或多道合適的沉積製程。可採用合適的光微影與蝕刻技術圖案化虛置閘極結構120，以露出鰭狀結構103A與103B的部份。虛置閘極結構120囓合鰭狀結構103A與103B的頂部與側部。
此處所述的用語「虛置」指的是在後段階段中將移除的犧牲結構，其將取代為另一結構如置換閘極製程中的高介電常數介電層與金屬閘極結構。置換閘極製程指的是在整個閘極製程的後段階段中，形成閘極結構的製程。
在第4圖中，沿著虛置閘極結構120的側壁形成閘極間隔物130。第4圖係基板的剖視圖，且剖視方向穿過第3C圖的n型井區108上的鰭狀結構103A。為簡化說明，半導體結構的形成方法將搭配第4至7圖說明，其僅顯示n型井區108上的鰭狀結構103A，而未顯示p型井區109上的鰭狀結構103B。在對n型井區108上的鰭狀結構103A進行製程的一或多道步驟時，可對鰭狀結構103B同時進行這些步驟，及/或以遮罩保護鰭狀結構103B。
閘極間隔物130可為或包含碳氮化矽、氮化矽、碳化矽、氮氧化矽、氧化矽、其他可行材料、或上述之組合。可順應性地沉積並非等向蝕刻(如乾蝕刻製程)用於閘極間隔物130的層狀物，以自鰭狀結構103A的表面移除用於閘極間隔物130的層狀物，並沿著虛置閘極結構120保留閘極間隔物130。
在方法10的步驟40中，形成凹陷150於鰭狀結構103A中。虛置閘極結構120未覆蓋而閘極間隔物130覆蓋的鰭狀結構103A的區域，被蝕刻以形成凹陷150。上述蝕刻方法可為 乾蝕刻製程及/或濕蝕刻製程。舉例來說，凹陷150的形成方法可採用非等向的濕蝕刻劑，比如氫氧化四甲基銨。氫氧化四甲基銨可在凹陷150中產生<111>平面，以形成晶面形狀的凹陷。在這些實施例中，可採用氫氧化四甲基銨蝕刻劑蝕刻基板102，且此蝕刻劑所含的水性溶液其氫氧化四甲基銨濃度介於1%至30%之間，而蝕刻溫度介於約20℃至約90℃之間。
在其他實施例中，凹陷150的底部及/或側壁的形狀可為角形、圓潤形、及/或其他形狀。形成於鰭狀結構103A中的凹陷150可具有所需的深度與寬度。舉例來說，凹陷150自鰭狀結構103A的頂部至凹陷150之最底端的深度150D，可介於約30nm至約100nm之間，在其他實施例中，凹陷150的深度150D介於約40nm至約60nm之間。凹陷150的寬度150W來自鰭狀結構103A的最寬長度，其可介於約20nm至約90nm之間。在其他實施例中，凹陷150的寬度150W介於約30nm至約50nm之間。對步驟50即將形成的組成漸變摻雜區160而言，凹陷150的深度150D與寬度150W可提供足夠的空間。
在方法10的步驟50中，形成組成漸變摻雜區160於凹陷的鰭狀結構103A中，如第5A與5B圖所示。第5A圖係一些實施例中基板102的剖視圖，其形成組成漸變摻雜區160於第4圖之凹陷的鰭狀結構103A中。第5B圖係一些實施例中，組成漸變摻雜區160在Z方向中的圖式。可採用虛置閘極結構120與閘極間隔物130作為遮罩，佈植摻質至凹陷的鰭狀結構103A中，以形成組成漸變摻雜區160於鰭狀結構103A的頂部。摻質的例子包含硼摻質如二氟化硼以用於p型裝置，不過亦可採用其他 摻質。在其他實施例中，摻質濃度比習知裝置中形成的輕摻雜源極/汲極區的摻質濃度低至少兩個級數。在這些實施例中，組成漸變的摻雜區160與輕摻雜源極/汲極區不同，因為其佈植製程在形成閘極間隔物130之後。輕摻雜源極/汲極區的佈植製程可能造成凹陷的鰭狀結構103A之頂部的摻質濃度過高。凹陷的鰭狀結構103A之頂部的摻質濃度過高，可能導致不想要的現象如摻質擴散至電晶體通道中，這將造成短通道效應及/或損傷虛置閘極結構120(或損傷其他基板結構與層狀物)。在一些例子中，可省略鰭狀結構103A的輕摻雜源極/汲極區。然而在其他例子中，可形成輕摻雜源極/汲極區於鰭狀結構103A中。
佈植摻質至凹陷的鰭狀結構103A中的方法，可採用離子佈植以得摻質漸變的輪廓。用以形成組成漸變摻雜區160的離子佈植製程之一例，包含的離子束能量介於近似1KeV至近似15KeV之間，且包含的傾斜角度介於近似0度至近似15度之間。斜向佈植有助於佈植組成漸變摻雜區160的側壁。佈植至鰭狀結構103A中的組成漸變摻雜區160之底部的摻質，其深度160DB介於約5nm至約20nm之間，且摻質濃度介於約1×1019cm-3至約1×1021cm-3之間。佈植至鰭狀結構103A中的組成漸變摻雜區160之中間部份的摻質，其深度160DM介於約3nm至約15nm之間，且摻質濃度介於約5×1018cm-3至約5×1020cm-3之間。佈植至鰭狀結構103A中的組成漸變摻雜區160之頂部的摻質，其深度160DT介於約1nm至約10nm之間，且摻質濃度介於約1×1018cm-3至約1×1020cm-3之間。在這些實施例中，佈植摻質至鰭狀結構103A的製程不需佈植後退火及/或額外的清潔步 驟。
在方法10的步驟60中，沉積源極/汲極區170於p型裝置區中凹陷的鰭狀結構103A中的組成漸變的摻雜區160上，如第6A與6B圖所示。第6A圖係一些實施例中基板102的剖視圖，其於第5A圖的鰭狀結構103A中的組成漸變摻雜區160上形成源極/汲極區170。第6B圖係一些實施例中，組成漸變摻雜區160與源極/汲極區170在Z方向中的圖式。源極/汲極區170位於虛置閘極結構120兩側上的凹陷的鰭狀結構103A的組成漸變摻雜區160上，並與個別的閘極間隔物130相鄰。虛置閘極結構120形成於具有鰭狀結構103A的n型井區108上，而鰭狀結構103A具有組成漸變摻雜區160(佈植有p型摻質)。上述結構之後將形成p型鰭狀場效電晶體結構。
源極/汲極區170包含的半導體材料，可磊晶成長於凹陷的鰭狀結構103A的凹陷150中的組成漸變摻雜區160上。舉例來說，p型鰭狀場效電晶體裝置的源極/汲極區170可包含矽鍺、摻雜硼的矽鍺、攙雜硼的矽、或類似物。舉例來說，源極/汲極區170可包含矽鍺，其鍺含量介於約30%至約70%之間。舉例來說，源極/汲極區170可包含摻雜硼的矽鍺，其鍺含量介於約30%至約70%之間，且其硼濃度介於約1×1019原子/cn3至約5×1021原子/cm3之間。矽鍺的源極/汲極區170的鍺含量，有助於誘發應變於通道裝置中，進而增加載子移動率。舉例來說，摻雜硼的矽的硼濃度可介於約1×1019原子/cm3至約5×1021原子/cm3之間。硼濃度有助於增加個別源極/汲極區170之間的載子移動率。磊晶成長源極/汲極區170的步驟，可選擇性成長於凹 陷的鰭狀結構103A的結晶表面上。在磊晶成長製程中，可垂直成長與水準成長源極/汲極區170以形成晶面，且晶面對應鰭狀結構103A的結晶平面。由於不同表面具有不同結晶取向，在不同表面上的成長速率也不同。因此源極/汲極區170的形狀可為鑽石狀結構或其他形狀，端視凹陷150的下表面與源極/汲極區170的磊晶成長之橫向成長與垂直成長而定。
源極/汲極區170的形成方法可為沉積多個層狀物，其具有不同濃度的元素(比如摻質及/或半導體元素如鍺)。源極/汲極區170可與相鄰的平行鰭狀結構上的相鄰源極/汲極區合併或不合併。
源極/汲極區170的沉積方法可為分子束磊晶、液相磊晶、氣相磊晶、選擇相磊晶成長、類似製程、任何其他合適的沉積製程、或任何上述的組合。可在磊晶沉積時原位摻雜源極/汲極區170，及/或佈植摻質至源極/汲極區170中。
在這些實施例中，源極/汲極區170可誘發應變於通道中，而通道由虛置閘極結構120覆蓋的鰭狀結構103A所定義。舉例來說，源極/汲極區170包含矽鍺時可誘發壓縮應變於通道中。應變通道層可增加載子移動率，因此增加裝置(如鰭狀場效電晶體裝置)的驅動電流。
第7圖顯示形成接點蝕刻停止層180，以及形成第一層間介電層182於接點蝕刻停止層180上之後的中間結構。一般而言，蝕刻停止層180在形成接點或通孔時，可提供停止蝕刻製程的機制。接點蝕刻停止層180的組成可為蝕刻選擇性不同於相鄰的層狀物或構件之介電材料。順應性地沉積接點蝕刻停 止層180於源極/汲極區170的表面以及閘極間隔物130的側壁與上表面上，且順應性沉積可為合適的沉積製程。接點蝕刻停止層180可包含或可為氮化矽、碳氮化矽、碳氧化矽、氮化碳、類似物、或上述之組合。第一層間介電層182可包含或可為氧化矽、低介電常數的介電材料(比如介電常數低於氧化矽之介電常數的材料)、氮氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、摻雜氟的矽酸鹽玻璃、有機矽酸鹽玻璃、碳氧化矽、旋轉塗佈玻璃、旋轉塗佈聚合物、碳矽材料、上述之化合物、上述之複合物、類似物、或上述之組合。在沉積第一層間介電層182之後，可以化學機械研磨等製程平坦化第一層間介電層182，其可移除硬遮罩層126並露出第6圖的虛置閘極結構120的虛置層124。
第7圖更顯示以個別的置換閘極結構190取代虛置閘極結構120、形成第二層間介電層184、與形成接點186之後的中間結構。移除虛置閘極結構120以形成溝槽，且移除方法可為適當的蝕刻製程。溝槽填有個別的置換閘極結構190。置換閘極結構190各自包含閘極介電層192、視情況形成的金屬襯墊層194、功函數調整層195、與導電閘極充填物196。順應性的閘極介電層192、視情況形成的金屬襯墊層194、與導電閘極充填物196的沉積方法可為合適的沉積技術。
閘極介電層192可順應性地形成於溝槽中，比如沿著鰭狀結構103A的側壁與上表面以及沿著閘極間隔物130的側壁。閘極介電層192可為氧化矽、氮化矽、高介電常數的介電材料、或上述之多層。高介電常數的介電材料(如介電常數大 於約7.0的介電材料)可包含或可為鉿、鋁、鋯、鑭、鎂、鈦、釔、鈧、鎦、釓、鏑、鈣、釤、或上述之組合的金屬氧化物或金屬矽酸鹽。
可順應性地形成一或多個金屬襯墊層194於閘極介電層192上。金屬襯墊層194可包含蓋層及/或阻障層。蓋層及/或阻障層可用以避免雜質擴散至下方的層狀物，或避免雜質自下方的層狀物擴散。蓋層及/或阻障層可包含氮化鉭、氮化鈦、類似物、或上述之組合。
功函數調整層195可擇以調整功函數值，使電晶體達到所需的臨界電壓。功函數調整層195包含鉭鋁、氮化鉭、碳化鉭鋁、碳化鉭、碳氮化鉭、氮化鉭矽、鈦、氮化鈦、氮化鈦鋁、銀、錳、鋯、釕、鉬、鋁、氮化鎢、鋯矽化物、鉬矽化物、鉭矽化物、鎳矽化物、其他合適的功函數材料、或上述之組合。
導電閘極充填物196形成於功函數調整層195上並填入溝槽。導電閘極充填物196可包括含金屬材料如鎢、鈷、釕、鋁、氮化鈦、氮化鉭、碳化鉭、氮化鋁鈦、碳化鋁鈦、氧化鋁鈦、上述之組合、或上述之多層。
移除第一層間介電層182、接點蝕刻停止層180、與閘極間隔物130的上表面上的導電閘極充填物196、視情況形成的金屬襯墊層194、與閘極介電層192的部份，且移除方法可為平坦化製程如化學機械研磨製程。
形成第二層間介電層184於第一層間介電層182、置換閘極結構190、閘極間隔物130、與接點蝕刻停止層180上。雖然未圖示，但一些例子可沉積蝕刻停止層於第一層間介電層 182上，而第二層間介電層184可沉積於蝕刻停止層上。第二層間介電層184可包含或可為氧化矽、低介電常數的介電材料、氮氧化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、摻雜硼的磷矽酸鹽玻璃、未摻雜的矽酸鹽玻璃、摻雜氟的矽酸鹽玻璃、有機矽酸鹽玻璃、碳氧化矽、旋轉塗佈玻璃、旋轉塗佈聚合物、碳矽材料、上述之化合物、上述之複合物、類似物、或上述之組合。第二層間介電層184的沉積方法可為任何可接受的沉積技術。
形成開口穿過第二層間介電層184、第一層間介電層182、與接點蝕刻停止層180至源極/汲極區170，以露出源極/汲極區170的至少部份。開口的形成方法可採用合適的光微影與一或多道蝕刻製程。接點186形成於開口中，以至源極/汲極區170。接點186亦可包含充填金屬如鎢、鋁、鈷、釕、銅、或其他合適金屬。接點186亦可包含矽化物於個別的源極/汲極區170上，以及阻障及/或黏著層於充填金屬與開口側壁之間。
第8圖係一些實施例中，形成半導體裝置(如鰭狀場效電晶體結構)於基板上之另一方法200的流程圖。在一些實施例中，方法200的細節將搭配第9至14圖說明，其為形成半導體結構100(如鰭狀場效電晶體半導體裝置)於基板102上之多種階段的圖式。
在方法200的步驟202中，形成鰭狀結構103A於n型井區108上的基板102上，如第9圖所示。第9圖的鰭狀結構103A與第3C圖的鰭狀結構103A類似，因此採用類似標號以簡化說明。鰭狀結構103A可為矽鍺鰭狀結構及/或矽鰭狀結構。
在方法200的步驟204中，形成第一組閘極結構與第 二組閘極結構於鰭狀結構103A上。舉例來說，兩組的虛置閘極結構120A與120B可形成於n型井區108上的鰭狀結構103A上。圖式中的兩組虛置閘極結構120A與120B各自具有兩個虛置鰭狀結構，但可具有任何數目的虛置鰭狀結構。虛置閘極結構120A與120B可形成於相同的鰭狀結構103A或不同的鰭狀結構103A上。每一虛置閘極結構120A與120B可包含介電層122、一或多個虛置層124、與硬遮罩層126。沿著虛置閘極結構120A與120B的側壁形成閘極間隔物130，如前所述。
每一組的虛置閘極結構120A與120B可位於不同區域中，比如邏輯核心區、記憶區(如埋置靜態隨機存取記憶區)、類比區、輸入/輸出區(又稱作周邊區)、虛置區(用以形成虛置圖案)、或類似區。舉例來說，虛置閘極結構120A可用於記憶區(如靜態隨機存取記憶區)，而虛置閘極結構120B可用於邏輯核心區。
在步驟206中，形成遮罩140於具有第二組的閘極結構(如虛置閘極結構120B)的鰭狀結構103A之區域上，而遮罩140未覆蓋具有第一組的閘極結構(如虛置閘極結構120A)的鰭狀結構103A之區域，如第10圖所示。遮罩140可為顯影的光阻，或以顯影的光阻圖案化之硬遮罩。
在方法200的步驟208中，形成凹陷150A於具有第一組閘極結構(如虛置閘極結構120A)的鰭狀結構103A的區域中。虛置閘極結構120A未覆蓋而閘極間隔物130覆蓋的鰭狀結構103A的區域，被蝕刻以形成凹陷150A。凹陷150A的底部及/或側壁的形狀可為角形、圓潤形、或平坦形。形成於鰭狀結構 103A中的凹陷150A可具有所需深度。
在方法200的步驟210中，形成組成漸變摻雜區160於凹陷的鰭狀結構103A中，如第11圖所示。在一些實施例中，第11圖係基板102的剖視圖，其形成組成漸變的摻雜區160於第10圖之凹陷的鰭狀結構103A中。可採用虛置閘極結構120A與閘極間隔物130作為遮罩，佈植摻質至凹陷的鰭狀結構103A中，以形成組成漸變摻雜區160於鰭狀結構103A的頂部。
在其他實施例中，摻質濃度比習知裝置中形成的輕摻雜源極/汲極區的摻質濃度低至少兩個級數。輕摻雜源極/汲極區的佈植製程可能造成凹陷的鰭狀結構103A之頂部的摻質濃度過高。凹陷的鰭狀結構103A之頂部的摻質濃度過高，可能導致不想要的現象如摻質擴散至電晶體通道中，這將造成短通道效應及/或損傷虛置閘極結構120(或損傷其他基板結構與層狀物)。在一些例子中，可省略鰭狀結構103A的輕摻雜源極/汲極區。然而在其他例子中，可形成輕摻雜源極/汲極區於鰭狀結構103A中。
佈植摻質至凹陷的鰭狀結構103A中的方法，可採用離子佈植以得摻質漸變的輪廓。摻質的例子包含硼摻質如二氟化硼以用於p型裝置，不過亦可採用其他摻質。用以形成組成漸變摻雜區160的離子佈植製程之一例，包含的離子束能量介於近似1KeV至近似15KeV之間，且包含的傾斜角度介於近似0度至近似15度之間。斜向佈植有助於佈植組成漸變摻雜區160的側壁。佈植至鰭狀結構103A中的組成漸變摻雜區160之底部的摻質，其深度160DB介於約5nm至約20nm之間，且摻質濃度 介於約1×1019cm-3至約1×1021cm-3之間。佈植至鰭狀結構103A中的組成漸變摻雜區160之中間部份的摻質，其深度160DM介於約3nm至約15nm之間，且摻質濃度介於約5×1018cm-3至約5×1020cm-3之間。佈植至鰭狀結構103A中的組成漸變摻雜區160之頂部的摻質，其深度160DT介於約1nm至約10nm之間，且摻質濃度介於約1×1018cm-3至約1×1020cm-3之間。在這些實施例中，佈植摻質至鰭狀結構103A的製程不需佈植後退火及/或額外的清潔步驟。
在步驟212中，覆蓋具有虛置閘極結構120B的鰭狀結構103A的區域之遮罩140被移除，如第12圖所示。遮罩140的移除方法可為灰化、蝕刻、濕式剝除、或另一合適製程。
在步驟214中，形成遮罩142於具有第一組閘極結構(如虛置閘極結構120A)的鰭狀結構103A的區域上，且遮罩142未覆蓋具有第二組閘極結構(如虛置閘極結構120B)的鰭狀結構103A的區域。遮罩142可為顯影的光阻，或採用顯影的光阻圖案化的硬遮罩。
在方法200的步驟216中，形成凹陷150B於具有第二組閘極結構(如虛置閘極結構120B)的鰭狀結構103A的區域中。虛置閘極結構120B未覆蓋而閘極間隔物130覆蓋的鰭狀結構103A的區域，被蝕刻以形成凹陷150B。凹陷150B的底部及/或側壁的形狀可為角形、圓潤形、或平坦形。鰭狀物103A中的凹陷150B可形成以具有所需深度。
在步驟218中，覆蓋具有虛置閘極結構120A的鰭狀結構103A之區域的遮罩142將被移除，如第13圖所示。移除遮 罩142的方法可為灰化、蝕刻、濕式剝除、或另一合適製程。
在方法200的步驟220中，源極/汲極區170沉積於具有虛置閘極結構120A於其上之凹陷的鰭狀結構103A的組成漸變摻雜區160上，並沉積於具有虛置閘極結構120B於其上之凹陷的鰭狀結構103A上(不具有組成漸變摻雜區，比如非佈植區)。具有虛置閘極結構120而無組成漸變摻雜區的凹陷的鰭狀結構103A的區域，之後可包含自源極/汲極區170擴散至凹陷的鰭狀結構103A中的摻質。
源極/汲極區170包含的半導體材料，可磊晶成長於凹陷的鰭狀結構103A的凹陷150A與150B中。舉例來說，p型鰭狀場效電晶體裝置的源極/汲極區170可包含矽鍺、摻雜硼的矽鍺、攙雜硼的矽、或類似物。源極/汲極區170的形成方法可為沉積多個層狀物。源極/汲極區170可與相鄰的平行鰭狀結構上的相鄰源極/汲極區合併或不合併。在這些實施例中，源極/汲極區170可誘發應變於通道中，而通道由虛置閘極結構120A與120B覆蓋的鰭狀結構103A所定義。舉例來說，源極/汲極區170包含矽鍺時可誘發壓縮應變於通道中。應變通道層可增加載子移動率，因此增加裝置(如鰭狀場效電晶體裝置)的驅動電流。
第14圖顯示形成接點蝕刻停止層180，以及形成第一層間介電層182於接點蝕刻停止層180上之後的中間結構。順應性地沉積接點蝕刻停止層180於源極/汲極區170的表面以及閘極間隔物130的側壁與上表面上，且順應性沉積可為合適的沉積製程。在沉積第一層間介電層182之後，可以化學機械研磨等製程平坦化第一層間介電層182，其可移除硬遮罩層126並露 出第13圖的虛置閘極結構120的虛置層124。
第14圖更顯示以個別的置換閘極結構190取代虛置閘極結構120、形成第二層間介電層184、與形成接點186之後的中間結構。移除虛置閘極結構120以形成溝槽，且移除方法可為適當的蝕刻製程。溝槽填有個別的置換閘極結構190。置換閘極結構190各自包含順應性的閘極介電層192、視情況形成的金屬襯墊層194、與導電閘極充填物196。順應性的閘極介電層192、視情況形成的金屬襯墊層194、與導電閘極充填物196的形成方法，可與第7圖的前述方法類似。
第二層間介電層184形成於第一層間介電層182、置換閘極結構190、閘極間隔物130、與接點蝕刻停止層180上。雖然未圖示，但一些例子可沉積蝕刻停止層於第一層間介電層182與其他層狀物上，而第二層間介電層184可沉積於蝕刻停止層上。第二層間介電層184的沉積方法可為任何可接受的沉積技術。
形成開口以穿過第二層間介電層184、第一層間介電層182、與接點蝕刻停止層180至源極/汲極區170，以露出源極/汲極區170的至少部份。開口的形成方法可採用合適的光微影與一或多道蝕刻製程。接點186形成於開口中，以至源極/汲極區170。接點186亦可包含矽化物於個別的源極/汲極區170上，以及阻障及/或黏著層於充填金屬與開口側壁之間。
應理解的是，第2至7圖與第9至14圖所示的鰭狀結構103A與103B以及虛置閘極結構120、120A、與120B僅用於說明目的。鰭狀結構與閘極結構的數目可為任何數目，端視應用而 定。雖然此處所述的閘極結構的製作方法採用置換閘極製程，但亦可採用本技術領域域中具有通常知識者已知的閘極優先製程製作閘極結構。雖然此處所述的源極/汲極之製作方法採用凹陷的鰭狀物，但源極/汲極的製作方法可不形成凹陷於鰭狀物中。
在這些實施例中，方法200形成p型場效電晶體結構於不同區域中。在一或多個區域中，p型場效電晶體結構具有組成漸變摻雜區160。在一或多個其他區域中，p型場效電晶體結構不具有組成漸變摻雜區(比如無佈植)。方法200可調整不同區域如邏輯核心區、記憶區、類比區、輸入/輸出區、虛置區、或其他合適區中的p型場效電晶體結構之通道電阻。
第15圖係一些實施例中，互補式金氧半裝置300的示意圖。互補式金氧半裝置的形成方法可為第1圖的方法10及/或第8圖的方法200。
互補式金氧半裝置包含p型場效電晶體裝置310與n型場效電晶體裝置320。p型場效電晶體裝置310具有組成漸變摻雜區160，其通道電阻低於約5.4KΩ*鰭狀物數目，且其寄生電阻低於約7.1KΩ*鰭狀物數目。在這些實施例中，p型場效電晶體裝置310的通道電阻介於約1KΩ*鰭狀物數目至約5.0KΩ*鰭狀物數目之間。在這些實施例中，p型場效電晶體裝置310的寄生電阻介於約1KΩ*鰭狀物數目至約7.0KΩ*鰭狀物數目之間。較低的通道電阻與寄生電阻有助於降低或避免互補式金氧半裝置300的閂鎖問題。在電流不受p型場效電晶體裝置310與n型場效電晶體320的閘極控制而自正極電源電壓VDD直接 接地GND時，將產生閂鎖問題。據信電流不受p型場效電晶體裝置310與n型場效電晶體320的閘極控制的原因在於，不具有組成漸變的摻雜區之鰭狀結構103A的高電阻。電流自正極電源電壓VDD直接接地GND，可能造成短路狀態與過量電流。具有組成漸變摻雜區160的P型場效電晶體裝置310，不需增加隔離區尺寸即可減少或避免閂鎖問題。
實施例
矽鍺鰭狀物形成於基板上，並使矽鍺鰭狀物凹陷以形成凹陷的矽鍺鰭狀物。在實施例1與實施例2中，組成漸變的硼摻雜區形成於凹陷的矽鍺鰭狀物上。進行佈植以形成組成漸變的硼摻雜區，且佈植能量介於約1KeV至約5KeV之間。在實施例1中，以介於約1×1011cm-2至約5×1013cm-2之間的摻質劑量佈植凹陷的矽鍺鰭狀物。在實施例2中，以介於約6×1013cm-2至約1×1014cm-2之間的摻質劑量佈植凹陷的矽鍺鰭狀物。
凹陷的鰭狀物特性量測如第1表所示。開關電流比(Ion/Ioff)提供個別閘極的開啟與關閉速度的量測標準。Ion為開啟電流，而Ioff為關閉電流。高開關電流比可視作半導體裝置效能高。實施例1與實施例2中，組成漸變摻雜區形成於凹陷的矽鍺鰭狀物上，可比其他裝置具有較高的開關電流比。開關電流比與通道電阻(及寄生電阻)成反比。寄生電阻包含閘極電阻與源極/汲極電阻。實施例1與實施例2中的組成漸變摻雜區形成於凹陷的矽鍺鰭狀物上，可比其他裝置具有更低的通道電阻與寄生電阻。
第1表
Figure 107125499-A0305-02-0024-1
在這些實施例中，組成漸變摻雜區160(如組成漸變的硼摻雜區)可降低通道電阻與寄生電阻。在這些實施例中，源極/汲極區可形成於凹陷的鰭狀物之組成漸變摻雜區160(如組成漸變硼摻雜區)上，其中源極/汲極區可誘發應變於通道區(由形成於鰭狀物上的閘極所定義)中。
在這些實施例中，組成漸變摻雜區160可用於互補式金氧半裝置中。舉例來說，凹陷的鰭狀結構103A如凹陷的矽鍺鰭狀物或凹陷的矽鰭狀物，其具有組成漸變摻雜區160並可用於p型場效電晶體或互補式金氧半裝置中。
應理解的是半導體裝置與其形成方法亦可包含額外的層狀物，比如光阻層、遮罩層、擴散阻障層、蓋層、矽化物層、蝕刻停止層、介電層、黏著層、或其他合適的層狀物。半導體裝置與其形成方法亦可包含額外製程，比如塗佈光阻(如旋轉塗佈)、軟烘烤、對準光罩、曝光、曝光後烘烤、顯影光阻、沖洗、乾燥、硬烘烤、偵測、蝕刻、平坦化、化學機械研磨、濕式清潔、灰化、及/或其他可行製程。
應理解的是，p型場效電晶體裝置亦可與n型場效電晶體裝置的形成方法整合。應理解的是，基板可包含多種層狀物(如導電層、半導體層、或絕緣層)及/或結構(摻雜區、井區、鰭狀物、源極/汲極區、隔離區、淺溝槽隔離結構、閘極結構、內連線線路、通孔、或其他合適結構)形成於基板之中及/或之 上。多個層狀物及/或結構用於製作半導體裝置與積體電路。在此處所述的方法步驟與圖式中，基板亦可包含額外材料形成於基板之中及/或之上。
在這些實施例中，可採用其他順序進行方法10的步驟與方法200的步驟。在這些實施例中，可省略方法10與方法200的這些步驟。在這些實施例中，可在方法10與方法200的步驟之間進行額外步驟。
一實施例為半導體裝置的形成方法。方法包括形成鰭狀物於基板上。形成閘極結構於鰭狀物上。形成凹陷於與閘極結構相鄰的鰭狀物中。以p型摻質形成組成漸變摻雜區於鰭狀物中。組成漸變摻雜區自凹陷的下表面延伸至垂直深度，且垂直深度低於鰭狀物中的凹陷。形成源極/汲極區於凹陷中與組成漸變摻雜區上。
在一實施例中，上述方法中的鰭狀物包括矽或矽鍺。
在一實施例中，上述方法中的p型摻質為硼摻質，其佈植至組成漸變摻雜區中的峰值濃度介於約1×1013cm-3至約1×1014cm-3之間。
在一實施例中，上述方法中的組成漸變摻雜區具有底部、中間部份、與頂部。
在一實施例中，上述方法中佈植p型摻質的離子束能量介於約1KeV至約15KeV之間。
在一實施例中，上述方法的源極/汲極區包含摻雜的矽鍺。
在一實施例中，上述方法的源極/汲極區誘發應變於 鰭狀物的通道中，且通道由閘極結構所定義。
一實施例為包含p型場效電晶體結構的半導體裝置。p型場效電晶體結構包含鰭狀物於基板上。閘極結構位於鰭狀物上。磊晶源極/汲極區位於與閘極結構相鄰的鰭狀物上。組成漸變摻雜區位於鰭狀物中，且自磊晶源極/汲極區的底部延伸至鰭狀物中。
在一實施例中，上述半導體裝置的組成漸變摻雜區包括在磊晶源極/汲極區的底部的鰭狀物表面之硼濃度，且硼濃度沿著鰭狀物的深度減少。
在一實施例中，上述半導體裝置的鰭狀物包括矽鰭狀物或矽鍺鰭狀物。
在一實施例中，上述半導體裝置的磊晶源極/汲極區包括摻雜的矽鍺。
在一實施例中，上述半導體裝置的源極/汲極區誘發應變於通道中，且通道由鰭狀物上的閘極結構所定義。
在一實施例中，上述半導體裝置包括n型場效電晶體結構，且n型場效電晶體結構包括第二鰭狀物於基板上。
在一實施例中，上述半導體裝置中的p型場效電晶體結構之寄生電阻介於約1KΩ*鰭狀物數目至約7.0KΩ*鰭狀物數目之間。
在一實施例中，上述半導體裝置包括第二p型場效電晶體結構，且第二p型場效電晶體結構包括第二鰭狀物位於基板上；第二閘極結構位於第二鰭狀物上；以及第二磊晶源極/汲極區位於與第二閘極結構相鄰的第二鰭狀物上。
在一實施例中，上述半導體裝置的第二磊晶源極/汲極區位於第二鰭狀物的非佈植區上。
一實施例為半導體裝置的另一形成方法。方法包括形成第一鰭狀結構與第二鰭狀結構於基板上。第一閘極結構形成於第一鰭狀結構上，且第二閘極結構形成於第二鰭狀結構上。第一凹陷形成於與第一閘極結構相鄰的第一鰭狀結構中。組成漸變摻雜區經由第一凹陷，形成於第一鰭狀結構中。第二凹陷形成於與第二閘極結構相鄰的第二鰭狀結構中。個別的源極/汲極區形成於(i)第一鰭狀結構中的組成漸變摻雜區上的第一凹陷中；以及(ii)第二鰭狀結構中的第二凹陷中。
在一實施例中，上述方法在形成個別的磊晶源極/汲極區時，未佈植第二鰭狀結構。
在一實施例中，上述方法的組成漸變摻雜區的形成方法為佈植p型摻質，且p型摻質的濃度介於約1×1013cm-3至1×1014cm-3之間。
在一實施例中，上述方法以分開製程形成第一鰭狀結構中的第一凹陷與第二鰭狀結構中的第二凹陷。
上述實施例之特徵有利於本技術領域中具有通常知識者理解本發明。本技術領域中具有通常知識者應理解可採用本發明實施例作基礎，設計並變化其他製程與結構以完成上述實施例之相同目的及/或相同優點。本技術領域中具有通常知識者亦應理解，這些等效置換並未脫離本發明實施例的精神與範疇，並可在未脫離本發明實施例的精神與範疇的前提下進行改變、替換、或更動。
100:半導體結構
102:基板
103A:鰭狀結構
110:磊晶材料
120:虛置閘極結構
122:介電層
124:虛置層
126:硬遮罩層
130:閘極間隔物
160:組成漸變摻雜區
170:源極/汲極區

Claims (9)

  1. 一種半導體裝置的形成方法，包括：形成一鰭狀物於一基板上；形成一閘極結構於該鰭狀物上；形成一凹陷於與該閘極結構相鄰的該鰭狀物中；以p型摻質形成一組成漸變摻雜區於該鰭狀物中，其中形成該組成漸變摻雜區的步驟包括：以p型摻質佈植該凹陷的下表面，其中一第一摻雜區自該凹陷的下表面延伸至一垂直深度，且該垂直深度低於該鰭狀物中的該凹陷；以及以p型摻質佈值該凹陷的側壁，其中形成於該凹陷的該側壁之部分上的一第二摻雜區自該凹陷的該側壁延伸至該鰭狀物中，其中沿著該凹陷的該側壁的摻質濃度係小於沿著該凹陷的該下表面的摻質濃度；以及形成一源極/汲極區於該凹陷中與該組成漸變摻雜區上。
  2. 如請求項1之半導體裝置的形成方法，其中該鰭狀物包括矽或矽鍺。
  3. 如請求項1之半導體裝置的形成方法，其中p型摻質為硼摻質，其佈植至該組成漸變摻雜區中的峰值濃度介於約1×1013cm-3至約1×1014cm-3之間。
  4. 一種包含p型場效電晶體結構的半導體裝置，且該p型場效電晶體結構包含：一鰭狀物位於一基板上； 一閘極結構位於該鰭狀物上；一磊晶源極/汲極區位於與該閘極結構相鄰的鰭狀物上；以及一組成漸變摻雜區位於該鰭狀物中，且自該磊晶源極/汲極區的底部延伸至該鰭狀物中，其中該鰭狀物具有一凹陷，該組成漸變摻雜區包括：一第一摻雜區，自該凹陷的下表面延伸至一垂直深度，且該垂直深度低於該鰭狀物中的該凹陷；以及一第二摻雜區，自該凹陷的側壁延伸至該鰭狀物中，其中沿著該凹陷的該側壁的摻質濃度小於沿著該凹陷的該下表面的摻質濃度。
  5. 如請求項4之包含p型場效電晶體結構的半導體裝置，其中該鰭狀物包括矽鰭狀物或矽鍺鰭狀物。
  6. 一種半導體裝置的形成方法，包括：形成一第一鰭狀結構與一第二鰭狀結構於一基板上；形成一第一閘極結構於該第一鰭狀結構上，並形成第二閘極結構於該第二鰭狀結構上；形成一第一凹陷於與該第一閘極結構相鄰的該第一鰭狀結構中；經由該第一凹陷形成一組成漸變摻雜區於該第一鰭狀結構中，其中形成該組成漸變摻雜區包括：形成一第一摻雜區自該第一凹陷的下表面延伸至一垂直深度，且該垂直深度低於該第一鰭狀結構中的該第一凹陷；以及 形成一第二摻雜區自該第一凹陷的側壁延伸至該第一鰭狀結構中，其中沿著該第一凹陷的該側壁的摻質濃度小於沿著該第一凹陷的該下表面的摻質濃度；形成一第二凹陷於與該第二閘極結構相鄰的該第二鰭狀結構中；以及形成個別的多個源極/漏極區於(i)該第一鰭狀結構中的該組成漸變摻雜區上的該第一凹陷中；以及(ii)該第二鰭狀結構中的該第二凹陷中。
  7. 如請求項6之半導體裝置的形成方法，其中在形成個別的該些源極/漏極區時，未佈植該第二鰭狀結構。
  8. 一種半導體裝置的形成方法，包括：形成一鰭狀物於一基板上；形成一閘極結構於該鰭狀物上；形成一凹陷於與該閘極結構相鄰的該鰭狀物中；形成p型摻質的一組成漸變摻雜區於該鰭狀物中，其中形成該組成漸變摻雜區的步驟包括：進行p型摻質的第一離子佈植於該凹陷的下表面上，其中一第一摻雜區自該凹陷的該下表面延伸至一垂直深度，且該垂直深度低於該鰭狀物中的該凹陷；以及進行p型摻質的第二離子佈植於該凹陷的側壁，其中一第二摻雜區自該凹陷的該側壁延伸至該鰭狀物中，其中沿著該凹陷的該側壁之一第一摻質濃度小於 沿著該凹陷的該下表面之一第二摻質濃度；在形成該組成漸變摻雜區之後，磊晶成長一半導體材料於該凹陷中；以及形成一源極/汲極區於該組成漸變摻雜區中。
  9. 如請求項8之半導體裝置的形成方法，其中沿著該凹陷的該側壁的最上側部分的一第三摻質濃度小於該第一摻質濃度。
TW107125499A 2018-04-10 2018-07-24 半導體裝置的形成方法與包含ｐ型場效電晶體結構的半導體裝置 TWI780187B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/949,273 US10763363B2 (en) 2018-04-10 2018-04-10 Gradient doped region of recessed fin forming a FinFET device
US15/949,273 2018-04-10

Publications (2)

Publication Number Publication Date
TW201944538A TW201944538A (zh) 2019-11-16
TWI780187B true TWI780187B (zh) 2022-10-11

Family

ID=68096588

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107125499A TWI780187B (zh) 2018-04-10 2018-07-24 半導體裝置的形成方法與包含ｐ型場效電晶體結構的半導體裝置

Country Status (3)

Country Link
US (2) US10763363B2 (zh)
CN (1) CN110364571B (zh)
TW (1) TWI780187B (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10483372B2 (en) 2017-09-29 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Spacer structure with high plasma resistance for semiconductor devices
CN110875184B (zh) * 2018-08-29 2023-08-18 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
KR102713891B1 (ko) 2019-06-10 2024-10-04 삼성전자주식회사 반도체 장치
US11264478B2 (en) * 2019-10-31 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with reduced defect and methods forming same
US11437490B2 (en) * 2020-04-08 2022-09-06 Globalfoundries U.S. Inc. Methods of forming a replacement gate structure for a transistor device
US11955482B2 (en) * 2020-05-18 2024-04-09 Intel Corporation Source or drain structures with high phosphorous dopant concentration
US11450572B2 (en) * 2020-05-22 2022-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11888064B2 (en) 2020-06-01 2024-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11515165B2 (en) * 2020-06-11 2022-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
KR20220020715A (ko) 2020-08-12 2022-02-21 삼성전자주식회사 집적회로 소자
KR20220083437A (ko) 2020-12-11 2022-06-20 삼성전자주식회사 집적회로 소자
US12068395B2 (en) * 2021-04-14 2024-08-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming an undoped region under a source/drain
US11949016B2 (en) * 2021-05-13 2024-04-02 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and related methods

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9093477B1 (en) * 2014-11-09 2015-07-28 United Microelectronics Corp. Implantation processing step for a recess in finFET
US20160043190A1 (en) * 2014-08-08 2016-02-11 Globalfoundries Inc. Semiconductor structure(s) with extended source/drain channel interfaces and methods of fabrication
US20170077244A1 (en) * 2015-09-15 2017-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8278179B2 (en) * 2010-03-09 2012-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. LDD epitaxy for FinFETs
US8569139B2 (en) * 2010-10-27 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing strained source/drain structures
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US9171929B2 (en) 2012-04-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of semiconductor device and method of making the strained structure
US9093530B2 (en) 2012-12-28 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of FinFET
US9159824B2 (en) 2013-02-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9299840B2 (en) 2013-03-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US9214555B2 (en) 2013-03-12 2015-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer for FinFET channels
US9245882B2 (en) 2013-09-27 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with gradient germanium-containing channels
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9548303B2 (en) 2014-03-13 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices with unique fin shape and the fabrication thereof
US9608116B2 (en) 2014-06-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. FINFETs with wrap-around silicide and method forming the same
US9287382B1 (en) * 2014-11-06 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for semiconductor device
US9564489B2 (en) 2015-06-29 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple gate field-effect transistors having oxygen-scavenged gate stack
US9548388B1 (en) * 2015-08-04 2017-01-17 International Business Machines Corporation Forming field effect transistor device spacers
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9793404B2 (en) 2015-11-30 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon germanium p-channel FinFET stressor structure and method of making same
CN107104137B (zh) * 2016-02-22 2021-11-02 联华电子股份有限公司 鳍状晶体管元件
US10262903B2 (en) * 2017-06-22 2019-04-16 Globalfoundries Inc. Boundary spacer structure and integration
CN109273360B (zh) * 2017-07-17 2021-07-20 联华电子股份有限公司 半导体装置的制作方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160043190A1 (en) * 2014-08-08 2016-02-11 Globalfoundries Inc. Semiconductor structure(s) with extended source/drain channel interfaces and methods of fabrication
US9093477B1 (en) * 2014-11-09 2015-07-28 United Microelectronics Corp. Implantation processing step for a recess in finFET
US20170077244A1 (en) * 2015-09-15 2017-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same

Also Published As

Publication number Publication date
TW201944538A (zh) 2019-11-16
US20200395481A1 (en) 2020-12-17
US11133415B2 (en) 2021-09-28
US20190312143A1 (en) 2019-10-10
CN110364571B (zh) 2023-04-28
CN110364571A (zh) 2019-10-22
US10763363B2 (en) 2020-09-01

Similar Documents

Publication Publication Date Title
TWI780187B (zh) 半導體裝置的形成方法與包含ｐ型場效電晶體結構的半導體裝置
US11935955B2 (en) Semiconductor device and methods of forming same
US12021143B2 (en) P-type strained channel in a fin field effect transistor (FinFET) device
TWI622129B (zh) 半導體結構及其製造方法
TWI702657B (zh) 鰭狀場效電晶體裝置與其形成方法
US11664420B2 (en) Semiconductor device and method
US9741716B1 (en) Forming vertical and horizontal field effect transistors on the same substrate
US11984489B2 (en) Air spacer for a gate structure of a transistor
US10269793B2 (en) Source/drain regions in fin field effect transistors (FinFETs) and methods of forming same
US10468308B2 (en) FinFET structures and methods of forming the same
US11532519B2 (en) Semiconductor device and method
US12068371B2 (en) Method for FinFET LDD doping
US12074071B2 (en) Source/drain structures and method of forming
TW202113943A (zh) 半導體裝置
US11348921B2 (en) Semiconductor structure and method of manufacturing the same
US9564317B1 (en) Method of forming a nanowire
US20240363443A1 (en) Source/Drain Structures and Method of Forming
US20220051950A1 (en) Gapfill structure and manufacturing methods thereof
TW202111782A (zh) 半導體裝置的形成方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent