CN109273360B - 半导体装置的制作方法 - Google Patents

半导体装置的制作方法 Download PDF

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CN109273360B
CN109273360B CN201710579227.XA CN201710579227A CN109273360B CN 109273360 B CN109273360 B CN 109273360B CN 201710579227 A CN201710579227 A CN 201710579227A CN 109273360 B CN109273360 B CN 109273360B
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dopant source
source layer
forming
doped region
semiconductor substrate
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CN109273360A (zh
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陈冠宏
李荣原
陆俊岑
杨崇立
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United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种半导体装置的制作方法，其包括下列步骤：提供半导体基板，其上设置有鳍状结构；在鳍状结构内形成凹槽，致使半导体基板部分暴露出于凹槽的底面；在凹槽的侧面以及底面顺向性地形成掺质来源层；移除位于凹槽底面的掺质来源层，致使半导体基板部分暴露出该凹槽底面；以及对掺质来源层施行热处理制作工艺，以于鳍状结构内形成侧面掺杂区。

Description

半导体装置的制作方法
技术领域
本发明涉及一种半导体装置的制作方法，特别是涉及一种具有多栅极场效晶体管结构的半导体装置的制作方法。
背景技术
目前，是以金属氧化物半导体场效晶体管元件(MOSFET)作为建构超大型集成电路的主要元件。在过去的数十年间，随着MOSFET的尺寸持续微缩，无论是元件速度、效能、电路密度或是单位尺寸价格均有显著的改进。对于一般的平面晶体管元件，由于栅极长度持续减缩，使得两侧的源/漏极会对载流子通道产生不良的影响，并可能改变通道电位。在这样的情况下，栅极将无法有效地控制载流子通道的开/关，进而影响了元件的效能。而此现象，也被称作是「短通道效应」(short-channel effects,SCE)。
为了抑制短通道效应的产生，业界已提出多种相对应地的解决方式，诸如掺杂浓度的提升、栅极氧化层厚度的降低以及超浅源/漏极接面(ultra-shallow source/drainjunctions)等等。然而，对于降低至次30纳米(nanometer,nm)的半导体元件而言，目前业界倾向采用具有多栅极结构(multi-gate)的场效晶体管作为解决短通道效应的主要方式。一般而言，多栅极场效晶体管包含有一突起的鳍状结构，其内设置有源/漏极区域以及通道区域，而一栅极介电层以及一栅极电极可以相对应地包覆鳍状结构的通道区域。对于现行的多栅极场效晶体管，其大体上可以满足元件微小化的需求，并具有有效控制短通道的能力。
然而，现行的技术仍无法有效克服三维结构掺杂浓度不均的问题。举例来说，尽管目前已有技术方案利用具有不同倾角的多次离子注入制作工艺以形成轻掺杂区(lightlydoped drain,LDD)及/或大倾角注入区(halo implant region)，但其掺杂均匀度依旧无法符合高端产品的需求。因此，业界仍需一种具有半导体装置的制作方法，以制作具有较佳轻掺杂区均匀度的多栅极场效晶体管。
发明内容
有鉴于此，本发明的一目的在于提供一种半导体装置的制作方法，以解决现有技术中的缺失。
根据本发明的一实施例，是提供一种半导体装置的制作方法，包括下列步骤：提供半导体基板，其上设置有鳍状结构；在鳍状结构内形成凹槽，致使半导体基板部分暴露出于凹槽的底面；在凹槽的侧面以及底面顺向性地形成掺质来源层；移除位于凹槽底面的掺质来源层，致使半导体基板部分暴露出于凹槽底面；以及对掺质来源层施行热处理制作工艺，以于鳍状结构内形成侧面掺杂区。
根据本发明的另一实施例，另包括在暴露出于凹槽底面的半导体基板内形成底面掺杂区，其中底面掺杂区具有第一导电型，侧面掺杂区具有第二导电型，且第一导电型相异于第二导电型。
根据本发明的另一实施例，其中移除位于凹槽底面的掺质来源层的时点是在形成底面掺杂区之前
根据本发明的另一实施例，其中在形成凹槽前，进一步包括形成栅极结构，栅极结构会覆盖住鳍状结构的部分区段。
根据本发明的另一实施例，其中掺质来源层会覆盖住栅极结构
根据本发明的另一实施例，其中在对掺质来源层施行热处理制作工艺之后，进一步包括移除位于凹槽侧面的掺质来源层。
根据本发明的另一实施例，其中在移除位于凹槽侧面的掺质来源层之后，进一步包括在凹槽内形成外延结构。
根据本发明的另一实施例，其中外延结构具有第一导电型。
根据本发明的另一实施例，其中掺质来源层的组成是选自硼硅酸盐玻璃(borosilicate glass,BSG)或磷硅酸盐玻璃(phosphosilicate glass,PSG)。
根据本发明的另一实施例，提供一种半导体装置的制作方法，包括下列步骤：提供一半导体基板，半导体基板具有第一区域和第二区域；形成至少二鳍状结构，分别位于第一区域内和第二区域内；形成至少二栅极结构，分别覆盖住第一区域和第二区域内的各鳍状结构的部分区段；在第一区域内的鳍状结构内形成第一凹槽，致使半导体基板部分暴露出于第一凹槽；在第一凹槽的侧面以及底面顺向性地形成第一掺质来源层；移除位于第一凹槽底面的第一掺质来源层；在暴露出于第一凹槽底面的半导体基板内形成第一掺杂区，其中第一掺杂区具有第一导电型；以及对掺质来源层施行热处理制作工艺，以于鳍状结构内形成第二掺杂区，其中第二掺杂区具有第二导电型，且第二导电型相异于第一导电型。
根据本发明的另一实施例，其中在移除位于第一凹槽侧面的第一掺质来源层之后，进一步包括在第一凹槽内形成第一外延结构。
根据本发明的另一实施例，其中第一外延结构具有第二导电型。
根据本发明的另一实施例，其中在形成第一外延结构之后，半导体装置的制作方法进一步包括下列步骤：形成一掩模层，覆盖住第一区域内的外延结构；在掩模层的覆盖下，在第二区域内的鳍状结构内形成第二凹槽，致使半导体基板部分暴露出于第二凹槽的底面；在掩模层的顶面、第二凹槽的侧面以及第二凹槽的底面顺向性地形成第二掺质来源层；移除位于第二凹槽底面的第二掺质来源层；在暴露出于第二凹槽底面的半导体基板内形成第三掺杂区，其中第三掺杂区具有第二导电型；以及对掺质来源层施行热处理制作工艺，以于鳍状结构内形成第四掺杂区，其中第四掺杂区具有第一导电型。
根据本发明的另一实施例，其中移除位于第二凹槽底面的第二掺质来源层的时点是在形成第三掺杂区之前。
根据本发明的另一实施例，其中在移除位于第二凹槽底面的第二掺质来源层的过程中，位于掩模层顶面的第二掺质来源层也会被同时移除。
根据本发明的另一实施例，其中在移除位于第二凹槽侧面的第二掺质来源层之后，进一步包括在第二凹槽内形成一第二外延结构。
根据本发明的另一实施例，其中第二外延结构具有第一导电型。
根据上述实施例，通过在凹槽内顺向性地形成掺质来源层，并对掺质来源层施行热处理制作工艺，可以在凹槽周边的鳍状结构内形成均匀分布的掺杂区，例如浅掺杂，相较于现有技术利用离子注入的方式形成浅掺杂区，通过上述实施例所形成的半导体装置可有效避免短通道效应的发生。此外，根据上述实施例，在凹槽底面的半导体基板中形成第一掺杂区和第三掺杂区的时点是在去除凹槽底面的掺质来源层之后，因此也可以让第一掺杂区和第三掺杂区的掺质浓度更加均匀，从而避免电流从凹槽底面贯穿进入或离开鳍状结构。
附图说明
图1为本发明一实施例所绘示的半导体装置于初始阶段的透视图；
图2为本发明一实施例所绘示的在鳍状结构内形成凹槽后的剖面示意图；
图3为本发明一实施例所绘示在凹槽的侧面以及底面顺向性地形成掺质来源层的剖面示意图；
图4为本发明一实施例所绘示移除凹槽底面的掺质来源层的剖面示意图；
图5为本发明一实施例所绘示在暴露出于凹槽底面的半导体基板中形成掺杂区的剖面示意图；
图6为本发明一实施例所绘示对掺质来源层施行热处理制作工艺后的剖面示意图；
图7为本发明一实施例所绘示在凹槽内形成外延结构后的剖面示意图；
图8为本发明一实施例所绘示在鳍状结构内形成凹槽后的剖面示意图；
图9为本发明一实施例所绘示在暴露出于凹槽底面的半导体基板中形成掺杂区的剖面示意图；
图10为本发明一实施例所绘示在凹槽内形成外延结构后的剖面示意图；
图11为本发明一实施例所绘示的半导体装置的制作方法流程图。
主要元件符号说明
200 半导体装置 202 半导体基板
203 浅沟槽绝缘结构 204 鳍状结构
206 栅极结构 208 栅极介电层
210 虚置电极 212 盖罩
214 第一间隙壁 216 第二间隙壁
218 第一区域 220 第二区域
222 第一凹槽 222a 底面
222b 侧面 224 第一掺杂区
226 第二掺杂区 402 掺质来源层
404 图案化蚀刻掩模层 602 第一外延结构
704 图案化掩模层 802 第二凹槽
802a 底面 802b 侧面
902 掺质来源层 904 第三掺杂区
906 第四掺杂区
具体实施方式
在下文中，是加以陈述本发明半导体装置制作方法的具体实施方式，以使本技术领域中具有通常技术者可据以实施本发明。该些具体实施方式可参考相对应的附图，使该些附图构成实施方式的一部分。虽然本发明的实施例揭露如下，然而其并非用以限定本发明，任何熟悉此技术者，在不脱离本发明的精神和范畴内，当可作些许的更动与润饰。
请参照图1，图1是根据本发明一实施例所绘示半导体装置于初始阶段的透视图。如图1所示，半导体装置200包括半导体基板202，半导体基板202上设置有浅沟槽绝缘(shallow trench isolation,STI)结构203、至少一鳍状结构204以及至少一栅极结构206。其中，鳍状结构204与栅极结构206之间可具有至少二直接接触面(至少包含二接触侧面)。因此，此具有多个直接接触面的场效晶体管可被称作是双栅极场效晶体管(double-gateMOSFET)或三栅极场效晶体管(tri-gate MOSFET)。
需注意的是，虽然图1中仅绘示单一栅极结构206和单一鳍状结构204，然而其个数可根据不同产品需求而有所增加。举例来说，半导体基板202上可设有一个以上互相平行的栅极结构206，使得同一条鳍状结构204可被一个以上的栅极结构206所覆盖。此外，同一条栅极结构206较佳的是用以作为同一导电型晶体管的栅极，例如作为PMOS晶体管的栅极或NMOS晶体管的栅极。
上述半导体基板202可例如是一硅基底、一含硅基底、一三五族半导体覆硅基底(例如GaAs-on-silicon)或一石墨烯覆硅基底(graphene-on-silicon)等半导体基底，但不限于此。
浅沟槽绝缘结构203是环绕鳍状结构204而设置。栅极结构206设置于浅沟槽绝缘结构203之上，并覆盖住鳍状结构204的部分区段。需注意的是，此处的鳍状结构204定义为突出于浅沟槽绝缘结构203顶面的区段。因此，鳍状结构204和半导体基板202的交界面可视为切齐于浅沟槽绝缘结构203的顶面。
栅极结构206由下至上包括栅极介电层208、虚置电极210以及盖罩212。此外，栅极结构206的侧壁可以被至少一层间隙壁所覆盖。举例而言，栅极结构206的侧壁可依序被第一间隙壁214和第二间隙壁216所覆盖。
需注意的是，栅极结构206可被视为是一虚置栅极结构(dummy gate structure)。换言之，栅极介电层208将于后续制作工艺中被替换成高介电常数栅极介电层，而虚置电极210将会被替换成导电金属层。在此实施态样下，栅极介电层可仅为一般方便于后续制作工艺中移除的牺牲材料，例如为一氧化层。虚置电极210的组成可以是多晶半导体材料，例如多晶硅，但不以此为限。盖层212可包括由氮化层或氧化层等所组成的单层或多层结构，作为一图案化的硬掩模。
图2是根据本发明一实施例所绘示在鳍状结构内形成凹槽后的剖面示意图。需注意的是，图2所示的结构是对应沿着图1鳍状结构长轴对半导体装置200所取的剖面。然而，图2所示的半导体装置200具有一第一区域218和一第二区域220。多个栅极结构206和多个鳍状结构204会分别设置于第一区域218和第二区域220内。其中，第一区域218和第二区域220可以用来分别容纳P型晶体管和N型晶体管，因此可以被分别称作是PMOS区和NMOS区。
仍如图2所示，形成一图案化蚀刻掩模层404，以覆盖住第二区域内的栅极结构206和鳍状结构204。通过设置图案化蚀刻掩模层404，可以定义出后续凹槽形成的区域。其中，图案化蚀刻掩模层404的材料可以选自氮化硅或碳化硅，但不限于此。
之后，在图案化蚀刻掩模层404的覆盖下，对半导体装置200施行一蚀刻制作工艺，较佳为各向异性干蚀刻制作工艺，以移除暴露出于第二间隙壁216和图案化蚀刻掩模层404的鳍状结构204和部分的半导体基板202。经过此蚀刻制作工艺，第一凹槽222会被形成于第一区域218的鳍状结构204内，且第一凹槽222位于栅极结构206的两侧。其中，各第一凹槽222具有底面222a和侧面222b，底面222a的深度较佳会深于浅沟槽结构203的顶面，致使底面222a下方的半导体基板202会被暴露出。上述蚀刻制作工艺可能是等离子体蚀刻制作工艺，其蚀刻气体成分包含溴化氢/氧气、六氟化硫/氯气等蚀刻气体，但不限于此。
图3是根据本发明一实施例所绘示在凹槽的侧面以及底面顺向性地形成掺质来源层的剖面示意图。根据上述形成第一凹槽222之后，如图3所示，可接着在第一凹槽222的侧面222b以及底面222a顺向性地形成掺质来源层402。其中，对于第一区域218是PMOS区的情况而言，掺质来源层402的材料较佳包含硼硅酸盐(borosilicate glass,BSG)等的含有P型掺质的薄膜。此外，掺质来源层402也会顺向性地覆盖住第二区域220内的图案化蚀刻掩模层404。
图4是根据本发明一实施例所绘示移除凹槽底面的掺质来源层的剖面示意图。如图4所示，可以利用各向异性蚀刻制作工艺，移除位于第一凹槽222底面222a的掺质来源层402，以暴露出位于第一凹槽222底面222a下方的半导体基板202。需注意的是，在此蚀刻过程中，部分位于栅极结构206及图案化蚀刻掩模层404上方的掺质来源层402也会被移除。即便如此，第一凹槽222的侧面222b仍会完全被掺质来源层402覆盖住。
图5是根据本发明一实施例所绘示在暴露出于凹槽底面的半导体基板中形成掺杂区的剖面示意图。如图5所示，可以施行一掺杂制作工艺，例如各向异性的离子注入制作工艺或等离子体掺杂制作工艺，以于暴露出于凹槽底面222a的半导体基板202中形成抗贯穿掺杂区(punch-through stopper region)，或称为底面掺杂区或第一掺杂区224，其具有第一导电型。对于第一区域218是PMOS区的情况而言，第一导电型为N型。需注意的是，在施行此掺杂制作工艺的过程中，由于凹槽底面222a不会被掺质来源层402覆盖，因此可使得掺质均匀地分布于暴露出于凹槽底面222a的半导体基板202中。换言之，具有均匀浓度的第一掺杂区224(或称为抗贯穿掺杂区)可更有效地避免电流从凹槽底面222a贯穿进入或离开。
图6是根据本发明一实施例所绘示对掺质来源层施行热处理制作工艺后的剖面示意图。如图6所示，可以施行一热处理，例如热退火制作工艺，使得掺质来源层402中的掺质扩散进入相邻的鳍状结构204和半导体基板202中，而形成一浅掺杂区(lightly dopeddrain,LDD)，或称为侧面掺杂区或第二掺杂区226，其具有第二导电型。对于第一区域218是PMOS区的情况而言，第二导电型为P型。
需注意的是，由于掺质来源层402是完整且密合地的覆盖住第一凹槽222的侧面222b，因此其中的掺质可均匀地扩散进入相邻的鳍状结构204和半导体基板202中。换言之，通过此扩散制作工艺，可以避免现有技术因为离子注入制作工艺所产生的阴影效应(shadow effect)。
此外，在施行此热处理的过程中，由于凹槽底面222a不会被掺质来源层402覆盖，因此第二掺杂区226(或称为侧面掺杂区)不会被形成于凹槽底面222a下方的半导体基板202中。换言之，即便施了热处理制作工艺，第一掺杂区224(或称为底面掺杂区或抗贯穿掺杂区)中具有第一导电型的掺质仍不会被掺质来源层402中的第二导电型的掺质中和，因此第一掺杂区224仍可保有优异的抗电流贯穿能力。
当施行热处理制作工艺后，可以通过蚀刻制作工艺，例如酸洗制作工艺，以完全移除掺质来源层402。
图7是根据本发明一实施例所绘示在凹槽内形成外延结构后的剖面示意图。如图7所示，在栅极结构206的各侧各自形成一第一外延结构602，其具有第二导电型，可作为后续晶体管元件源/漏极的主体区域。在此需注意的是，根据此第一实施例，外延成长制作工艺较佳为一原位(in-situ)成长制作工艺。举例来说，对于一PMOS元件制作工艺，外延成长制作工艺可以是在形成硅化锗单晶的同时，同时掺杂特定导电电性的掺质，例如硼，使得第一外延结构602达到所需的电性而直接构成PMOS元件的源/漏极掺杂区。
图8是根据本发明一实施例所绘示在鳍状结构内形成凹槽后的剖面示意图。如图8所示，形成一图案化掩模层704，以覆盖住第一区域218内的栅极结构206、鳍状结构204和第一外延结构602。通过设置图案化掩模层704，可以定义出后续凹槽形成的区域。其中，图案化掩模层704的材料可以选自单层或多层的光阻，但不限于此。
之后，仍如图8所示，在图案化掩模层704的覆盖下，对半导体装置200施行一蚀刻制作工艺，较佳为一各向异性干蚀刻制作工艺，以移除暴露出于第二间隙壁216和图案化掩模层704的鳍状结构204和部分的半导体基板202。经过此蚀刻制作工艺，第二凹槽802会被形成于第二区域220的鳍状结构204内，且第二凹槽802位于栅极结构206的两侧。其中，各第二凹槽802具有底面802a和侧面802b，底面802a的深度较佳会深于浅沟槽结构203的顶面，致使底面802a下方的半导体基板202会被暴露出。上述蚀刻制作工艺可能是等离子体蚀刻制作工艺，其蚀刻气体成分包含溴化氢/氧气、六氟化硫/氯气等蚀刻气体，但不限于此。
图9是根据本发明一实施例所绘示在暴露出于凹槽底面的半导体基板中形成掺杂区的剖面示意图。根据上述形成第二凹槽802之后，如图9所示，可接着在第二凹槽802的侧面802b以及底面802a顺向性地形成掺质来源层902。其中，对于第二区域220是NMOS区的情况而言，掺质来源层902的材料较佳包含磷硅酸盐(phosphosilicate glass,PSG)等的含有N型掺质的薄膜。此外，掺质来源层902也会顺向性地覆盖住第一区域218内的图案化掩模层704。
仍如图9所示，可以利用各向异性蚀刻制作工艺，移除位于第二凹槽802底面802a的掺质来源层902，以暴露出位于第二凹槽802底面802a下方的半导体基板202。需注意的是，在此蚀刻过程中，部分位于栅极结构206及图案化掩模层704上方的掺质来源层402也会被移除。即便如此，第二凹槽802的侧面802b仍会完全被掺质来源层902覆盖住。
仍如图9所示，可以施行一掺杂制作工艺，例如各向异性的离子注入制作工艺或等离子体掺杂制作工艺，以于暴露出于凹槽底面802a的半导体基板202中形成抗贯穿掺杂区(punch-through stopper region)，或称为底面掺杂区或第三掺杂区904，其具有第二导电型。对于第二区域220是NMOS区的情况而言，第二导电型为P型。需注意的是，在施行此掺杂制作工艺的过程中，由于凹槽底面802a不会被掺质来源层902覆盖，因此可使得掺质均匀地分布于暴露出于凹槽底面802a的半导体基板202中。换言之，具有均匀浓度的第三掺杂区904(或称为底面掺杂区或抗贯穿掺杂区)可更有效地避免电流从凹槽底面802a贯穿进入或离开。
接着，可以施行一热处理制作工艺，例如热退火制作工艺，使得掺质来源层902中的掺质扩散进入相邻的鳍状结构204和半导体基板202中，而形成一浅掺杂区(lightlydoped drain,LDD)，或称为侧面掺杂区或第四掺杂区，其具有第一导电型。对于第二区域220是NMOS区的情况而言，第一导电型为N型。
根据上述施行热处理制作工艺之后，由于掺质来源层902是完整且密合地的覆盖住第二凹槽802的侧面802b，因此其中的掺质可均匀地扩散进入相邻的鳍状结构204和半导体基板202中。换言之，通过此扩散制作工艺，可以避免现有技术因为离子注入制作工艺所产生的阴影效应(shadow effect)。
此外，在施行此热处理的过程中，由于凹槽底面802a不会被掺质来源层902覆盖，因此第四掺杂区不会被形成于凹槽底面802a下方的半导体基板202中。换言之，即便施了热处理制作工艺，第三掺杂区904(或称为底面掺杂区或抗贯穿掺杂区)中具有第二导电型的掺质仍不会被掺质来源层902中的第一导电型的掺质中和，因此第三掺杂区904仍可保有优异的抗电流贯穿能力。
当施行热处理制作工艺后，可以通过蚀刻制作工艺，例如酸洗制作工艺，以完全移除掺质来源层902。
图10是根据本发明一实施例所绘示在凹槽内形成外延结构后的剖面示意图。在完成图9的制作工艺阶段后，如图10所示，第四掺杂区906可以均匀分布于第二凹槽802周边的鳍状结构204和半导体基板202中，但不会被形成于凹槽底面802a下方的半导体基板202中。之后，如图10所示，在栅极结构206的各侧各自形成一第二外延结构910，其具有第一导电型，可作为后续晶体管元件源/漏极的主体区域。在此需注意的是，根据此第一实施例，外延成长制作工艺较佳为一原位(in-situ)成长制作工艺。举例来说，对于一NMOS元件制作工艺，外延成长制作工艺可以是在形成硅化磷单晶的同时，同时掺杂特定导电电性的掺质，例如磷，使得第二外延结构910达到所需的电性而直接构成NMOS元件的源/漏极掺杂区。
图11是根据本发明一实施例所绘示的半导体装置的制作方法流程图，其至少包括下述步骤。步骤1102：提供半导体基板，半导体基板中设置有鳍状结构；1104：在鳍状结构内形成凹槽；1106：在凹槽的侧壁以及底面顺向性地形成掺质来源层；1108：移除位于凹槽底面的掺质来源层；1110：在暴露出于凹槽底部的鳍状结构内形成第一掺杂区，其中第一掺杂区具第一导电型；1112：对掺质来源层施行热处理制作工艺，以于鳍状结构内形成第二掺杂区，其中第二掺杂区具有第二导电型，且第二导电型相异于第一导电型。
此外，根据本发明的其他实施例，也可以通过等离子体掺杂制作工艺，以形成上述的第二掺杂区226和第四掺杂区906，因而可以省略沉积掺质来源层402、902和施行热处理的制作工艺。
根据上述实施例，通过在凹槽内顺向性地形成掺质来源层，并对掺质来源层施行热处理制作工艺，可以在凹槽周边的鳍状结构内形成均匀分布的掺杂区，例如浅掺杂，相较于现有技术利用离子注入的方式形成浅掺杂区，通过上述实施例所形成的半导体装置可有效避免短通道效应的发生。此外，根据上述实施例，在凹槽底面的半导体基板中形成第一掺杂区和第三掺杂区的时点是在去除凹槽底面的掺质来源层之后，因此也可以让第一掺杂区和第三掺杂区的掺质浓度更加均匀，从而避免电流从凹槽底面贯穿进入或离开鳍状结构。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (16)

1.一种半导体装置的制作方法，包括：
提供一半导体基板，该半导体基板上设置有至少一鳍状结构；
在该鳍状结构内形成至少一凹槽，致使该半导体基板部分暴露出于该凹槽的底面；
在该凹槽的侧面以及底面顺向性地形成一掺质来源层；
移除位于该凹槽底面的该掺质来源层，致使该半导体基板部分暴露出于该凹槽底面；
在暴露出于该凹槽底面的该半导体基板内形成一底面掺杂区，其中该底面掺杂区具有第一导电型，该侧面掺杂区具有第二导电型，且该第一导电型相异于该第二导电型；以及
对该掺质来源层施行热处理制作工艺，以于该鳍状结构内形成一侧面掺杂区。
2.如权利要求1所述的半导体装置的制作方法，其中移除位于该凹槽底面的该掺质来源层的时点是在形成该底面掺杂区之前。
3.如权利要求1所述的半导体装置的制作方法，其中在形成该凹槽前，进一步包括形成栅极结构，该栅极结构会覆盖住该鳍状结构的部分区段。
4.如权利要求3所述的半导体装置的制作方法，其中该掺质来源层会覆盖住该栅极结构。
5.如权利要求1所述的半导体装置的制作方法，其中在对该掺质来源层施行该热处理制作工艺之后，进一步包括移除位于该凹槽侧面的该掺质来源层。
6.如权利要求5所述的半导体装置的制作方法，其中在移除位于该凹槽侧面的该掺质来源层之后，进一步包括在该凹槽内形成一外延结构。
7.如权利要求6所述的半导体装置的制作方法，其中该底面掺杂区具有一第一导电型，该外延结构具有一第二导电型，且该第一导电型相异于该第二导电型。
8.如权利要求1所述的半导体装置的制作方法，其中该掺质来源层的组成是选自硼硅酸盐玻璃(borosilicate glass,BSG)或磷硅酸盐玻璃(phosphosilicate glass,PSG)。
9.一种半导体装置的制作方法，包括：
提供一半导体基板，该半导体基板具有第一区域和第二区域；
形成至少二鳍状结构，分别位于该第一区域内和该第二区域内；
形成至少二栅极结构，分别覆盖住该第一区域和该第二区域内的各该鳍状结构的部分区段；
在该第一区域内的该鳍状结构内形成至少一第一凹槽，致使该半导体基板部分暴露出于该第一凹槽；
在该第一凹槽的侧面以及底面顺向性地形成一第一掺质来源层；
移除位于该第一凹槽底面的该第一掺质来源层；
在暴露出于该第一凹槽底面的该半导体基板内形成一第一掺杂区，其中该第一掺杂区具有一第一导电型；以及
对该掺质来源层施行热处理制作工艺，以于该鳍状结构内形成一第二掺杂区，其中该第二掺杂区具有一第二导电型，且该第二导电型相异于该第一导电型。
10.如权利要求9所述的半导体装置的制作方法，其中在移除位于该第一凹槽侧面的该第一掺质来源层之后，进一步包括在该第一凹槽内形成一第一外延结构。
11.如权利要求10所述的半导体装置的制作方法，其中该第一外延结构具有该第二导电型。
12.如权利要求10所述的半导体装置的制作方法，其中在形成该第一外延结构之后，该制作方法进一步包括：
形成一掩模层，覆盖住该第一区域内的该外延结构；
在该掩模层的覆盖下，在该第二区域内的该鳍状结构内形成至少一第二凹槽，致使该半导体基板部分暴露出于该第二凹槽的底面；
在该掩模层的顶面、该第二凹槽的侧面以及该第二凹槽的底面顺向性地形成一第二掺质来源层；
移除位于该第二凹槽底面的该第二掺质来源层；
在暴露出于该第二凹槽底面的该半导体基板内形成一第三掺杂区，其中该第三掺杂区具有该第二导电型；以及
对该掺质来源层施行热处理制作工艺，以于该鳍状结构内形成一第四掺杂区，其中该第四掺杂区具有该第一导电型。
13.如权利要求12所述的半导体装置的制作方法，其中移除位于该第二凹槽底面的该第二掺质来源层的时点是在形成该第三掺杂区之前。
14.如权利要求12所述的半导体装置的制作方法，其中在移除位于该第二凹槽底面的该第二掺质来源层的过程中，位于该掩模层顶面的该第二掺质来源层也会被同时移除。
15.如权利要求12所述的半导体装置的制作方法，其中在移除位于该第二凹槽侧面的该第二掺质来源层之后，进一步包括在该第二凹槽内形成一第二外延结构。
16.如权利要求15所述的半导体装置的制作方法，其中该第二外延结构具有该第一导电型。
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