CN110364571A - 半导体装置的形成方法 - Google Patents

半导体装置的形成方法 Download PDF

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Publication number
CN110364571A
CN110364571A CN201810789550.4A CN201810789550A CN110364571A CN 110364571 A CN110364571 A CN 110364571A CN 201810789550 A CN201810789550 A CN 201810789550A CN 110364571 A CN110364571 A CN 110364571A
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fin
recess
source
doped region
compositionally graded
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CN110364571B (zh
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林俊豪
林育樟
聂俊峰
张惠政
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一实施例为半导体装置的形成方法。方法包括形成鳍状物于基板上。形成栅极结构于鳍状物上。形成凹陷于与栅极结构相邻的鳍状物中。以p型掺质形成组成渐变掺杂区于鳍状物中。组成渐变掺杂区自凹陷的下表面延伸至垂直深度，且垂直深度低于鳍状物中的凹陷。形成源极/漏极区于凹陷中与组成渐变掺杂区上。

Description

半导体装置的形成方法
技术领域
本公开实施例涉及半导体装置，更特别涉及源极/漏极区下的组成渐变掺杂区(gradient doped region)。
背景技术
随着半导体产业进展至纳米工艺节点以求更高装置密度、更高效能、与更低成本，工艺与设计所面临的挑战导致三维设计如鳍状场效晶体管的发展。一般制作半导体装置的方法为蚀刻至基板中，以形成自基板凸起的鳍状结构。鳍状场效晶体管的通道形成于垂直的鳍状物中。栅极结构位于鳍状结构上以包覆鳍状结构。在通道区上的栅极结构有利于栅极控制其围绕的通道。鳍状场效晶体管装置具有多种优点，比如减少短通道效应及增加电流。
随着装置尺寸持续缩小，可采用金属栅极取代一般的多晶硅栅极以改善鳍状场效晶体管装置效能。形成金属栅极的工艺之一为置换栅极工艺(亦称作栅极后制(gate-last，后栅极)工艺)，其最后才制作最终的栅极堆叠。然而在进阶工艺节点中，实施此集成电路工艺仍具有挑战。
发明内容
本公开一实施例提供的半导体装置的形成方法，包括：形成鳍状物于基板上；形成栅极结构于鳍状物上；形成凹陷于与栅极结构相邻的鳍状物中；以p型掺质形成组成渐变掺杂区于鳍状物中，组成渐变掺杂区自凹陷的下表面延伸至垂直深度，且垂直深度低于鳍状物中的凹陷；以及形成源极/漏极区于凹陷中与组成渐变掺杂区上。
附图说明
图1是一些实施例中，形成半导体装置的方法的流程图。
图2、图3B与图3C、图4、图5A与图5B、图6A与图6B、及图7是一些实施例中，半导体装置于形成半导体装置的中间阶段的中间结构的剖视图。
图3A是一些实施例中，具有两个栅极结构形成于第一组的两个鳍状结构与第二组的两个鳍状结构上的基板的剖视图。
图8是一些实施例中，形成半导体装置如鳍状场效晶体管结构于基板上的另一方法的流程图。
图9、10、11、12、13、与14是一些实施例中，半导体装置于形成半导体装置的中间阶段的中间结构的剖视图。
图15是一些实施例中，互补式金属氧化物半导体装置的示意图。
符号说明
GND 接地
VDD 正极电源电压
10、200 方法
20、30、40、50、60、202、204、206、208、210、212、214、216、218、220 步骤
100 半导体结构
102 基板
103A、103B 鳍状结构
105 绝缘材料
108 n型井区
109 p型井区
110 外延材料
120、120A、120B 虚置栅极结构
122 介电层
124 虚置层
126 硬遮罩层
130 栅极间隔物
140、142 遮罩
150、150A、150B 凹陷
150D、160DB、160DM、160DT 深度
150W 宽度
160 组成渐变掺杂区
170 源极/漏极区
180 接点蚀刻停止层
182 第一层间介电层
184 第二层间介电层
186 接点
190 置换栅极结构
192 栅极介电层
194 金属衬垫层
195 功函数调整层
196 导电栅极充填物
300 互补式金属氧化物半导体装置
310 p型场效晶体管装置
320 n型场效晶体管装置
具体实施方式
下述内容提供的不同实施例可实施本公开的不同结构。特定构件与排列的实施例是用以简化而非局限本公开实施例。举例来说，形成第一构件于第二构件上的叙述包含两者直接接触，或两者之间隔有其他额外构件而非直接接触。此外，本公开的多种例子中可重复标号，但这些重复仅用以简化与清楚说明，不代表不同实施例和/或设置之间具有相同标号的单元之间具有相同的对应关系。
此外，空间性的相对用语如“下方”、“其下”、“较下方”、“上方”、“较上方”、或类似用语可用于简化说明某一元件与另一元件在图示中的相对关系。空间性的相对用语可延伸至以其他方向使用的元件，而非局限于图示方向。元件亦可转动90°或其他角度，因此方向性用语仅用以说明图示中的方向。
此处公开的实施例一般涉及形成组成渐变掺杂区于鳍状结构的方法，比如沿着凹陷的表面(如下表面)形成p型应变通道装置的源极/漏极结构。在这些实施例中，组成渐变掺杂区有助于降低p型应变通道装置的通道电阻与寄生电阻。在这些实施例中，较低的通道电阻和/或较低的寄生电阻有助于减少或避免互补式金属氧化物半导体装置的闩锁(latch-up，闭锁)问题。
图1是一些实施例中，形成半导体装置(如鳍状场效晶体管结构)于基板上的方法10的流程图。在一些实施例中，方法10的细节将搭配图2至图7说明，其为形成半导体结构100(如鳍状场效晶体管半导体装置)于基板102上的多种阶段的附图。
图2是基板102的剖视图。基板102可为半导体晶圆如硅晶圆。基板102可改为或额外包含半导体元素材料、半导体化合物材料、和/或半导体合金材料。半导体元素材料的例子可包含但不限于硅或锗。在这些实施例中，基板102为本质硅基板，其可适当地掺杂n型掺质以形成n型井区，并掺杂p型掺质以形成p型井区。在这些实施例中，基板102为p型基板，其含有p型掺质以形成p型井区109，并掺杂n型掺质以形成n型井区108。在这些实施例中，基板102为n型基板，其含有n型掺质以形成n型井区108，并掺杂p型掺质以形成p型井区109。
在方法10的步骤20中，形成一或多个鳍状结构103A于n型井区108的基板102上。一或多个鳍状结构103B亦可形成于p型井区上。鳍状结构103A与鳍状结构103B可同时形成或分开形成。在这些实施例中，图案化基板102以形成鳍状结构103A与103B。进行图案化工艺以形成凹陷(未图示)于基板102中，以定义基板102中的鳍状结构103A与103B。凹陷具有绝缘材料105形成其中。可采用任何合适方法图案化鳍状结构103A与103B。举例来说，鳍状结构103A与103B的图案化方法可采用一或多道光微影工艺，包括双重图案化工艺或多重图案化工艺。一般而言，双重图案化或多重图案化工艺结合光微影与自对准工艺，其产生的图案间距小于单一的直接光微影工艺所得的图案间距。举例来说，一实施例可形成牺牲层于基板上，并采用光微影工艺图案化牺牲层。采用自对准工艺，以沿着图案化的牺牲层形成间隔物。接着移除牺牲层，而保留的间隔物接着可用于图案化鳍状结构103A与103B。
如图2所示，基板亦可包含外延材料(epitaxial material，磊晶材料)110形成于基板102上，以形成鳍状结构103A。举例来说，外延材料110可沉积于基板102的n型井区108上。外延材料110形成鳍状结构103A，其可为硅锗(SixGe1-x，其中x介于近似0与1之间)。举例来说，SixGe1-x的鳍状结构103A中，x介于约0.05至约0.50之间时，其可用于形成应变通道于p型场效晶体管装置中。在其他实施例中，外延材料110形成的鳍状结构103A可为锗、III-V族半导体化合物、II-VI族半导体化合物、或类似物。举例来说，用以形成III-V族半导体化合物的材料包括砷化铟、砷化铝、砷化镓、磷化铟、氮化镓、砷化铟镓、砷化铟铝、锑化镓、锑化铝、磷化铝、磷化镓、或类似物。外延材料110的沉积方法可为化学气相沉积、低压化学气相沉积、原子层化学气相沉积、超真空化学气相沉积、远端等离子体增强化学气相沉积、气相外延、分子束外延、任何其他合适的沉积工艺、或任何其组合。
在图2所示的实施例中，图案化与蚀刻基板102及其上的外延材料110，可形成鳍状结构103A(如硅锗鳍状结构)。图案化与蚀刻基板102(不具有外延材料110或具有硅外延材料于其上)可形成硅的鳍状结构103B。在其他实施例中，n型井区108上的鳍状结构103A亦可包含硅的鳍状结构(不具有外延材料110)。
在一些实施例中，定义鳍状结构103A与103B的凹陷可填有绝缘材料105。绝缘材料105可形成浅沟槽隔离结构。绝缘材料105可为或包含氧化硅、氮化硅、氮氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂硼的磷硅酸盐玻璃、其他介电层、或上述的多层。绝缘材料105的沉积方法可为任何可接受的沉积工艺。使绝缘材料105凹陷，可使鳍状结构103A与103B凸起高于绝缘材料105。
在其他实施例中，可形成介电层于半导体的基板102的上表面上、蚀刻穿过介电层以形成沟槽、外延成长外延结构(如单质外延或异质外延结构)于沟槽中、以及使介电层凹陷以让外延结构自介电层凸起形成鳍状物。这些工艺形成的鳍状物，一般可具有与图2所示者类似的结构。
在方法10的步骤30中，形成栅极结构(如虚置栅极结构120)于鳍状结构103A与103B上，如图3A至图3C所示。图3A是一些实施例中，图2的基板102的透视图，其具有两个虚置栅极结构120形成于两个鳍状结构103A(如硅锗鳍状物或硅鳍状物)与两个鳍状结构103B(如硅鳍状物)上。图3B是基板102在图3A的平面Y中的剖视图，其纵向地沿着虚置栅极结构120之一。图3A与图3B的半导体结构100显示形成互补式金属氧化物半导体装置的阶段之一。形成于n型井区108上的鳍状结构103A上的栅极结构，可形成p型场效晶体管装置。形成于p型井区109上的鳍状结构103B上的栅极结构，可形成n型场效晶体管装置。图3C是基板102在图3A中的X平面的剖视图，其穿过n型井区108的鳍状结构103A。
虚置栅极结构120可包含介电层122、一或多个虚置层124、与硬遮罩层126。介电层122可为氧化硅、氮氧化硅、其他介电层、或上述的多层。虚置层124可为多晶硅层或其他合适材料。硬遮罩层126可为任何合适材料，比如氮化硅、氮氧化硅、或碳氮化硅，其可图案化基板上的虚置栅极结构120至具有所需结构与尺寸。介电层122、虚置层124、与硬遮罩层126的沉积方法可为一或多道合适的沉积工艺。可采用合适的光微影与蚀刻技术图案化虚置栅极结构120，以露出鳍状结构103A与103B的部分。虚置栅极结构120啮合鳍状结构103A与103B的顶部与侧部。
此处所述的用语“虚置”指的是在后段阶段中将移除的牺牲结构，其将取代为另一结构如置换栅极工艺中的高介电常数介电层与金属栅极结构。置换栅极工艺指的是在整个栅极工艺的后段阶段中，形成栅极结构的工艺。
在图4中，沿着虚置栅极结构120的侧壁形成栅极间隔物130。图4是基板的剖视图，且剖视方向穿过图3C的n型井区108上的鳍状结构103A。为简化说明，半导体结构的形成方法将搭配图4至图7说明，其仅显示n型井区108上的鳍状结构103A，而未显示p型井区109上的鳍状结构103B。在对n型井区108上的鳍状结构103A进行工艺的一或多道步骤时，可对鳍状结构103B同时进行这些步骤，和/或以遮罩保护鳍状结构103B。
栅极间隔物130可为或包含碳氮化硅、氮化硅、碳化硅、氮氧化硅、氧化硅、其他可行材料、或其组合。可顺应性地沉积并非等向蚀刻(如干蚀刻工艺)用于栅极间隔物130的层状物，以自鳍状结构103A的表面移除用于栅极间隔物130的层状物，并沿着虚置栅极结构120保留栅极间隔物130。
在方法10的步骤40中，形成凹陷150于鳍状结构103A中。虚置栅极结构120未覆盖而栅极间隔物130覆盖的鳍状结构103A的区域，被蚀刻以形成凹陷150。上述蚀刻方法可为干蚀刻工艺和/或湿蚀刻工艺。举例来说，凹陷150的形成方法可采用非等向的湿蚀刻剂，比如氢氧化四甲基铵。氢氧化四甲基铵可在凹陷150中产生<111>平面，以形成晶面形状的凹陷。在这些实施例中，可采用氢氧化四甲基铵蚀刻剂蚀刻基板102，且此蚀刻剂所含的水性溶液其氢氧化四甲基铵浓度介于1％至30％之间，而蚀刻温度介于约20℃至约90℃之间。
在其他实施例中，凹陷150的底部和/或侧壁的形状可为角形(angular)、圆润形(rounded，倒圆形)和/或其他形状。形成于鳍状结构103A中的凹陷150可具有所需的深度与宽度。举例来说，凹陷150自鳍状结构103A的顶部至凹陷150的最底端的深度150D，可介于约30nm至约100nm之间，在其他实施例中，凹陷150的深度150D介于约40nm至约60nm之间。凹陷150的宽度150W来自鳍状结构103A的最宽长度，其可介于约20nm至约90nm之间。在其他实施例中，凹陷150的宽度150W介于约30nm至约50nm之间。对步骤50即将形成的组成渐变掺杂区160而言，凹陷150的深度150D与宽度150W可提供足够的空间。
在方法10的步骤50中，形成组成渐变掺杂区160于凹陷的鳍状结构103A中，如图5A与5B所示。图5A是一些实施例中基板102的剖视图，其形成组成渐变掺杂区160于图4的凹陷的鳍状结构103A中。图5B是一些实施例中，组成渐变掺杂区160在Z方向中的视图。可采用虚置栅极结构120与栅极间隔物130作为遮罩，布植掺质至凹陷的鳍状结构103A中，以形成组成渐变掺杂区160于鳍状结构103A的顶部。掺质的例子包含硼掺质如二氟化硼以用于p型装置，不过亦可采用其他掺质。在其他实施例中，掺质浓度比现有装置中形成的轻掺杂源极/漏极区的掺质浓度低至少两个级数。在这些实施例中，组成渐变掺杂区160与轻掺杂源极/漏极区不同，因为其布植工艺在形成栅极间隔物130之后。轻掺杂源极/漏极区的布植工艺可能造成凹陷的鳍状结构103A的顶部的掺质浓度过高。凹陷的鳍状结构103A的顶部的掺质浓度过高，可能导致不想要的现象如掺质扩散至晶体管通道中，这将造成短通道效应和/或损伤虚置栅极结构120(或损伤其他基板结构与层状物)。在一些例子中，可省略鳍状结构103A的轻掺杂源极/漏极区。然而在其他例子中，可形成轻掺杂源极/漏极区于鳍状结构103A中。
布植掺质至凹陷的鳍状结构103A中的方法，可采用离子布植以获得掺质渐变的轮廓。用以形成组成渐变掺杂区160的离子布植工艺的一例，包含的离子束能量介于近似1KeV至近似15KeV之间，且包含的倾斜角度介于近似0度至近似15度之间。斜向布植有助于布植组成渐变掺杂区160的侧壁。布植至鳍状结构103A中的组成渐变掺杂区160的底部的掺质，其深度160DB介于约5nm至约20nm之间，且掺质浓度介于约1×1019cm-3至约1×1021cm-3之间。布植至鳍状结构103A中的组成渐变掺杂区160的中间部分的掺质，其深度160DM介于约3nm至约15nm之间，且掺质浓度介于约5×1018cm-3至约5×1020cm-3之间。布植至鳍状结构103A中的组成渐变掺杂区160的顶部的掺质，其深度160DT介于约1nm至约10nm之间，且掺质浓度介于约1×1018cm-3至约1×1020cm-3之间。在这些实施例中，布植掺质至鳍状结构103A的工艺不需布植后退火和/或额外的清洁步骤。
在方法10的步骤60中，沉积源极/漏极区170于p型装置区中凹陷的鳍状结构103A中的组成渐变掺杂区160上，如图6A与图6B所示。图6A是一些实施例中基板102的剖视图，其于图5A的鳍状结构103A中的组成渐变掺杂区160上形成源极/漏极区170。图6B是一些实施例中，组成渐变掺杂区160与源极/漏极区170在Z方向中的视图。源极/漏极区170位于虚置栅极结构120两侧上的凹陷的鳍状结构103A的组成渐变掺杂区160上，并与个别的栅极间隔物130相邻。虚置栅极结构120形成于具有鳍状结构103A的n型井区108上，而鳍状结构103A具有组成渐变掺杂区160(布植有p型掺质)。上述结构之后将形成p型鳍状场效晶体管结构。
源极/漏极区170包含的半导体材料，可外延成长于凹陷的鳍状结构103A的凹陷150中的组成渐变掺杂区160上。举例来说，p型鳍状场效晶体管装置的源极/漏极区170可包含硅锗、掺杂硼的硅锗、掺杂硼的硅、或类似物。举例来说，源极/漏极区170可包含硅锗，其锗含量介于约30％至约70％之间。举例来说，源极/漏极区170可包含掺杂硼的硅锗，其锗含量介于约30％至约70％之间，且其硼浓度介于约1×1019原子/cm3至约5×1021原子/cm3之间。硅锗的源极/漏极区170的锗含量，有助于诱发应变于通道装置中，进而增加载子移动率。举例来说，掺杂硼的硅中的硼浓度可介于约1×1019原子/cm3至约5×1021原子/cm3之间。硼浓度有助于增加个别源极/漏极区170之间的载子移动率。外延成长源极/漏极区170的步骤，可选择性成长于凹陷的鳍状结构103A的结晶表面上。在外延成长工艺中，可垂直成长与水平成长源极/漏极区170以形成晶面，且晶面对应鳍状结构103A的结晶平面。由于不同表面具有不同结晶取向，在不同表面上的成长速率也不同。因此源极/漏极区170的形状可为钻石状结构或其他形状，视凹陷150的下表面与源极/漏极区170的外延成长的横向成长与垂直成长而定。
源极/漏极区170的形成方法可为沉积多个层状物，其具有不同浓度的元素(比如掺质和/或半导体元素如锗)。源极/漏极区170可与相邻的平行鳍状结构上的相邻源极/漏极区合并或不合并。
源极/漏极区170的沉积方法可为分子束外延、液相外延、气相外延、选择相外延成长、类似工艺、任何其他合适的沉积工艺、或任何其组合。可在外延沉积时原位掺杂源极/漏极区170，和/或布植掺质至源极/漏极区170中。
在这些实施例中，源极/漏极区170可诱发应变于通道中，而通道由虚置栅极结构120覆盖的鳍状结构103A所定义。举例来说，源极/漏极区170包含硅锗时可诱发压缩应变于通道中。应变通道层可增加载子移动率，因此增加装置(如鳍状场效晶体管装置)的驱动电流。
图7显示形成接点蚀刻停止层180，以及形成第一层间介电层182于接点蚀刻停止层180上之后的中间结构。一般而言，蚀刻停止层180在形成接点或通孔时，可提供停止蚀刻工艺的机制。接点蚀刻停止层180的组成可为蚀刻选择性不同于相邻的层状物或构件的介电材料。顺应性地沉积接点蚀刻停止层180于源极/漏极区170的表面以及栅极间隔物130的侧壁与上表面上，且顺应性沉积可为合适的沉积工艺。接点蚀刻停止层180可包含或可为氮化硅、碳氮化硅、碳氧化硅、氮化碳、类似物、或其组合。第一层间介电层182可包含或可为氧化硅、低介电常数的介电材料(比如介电常数低于氧化硅的介电常数的材料)、氮氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂硼的磷硅酸盐玻璃、未掺杂的硅酸盐玻璃、掺杂氟的硅酸盐玻璃、有机硅酸盐玻璃、碳氧化硅、旋转涂布玻璃、旋转涂布聚合物、碳硅材料、上述的化合物、上述的复合物、类似物、或其组合。在沉积第一层间介电层182之后，可以化学机械研磨等工艺平坦化第一层间介电层182，其可移除硬遮罩层126并露出图6的虚置栅极结构120的虚置层124。
图7还显示以个别的置换栅极结构190取代虚置栅极结构120、形成第二层间介电层184、与形成接点186之后的中间结构。移除虚置栅极结构120以形成沟槽，且移除方法可为适当的蚀刻工艺。沟槽填有个别的置换栅极结构190。置换栅极结构190各自包含栅极介电层192、视情况形成的金属衬垫层194、功函数(work function)调整层195、与导电栅极充填物196。顺应性的栅极介电层192、视情况形成的金属衬垫层194、与导电栅极充填物196的沉积方法可为合适的沉积技术。
栅极介电层192可顺应性地形成于沟槽中，比如沿着鳍状结构103A的侧壁与上表面以及沿着栅极间隔物130的侧壁。栅极介电层192可为氧化硅、氮化硅、高介电常数的介电材料、或上述的多层。高介电常数的介电材料(如介电常数大于约7.0的介电材料)可包含或可为铪、铝、锆、镧、镁、钛、钇、钪、镏、钆、镝、钙、钐、或其组合的金属氧化物或金属硅酸盐。
可顺应性地形成一或多个金属衬垫层194于栅极介电层192上。金属衬垫层194可包含盖层和/或阻障层。盖层和/或阻障层可用以避免杂质扩散至下方的层状物，或避免杂质自下方的层状物扩散。盖层和/或阻障层可包含氮化钽、氮化钛、类似物、或其组合。
功函数调整层195可选择为调整功函数值，使晶体管达到所需的临界电压。功函数调整层195包含钽铝、氮化钽、碳化钽铝、碳化钽、碳氮化钽、氮化钽硅、钛、氮化钛、氮化钛铝、银、锰、锆、钌、钼、铝、氮化钨、锆硅化物、钼硅化物、钽硅化物、镍硅化物、其他合适的功函数材料、或其组合。
导电栅极充填物196形成于功函数调整层195上并填入沟槽。导电栅极充填物196可包括含金属材料如钨、钴、钌、铝、氮化钛、氮化钽、碳化钽、氮化铝钛、碳化铝钛、氧化铝钛、其组合、或上述的多层。
移除第一层间介电层182、接点蚀刻停止层180、与栅极间隔物130的上表面上的导电栅极充填物196、视情况形成的金属衬垫层194、与栅极介电层192的部分，且移除方法可为平坦化工艺如化学机械研磨工艺。
形成第二层间介电层184于第一层间介电层182、置换栅极结构190、栅极间隔物130、与接点蚀刻停止层180上。虽然未图示，但一些例子可沉积蚀刻停止层于第一层间介电层182上，而第二层间介电层184可沉积于蚀刻停止层上。第二层间介电层184可包含或可为氧化硅、低介电常数的介电材料、氮氧化硅、磷硅酸盐玻璃、硼硅酸盐玻璃、掺杂硼的磷硅酸盐玻璃、未掺杂的硅酸盐玻璃、掺杂氟的硅酸盐玻璃、有机硅酸盐玻璃、碳氧化硅、旋转涂布玻璃、旋转涂布聚合物、碳硅材料、上述的化合物、上述的复合物、类似物、或其组合。第二层间介电层184的沉积方法可为任何可接受的沉积技术。
形成开口穿过第二层间介电层184、第一层间介电层182、与接点蚀刻停止层180至源极/漏极区170，以露出源极/漏极区170的至少部分。开口的形成方法可采用合适的光微影与一或多道蚀刻工艺。接点186形成于开口中，以至源极/漏极区170。接点186亦可包含充填金属如钨、铝、钴、钌、铜、或其他合适金属。接点186亦可包含硅化物于个别的源极/漏极区170上，以及阻障和/或粘着层于充填金属与开口侧壁之间。
图8是一些实施例中，形成半导体装置(如鳍状场效晶体管结构)于基板上的另一方法200的流程图。在一些实施例中，方法200的细节将搭配图9至图14说明，其为形成半导体结构100(如鳍状场效晶体管半导体装置)于基板102上的多种阶段的视图。
在方法200的步骤202中，形成鳍状结构103A于n型井区108上的基板102上，如图9所示。图9的鳍状结构103A与图3C的鳍状结构103A类似，因此采用类似标号以简化说明。鳍状结构103A可为硅锗鳍状结构和/或硅鳍状结构。
在方法200的步骤204中，形成第一组栅极结构与第二组栅极结构于鳍状结构103A上。举例来说，两组的虚置栅极结构120A与120B可形成于n型井区108上的鳍状结构103A上。附图中的两组虚置栅极结构120A与120B各自具有两个虚置鳍状结构，但可具有任何数目的虚置鳍状结构。虚置栅极结构120A与120B可形成于相同的鳍状结构103A或不同的鳍状结构103A上。每一虚置栅极结构120A与120B可包含介电层122、一或多个虚置层124、与硬遮罩层126。沿着虚置栅极结构120A与120B的侧壁形成栅极间隔物130，如前所述。
每一组的虚置栅极结构120A与120B可位于不同区域中，比如逻辑核心区、存储区(如埋置静态随机存取存储区)、模拟区、输入/输出区(又称作周边区)、虚置区(用以形成虚置图案)、或类似区。举例来说，虚置栅极结构120A可用于存储区(如静态随机存取存储区)，而虚置栅极结构120B可用于逻辑核心区。
在步骤206中，形成遮罩140于具有第二组的栅极结构(如虚置栅极结构120B)的鳍状结构103A的区域上，而遮罩140未覆盖具有第一组的栅极结构(如虚置栅极结构120A)的鳍状结构103A的区域，如图10所示。遮罩140可为显影的光刻胶，或以显影的光刻胶图案化的硬遮罩。
在方法200的步骤208中，形成凹陷150A于具有第一组栅极结构(如虚置栅极结构120A)的鳍状结构103A的区域中。虚置栅极结构120A未覆盖而栅极间隔物130覆盖的鳍状结构103A的区域，被蚀刻以形成凹陷150A。凹陷150A的底部和/或侧壁的形状可为角形、圆润形、或平坦形。形成于鳍状结构103A中的凹陷150A可具有所需深度。
在方法200的步骤210中，形成组成渐变掺杂区160于凹陷的鳍状结构103A中，如图11所示。在一些实施例中，图11是基板102的剖视图，其形成组成渐变掺杂区160于图10的凹陷的鳍状结构103A中。可采用虚置栅极结构120A与栅极间隔物130作为遮罩，布植掺质至凹陷的鳍状结构103A中，以形成组成渐变掺杂区160于鳍状结构103A的顶部。
在其他实施例中，掺质浓度比现有装置中形成的轻掺杂源极/漏极区的掺质浓度低至少两个级数。轻掺杂源极/漏极区的布植工艺可能造成凹陷的鳍状结构103A的顶部的掺质浓度过高。凹陷的鳍状结构103A的顶部的掺质浓度过高，可能导致不想要的现象如掺质扩散至晶体管通道中，这将造成短通道效应和/或损伤虚置栅极结构120(或损伤其他基板结构与层状物)。在一些例子中，可省略鳍状结构103A的轻掺杂源极/漏极区。然而在其他例子中，可形成轻掺杂源极/漏极区于鳍状结构103A中。
布植掺质至凹陷的鳍状结构103A中的方法，可采用离子布植以得掺质渐变的轮廓。掺质的例子包含硼掺质如二氟化硼以用于p型装置，不过亦可采用其他掺质。用以形成组成渐变掺杂区160的离子布植工艺的一例，包含的离子束能量介于近似1KeV至近似15KeV之间，且包含的倾斜角度介于近似0度至近似15度之间。斜向布植有助于布植组成渐变掺杂区160的侧壁。布植至鳍状结构103A中的组成渐变掺杂区160的底部的掺质，其深度160DB介于约5nm至约20nm之间，且掺质浓度介于约1×1019cm-3至约1×1021cm-3之间。布植至鳍状结构103A中的组成渐变掺杂区160的中间部分的掺质，其深度160DM介于约3nm至约15nm之间，且掺质浓度介于约5×1018cm-3至约5×1020cm-3之间。布植至鳍状结构103A中的组成渐变掺杂区160的顶部的掺质，其深度160DT介于约1nm至约10nm之间，且掺质浓度介于约1×1018cm-3至约1×1020cm-3之间。在这些实施例中，布植掺质至鳍状结构103A的工艺不需布植后退火和/或额外的清洁步骤。
在步骤212中，覆盖具有虚置栅极结构120B的鳍状结构103A的区域的遮罩140被移除，如图12所示。遮罩140的移除方法可为灰化、蚀刻、湿式剥除、或另一合适工艺。
在步骤214中，形成遮罩142于具有第一组栅极结构(如虚置栅极结构120A)的鳍状结构103A的区域上，且遮罩142未覆盖具有第二组栅极结构(如虚置栅极结构120B)的鳍状结构103A的区域。遮罩142可为显影的光刻胶，或采用显影的光刻胶图案化的硬遮罩。
在方法200的步骤216中，形成凹陷150B于具有第二组栅极结构(如虚置栅极结构120B)的鳍状结构103A的区域中。虚置栅极结构120B未覆盖而栅极间隔物130覆盖的鳍状结构103A的区域，被蚀刻以形成凹陷150B。凹陷150B的底部和/或侧壁的形状可为角形、圆润形、或平坦形。鳍状物103A中的凹陷150B可形成以具有所需深度。
在步骤218中，覆盖具有虚置栅极结构120A的鳍状结构103A的区域的遮罩142将被移除，如图13所示。移除遮罩142的方法可为灰化、蚀刻、湿式剥除、或另一合适工艺。
在方法200的步骤220中，源极/漏极区170沉积于具有虚置栅极结构120A于其上的凹陷的鳍状结构103A的组成渐变掺杂区160上，并沉积于具有虚置栅极结构120B于其上的凹陷的鳍状结构103A上(不具有组成渐变掺杂区，比如非布植区)。具有虚置栅极结构120而无组成渐变掺杂区的凹陷的鳍状结构103A的区域，之后可包含自源极/漏极区170扩散至凹陷的鳍状结构103A中的掺质。
源极/漏极区170包含的半导体材料，可外延成长于凹陷的鳍状结构103A的凹陷150A与150B中。举例来说，p型鳍状场效晶体管装置的源极/漏极区170可包含硅锗、掺杂硼的硅锗、掺杂硼的硅、或类似物。源极/漏极区170的形成方法可为沉积多个层状物。源极/漏极区170可与相邻的平行鳍状结构上的相邻源极/漏极区合并或不合并。在这些实施例中，源极/漏极区170可诱发应变于通道中，而通道由虚置栅极结构120A与120B覆盖的鳍状结构103A所定义。举例来说，源极/漏极区170包含硅锗时可诱发压缩应变于通道中。应变通道层可增加载子移动率，因此增加装置(如鳍状场效晶体管装置)的驱动电流。
图14显示形成接点蚀刻停止层180，以及形成第一层间介电层182于接点蚀刻停止层180上之后的中间结构。顺应性地沉积接点蚀刻停止层180于源极/漏极区170的表面以及栅极间隔物130的侧壁与上表面上，且顺应性沉积可为合适的沉积工艺。在沉积第一层间介电层182之后，可以化学机械研磨等工艺平坦化第一层间介电层182，其可移除硬遮罩层126并露出图13的虚置栅极结构120的虚置层124。
图14还显示以个别的置换栅极结构190取代虚置栅极结构120、形成第二层间介电层184、与形成接点186之后的中间结构。移除虚置栅极结构120以形成沟槽，且移除方法可为适当的蚀刻工艺。沟槽填有个别的置换栅极结构190。置换栅极结构190各自包含顺应性的栅极介电层192、视情况形成的金属衬垫层194、与导电栅极充填物196。顺应性的栅极介电层192、视情况形成的金属衬垫层194、与导电栅极充填物196的形成方法，可与图7的前述方法类似。
第二层间介电层184形成于第一层间介电层182、置换栅极结构190、栅极间隔物130、与接点蚀刻停止层180上。虽然未图示，但一些例子可沉积蚀刻停止层于第一层间介电层182与其他层状物上，而第二层间介电层184可沉积于蚀刻停止层上。第二层间介电层184的沉积方法可为任何可接受的沉积技术。
形成开口以穿过第二层间介电层184、第一层间介电层182、与接点蚀刻停止层180至源极/漏极区170，以露出源极/漏极区170的至少部分。开口的形成方法可采用合适的光微影与一或多道蚀刻工艺。接点186形成于开口中，以至源极/漏极区170。接点186亦可包含硅化物于个别的源极/漏极区170上，以及阻障和/或粘着层于充填金属与开口侧壁之间。
应理解的是，图2至7与图9至14所示的鳍状结构103A与103B以及虚置栅极结构120、120A、与120B仅用于说明目的。鳍状结构与栅极结构的数目可为任何数目，视应用而定。虽然此处所述的栅极结构的制作方法采用置换栅极工艺，但亦可采用本技术领域中技术人员已知的栅极优先工艺制作栅极结构。虽然此处所述的源极/漏极的制作方法采用凹陷的鳍状物，但源极/漏极的制作方法可不形成凹陷于鳍状物中。
在这些实施例中，方法200形成p型场效晶体管结构于不同区域中。在一或多个区域中，p型场效晶体管结构具有组成渐变掺杂区160。在一或多个其他区域中，p型场效晶体管结构不具有组成渐变掺杂区(比如无布植)。方法200可调整不同区域如逻辑核心区、存储区、模拟区、输入/输出区、虚置区、或其他合适区中的p型场效晶体管结构的通道电阻。
图15是一些实施例中，互补式金属氧化物半导体装置300的示意图。互补式金属氧化物半导体装置的形成方法可为图1的方法10和/或图8的方法200。
互补式金属氧化物半导体装置包含p型场效晶体管装置310与n型场效晶体管装置320。p型场效晶体管装置310具有组成渐变掺杂区160，其通道电阻低于约5.4KΩ*鳍状物数目，且其寄生电阻低于约7.1KΩ*鳍状物数目。在这些实施例中，p型场效晶体管装置310的通道电阻介于约1KΩ*鳍状物数目至约5.0KΩ*鳍状物数目之间。在这些实施例中，p型场效晶体管装置310的寄生电阻介于约1KΩ*鳍状物数目至约7.0KΩ*鳍状物数目之间。较低的通道电阻与寄生电阻有助于降低或避免互补式金属氧化物半导体装置300的闩锁问题。在电流不受p型场效晶体管装置310与n型场效晶体管320的栅极控制而自正极电源电压VDD直接接地GND时，将产生闩锁问题。据信电流不受p型场效晶体管装置310与n型场效晶体管320的栅极控制的原因在于，不具有组成渐变掺杂区的鳍状结构103A的高电阻。电流自正极电源电压VDD直接接地GND，可能造成短路状态与过量电流。具有组成渐变掺杂区160的P型场效晶体管装置310，不需增加隔离区尺寸即可减少或避免闩锁问题。
实施例
硅锗鳍状物形成于基板上，并使硅锗鳍状物凹陷以形成凹陷的硅锗鳍状物。在实施例1与实施例2中，组成渐变(gradient)的硼掺杂区形成于凹陷的硅锗鳍状物上。进行布植以形成组成渐变的硼掺杂区，且布植能量介于约1KeV至约5KeV之间。在实施例1中，以介于约1×1011cm-2至约5×1013cm-2之间的掺质剂量布植凹陷的硅锗鳍状物。在实施例2中，以介于约6×1013cm-2至约1×1014cm-2之间的掺质剂量布植凹陷的硅锗鳍状物。
凹陷的鳍状物特性测量如第1表所示。开关电流比(Ion/Ioff)提供个别栅极的开启与关闭速度的测量标准。Ion为开启电流，而Ioff为关闭电流。高开关电流比可视作半导体装置效能高。实施例1与实施例2中，组成渐变掺杂区形成于凹陷的硅锗鳍状物上，可比其他装置具有较高的开关电流比。开关电流比与通道电阻(及寄生电阻)成反比。寄生电阻包含栅极电阻与源极/漏极电阻。实施例1与实施例2中的组成渐变掺杂区形成于凹陷的硅锗鳍状物上，可比其他装置具有更低的通道电阻与寄生电阻。
第1表
实施例1 实施例2
开关电流比 35％ 39％
通道电阻 4.64 3.87
寄生电阻 6.89 6.32
在这些实施例中，组成渐变掺杂区160(如组成渐变的硼掺杂区)可降低通道电阻与寄生电阻。在这些实施例中，源极/漏极区可形成于凹陷的鳍状物的组成渐变掺杂区160(如组成渐变的硼掺杂区)上，其中源极/漏极区可诱发应变于通道区(由形成于鳍状物上的栅极所定义)中。
在这些实施例中，组成渐变掺杂区160可用于互补式金属氧化物半导体装置中。举例来说，凹陷的鳍状结构103A如凹陷的硅锗鳍状物或凹陷的硅鳍状物，其具有组成渐变掺杂区160并可用于p型场效晶体管或互补式金属氧化物半导体装置中。
应理解的是半导体装置与其形成方法亦可包含额外的层状物，比如光刻胶层、遮罩层、扩散阻障层、盖层、硅化物层、蚀刻停止层、介电层、粘着层、或其他合适的层状物。半导体装置与其形成方法亦可包含额外工艺，比如涂布光刻胶(如旋转涂布)、软烘烤、对准掩模、曝光、曝光后烘烤、显影光刻胶、冲洗、干燥、硬烘烤、检测、蚀刻、平坦化、化学机械研磨、湿式清洁、灰化、和/或其他可行工艺。
应理解的是，p型场效晶体管装置亦可与n型场效晶体管装置的形成方法整合。应理解的是，基板可包含多种层状物(如导电层、半导体层、或绝缘层)和/或结构(掺杂区、井区、鳍状物、源极/漏极区、隔离区、浅沟槽隔离结构、栅极结构、内连线线路、通孔、或其他合适结构)形成于基板之中和/或之上。多个层状物和/或结构用于制作半导体装置与集成电路。在此处所述的方法步骤与附图中，基板亦可包含额外材料形成于基板之中和/或之上。
在这些实施例中，可采用其他顺序进行方法10的步骤与方法200的步骤。在这些实施例中，可省略方法10与方法200的这些步骤。在这些实施例中，可在方法10与方法200的步骤之间进行额外步骤。
一实施例为半导体装置的形成方法。方法包括形成鳍状物于基板上。形成栅极结构于鳍状物上。形成凹陷于与栅极结构相邻的鳍状物中。以p型掺质形成组成渐变掺杂区于鳍状物中。组成渐变掺杂区自凹陷的下表面延伸至垂直深度，且垂直深度低于鳍状物中的凹陷。形成源极/漏极区于凹陷中与组成渐变掺杂区上。
在一实施例中，上述方法中的鳍状物包括硅或硅锗。
在一实施例中，上述方法中的p型掺质为硼掺质，其布植至组成渐变掺杂区中的峰值浓度介于约1×1013cm-3至约1×1014cm-3之间。
在一实施例中，上述方法中的组成渐变掺杂区具有底部、中间部分、与顶部。
在一实施例中，上述方法中布植p型掺质的离子束能量介于约1KeV至约15KeV之间。
在一实施例中，上述方法的源极/漏极区包含掺杂的硅锗。
在一实施例中，上述方法的源极/漏极区诱发应变于鳍状物的通道中，且通道由栅极结构所定义。
一实施例为包含p型场效晶体管结构的半导体装置。p型场效晶体管结构包含鳍状物于基板上。栅极结构位于鳍状物上。外延源极/漏极区位于与栅极结构相邻的鳍状物上。组成渐变掺杂区位于鳍状物中，且自外延源极/漏极区的底部延伸至鳍状物中。
在一实施例中，上述半导体装置的组成渐变掺杂区包括在外延源极/漏极区的底部的鳍状物表面的硼浓度，且硼浓度沿着鳍状物的深度减少。
在一实施例中，上述半导体装置的鳍状物包括硅鳍状物或硅锗鳍状物。
在一实施例中，上述半导体装置的外延源极/漏极区包括掺杂的硅锗。
在一实施例中，上述半导体装置的源极/漏极区诱发应变于通道中，且通道由鳍状物上的栅极结构所定义。
在一实施例中，上述半导体装置包括n型场效晶体管结构，且n型场效晶体管结构包括第二鳍状物于基板上。
在一实施例中，上述半导体装置中的p型场效晶体管结构的寄生电阻介于约1KΩ*鳍状物数目至约7.0KΩ*鳍状物数目之间。
在一实施例中，上述半导体装置包括第二p型场效晶体管结构，且第二p型场效晶体管结构包括第二鳍状物位于基板上；第二栅极结构位于第二鳍状物上；以及第二外延源极/漏极区位于与第二栅极结构相邻的第二鳍状物上。
在一实施例中，上述半导体装置的第二外延源极/漏极区位于第二鳍状物的非布植区上。
一实施例为半导体装置的另一形成方法。方法包括形成第一鳍状结构与第二鳍状结构于基板上。第一栅极结构形成于第一鳍状结构上，且第二栅极结构形成于第二鳍状结构上。第一凹陷形成于与第一栅极结构相邻的第一鳍状结构中。组成渐变掺杂区经由第一凹陷，形成于第一鳍状结构中。第二凹陷形成于与第二栅极结构相邻的第二鳍状结构中。个别的源极/漏极区形成于(i)第一鳍状结构中的组成渐变掺杂区上的第一凹陷中；以及(ii)第二鳍状结构中的第二凹陷中。
在一实施例中，上述方法在形成个别的外延源极/漏极区时，未布植第二鳍状结构。
在一实施例中，上述方法的组成渐变掺杂区的形成方法为布植p型掺质，且p型掺质的浓度介于约1×1013cm-3至1×1014cm-3之间。
在一实施例中，上述方法以分开工艺形成第一鳍状结构中的第一凹陷与第二鳍状结构中的第二凹陷。
上述实施例的特征有利于本技术领域中技术人员理解本公开。本技术领域中技术人员应理解可采用本公开实施例作基础，设计并变化其他工艺与结构以完成上述实施例的相同目的和/或相同优点。本技术领域中技术人员亦应理解，这些等效置换并未脱离本公开实施例的构思与范围，并可在未脱离本公开实施例的构思与范围的前提下进行改变、替换、或变动。

Claims (1)

1.一种半导体装置的形成方法，包括：
形成一鳍状物于一基板上；
形成一栅极结构于该鳍状物上；
形成一凹陷于与该栅极结构相邻的该鳍状物中；
以p型掺质形成一组成渐变掺杂区于该鳍状物中，该组成渐变掺杂区自该凹陷的下表面延伸至一垂直深度，且该垂直深度低于该鳍状物中的该凹陷；以及
形成一源极/漏极区于该凹陷中与该组成渐变掺杂区上。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10483372B2 (en) 2017-09-29 2019-11-19 Taiwan Semiconductor Manufacturing Co., Ltd. Spacer structure with high plasma resistance for semiconductor devices
CN110875184B (zh) * 2018-08-29 2023-08-18 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
KR20200141142A (ko) 2019-06-10 2020-12-18 삼성전자주식회사 반도체 장치
US11264478B2 (en) 2019-10-31 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Transistors with reduced defect and methods forming same
US11437490B2 (en) * 2020-04-08 2022-09-06 Globalfoundries U.S. Inc. Methods of forming a replacement gate structure for a transistor device
US11955482B2 (en) * 2020-05-18 2024-04-09 Intel Corporation Source or drain structures with high phosphorous dopant concentration
US11450572B2 (en) * 2020-05-22 2022-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11888064B2 (en) * 2020-06-01 2024-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
US11515165B2 (en) * 2020-06-11 2022-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method
KR20220020715A (ko) 2020-08-12 2022-02-21 삼성전자주식회사 집적회로 소자
KR20220083437A (ko) 2020-12-11 2022-06-20 삼성전자주식회사 집적회로 소자
US20220336640A1 (en) * 2021-04-14 2022-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Undoped Region Under Source/Drain And Method Forming Same

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102194697A (zh) * 2010-03-09 2011-09-21 台湾积体电路制造股份有限公司 半导体结构的形成方法
CN102456628A (zh) * 2010-10-27 2012-05-16 台湾积体电路制造股份有限公司 制造应变源/漏极结构的方法
US9287382B1 (en) * 2014-11-06 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for semiconductor device
US9548388B1 (en) * 2015-08-04 2017-01-17 International Business Machines Corporation Forming field effect transistor device spacers
US20170077244A1 (en) * 2015-09-15 2017-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same
CN107104137A (zh) * 2016-02-22 2017-08-29 联华电子股份有限公司 鳍状晶体管元件

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
US9171929B2 (en) 2012-04-25 2015-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Strained structure of semiconductor device and method of making the strained structure
US9093530B2 (en) 2012-12-28 2015-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fin structure of FinFET
US9159824B2 (en) 2013-02-27 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with strained well regions
US9299840B2 (en) 2013-03-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US9214555B2 (en) 2013-03-12 2015-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Barrier layer for FinFET channels
US9245882B2 (en) 2013-09-27 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs with gradient germanium-containing channels
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
US9548303B2 (en) 2014-03-13 2017-01-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET devices with unique fin shape and the fabrication thereof
US9608116B2 (en) 2014-06-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. FINFETs with wrap-around silicide and method forming the same
US9679990B2 (en) * 2014-08-08 2017-06-13 Globalfoundries Inc. Semiconductor structure(s) with extended source/drain channel interfaces and methods of fabrication
US9093477B1 (en) * 2014-11-09 2015-07-28 United Microelectronics Corp. Implantation processing step for a recess in finFET
US9564489B2 (en) 2015-06-29 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple gate field-effect transistors having oxygen-scavenged gate stack
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US9793404B2 (en) 2015-11-30 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon germanium p-channel FinFET stressor structure and method of making same
US10262903B2 (en) * 2017-06-22 2019-04-16 Globalfoundries Inc. Boundary spacer structure and integration
CN109273360B (zh) * 2017-07-17 2021-07-20 联华电子股份有限公司 半导体装置的制作方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102194697A (zh) * 2010-03-09 2011-09-21 台湾积体电路制造股份有限公司 半导体结构的形成方法
CN102456628A (zh) * 2010-10-27 2012-05-16 台湾积体电路制造股份有限公司 制造应变源/漏极结构的方法
US9287382B1 (en) * 2014-11-06 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for semiconductor device
US9548388B1 (en) * 2015-08-04 2017-01-17 International Business Machines Corporation Forming field effect transistor device spacers
US20170077244A1 (en) * 2015-09-15 2017-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same
CN107104137A (zh) * 2016-02-22 2017-08-29 联华电子股份有限公司 鳍状晶体管元件

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