CN107104137A - 鳍状晶体管元件 - Google Patents

鳍状晶体管元件 Download PDF

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CN107104137A
CN107104137A CN201610096049.0A CN201610096049A CN107104137A CN 107104137 A CN107104137 A CN 107104137A CN 201610096049 A CN201610096049 A CN 201610096049A CN 107104137 A CN107104137 A CN 107104137A
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layer
fin
dopant well
transistor element
conductivity
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CN107104137B (zh
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林廷燿
周玲君
李坤宪
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United Microelectronics Corp
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Abstract

本发明公开一种鳍状晶体管(finFET)元件，其包含至少一鳍状结构，一第一导电型态掺杂阱以及一与之相邻的第二导电型态掺杂阱定义于该鳍状结构上，一凹槽位于该鳍状结构中，并位于该第一导电型态掺杂阱与该第二导电型态掺杂阱之间，一绝缘层位于该凹槽内，以及一金属栅极横跨并位于该绝缘层上。

Description

鳍状晶体管元件
技术领域
本发明涉及一种高压金属氧化物半导体(high voltagemetal-oxide-semiconductor，以下简称为HV MOS)晶体管元件，尤其是涉及一种高压横向双扩散金属氧化物半导体(high voltage lateral double-diffusedmetal-oxide-semiconductor，HV-LDMOS)晶体管元件。
背景技术
在具有高压处理能力的功率元件中，双扩散金属氧化物半导体(double-diffused MOS，DMOS)晶体管元件持续受到重视。常见的DMOS晶体管元件有垂直双扩散金属氧化物半导体(vertical double-diffused MOS，VDMOS)与横向双扩散金属氧化物半导体(LDMOS)晶体管元件。而LDMOS晶体管元件因具有较高的操作频宽与操作效率，以及易与其他集成电路整合的平面结构，现已广泛地应用于高电压操作环境中，如中央处理器电源供应(CPU power supply)、电源管理系统(power management system)、直流/交流转换器(AC/DC converter)以及高功率或高频段的功率放大器等等。LDMOS晶体管元件主要的特征为源极端所设置的低掺杂浓度、大面积的横向扩散漂移区域，其目的在于缓和源极端与漏极端之间的高电压，因此可使LDMOS晶体管元件获得较高的击穿电压(breakdown voltage)。
由于HV MOS晶体管元件所追求的两个主要特性为高元件密度以及高击穿电压，且这两个要求常常是彼此冲突难以权衡的。因此目前仍需要一种可在高电压环境下正常运作，且满足高击穿电压但不致降低元件密度的解决途径。
发明内容
本发明提供一种鳍状晶体管(finFET)元件，包含至少一鳍状结构，一第一导电型态掺杂阱以及一与之相邻的第二导电型态掺杂阱定义于该鳍状结构上，一凹槽位于该鳍状结构中，并位于该第一导电型态掺杂阱与该第二导电型态掺杂阱之间，一绝缘层位于该凹槽内，以及一金属栅极横跨并位于该绝缘层上。
本发明另提供一种鳍状晶体管(finFET)元件，包含至少一鳍状结构，一第一导电型态掺杂阱以及一与之相邻的第二导电型态掺杂阱定义于该鳍状结构上，一区域边界位于该第一导电型态掺杂阱与该第二导电型态掺杂阱之间，一凹槽位于该鳍状结构中，并位于该第一导电型态掺杂阱与该第二导电型态掺杂阱之间，一绝缘层位于该凹槽内，以及一金属栅极横跨并位于该绝缘层上，其中该金属栅极的一侧壁与该区域边界对齐。
本发明提供一种具有LDMOS结构的高压鳍状晶体管。通过设置一绝缘层在工作栅极下，不仅增加LDMOS的源极至漏极的长度(也就是通道长度)，也同时提高LDMOS的击穿电压。此外，本发明的高压鳍状晶体管结构可与目前现有的技术相容，却不会增加晶体管元件的大小。
附图说明
图1至图8绘示根据本发明第一较佳实施例的一具有横向双扩散金属氧化物半导体的高压鳍状晶体管的结构示意图，其中:
图1绘示鳍状结构位于一基底上；
图2绘示形成一绝缘层于该鳍状结构内；
图3绘示形成多个虚置栅极堆叠结构于该鳍状结构上；
图4-图5绘示形成多个外延层于该鳍状结构上；
图6绘示形成一绝缘层于该鳍状结构上，并对该些外延层进行一离子掺杂步骤；
图7-图8绘示形成多个金属栅极结构于该鳍状结构上。
图9至图10绘示根据本发明第二较佳实施例的一具有横向双扩散金属氧化物半导体的高压鳍状晶体管的结构示意图，其中:
图9绘示形成多个虚置栅极堆叠结构于一鳍状结构上；
图10绘示形成多个金属栅极结构于该鳍状结构上。
图11绘示根据本发明第三较佳实施例的一具有横向双扩散金属氧化物半导体的高压鳍状晶体管的结构示意图。
图12与图13绘示根据本发明另外两较佳实施例的具有横向双扩散金属氧化物半导体的高压鳍状晶体管的结构示意图。
主要元件符号说明
100 高压鳍状晶体管
110 基底
120 鳍状结构
122 凹槽
122A 凹槽
122B 凹槽
130 绝缘层
130A 绝缘层
130B 绝缘层
142 虚置栅极堆叠结构
143 虚置栅极堆叠结构
143A 虚置栅极堆叠结构
144 栅极堆叠结构
144A 栅极堆叠结构
144B 栅极堆叠结构
144C 栅极堆叠结构
144D 栅极堆叠结构
145 间隙壁
146 栅极氧化层
146A 栅极氧化层
148 虚置栅极层
148B 侧壁
149 开口
150 开口
152 外延层
152A 外延层
152B 外延层
160 绝缘层
170 开口
172 高介电常数层
182 导电层
190 通道
192 栅极结构
193 栅极结构
194 栅极结构
194A 栅极结构
S1 源极掺杂层
D1 漏极掺杂层
DP1 第一掺杂层
P1 垂直延伸部
P2 水平延伸部
P3 垂直延伸部
P4 水平延伸部
Z1 第一导电型态掺杂阱
Z2 第二导电型态掺杂阱
V1 垂直交界线
具体实施方式
图1至图8绘示根据本发明第一较佳实施例的一具有横向双扩散金属氧化物半导体(double-diffused metal-oxide-semiconductor，HV-LDMOS)的高压鳍状晶体管(high-voltage finFET)的结构示意图。以下依序介绍制作此具有横向双扩散金属氧化物半导体的高压鳍状晶体管的方法:
请参考图1，首先提供一基底110，例如一半导体基底。基底110上包含有至少一鳍状结构120。其中鳍状结构120定义有两个区域，分别是彼此相邻的一第一导电型态掺杂阱Z1以及一第二导电型态掺杂阱Z2，其中第一导电型态掺杂阱Z1与第二导电型态掺杂阱Z2具有互补的导电型态，举例来说，第一导电型态掺杂阱Z1为一N型掺杂阱，而第二导电型态掺杂阱Z2为一P型掺杂阱，或是第一导电型态掺杂阱Z1为一P型掺杂阱，而第二导电型态掺杂阱Z2为一N型掺杂阱。
接下来请参考图2，通过一曝光显影等方式，在鳍状结构120中形成一凹槽122，其中凹槽122位于第一导电型态掺杂阱Z1与第二导电型态掺杂阱Z2的交界处，也就是说，凹槽122与第一导电型态掺杂阱Z1以及第二导电型态掺杂阱Z2皆有部分重叠。接着，一绝缘层130填入凹槽122中，其中绝缘层130并未填满凹槽122，而仅部分填入凹槽122之内，并在凹槽122内留有部分空间。因此，如图2所示，绝缘层130的顶面较鳍状结构120的顶面更低。
接着如图3所示，在凹槽122中部分填入绝缘层130之后，接着形成多个虚置栅极堆叠结构142于鳍状结构120上，以及至少一栅极堆叠结构144于鳍状结构120上并部分填入凹槽122内。此外，形成多个间隙壁145，分别位于虚置栅极堆叠结构142与栅极堆叠结构144的两侧。本实施例中，虚置栅极堆叠结构142可能位于第一导电型态掺杂阱Z1或第二导电型态掺杂阱Z2内，而栅极堆叠结构144则同时位于第一导电型态掺杂阱Z1以及第二导电型态掺杂阱Z2内。此外，各虚置栅极堆叠结构142彼此之间并不互相接触，也不与栅极堆叠结构144直接接触。
上述形成虚置栅极堆叠结构142、栅极堆叠结构144的方法如下:首先，形成一栅极氧化层146于鳍状结构120表面，以及覆盖于凹槽122的内部侧壁，接着再形成一虚置栅极层148(例如一多晶硅层)于栅极氧化层146，值得注意的是，虚置栅极层148填满凹槽122，且同时位于鳍状结构120的上方。接下来，进行一蚀刻步骤，移除部分的栅极氧化层146与虚置栅极层148，以形成虚置栅极堆叠结构142与栅极堆叠结构144。其中，因为栅极堆叠结构144填入于凹槽122，并且位于绝缘层130上，因此栅极堆叠结构144包含有一垂直延伸部P1以及一水平延伸部P2。其中垂直延伸部P1填满凹槽122并且位于绝缘层130上，水平延伸部P2则位于鳍状结构120上，并且跨越第一导电型态掺杂阱Z1以及一第二导电型态掺杂阱Z2。此外，本实施例中，垂直延伸部P1与水平延伸部P2的延伸方向较佳互相垂直。
值得注意的是，由于栅极堆叠结构144中的栅极氧化层146(图3中标示为栅极氧化层146A)沿着凹槽122的表面形成，例如通过一沉积步骤所形成，因此其具有一“倒Ω”型剖面。此外，各虚置栅极堆叠结构142也同样包含有栅极氧化层146以及虚置栅极层148，但各虚置栅极堆叠结构142中的栅极氧化层146仅有一平坦剖面结构。
请参考图4与图5，如图4所示，在形成虚置栅极堆叠结构142与栅极堆叠结构144之后，接着进行一蚀刻步骤，以在鳍状结构120中形成多个开口150，其中各开口150位于虚置栅极堆叠结构142两侧，或是位于栅极堆叠结构144两侧。接下来，如图5所示，可以选择性地形成多个外延层152于各开口150中，例如通过一选择性外延成长(Selective Epitaxial Growth，SEG)步骤或其他适合的方法，较佳而言，各外延层152的一顶面与鳍状结构120的顶面切齐，但不限于此。此外，本实施例中，包含有形成凹槽150与外延层152的步骤，但在其他实施例中，也可以省略形成凹槽与外延层的步骤，也属于本发明的涵盖范围内。
请参考图6，接下来，对各外延层152进行一掺杂步骤。此外，
在其他实施例中，若外延层没有形成，则对鳍状结构120进行一掺杂步骤。本实施例中，各外延层152皆被掺杂一具有第一导电型态的离子，而与第一导电型态掺杂阱Z1具有相同的导电型态。其中，第一导电型态掺杂阱Z1内且相邻绝缘层130一侧的一外延层152(标示为152A)，被掺杂之后形成一漏极掺杂层D1；另外，第二导电型态掺杂阱Z2内且相邻绝缘层130旁的另一外延层152(标示为152B)，被掺杂后形成一源极掺杂层S1，而其余被掺杂后的外延层152则定义为第一掺杂层DP1，因此本实施例中，第一掺杂层DP1并不位于源极掺杂层S1与漏极掺杂层D1之间的区域。
在一实施例中，若第一导电型态掺杂阱Z1为一N型掺杂阱，而第二导电型态掺杂阱Z2为一P型掺杂阱，则上述的源极掺杂层S1、漏极掺杂层D1与第一掺杂层DP1皆可通过掺杂适当离子(例如磷、砷离子)而形成N型掺杂区。除此之外，外延层152例如为一硅磷外延层(Phosphorus-doped-Siliconepitaxial layer)，以进一步提供通道拉伸应力，但不限于此。此时的高压鳍状晶体管即定义为一N型高压鳍状晶体管。
在另一实施例中，若第一导电型态掺杂阱Z1为一P型掺杂阱，而第二导电型态掺杂阱Z2为一N型掺杂阱，则上述的源极掺杂层S1、漏极掺杂层D1与第一掺杂层DP1皆可通过掺杂适当离子(例如硼离子)而形成P型掺杂区。除此之外，外延层152例如为一硅锗外延层(Silicon-Germanium epitaxiallayer)，以进一步提供通道压缩应力，但不限于此。而此时的高压鳍状晶体管即定义为一P型高压鳍状晶体管。
接下来，可全面性于鳍状结构120以及虚置栅极堆叠结构142、栅极堆叠结构144上先形成一绝缘层(图未示)，上述绝缘层例如为氮化硅等绝缘材质。接下来进行一平坦化制作工艺，例如化学机械研磨(CMP)，以移除多余的绝缘层，并且曝露出各虚置栅极堆叠结构142与栅极堆叠结构144。因此，多个绝缘层160形成于各外延层152上，其中绝缘层160填入虚置栅极堆叠结构142与栅极堆叠结构144之间的空隙，或是填入各虚置栅极堆叠结构142之间的空隙。
在上述漏极掺杂层D1、源极掺杂层S1与第一掺杂层DP1完成后，进行一金属栅极置换(replacement metal gate,RMG)步骤，将虚置栅极堆叠结构142与栅极堆叠结构144置换成金属栅极。接着如图7至图8所示，金属栅极置换步骤包含:首先，将虚置栅极堆叠结构142与栅极堆叠结构144的虚置栅极层148移除，并形成多个开口170于各绝缘层160之间。上述移除的方式例如为一蚀刻步骤。值得注意的是，在本实施例的图7中，并未将栅极氧化层146移除，但在本发明的其他实施例中，栅极氧化层146可选择性随着虚置栅极层148被一并移除，也属于本发明的涵盖范围内。另外，若栅极氧化层146在此步骤中被移除，则后续在形成金属栅极之前，需重新形成另外一栅极氧化层于金属栅极的导电层与鳍状结构120之间，上述形成栅极氧化层的方法例如通过一原位蒸气生成(in-situ steam generation，ISSG)但不限于此。
接下来，如图8所示，依序形成一高介电常数层172于各开口170内，以及形成一导电层182于高介电常数层172上，以完成多个栅极结构192以及至少一栅极结构194，栅极结构192与栅极结构194皆包含有栅极氧化层146、高介电常数层172与导电层182。此外，栅极结构192与栅极结构194的形状分别与原先虚置栅极堆叠结构142与栅极堆叠结构144相同，因此栅极结构194同样包含有一垂直延伸部P3以及一水平延伸部P4(对应图3中的垂直延伸部P1以及水平延伸部P2)。
本实施例中，高介电常数层172包含有介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide，HfO2)、硅酸铪氧化合物(hafnium silicon oxide，HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化铝(aluminum oxide，Al2O3)、氧化镧(lanthanum oxide，La2O3)、氧化钽(tantalumoxide，Ta2O5)、氧化钇(yttrium oxide，Y2O3)、氧化锆(zirconium oxide，ZrO2)、钛酸锶(strontium titanate oxide，SrTiO3)、硅酸锆氧化合物(zirconium siliconoxide，ZrSiO4)、锆酸铪(hafnium zirconium oxide，HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(lead zirconatetitanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其组合所组成的群组。而导电层182则可包含有功函数金属层以及/或是具有优良填充能力与较低阻值的金属或金属氧化物，例如钨(tungsten，W)、铝(aluminum，Al)、铝化钛(titanium aluminide，TiAl)或氧化铝钛(titanium aluminum oxide，TiAlO)，但不限于此。到此步骤为止，本实施例的所述具有LDMOS结构的具有LDMOS结构的高压鳍状晶体管100已完成。
值得注意的是，上述栅极结构194位于源极掺杂层S1与漏极掺杂层D1之间，并且同时位于绝缘层130的正上方。本发明的其中一特点在于，在具有LDMOS结构的高压鳍状晶体管100运作过程中，由于栅极结构194位于第一导电型态掺杂阱Z1与第二导电型态掺杂阱Z2的交界处，因此栅极结构194作为控制晶体管的通道开启与否的开关，可视为一工作栅极(workinggate)，而其余的栅极结构192则被视作为虚置栅极(dummy gate)。本发明的目的之一在于提高LDMOS的击穿电压(breakdown voltage)，因此在栅极结构(工作栅极)194的下方设置有绝缘层130，绝缘层130位于源极掺杂层S1与漏极掺杂层D1之间，可避免晶体管的源极与漏极之间产生穿隧(punchthrough)现象，进而预防晶体管的源极与漏极之间产生漏电流。换句话说，由于设置绝缘层130，LDMOS的通道190(由源极掺杂层S1至第一导电型态掺杂阱Z1)仅能形成于绝缘层130的下方位置，因此LDMOS的通道长度将会增加。通过绝缘层的设置，LDMOS的击穿电压可有效地提升。与现有的LDMOS结构相比，由于绝缘层130仅设置于鳍状结构120之内，因此虽然LDMOS的通道长度增加，却不会占用更多元件表面积，所以每一单位的LDMOS大小(从剖视图来看，即为源极掺杂层S1与漏极掺杂层D1之间的水平长度)并不会额外增加，本发明的结构适用于现有的具有LDMOS结构的高压鳍状晶体管。
除此之外，本发明的另外一优点在于工作栅极(栅极结构194)包含有一垂直延伸部P1延伸入鳍状结构120中，因此在不额外增加整体元件面积的情况下，工作栅极接触到鳍状结构的面积增加，因此也可以一并提高工作栅极对于LDMOS元件的控制性。
下文将针对本发明的高压鳍状晶体管结构的不同实施样态进行说明，且为简化说明，以下说明主要针对各实施例不同之处进行详述，而不再对相同之处作重复赘述。此外，本发明的各实施例中相同的元件以相同的标号进行标示，以利于各实施例间互相对照。
图9-图10绘示本发明第二较佳实施例的一具有横向双扩散金属氧化物半导体的高压鳍状晶体管的结构示意图。本实施例中，同样包含有一基底110、一鳍状结构120，且鳍状结构120上定义有第一导电型态掺杂阱Z1与第二导电型态掺杂阱Z2，以及一凹槽122位于第一导电型态掺杂阱Z1与第二导电型态掺杂阱Z2的交界处，一绝缘层130部分填入凹槽122中(请参考第一实施例所述的图1与图2)。与上述第一较佳实施利不同之处在于，本实施例中形成的栅极堆叠结构144A结构与上述第一较佳实施例所述的栅极堆叠结构144不同。详细而言，在形成栅极堆叠结构144之后(参考图3)，更进行一蚀刻步骤，以形成一开口149于部分凹槽122中，并将栅极堆叠结构144分割为两部分:一栅极堆叠结构144A与一虚置栅极堆叠结构143。本实施例中，栅极堆叠结构144A并未完整填满凹槽122，而且栅极堆叠结构144A的其中一侧壁148B与第一导电型态掺杂阱Z1与第二导电型态掺杂阱Z2的垂直交界线(图9中标示为V1)对齐，因此本实施例中栅极堆叠结构144A所包含的栅极氧化层146具有一“Z”型剖面。
接下来，与第一较佳实施例相同，依序进行后续步骤，包含形成外延层、进行离子掺杂步骤、形成绝缘层以及进行金属栅极置换步骤等。上述步骤与第一较佳实施例所述的步骤相同，在此不在赘述。本发明第二较佳实施例最终完成的LDMOS结构如图10所示，其中栅极结构194A的一侧壁与第一导电型态掺杂阱Z1与第二导电型态掺杂阱Z2的垂直交界线对齐，另外栅极结构193则位于栅极结构194A与漏极掺杂层之间。除此之外，其余各部件的特征、材料特性以及制作方法与上述第一较佳实施例相似，故在此并不再赘述。
在本发明的其他实施例中，如图11所示，其绘示本发明第三较佳实施例的一具有横向双扩散金属氧化物半导体的高压鳍状晶体管(high-voltagefinFET)的结构示意图。与上述第二较佳实施例的结构相似，栅极堆叠结构144B的其中一侧壁148B与第一导电型态掺杂阱Z1与第二导电型态掺杂阱Z2的垂直交界线(图9中标示为V1)对齐，而本实施例与上述第二较佳实施利不同之处在于，虚置栅极堆叠结构143A同时位于鳍状结构120表面上以及部分凹槽122中。除此之外，其余各部件的特征、材料特性以及制作方法与上述第二较佳实施例相似，故在此并不再赘述。
在本发明的其他实施例中，如图12与图13所示，其绘示本发明另外两较佳实施例的具有横向双扩散金属氧化物半导体的高压鳍状晶体管的结构示意图。在一实施例中，凹槽122A的位置并不位于第一导电型态掺杂阱Z1与第二导电型态掺杂阱Z2的交界处，而是位于第一导电型态掺杂阱Z1内(如图12所示)，而栅极堆叠结构144C位于凹槽122A内的绝缘层130A上。或是在其他实施例中，凹槽122B可能位于第二导电型态掺杂阱Z2内(如图13所示)，而栅极堆叠结构144D位于凹槽122B内的绝缘层130B上。上述结构也属于本发明的涵盖范围内，除此之外，其余各部件的特征、材料特性以及制作方法与上述第一较佳实施例相似，故在此并不再赘述。
综上所述，本发明提供一种具有LDMOS结构的高压鳍状晶体管。通过设置一绝缘层在工作栅极下，不仅增加LDMOS的源极至漏极的长度(也就是通道长度)，也同时提高LDMOS的击穿电压。此外，LDMOS中的各元件，包含绝缘层、虚置栅极、工作栅极、源极掺杂层与漏极掺杂层都设置在同一高压鳍状晶体管内，因此本发明的结构并不会降低元件密度，换句话说，本发明的高压鳍状晶体管结构可与目前现有的技术相容，却不会增加晶体管元件的大小。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (20)

1.一种鳍状晶体管(finFET)元件，包含:
至少一鳍状结构，包含有第一导电型态掺杂阱以及与之相邻的第二导电型态掺杂阱定义于该鳍状结构上；
凹槽，位于该鳍状结构中，并位于该第一导电型态掺杂阱与该第二导电型态掺杂阱之间；
绝缘层，位于该凹槽内；以及
金属栅极，横跨并位于该绝缘层上。
2.如权利要求1所述的鳍状晶体管元件，其中该金属栅极包含有垂直延伸部以及水平延伸部，该水平延伸部与该垂直延伸部互相连接。
3.如权利要求2所述的鳍状晶体管元件，其中该垂直延伸部延伸至该鳍状结构内。
4.如权利要求1所述的鳍状晶体管元件，其中该鳍状晶体管元件包含具有横向双扩散金属氧化物半导体(LDMOS)的高压鳍状晶体管元件。
5.如权利要求1所述的鳍状晶体管元件，还包含多个虚置栅极横跨并位于该鳍状结构上。
6.如权利要求5所述的鳍状晶体管元件，其中各该虚置栅极与该金属栅极皆分别包含金属栅极材料层以及高介电常数层，且该高介电常数层位于该鳍状结构以及该金属栅极材料层之间。
7.如权利要求5所述的鳍状晶体管元件，还包含源极掺杂层，位于该第一导电型态掺杂阱内，以及漏极掺杂层，位于该第二导电型态掺杂阱内，其中该源极掺杂层位于该金属栅极以及一虚置栅极之间，而该漏极掺杂层位于该金属栅极以及另一虚置栅极之间。
8.如权利要求7所述的鳍状晶体管元件，其中该第一导电型态掺杂阱是一N型导电型态区域，该第二导电型态掺杂阱是一P型导电型态区域，且该漏极掺杂层与该源极掺杂层皆为N型掺杂层。
9.如权利要求8所述的鳍状晶体管元件，其中该漏极掺杂层与该源极掺杂层包含硅磷外延层(phosphorus-doped-silicon epitaxial layer)。
10.如权利要求7所述的鳍状晶体管元件，其中该第一导电型态掺杂阱是一P型导电型态区域，该第二导电型态掺杂阱是一N型导电型态区域，且该漏极掺杂层与该源极掺杂层皆为P型掺杂层。
11.如权利要求10所述的鳍状晶体管元件，其中该漏极掺杂层与该源极掺杂层包含硅锗外延层(silicon-germanium epitaxial layer)。
12.一种鳍状晶体管(finFET)元件，包含:
至少一鳍状结构，包含有第一导电型态掺杂阱以及与之相邻的第二导电型态掺杂阱定义于该鳍状结构上，一区域边界位于该第一导电型态掺杂阱与该第二导电型态掺杂阱之间；
凹槽，位于该鳍状结构中，并位于该第一导电型态掺杂阱与该第二导电型态掺杂阱之间；
绝缘层，位于该凹槽内；以及
金属栅极，横跨并位于该绝缘层上，其中该金属栅极的一侧壁与该区域边界对齐。
13.如权利要求12所述的鳍状晶体管元件，还包含多个虚置栅极横跨并位于该鳍状结构上。
14.如权利要求13所述的鳍状晶体管元件，还包含源极掺杂层，位于该第一导电型态掺杂阱内，以及漏极掺杂层，位于该第二导电型态掺杂阱内，其中该源极掺杂层位于该金属栅极以及一虚置栅极之间，而该漏极掺杂层位于该金属栅极以及另一虚置栅极之间。
15.如权利要求14所述的鳍状晶体管元件，其中至少一虚置栅极位于该金属栅极与该漏极掺杂层之间。
16.如权利要求15所述的鳍状晶体管元件，其中该至少一虚置栅极部分位于该凹槽中。
17.如权利要求14所述的鳍状晶体管元件，其中该第一导电型态掺杂阱是N型导电型态区域，该第二导电型态掺杂阱是P型导电型态区域，且该漏极掺杂层与该源极掺杂层皆为N型掺杂层。
18.如权利要求14所述的鳍状晶体管元件，其中该第一导电型态掺杂阱是P型导电型态区域，该第二导电型态掺杂阱是N型导电型态区域，且该漏极掺杂层与该源极掺杂层皆为P型掺杂层。
19.如权利要求13所述的鳍状晶体管元件，其中各该虚置栅极与该金属栅极皆分别包含金属栅极材料层以及高介电常数层，且该高介电常数层位于该鳍状结构以及该金属栅极材料层之间。
20.如权利要求13所述的鳍状晶体管元件，其中该绝缘层的一顶面低于该鳍状结构的一顶面。
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