CN102148253A - 半导体元件及其制作方法 - Google Patents
半导体元件及其制作方法 Download PDFInfo
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Abstract
本发明提供一种半导体元件及其制作方法,其中该半导体元件包括一晶体管,晶体管包括一基底、设置于基底中的第一和第二阱,其中第一和第二阱掺杂不同型态的掺杂物。晶体管包括至少部分设置于第一阱上方的第一栅极、设置于第二阱上方的第二栅极、及分别设置于第一和第二阱中的源极区和漏极区,源极区和漏极区掺杂相同型态的掺杂物。本发明使用虚设栅极放宽现今技术严格的迭对需求,并不需要额外成本。
Description
技术领域
本发明涉及一种半导体元件的制造方法,尤其涉及一种形成半导体元件的栅极的方法。
背景技术
半导体集成电路工业已经历快速的成长。集成电路(IC)材料技术上的改进已制作出好几世代的集成电路,其中每个世代均较前一世代复杂。然而,上述的发展均使IC的制造工艺与制造变得更为复杂,因此,IC制造工艺也需要有相对应的进展以实现先进的集成电路。在集成电路发展的过程中,功能密度(亦即单位芯片区域内连线元件的数目)已普遍的增加,而几何尺寸(使用制造工艺所制造出来最小的组件)则缩小。
在缩小侧向扩散金属氧化物半导体晶体管(LDMOS)的几何尺寸时遇到挑战。侧向扩散金属氧化物半导体晶体管(LDMOS)是具有低导通电阻与高阻断电压能力的非对称功率金属氧化物半导体场效晶体管(MOSFET)。此侧向扩散金属氧化物半导体晶体管(LDMOS)的高阻断电压能力可经由形成阻抗路径达成,其作为侧向扩散金属氧化物半导体晶体管(LDMOS)的通道区的压降。现今的技术是使用轻掺杂源极/漏极区以定义阻抗路径。因此,阻抗路径非常浅,且特别是当几何尺寸持续的缩小时。浅阻抗路径可能无法提供LDMOS晶体管所需求的高阻抗。更进一步来说,几何尺寸的微缩在制作LDMOS晶体管遇到精确对准和迭对(overlay)控制的挑战。
因此,即使现今LDMOS晶体管的制作方法已能满足预期的目的,但并非在各方面皆令人满意。
发明内容
为了解决上述问题,本发明提供一种半导体元件,包括一晶体管,晶体管包括一基底、设置于基底中的第一和第二阱,其中第一和第二阱掺杂不同型态的掺杂物、至少部分设置于第一阱上方的第一栅极、设置于第二阱上方的第二栅极、及分别设置于第一和第二阱中的源极区和漏极区,源极区和漏极区掺杂相同型态的掺杂物。
本发明提供一种半导体元件,包括一晶体管,晶体管包括一基底、一设置于基底中的第一和第二阱,第一和第二阱具有相对的掺杂极性、分别设置于第一阱的一区域和第二阱的一区域上方的第一栅极和第二栅极,第一和第二栅极以一间隔分开、及分别设置于第一和第二阱中的源极区和漏极区,源极区和漏极区具有相同的掺杂极性,其中第一栅极设置于源极区和间隔间,其中第二栅极设置于漏极区和间隔间。
本发明提供一种半导体元件的制作方法,包括以下步骤:提供一基底;形成第一和一第二阱于基底中,第一和第二阱掺杂不同型态的掺杂物;形成一第一栅极,至少部分位于第一阱上方;形成第二栅极于第二阱上方;及
分别于第一和第二阱中形成源极区和漏极区,源极区和漏极区掺杂相同型态的掺杂物。
本发明实施例使用虚设栅极放宽现今技术严格的迭对需求。本发明实施例的另一优点是制造工艺相容于传统的高介电常数金属栅极取代栅极制造工艺,因此实行本实施例并不需要额外的花费。
为让本发明的上述目的、特征及优点能更明显易懂,下文特举一优选实施例,并配合附图,作详细说明如下。
附图说明
图1是一流程图,揭示根据本发明形成半导体元件的方法。
图2-图9显示图1方法在各制作阶段的半导体元件的剖面示意图。
图10显示本发明图1方法另一实施例的半导体元件的剖面示意图。
上述附图中的附图标记说明如下:
11~方法;13~步骤;
15~步骤;17~步骤;
19~步骤;20~栅极结构;
21~步骤;40A~LDMOS元件;40B~LDMOS元件;45~基底;50~隔离结构;51~隔离结构;60~P阱;61~N阱;70~栅极堆叠;71~栅极堆叠;80~栅极介电层;81~栅极介电层;90~栅电极层(闸电极层);91~栅电极层;100~硬式掩模层;101~硬式掩模层;102~间隔区;103~距离;105~N型轻掺杂源极区;
110~栅极间隙壁;111~栅极间隙壁;112~栅极间隙壁;113~栅极间隙壁;120~光致抗蚀剂掩模;130~重掺杂源极区;131~重掺杂漏极区;140~图案化阻抗保护氧化层;
150~自对准金属硅化物;151~自对准金属硅化物;
160~层间介电层;170~化学机械研磨制造工艺;
180~沟槽;181~沟槽;190~高介电常数栅极介电层;
191~高介电常数栅极介电层;
200~导电层;201~导电层;
210~导电层;211~导电层;
220A~栅极结构;221~虚设栅极结构;221A~栅极结构;240~空乏区;250~电流路径。
具体实施方式
以下提供许多不同实施例或范例,以实行本发明各种不同实施例的特征。以下将针对特定实施例的构成与排列方式作简要描述,当然,以下的描述仅是范例,非用来限定本发明。举例来说,于第一元件“上方”或“之上”形成第二元件的叙述可包括第一元件和第二元件直接接触的实施例,但亦包括一额外的元件形成于第一元件和第二元件间的实施例,而使第一元件和第二元件没有直接接触。此外,本发明在各范例中可能会出现重复的元件标号,但上述的重复仅是用来简要和清楚的描述本发明,并不代表各实施范例和结构之间有必然关联。
图1是一半导体元件制作方法11的流程图。方法11首先进行步骤13,提供一基底。接着进行步骤15,形成第一和第二阱于基底中,第一和第二阱掺杂有不同型态的掺杂物。方法11接着进行步骤17,形成第一栅极于至少部分第一阱上方。方法11继续进行步骤19,形成第二栅极于第二阱上方。方法11接续进行步骤21,分别形成源极区和漏极区于第一和第二阱中,源极区和漏极区掺杂同样型态的掺杂物。
图2-图9显示图1方法11在各制作阶段的LDMOS元件40A的剖面示意图。图10显示图1方法11另一实施例在一制作阶段的LDMOS元件40B的剖面示意图。可理解的是,图2-图10是经过简化,以更容易了解本发明的概念。因此,额外的制造工艺可提供在图1的方法11之前、之间或之后,且一些其它的制造工艺在此仅简要的描述。
在本实施例中,半导体元件是N型侧向扩散金属氧化物半导体场效晶体管(LDMOS)。可以理解的是,本发明另一实施例可形成P型LDMOS。请往回参照图2,以40标示N型LDMOS,LDMOS元件40包括一基底45,基底45是掺杂例如硼的P型掺杂物的硅基底。在另一实施例中,基底45是掺杂例如砷或磷的N型掺杂物的硅基底。
于基底中形成隔离结构50、51。在一实施例中,隔离结构50、51是包括介电材料的浅沟槽隔离(STI)结构,其中介电材料可以是氧化硅或氮化硅。形成P阱60和N阱61于基底45中,且介于隔离结构50、51间。P阱60是掺杂例如硼的P型掺杂物,N阱61是掺杂例如砷或磷的N型掺杂物。
之后,形成栅极堆叠70、71于基底45上方。栅极堆叠70、71分别包括栅极介电层80、81。在一实施例中,栅极介电层80、81各包括氧化硅。在另一实施例中,栅极介电层80、81各包括高介电常数材料。高介电常数材料是介电常数大于氧化硅的介电常数的材料,其中氧化硅(SiO2)的介电常数约为4。举例来说,高介电常数材料为氧化铪(HfO2),其介电常数约介于18至40之间。在另一实施例中,高介电常数材料可包括以下材料之一:ZrO2、Y2O3、La2O5、Gd2O5、TiO2、Ta2O5、HfErO、HfLaO、HfYO、HfGdO、HfAlO、HfZrO、HfTiO、HfTaO、SrTiO或上述之组合。
栅极堆叠70、71亦包括分别位于栅极介电层80、81上方的栅电极层90、91,栅电极层90、91各包括多晶硅。栅极堆叠70、71还包括分别位于栅电极层90、91上方的硬式掩模层100、101,硬式掩模层100、101各包括例如氧化硅或氮化硅的介电材料。虽然在此并未揭示,硬式掩模层100、101是借由一图案化光致抗蚀剂层图案化一硬式掩模材料形成。之后使用硬式掩模层100、101来图案化栅电极层90、91和其下的栅极介电层80、81,以形成栅极堆叠70、71。
如图2所揭示,部分的栅极堆叠70是形成在P阱60上方,且另一部分的栅极堆叠70是形成在N阱61上方。栅极堆叠71是用做一虚设(dummy)栅极,其理由将会在以下讨论,且栅极堆叠71是形成在N阱61上方。栅极堆叠70、71是以具有一距离103的间隔区102分开。在形成栅极堆叠70、71之后,形成N型轻掺杂源极区105于P阱60中,轻掺杂源极区是以此领域所熟知的注入制造工艺或扩散制造工艺形成,其掺杂例如砷或磷的N型掺杂物。
请参照图3,形成栅极间隙壁110、111于栅极堆叠70的侧壁,且形成栅极间隙壁112、113于栅极堆叠71的侧壁。栅极间隙壁110、111可视为部分的栅极堆叠70,且栅极间隙壁112、113可视为部分的之栅极堆叠71。栅极间隙壁110-113是使用一沉积制造工艺和一蚀刻制造工艺(例如一各向异性蚀刻制造工艺)形成。栅极间隙壁110-113包括适合的介电材料,例如氮化硅、氧化硅、碳化硅、氮氧化硅或上述的组合。之后,形成一光致抗蚀剂掩模120于基底45上方。光致抗蚀剂掩模120是借由以下步骤形成:形成一光致抗蚀剂层于基底45上方,且以本领域所熟知的光刻技术将光致抗蚀剂层图案化成光致抗蚀剂掩模120。如图3所示,光致抗蚀剂掩模120设置于部分的栅极堆叠70和部分的栅极堆叠71上方,且填入间隔区102。光致抗蚀剂掩模120的目的是保护间隔区102下的N阱61,防止其在后续的注入制造工艺(或掺杂制造工艺)掺入掺杂物。
请参照图4,分别形成一重掺杂源极区130和一重掺杂漏极区131于P阱60和N阱61中。重掺杂源极区130和重掺杂漏极区131可借由本领域熟知的离子注入制造工艺或扩散制造工艺形成。源极区130和漏极区131亦可以称为有源区。源极区130和漏极区131各掺杂例如砷或磷的N型掺杂物。由于掺杂物无法穿过栅极堆叠70、71和围绕栅极堆叠70、71的间隙壁110-113,源极区130会自对准栅极堆叠70的栅极间隙壁110,漏极区131会自对准栅极堆叠71的栅极间隙壁113。如以上所讨论的,光致抗蚀剂掩模120保护其下的N阱61,防止其在离子注入制造工艺中被注入。
传统形成LDMOS元件的方法不包括形成栅极堆叠71。传统的方法本身是依靠使用一光致抗蚀剂掩模,以精准的定义LDMOS元件的漏极区的位置,此会增加用以形成光致抗蚀剂掩模的光刻制造工艺的负担,且可能会导致不想要的结果。在此,栅极堆叠71使漏极区131以自对准的方式形成,因此,漏极区131的边缘对准栅极间隙壁113的边缘。光致抗蚀剂掩模120是用来保护间隔区102下的N阱61,防止其被掺杂,不再用来定义漏极区131的区域。因此,光致抗蚀剂掩模120迭对(overlay)的需求较宽松,其可以形成宽一点或窄一点,而不会影响到漏极区131的区域,只要光致抗蚀剂掩模120的边缘形成在栅极堆叠70、71“之中”即可。此外,在一半导体制造工艺中,形成栅极堆叠70、71的制造阶段相较于其它的制造阶段,一般具有最佳的迭对控制。在图4所示的实施例中,虚设栅极堆叠71是用来定义漏极区131的区域。由于迭对控制在虚设栅极堆叠71的制作阶段是相对较佳,其相较于使用光致抗蚀剂掩模定义漏极区131的方法,可更精准的控制漏极区131的确切区域或尺寸。
请参照图5,以本领域熟知的剥除或灰化制造工艺移除光致抗蚀剂掩模120。后续,形成一图案化阻抗保护氧化(resist protection oxide,RPO)层140,部分填满间隔区102。此图案化阻抗保护氧化(RPO)层140是以下述步骤形成:沉积一图案化阻抗保护氧化(RPO)材料于基底45和栅极堆叠70、71上方,进行一光刻制造工艺,以图案化光致抗蚀剂(未示出)为掩模,图案化阻抗保护氧化(RPO)材料。在被光致抗蚀剂图案化后,图案化阻抗保护氧化(RPO)层140是设置于栅极间隙壁111、112和部分的栅极堆叠70、71上方。之后,于基底45暴露的表面进行硅化制造工艺,以形成自对准金属硅化物150、151。图案化阻抗保护氧化(RPO)层140和硬式掩模100、101在硅化制造工艺中是用做硅化掩模。
类似于配合图4所讨论的,在图5的实施例中形成虚设栅极堆叠71放宽了图案化阻抗保护氧化(RPO)层140的迭对需求。换句话说,自对准金属硅化物150、151的尺寸不再依靠光致抗蚀剂掩模(未示出)精准的迭对控制。
请参照图6,移除图案化阻抗保护氧化(RPO)层140,且形成一层间介电层160于基底45和栅极堆叠70、71上方。层间介电层160可以由化学气相沉积法、高密度等离子体化学气相沉积法、旋转涂布法、溅镀法或其它适合的方法形成。层间介电层160可包括氧化硅。在其它的实施例中,层间介电层160可包括氮氧化硅、氮化硅或低介电材料。
请参照图7,于层间介电层160上进行一化学机械研磨制造工艺170,以暴露栅极堆叠70、71的顶部表面。在另一实施例中,在形成层间介电层160前,没有移除图案化阻抗保护氧化(RPO)层140,而是以化学机械研磨制造工艺170将之移除。在化学机械研磨制造工艺170之后,栅极堆叠70、71任一侧的顶部表面大致上和层间介电层160的顶部表面共面。如此一来,即露出硬式掩模100、101。虽然图中未显示,本发明尚可于LDMOS元件40上进行一或多次退火制造工艺,以活化源极区130和漏极区131。这些退火制造工艺可在化学机械研磨制造工艺170之前或之后进行。
请参照图8,移除栅极堆叠70、71以形成沟槽(或开口)180、181,分别取代栅极堆叠70、71。栅极堆叠70、71可以本领域所熟知的湿蚀刻制造工艺或干蚀刻制造工艺移除,LDMOS元件40剩下的层保持大体上未蚀刻,其包括栅极间隙壁110-113和层间介电层160。此是依照“高介电在后(high-klast)”制造工艺进行。在另一实施例中,栅极介电层80、81各包括以上所讨论的高介电常数材料(而非氧化硅),且其没有被移除。另一实施例是依照“后栅极(gate last)”制造工艺进行,其将会在以后的附图中揭示。
请参照图9,分别形成一高介电常数栅极介电层190、191于沟槽180、181中。高介电常数栅极介电层190、191各包括以上所讨论的高介电常数材料。虽然未揭示,可理解的是,在形成高介电常数栅极介电层190、191之前,可形成一介面层于沟槽180、181中。形成导电层200、201于沟槽180、181中高介电常数栅极介电层190、191的上方。导电层200包括N型功函数金属(N-金属),其可以是Ti、Al、Ta、ZrSi2或上述的组合。导电层201包括P型功函数金属(P-金属),其可以是Mo、Ru、Ir、Pt、PtSi、MoN、WNx或上述的组合。N-金属和P-金属各具有对应的功函数值范围。导电层200、201可以由化学气相沉积法(CVD)、物理气相沉积法(PVD)或其它适合的技术形成。之后,分别形成导电层210、211于沟槽180、181中和导电层200、201上方。导电层210、211各包括钨、铝、铜和上述的组合。导电层210、211可以由化学气相沉积法(CVD)、物理气相沉积法(PVD)、电镀法或其它适合的技术形成。
栅极结构220(或栅极堆叠)是由导电层200、210和高介电常数栅极介电层190形成,且虚设栅极结构221(或栅极堆叠)是由导电层211、201和高介电常数栅极介电层191形成。导电层200、210一起构成栅极结构220的栅电极部分,且导电层201、211一起构成虚设栅极结构221的虚设栅电极部分。
导电层200调整LDMOS元件40的功函数,以达到期望的起始电压。因此,导电层200亦可以称为功函数金属层。导电层210作为栅电极220的主要导电部分且可以称为填充金属层。
虚设栅极结构221的导电层201导致在虚设栅极结构221下方的N阱61中形成一空乏区240。由于每个材料具有不同的功函数值(或数值范围),空乏区240的尺寸和导电层201的材料组成相关。举例来说,在一导电层201包括Mo的实施例中,导电层201的功函数的范围是介于约4.5~4.9之间。在另一导电层包括Pt的实施例中,导电层的功函数的范围是介于约5.2~5.6之间。空乏区240的宽度及/或深度随着导电层201功函数的数值变化。换言之,空乏区240的尺寸是导电层201的金属成份的函数。
空乏区240大体上没有电荷载子,因此不运载电流。由于空乏区240的存在,电流路径250(从源极区105至漏极区131的电流路径)是以围绕着空乏区240流动的方式延伸。延伸的电流路径250有效的增加源极区130和漏极区131间的阻抗路径的电阻。栅极-漏极电压(Vgd)有一部分是配置于源极区130和漏极区131间的阻抗路径。换句话说,阻抗路径作为通道区的压降。为了最佳化LDMOS元件40的效能,可大部分的Vgd分配至上述阻抗路径(或以具有较大的压降),其可借由增加阻抗路径的电阻达成。现今的技术借由移动漏极区,使其更进一步远离源极区,以增加阻抗路径的电阻,但会增加LDMOS元件40的尺寸,这方法并不理想。相较佳下,图9所揭示的实施例提供增加阻抗路径电阻的优点,而没有增加LDMOS元件的尺寸。
图2-图9上述讨论的实施例亦提供其它的优点,可以理解的是不同的实施例可提供不同的优点,且不需要所有实施例均具有特定的优点。其一优点是:如以上配合图4和图5所讨论的,本实施例使用虚设栅极放宽现今技术严格的迭对需求。本实施例的另一优点是制造工艺相容于传统的高介电常数金属栅极取代栅极制造工艺,因此实行本实施例并不需要额外的花费。
图10显示图1方法11另一“后栅极”实施例的剖面示意图。在“后栅极”的实施例中,栅极介电层80、81包括高介电常数材料,且其在移除栅电极层90、91形成沟槽后不须被移除,因此在此实施例中不需要形成高介电常数栅极介电层190、191(图9)。在移除栅电极层90、91之后,形成导电层200、210于沟槽中,且沟槽外的材料之后在一化学机械研磨制造工艺(CMP)中被移除。栅极结构220A是借由栅极介电层80和导电层200、210形成,且虚设栅极结构221A是借由栅极介电层81和导电层201、211形成。类似于上述图2-10讨论的“高介电常数在后”实施例,虚设栅极结构221A包括其下的空乏区240,且其具有类似的优点。
可理解的是,本发明尚可进行额外的制造工艺以完成LDMOS元件40的制作。举例来说,此额外的制造工艺可包括沉积保护层、形成接点、形成内连线结构(例如导线、插塞、金属层和内层介电层,以提供上述LDMOS元件的电性连接)。为简化说明,上述额外的制造工艺不在此描述。
虽然本发明已揭示优选实施例如上,然其并非用以限定本发明,任何熟悉本领域的普通技术人员,在不脱离本发明的精神和范围内,当可做些许更动与润饰,因此本发明的保护范围当视所附的权利要求所界定的范围为准。
Claims (10)
1.一种半导体元件,包括一晶体管,该晶体管包括:
一基底;
一第一阱和一第二阱,设置于该基底中,该第一和第二阱掺杂不同型态的掺杂物;
一第一栅极,至少部分设置于该第一阱上方;
一第二栅极,设置于该第二阱上方;及
一源极区和一漏极区,分别设置于该第一和第二阱中,该源极区和漏极区掺杂相同型态的掺杂物。
2.如权利要求1所述的半导体元件,其中该源极区和该第二栅极设置于该第一栅极的相反边,且其中该漏极区和该第一栅极设置于该第二栅极的相反边。
3.如权利要求1项所述的半导体元件,其中该第一栅极部分设置于该第二阱上方。
4.如权利要求1所述的半导体元件,其中每个第一和第二栅极均包括一栅极堆叠和形成于该栅极堆叠两侧的栅极间隙壁,其中该源极区对准该第一栅极其中一个栅极间隙壁,该漏极区对准该第二栅极其中一个栅极间隙壁。
5.如权利要求1所述的半导体元件,其中该晶体管是侧向扩散金属氧化物半导体场效晶体管。
6.如权利要求1所述的半导体元件,还包括设置于该第二栅极下的一空乏区,其中该空乏区的尺寸和该第二栅极的材料组成相关。
7.一种半导体元件,包括一晶体管,该晶体管包括:
一基底;
一第一阱和一第二阱,设置于该基底中,该第一和第二阱具有相反的掺杂极性;
一第一栅极和一第二栅极,分别设置于该第一阱和该第二阱上方,该第一和第二栅极以一间隔分开;及
一源极区和一漏极区,分别设置于该第一和第二阱中,该源极区和漏极区具有相同的掺杂极性;
其中该第一栅极设置于该源极区和该间隔之间,其中该第二栅极设置于该漏极区和该间隔之间。
8.如权利要求7所述的半导体元件,其中该第一栅极部分设置于该第二阱上方,且每个第一和第二栅极均包括一栅极堆叠和形成于该栅极堆叠两侧的栅极间隙壁,其中该源极区对准该第一栅极其中一个栅极间隙壁,该漏极区对准该第二栅极其中一个栅极间隙壁。
9.如权利要求8所述的半导体元件,其中该第一栅电极包括一第一型态的功函数金属,该第二栅电极包括一与该第一型态相反的第二型态的功函数金属,且其中该晶体管还包括一设置于该第二栅极下的空乏区,其中该空乏区的尺寸和该第二栅电极的功函数金属的材料组成相关。
10.一种半导体元件的制作方法,包括:
提供一基底;
形成一第一阱和一第二阱于该基底中,该第一和第二阱掺杂不同型态的掺杂物;
形成一第一栅极,至少部分位于该第一阱上方;
形成一第二栅极于该第二阱上方;及
分别于该第一和第二阱中形成一源极区和一漏极区,该源极区和漏极区掺杂相同型态的掺杂物。
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