CN116266556A - 半导体元件及其制作方法 - Google Patents

半导体元件及其制作方法 Download PDF

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Publication number
CN116266556A
CN116266556A CN202111550730.5A CN202111550730A CN116266556A CN 116266556 A CN116266556 A CN 116266556A CN 202111550730 A CN202111550730 A CN 202111550730A CN 116266556 A CN116266556 A CN 116266556A
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top surface
dielectric layer
voltage region
gate dielectric
gate electrode
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许智凯
傅思逸
林毓翔
林建廷
邱淳雅
许嘉榕
陈金宏
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to CN202111550730.5A priority Critical patent/CN116266556A/zh
Priority to US17/586,699 priority patent/US20230197523A1/en
Publication of CN116266556A publication Critical patent/CN116266556A/zh
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Abstract

本发明公开一种半导体元件及其制作方法，其中该制作半导体元件的方法为主要先提供具有高压区、中压区以及低压区的基底，然后形成第一晶体管于高压区以及第二晶体管于低压区。其中第一晶体管包含第一基座设于基底上、第一栅极介电层设于第一基座上以及第一栅极电极设于第一栅极介电层上。第二晶体管则包含一鳍状结构设于基底上以及第二栅极电极设于鳍状结构上，其中第一栅极介电层顶表面切齐鳍状结构顶表面。

Description

半导体元件及其制作方法
技术领域
本发明涉及一种制作半导体元件的方法，尤其是涉及一种整合高压元件、中压元件以及低压元件的方法。
背景技术
以目前的半导体技术水准，业界已能将控制电路、存储器、低压操作电路以及高压操作电路及元件同时整合制作在单一芯片上，由此降低成本，同时提高操作效能，其中如垂直扩散金属氧化物半导体(vertical double-diffusion metal-oxide-semiconductor,VDMOS)、绝缘栅极双载流子晶体管(insulated gate bipolar transistor,IGBT)以及横向扩散金属氧化物半导体(lateral-diffusion metal-oxide-semiconductor,LDMOS)等制作在芯片内的高压元件，由于具有较佳的切换效率(power switching efficiency)，因此又较常被应用。如本领域技术人员所知，前述的高压元件往往被要求能够承受较高的击穿电压，并且能在较低的阻值下操作。
另外随着元件尺寸持续地缩小，现有平面式(planar)场效晶体管元件的发展已面临制作工艺上的极限。为了克服制作工艺限制，以非平面(non-planar)的场效晶体管元件，例如鳍状场效晶体管(fin field effect transistor,Fin FET)元件来取代平面晶体管元件已成为目前的主流发展趋势。由于鳍状场效晶体管元件的立体结构可增加栅极与鳍状结构的接触面积，因此，可进一步增加栅极对于载流子沟道区域的控制，从而降低小尺寸元件面临的漏极引发能带降低(drain induced barrier lowering,DIBL)效应，并可以抑制短沟道效应(short channel effect,SCE)。再者，由于鳍状场效晶体管元件在同样的栅极长度下会具有更宽的沟道宽度，因而可获得加倍的漏极驱动电流。甚而，晶体管元件的临界电压(threshold voltage)也可通过调整栅极的功函数而加以调控。
然而随着元件尺寸持续缩小下现行高压元件与低压元件如鳍状结构场效晶体管的整合上仍存在许多挑战，例如漏电流以及击穿电压的控制等等。因此，如何改良现有高压元件架构即为现今一重要课题。
发明内容
本发明一实施例公开一种制作半导体元件的方法，其主要先提供具有高压区、中压区以及低压区的基底，然后形成第一晶体管于高压区以及第二晶体管于低压区。其中第一晶体管包含第一基座设于基底上、第一栅极介电层设于第一基座上以及第一栅极电极设于第一栅极介电层上。第二晶体管则包含一鳍状结构设于基底上以及第二栅极电极设于鳍状结构上，其中第一栅极介电层顶表面切齐鳍状结构顶表面。
本发明另一实施例公开一种半导体元件，其主要包含一基底具有高压区、中压区以及低压区，第一晶体管设于高压区以及第二晶体管设于低压区。其中第一晶体管包含第一基座设于基底上、第一栅极介电层设于第一基座上以及第一栅极电极设于第一栅极介电层上。第二晶体管则包含一鳍状结构设于基底上以及第二栅极电极设于鳍状结构上，其中第一栅极介电层顶表面切齐鳍状结构顶表面。
附图说明
图1至图11为本发明一实施例制作半导体元件的方法示意图。
主要元件符号说明
12:基底
14:高压区
16:中压区
18低压区
20:基座
22:基座
24:鳍状结构
26:衬垫层
28:衬垫层
30:硬掩模
32:绝缘层
34:掺杂区
36:硬掩模
38:图案化掩模
40:凹槽
42:栅极介电层
44:硬掩模
46:图案化掩模
48:栅极介电层
50:浅沟隔离
52:栅极介电层
54:栅极结构
56:栅极结构
58:栅极结构
60:栅极材料层
62:硬掩模
64:硬掩模
66:栅极电极
68:外延层
70:源极/漏极区域
72:静电放电保护环
74:层间介电层
76:高介电常数介电层
78:功函数金属层
80:低阻抗金属层
82:硬掩模
84:接触插塞
114:高压元件
116:中压元件
118:低压元件
具体实施方式
请参照图1至图11，图1至图11为本发明一实施例制作半导体元件的方法示意图，其中图1为本发明一实施例制作半导体元件的上视图，图2至图11则为图1中沿着切线AA’、切线BB’以及切线CC’方向制作半导体元件的剖面示意图。如图1至图2所示，首先提供一基底12，例如一硅基底或硅覆绝缘(SOI)基板，其上定义有三个或三个以上的晶体管区，例如包括一高压区14、一中压区16以及一低压区18，其中高压区14中设有高压元件114，中压区16中设有中压元件116，且低压区18中设有低压元件118，且图2至图11较佳为沿着图1高压区14中切线AA’、中压区14中切线BB’以及低压区18中切线CC’方向制作半导体元件的方法示意图。在本实施例中，高压区14、中压区16以及低压区18可包含相同导电型式或不同导电型式的晶体管区，例如各为PMOS晶体管区以及/或NMOS晶体管区，且三个区域分别预定为后续制作不同临界电压(threshold voltage)的栅极结构。在本实施例中可先选择于高压区14与中压区16中利用离子注入制作工艺形成P型深阱区并于低压区18中形成N型深阱区，但各区域的导电型式均不局限于此。
然后于高压区14与中压区16的基底12上各形成基座20、22以及于低压区18的基底上形成多个鳍状结构24。依据本发明的优选实施例，基座20、22与鳍状结构24较佳通过侧壁图案转移(sidewall image transfer,SIT)技术制得，其程序大致包括：提供一布局图案至计算机系统，并经过适当地运算以将相对应的图案定义于光掩模中。后续可通过光刻及蚀刻制作工艺，以形成多个等距且等宽的图案化牺牲层或轴心体(mandrel)于基底上，使其个别外观呈现条状。之后依序施行沉积及蚀刻制作工艺，以于图案化牺牲层的各侧壁形成间隙壁。继以去除图案化牺牲层，并在间隙壁的覆盖下施行蚀刻制作工艺，使得间隙壁所构成的图案被转移至基底内，再伴随鳍状结构切割制作工艺(fin cut)而获得所需的图案化结构，例如条状图案化鳍状结构。
除此之外，基座20、22与鳍状结构24的形成方式又可包含先形成一图案化掩模(图未示)于基底12上，再经过一蚀刻制作工艺，将图案化掩模的图案转移至基底12中以形成基座20、22与鳍状结构24。另外，基座20、22与鳍状结构24的形成方式另也可以是先制作一图案化硬掩模层(图未示)于基底12上，并利用外延制作工艺于暴露出于图案化硬掩模层的基底12上成长出例如包含硅锗的半导体层，而此半导体层即可作为相对应的基座20、22与鳍状结构24。这些形成基座20、22与鳍状结构24的实施例均属本发明所涵盖的范围。
在本实施例中，各基座20、22与鳍状结构24顶表面可于上述图案化过中设有一衬垫层26、一衬垫层28以及一硬掩模30于基底12上，其中衬垫层26较佳包含氧化硅，衬垫层28较佳包含氮化硅，硬掩模30较佳包含氧化硅，但均不局限于此。
然后如图3所示，进行一可流动式化学气相沉积(flowable chemical vapordeposition,FCVD)制作工艺形成一由氧化硅所构成的绝缘层32于基座20、22与鳍状结构24上并填满基座20、22与鳍状结构24之间的凹槽，再进行一平坦化制作工艺例如利用化学机械研磨(chemical mechanical polishing,CMP)去除硬掩模30使衬垫层28顶表面切齐绝缘层32顶表面。
随后如图4所示，先利用蚀刻去除由氮化硅所构成的衬垫层28暴露出下方由氧化硅所构成的衬垫层26，使两侧的绝缘层32顶表面略为高于衬垫层26顶表面并同时形成凹槽(图未示)于衬垫层26正上方，然后进行一离子注入制作工艺于高压区14的基座20两侧内形成掺杂区34，其中掺杂区34较佳作为后续高压元件114的轻掺杂漏极。接着形成一硬掩模36于高压区14、中压区16以及低压区18的基座20、22、鳍状结构24以及绝缘层32上并填满衬垫层26上方的凹槽。在本实施例中硬掩模36较佳包含氮化硅，但不局限于此。
随后如图5所示，先形成一图案化掩模38例如图案化光致抗蚀剂于中压区16与低压区18的硬掩模36上且图案化掩模38具有一开口暴露出高压区14的部分硬掩模36表面，再利用图案化掩模38为掩模进行一蚀刻制作工艺去除高压区14的部分硬掩模36、部分基座20与基座22两侧的部分绝缘层32形成凹槽40。
如图6所示，然后进行一氧化物成长制作工艺或更具体而言一快速热氧化(rapidthermal oxidation,RTO)制作工艺以形成一由氧化硅所构成的栅极介电层42于高压区14的基座20上，再完全去除图案化掩模38与下方的硬掩模36。其中所成长的栅极介电层42两侧仍有部分之前利用图案化掩模所形成的凹槽40，且栅极介电层42顶表面较佳与中压区16与低压区18的绝缘层32顶表面切齐。
接着可形成另一图案化掩模(图未示)例如图案化光致抗蚀剂覆盖高压区14与中压区16的绝缘层32且图案化掩模具有一开口暴露出低压区18的衬垫层26与绝缘层32顶表面，进行一离子注入制作工艺将掺质注入低压区18的鳍状结构24内调整元件的临界电压(threshold voltage)，再去除图案化掩模。
随后如图7所示，先全面性形成一由氮化硅所构成的硬掩模44覆盖高压区14、中压区16以及低压区18包括高压区14的栅极介电层42、中压区16的基座24以及低压区18的鳍状结构24上，再形成另一图案化掩模46例如图案化光致抗蚀剂覆盖高压区14与低压区16的绝缘层32，且图案化掩模46具有一开口暴露出中压区16的硬掩模44。紧接着利用图案化掩模46为掩模进行一蚀刻制作工艺去除中压区16的硬掩模44、部分绝缘层32、衬垫层26甚至部分基座22并暴露出基座22表面。
然后如图8所示，先进行另一氧化物成长制作工艺例如一快速热氧化(rapidthermal oxidation,RTO)制作工艺以形成一由氧化硅所构成的栅极介电层48于中压区16的基座22上，其中中压区16的栅极介电层48顶表面较佳切齐高压区14的栅极介电层42顶表面同时高压区14的栅极介电层42厚度较佳大于中压区16的栅极介电层48厚度。在本实施例中高压区14的栅极介电层42厚度可约中压区16的栅极介电层48厚度两倍以上例如三倍、四倍甚至五倍。
接着去除原本设于高压区14、中压区16以及低压区18的图案化掩模46与剩余的硬掩模44，再进行一蚀刻制作工艺完全去除低压区14鳍状结构24顶部的衬垫层26并暴露出鳍状结构24顶表面以及去除高压区14、中压区16以及低压区18部分绝缘层32，使剩余的绝缘层32顶表面略低于高压区14与中压区16的基座20、22以及低压区18的鳍状结构24顶表面形成浅沟隔离(shallow trench isolation,STI)50。需注意的是，在本阶段高压区14的栅极介电层42顶表面较佳切齐中压区16的栅极介电层48顶表面以及低压区18的鳍状结构24顶表面。
如图9所示，随后进行一氧化制作工艺例如现场蒸气成长制作工艺(in-situsteam generation,ISSG)制作工艺形成一由氧化硅所构成的栅极介电层52于低压区18的鳍状结构24表面。接着可于高压区14、中压区16以及低压区18的基座20、22与鳍状结构24上分别形成栅极结构54、56、58或虚置栅极。在本实施例中，栅极结构54、56、58的制作方式可依据制作工艺需求以先栅极(gate first)制作工艺、后栅极(gate last)制作工艺的先高介电常数介电层(high-k first)制作工艺或后栅极制作工艺的后高介电常数介电层(high-k last)制作工艺等方式制作完成。以本实施例的后高介电常数介电层制作工艺为例，可先依序形成一由多晶硅所构成的栅极材料层60、一由氮化硅所构成的硬掩模62、一由氧化硅所构成的硬掩模64于各区域的栅极介电层42、48、52上，并利用一图案化光致抗蚀剂(图未示)当作掩模进行一图案转移制作工艺，以单次蚀刻或逐次蚀刻步骤，去除部分硬掩模62、64、部分栅极材料层60甚至中压区16的部分栅极介电层48，然后剥除图案化光致抗蚀剂，以于各区域的基底12上个别形成由栅极介电层42、48、52与图案化的栅极材料层60所构成的栅极结构54、56、58，其中图案化的栅极材料层60较佳成为各区域的栅极电极66。
随后分别在栅极结构54、56、58侧壁形成至少一间隙壁(图未示)。在本实施例中，间隙壁可为单一间隙壁或复合式间隙壁，例如可细部包含一偏位间隙壁(图未示)以及一主间隙壁(图未示)，偏位间隙壁与主间隙壁较佳包含不同材料，且两者均可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组，但不局限于此。
请继续参照图10，图10为本发明一实施例沿着图1高压区14中切线AA’、中压区14中切线BB’以及低压区18中切线DD’方向制作半导体元件的方法示意图。如图10所示，可先形成一图案化掩模(图未示)如图案化光致抗蚀剂覆盖高压区14与中压区16，再进行一干蚀刻及/或湿蚀刻制作工艺，利用低压区18的栅极结构58与间隙壁为蚀刻掩模，沿着间隙壁向下单次或多次蚀刻基底12，以于栅极结构58两侧的基底12中形成凹槽(图未示)。接着进行一选择性外延成长(selective epitaxial growth,SEG)制作工艺，以于凹槽中形成外延层68。需注意的是，本实施例仅于低压区18的栅极结构58两侧形成外延层68但高压区14与中压区16则较佳不形成任何外延层。另外低压区18的硬掩模64可于形成凹槽时被部分去除，使低压区18的硬掩模64顶表面略低于高压区14与中压区16的硬掩模64顶表面。
从图10的剖面来看，低压区18的外延层68较佳与凹槽具有相同的截面形状，如圆弧、六边形(hexagon；又称sigmaΣ)或八边形(octagon)的截面形状，但也可以是其他截面形状。在本发明优选实施例中，外延层68根据不同的金属氧化物半导体(MOS)晶体管类型而可以具有不同的材质，举例来说，若该金属氧化物半导体晶体管为一P型晶体管(PMOS)时，外延层68可选择包含硅化锗(SiGe)、硅化锗硼(SiGeB)或硅化锗锡(SiGeSn)。而在本发明另一实施例中，若该金属氧化物半导体晶体管为一N型晶体管(NMOS)时，外延层68可选择包含碳化硅(SiC)、碳磷化硅(SiCP)或磷化硅(SiP)。此外，选择性外延制作工艺可以用单层或多层的方式来形成，且其异质原子(例如锗原子或碳原子)也可以渐层的方式改变，但较佳是使外延层68的表面较淡或者无锗原子，以利后续金属硅化物层的形成。
随后可先利用光刻及蚀刻制作工艺去除中压区16的部分栅极介电层48暴露出栅极结构56两侧的基座22顶表面，再进行一道或一道以上离子注入制作工艺，分别于高压区14与中压区16栅极结构54、56两侧的基座20、22内形成源极/漏极区域70，以及于高压区14中高压晶体管外围的基座20内形成掺杂区作为静电放电保护环72，其中高压区14中的源极/漏极区域70与静电放电保护环72较佳包含不同导电型式的掺质，例如一者包含N型掺质另一者则包含P型掺质。
依据本发明一实施例，又可选择性于低压区18中外延层68的一部分或全部形成源极/漏极区域70。在一实施例中，低压区18中源极/漏极区域70的形成也可同步(in-situ)于选择性外延成长制作工艺进行，例如金属氧化物半导体是PMOS时，形成硅化锗外延层、硅化锗硼外延层或硅化锗锡外延层，可以伴随着注入P型掺质；或是当金属氧化物半导体是NMOS时，形成硅化碳外延层、硅化碳磷外延层或硅化磷外延层，可以伴随着注入N型掺质。由此可省略后续利用额外离子注入步骤形成P型/N型晶体管的源极/漏极区域70。此外在另一实施例中，源极/漏极区域70的掺质也可以渐层的方式形成。
然后如图11所示，可选择性形成一由氮化硅所构成的接触洞蚀刻停止层(contactetch stop layer,CESL)(图未示)于基底12上并覆盖高压区14、中压区16以及低压区18的栅极结构54、56、58，再形成一层间介电层74于接触洞蚀刻停止层上。接着进行一平坦化制作工艺，例如利用化学机械研磨(chemical mechanical polishing,CMP)去除部分层间介电层74及部分接触洞蚀刻停止层使硬掩模64上表面与层间介电层74上表面齐平。
随后进行一金属栅极置换制作工艺将高压区14、中压区16以及低压区18的各栅极结构54、56、58转换为金属栅极。例如可先进行一选择性的干蚀刻或湿蚀刻制作工艺，例如利用氨水(ammonium hydroxide,NH4OH)或氢氧化四甲铵(TetramethylammoniumHydroxide,TMAH)等蚀刻溶液来去除硬掩模62、64以及栅极结构54、56、58中的栅极材料层60以于层间介电层74中形成凹槽(图未示)。之后依序形成一高介电常数介电层76以及至少包含功函数金属层78与低阻抗金属层80的导电层于凹槽内，并再搭配进行一平坦化制作工艺使U型高介电常数介电层76、U型功函数金属层78与低阻抗金属层80的表面与层间介电层74表面齐平，其中高介电常数介电层76、功函数金属层78与低阻抗金属层80较佳一同各晶体管或各元件的栅极电极66。
在本实施例中，高介电常数介电层76包含介电常数大于4的介电材料，例如选自氧化铪(hafnium oxide,HfO2)、硅酸铪氧化合物(hafnium silicon oxide,HfSiO4)、硅酸铪氮氧化合物(hafnium silicon oxynitride,HfSiON)、氧化铝(aluminum oxide,Al2O3)、氧化镧(lanthanum oxide,La2O3)、氧化钽(tantalum oxide,Ta2O5)、氧化钇(yttrium oxide,Y2O3)、氧化锆(zirconium oxide,ZrO2)、钛酸锶(strontium titanate oxide,SrTiO3)、硅酸锆氧化合物(zirconium silicon oxide,ZrSiO4)、锆酸铪(hafnium zirconium oxide,HfZrO4)、锶铋钽氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、锆钛酸铅(leadzirconate titanate,PbZrxTi1-xO3,PZT)、钛酸钡锶(barium strontium titanate,BaxSr1- xTiO3,BST)、或其组合所组成的群组。
功函数金属层78较佳用以调整形成金属栅极的功函数，使其适用于N型晶体管(NMOS)或P型晶体管(PMOS)。若晶体管为N型晶体管，功函数金属层78可选用功函数为3.9电子伏特(eV)～4.3eV的金属材料，如铝化钛(TiAl)、铝化锆(ZrAl)、铝化钨(WAl)、铝化钽(TaAl)、铝化铪(HfAl)或TiAlC(碳化钛铝)等，但不以此为限；若晶体管为P型晶体管，功函数金属层78可选用功函数为4.8eV～5.2eV的金属材料，如氮化钛(TiN)、氮化钽(TaN)或碳化钽(TaC)等，但不以此为限。功函数金属层78与低阻抗金属层80之间可包含另一阻障层(图未示)，其中阻障层的材料可包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等材料。低阻抗金属层80则可选自铜(Cu)、铝(Al)、钨(W)、钛铝合金(TiAl)、钴钨磷化物(cobalttungsten phosphide，CoWP)等低电阻材料或其组合。由于依据金属栅极置换制作工艺将虚置栅极转换为金属栅极是本领域技术人员所熟知技术，在此不另加赘述。接着可去除部分高介电常数介电层76、部分功函数金属层78与部分低阻抗金属层80形成凹槽(图未示)，然后再填入一硬掩模82于凹槽内并使硬掩模82与层间介电层74表面齐平，其中硬掩模82可选自由氧化硅、氮化硅、氮氧化硅以及氮碳化硅所构成的群组。
之后可进行一图案转移制作工艺，例如可利用一图案化掩模去除栅极结构54、56、58旁的部分的层间介电层74以及部分接触洞蚀刻停止层以形成多个接触洞(图未示)并暴露出源极/漏极区域70。然后再于各接触洞中填入所需的金属材料，例如包含钛(Ti)、氮化钛(TiN)、钽(Ta)、氮化钽(TaN)等的阻障层材料以及选自钨(W)、铜(Cu)、铝(Al)、钛铝合金(TiAl)、钴钨磷化物(cobalt tungsten phosphide，CoWP)等低电阻材料或其组合的低阻抗金属层。之后进行一平坦化制作工艺，例如以化学机械研磨去除部分金属材料以分别形成接触插塞84于各接触洞内电连接源极/漏极区域70。至此即完成本发明优选实施例一半导体元件的制作。
请再参照图1与图11，图1与图11又分别公开本发明一实施例的一半导体元件的结构示意图。如图1与图11所示，半导体元件主要包含一基底12具有高压区14、中压区16以及低压区18，高压元件114设于高压区14，中压元件116设于中压区16以及低压元件118设于低压区18，静电放电保护环72环绕高压元件114以及浅沟隔离50环绕高压元件114、中压元件116以及低压元件118。其中高压元件114包含基座20设于基底12上、栅极介电层42设于基座20上、由高介电常数介电层76、功函数金属层78与低阻抗金属层80所构成的栅极电极66设于栅极介电层42上以及源极/漏极区域70设于栅极电极66两侧的基座20内。
中压元件116包含基座22设于基底12上、栅极介电层48设于基座20上、由高介电常数介电层76、功函数金属层78与低阻抗金属层80所构成的栅极电极66设于栅极介电层48上以及源极/漏极区域70设于栅极电极66两侧的基座22内。低压元件118则包含多个鳍状结构24设于基底12、栅极介电层52设于鳍状结构24上、由高介电常数介电层76、功函数金属层78与低阻抗金属层80所构成的栅极电极66设于栅极介电层52上以及源极/漏极区域70设于栅极电极66两侧的鳍状结构24或基底12内。
从细部来看，高压区14的栅极电极66顶表面较佳切齐中压区16与低压区18的栅极电极66顶表面，高压区14的栅极介电层42顶表面较佳切齐中压区16的栅极介电层48顶表面与低压区18的鳍状结构24顶表面，低压区18的栅极介电层52顶表面可略高于高压区14的栅极介电层42顶表面与中压区16的栅极介电层48顶表面，高压区14的源极/漏极区域70顶表面切齐低压区18的鳍状结构24顶表面，且静电放电保护环72顶表面切齐源极/漏极区域70顶表面。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (17)

1.一种制作半导体元件的方法，其特征在于，包含：
提供基底包含高压区、中压区以及低压区；
形成高压元件于该高压区，该高压元件包含：
第一基座，设于该基底上；
第一栅极介电层，设于该第一基座上；以及
第一栅极电极，设于该第一栅极介电层上；
形成低压元件于该低压区，该低压元件包含：
鳍状结构，设于该基底上；以及
第二栅极电极，设于该鳍状结构上，其中该第一栅极介电层顶表面切齐该鳍状结构顶表面。
2.如权利要求1所述的方法，其中该第一栅极电极顶表面切齐该第二栅极电极顶表面。
3.如权利要求1所述的方法，另包含：
形成该第一基座于该高压区、第二基座于该中压区以及该鳍状结构于该低压区；
形成绝缘层环绕该第一基座、该第二基座以及该鳍状结构；
去除部分该第一基座；
形成该第一栅极介电层于该第一基座上；
形成第二栅极介电层于该第二基座上；
去除该绝缘层以形成浅沟隔离；
形成第三栅极介电层于该鳍状结构上；
形成该第一栅极电极于该第一栅极介电层上、该第二栅极电极于该第三栅极介电层上以及第三栅极电极于该第二栅极介电层上；
形成第一源极/漏极区域于该第一栅极电极旁；以及
形成第二源极/漏极区域于该第二栅极电极旁。
4.如权利要求3所述的方法，其中该第一栅极介电层顶表面切齐该第二栅极介电层顶表面。
5.如权利要求3所述的方法，其中该第一栅极电极顶表面切齐该第三栅极电极顶表面。
6.如权利要求3所述的方法，其中该第一源极/漏极区域顶表面切齐该鳍状结构顶表面。
7.如权利要求3所述的方法，另包含形成一静电放电保护环环绕该高压元件。
8.如权利要求7所述的方法，其中该静电放电保护环顶表面切齐该第一源极/漏极区域顶表面。
9.一种半导体元件，其特征在于，包含：
基底包含高压区、中压区以及低压区；
高压元件设于该高压区，该高压元件包含：
第一基座，设于该基底上；
第一栅极介电层，设于该第一基座上；以及
第一栅极电极，设于该第一栅极介电层上；
低压元件设于该低压区，该低压元件包含：
鳍状结构，设于该基底上；以及
第二栅极电极，设于该鳍状结构上，其中该第一栅极介电层顶表面切齐该鳍状结构顶表面。
10.如权利要求9所述的半导体元件，其中该第一栅极电极顶表面切齐该第二栅极电极顶表面。
11.如权利要求9所述的半导体元件，其中该高压元件包含源极/漏极区域设于该第一栅极电极旁，且该源极/漏极区域顶表面切齐该鳍状结构顶表面。
12.如权利要求11所述的半导体元件，另包含浅沟隔离设于该第一基座与该源极/漏极区域之间。
13.如权利要求11所述的半导体元件，另包含形成静电放电保护环环绕该高压元件。
14.如权利要求13所述的半导体元件，其中该静电放电保护环顶表面切齐该源极/漏极区域顶表面。
15.如权利要求9所述的半导体元件，另包含中压元件设于该中压区，该中压元件包含：
第二基座，设于该基底上；
第二栅极介电层，设于该第二基座上；以及
第三栅极电极，设于该第二栅极介电层上。
16.如权利要求15所述的半导体元件，其中该第二栅极介电层顶表面切齐该第一栅极介电层顶表面。
17.如权利要求15所述的半导体元件，其中该第一栅极电极顶表面切齐该第三栅极电极顶表面。
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