TWI509710B - 具有改良之閘極高度均勻性的半導體裝置及其製造方法 - Google Patents

具有改良之閘極高度均勻性的半導體裝置及其製造方法 Download PDF

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TWI509710B
TWI509710B TW101137887A TW101137887A TWI509710B TW I509710 B TWI509710 B TW I509710B TW 101137887 A TW101137887 A TW 101137887A TW 101137887 A TW101137887 A TW 101137887A TW I509710 B TWI509710 B TW I509710B
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Ruilong Xie
Xiuyu Cai
Andy C Wei
Robert Miller
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Globalfoundries Us Inc
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Description

具有改良之閘極高度均勻性的半導體裝置及其製造方法
本揭示內容大體有關於半導體裝置及半導體裝置之製造方法，且更特別的是，有關於具有改良之閘極高度均勻性的半導體裝置以及具有改良之閘極高度均勻性之半導體裝置的製造方法。
隨著技術節點縮短，有些積體電路設計一直企圖排除使用多晶矽閘極以及用減少的特徵尺寸來改善裝置效能。解決方案之一是用金屬閘極結構取代多晶矽閘極結構。取代金屬閘極結構(replacement metal gate structure)可提供優異的Tinv (反轉層厚度)-Vt (臨界電壓)效能。不過，習知製造方法難以控制取代金屬閘極結構高度。具體言之，多個間隔體蝕刻和源極/汲極預磊晶清洗製程(pre epi clean proces)導致覆蓋臨時多晶矽閘極的硬遮罩有厚度差異。習知上，在取代金屬閘極製備期間，硬遮罩係用作平坦化製程的終止物(stop)。因此，硬遮罩厚度的變異導致取代金屬閘極結 構高度的變異。最好排除取代金屬閘極結構高度的變異以改善裝置效能。
此外，隨著閘極間距減少，閘極與接觸栓塞(contact plug)之間的寄生電容分量變得愈來愈重要。因此，最好在閘極與接觸件之間實現較低的K介電值以減少電容。
因此，最好提供具有均勻高度之金屬閘極結構的半導體裝置以及具有均勻高度之金屬閘極結構的半導體裝置製造方法。此外，最好提供寄生電容減少之半導體裝置及其製造方法。此外，閱讀以下結合附圖的【實施方式】及【申請專利範圍】的詳細說明和以上【技術領域】及【先前技術】可明白其他合意的特徵及特性。
提供數種半導體裝置及其製造方法。根據一個具體實施例，半導體裝置之製造方法包括下列步驟：在半導體表面上形成包含多晶矽閘極及帽蓋的臨時閘極結構。形成間隔體於該臨時閘極結構四周。移除該帽蓋與該間隔體之一部份。沉積覆於該多晶矽閘極上的均勻內襯(uniform liner)。該方法移除覆於該多晶矽閘極上之該均勻內襯的一部份以及該多晶矽閘極以形成閘極溝槽。然後，在該閘極溝槽中形成取代金屬閘極。
在另一具體實施例中，提供半導體裝置之製造方法，其係包括在半導體表面上形成數個臨時閘極結構。該方法更包括在該等臨時閘極結構四周形成主動區。移除覆於該等臨時閘極結構上及毗鄰該等臨時閘極結構的材料以暴露 該等臨時閘極結構。然後，沉積覆於該等臨時閘極結構上的均勻內襯。在該均勻內襯上面沉積絕緣體材料。平坦化該絕緣體材料至該均勻內襯以暴露覆於該等臨時閘極結構上之該均勻內襯的數個部份。移除該均勻內襯的暴露部份與該臨時閘極結構以形成數個閘極溝槽。然後，在該等閘極溝槽中形成取代金屬閘極。
根據另一具體實施例，提供一種半導體裝置，其係包含半導體基板與形成於該半導體基板上的數個取代金屬閘極結構。該等取代金屬閘極結構有均勻高度及側面。安置與該等取代金屬閘極結構之側面毗鄰的間隔體。每個間隔體包含頂部與底部。每個頂部由均勻的氮化物內襯形成以及有頂厚度，以及每個底部有大於該頂厚度的底厚度。
10‧‧‧半導體裝置
12‧‧‧半導體基板
16‧‧‧P型通道場效電晶體(PFET)區
18‧‧‧N型通道FET(NFET)區
20‧‧‧臨時閘極氧化物層
22‧‧‧臨時多晶矽層、臨時多晶矽閘極、多晶矽閘極
24‧‧‧臨時覆蓋層、覆蓋層
30‧‧‧PFET臨時閘極結構、PFET多晶矽閘極結構
32‧‧‧NFET臨時閘極結構、NFET多晶矽閘極結構
34‧‧‧過渡臨時閘極結構
38‧‧‧層
40‧‧‧遮罩
44‧‧‧PFET間隔體
48‧‧‧PFET主動區
52‧‧‧層
54‧‧‧遮罩
56‧‧‧NFET間隔體
60‧‧‧NFET主動區
62‧‧‧間隔體層
66‧‧‧絕緣體層
70‧‧‧均勻內襯
72‧‧‧附加內襯
76‧‧‧絕緣體層
80‧‧‧絕緣體層
84‧‧‧閘極溝槽
88‧‧‧取代金屬閘極結構
92‧‧‧層間電介質材料
94‧‧‧通孔溝槽
96‧‧‧接觸栓塞
97‧‧‧間隔體
98‧‧‧下半部
99‧‧‧上半部
以下用附圖描述具有改良之取代金屬閘極結構高度均勻性的半導體裝置之具體實施例以及該等半導體裝置的製造方法，其中類似的元件用相同的元件符號表示。
第1圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第2圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第3圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第4圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟； 第5圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第6圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第7圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第8圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第9圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第10圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第11圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第12圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第13圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第14圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第15圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；第16圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟；以及 第17圖以橫截面圖示部份半導體裝置以及製造半導體裝置的方法步驟。
以下的詳細說明在本質上只是用來示範說明而非旨在限制如本發明申請專利範圍所述之半導體裝置或該等半導體裝置的製造方法。此外，希望不受【技術領域】、【先前技術】、或【發明內容】或以下【實施方式】之中明示或暗示的理論約束。
根據本文的各種具體實施例，提供有具改良閘極高度均勻性之取代金屬閘極結構的半導體裝置以及具改良閘極高度均勻性之半導體裝置的製造方法。在一示範具體實施例中，該半導體裝置製造方法包括由臨時閘極結構移除包含內襯及帽蓋的硬遮罩層以暴露多晶矽閘極。在習知方法中，硬遮罩層在經歷各種蝕刻製程後有可變厚度。在此，在移除可變的硬遮罩層後，沉積均勻內襯於多晶矽閘極上面。隨後的平坦化步驟用該均勻內襯作為終止物。由於均勻內襯在平坦化之前不能忍受蝕刻製程而保有實質均勻的厚度。結果，均勻內襯的平坦化及後續蝕刻產生深度實質不變的閘極溝槽，以及隨後，形成於閘極溝槽之中的取代金屬閘極結構有實質均勻的高度。
第1圖至第17圖根據本文的各種具體實施例依序圖示用於製造具有均勻高度之取代金屬閘極結構之半導體裝置的方法。設計及構造半導體裝置的各種步驟為眾所周知，因此，為簡潔起見，本文只簡述或完全省略掉許多習知步 驟而不提供眾所周知的加工細節。此外，應注意，半導體裝置含有數量不同的組件而圖中的單一組件可能代表多個組件。再者，儘管以平面型裝置圖解說明，然而方法及半導體裝置可應用於finFET裝置。
此時翻到第1圖，半導體裝置10的示範製造方法由以下步驟開始：提供其上可形成淺溝槽隔離(STI)結構、源極/汲極區、源極/汲極延伸區、閘極電介質、接觸件、間隔體、硬遮罩層、及其他特徵的半導體基板12。半導體基板12通常為矽晶圓以及包含本技藝所習知的各種摻雜組構(doping configuration)以定義P型通道場效電晶體(PFET)區16和N型通道FET(NFET)區18。半導體基板12也可包含其他初級半導體材料，例如鍺。或者，半導體基板12可包含化合物半導體，例如碳化矽、砷化鎵、砷化銦、銻化銦、或磷化銦。此外，半導體基板12視需要可包含磊晶層(epi layer)，可賦予應變用以增強效能及/或可包含絕緣體上矽(SOI)結構。如圖示，在半導體基板12上沉積臨時閘極氧化物層20。此外，在臨時閘極氧化物層20上面沉積臨時多晶矽層22及臨時覆蓋層24，例如氮化矽。在某些具體實施例中，使硬遮罩層(例如，由氧化矽、氧化鉿或氧化鋁構成約3奈米的薄層)位在臨時多晶矽層22上，亦即，在臨時多晶矽層22與臨時覆蓋層24之間。蝕刻該等層20、22及24(以及任何附加層，例如視需要的硬遮罩層)，例如用反應離子蝕刻法(RIE)，以形成PFET臨時閘極結構30、NFET臨時閘極結構32，以及視需要，形成過渡臨時閘極 結構34。
在該等閘極結構30、32、34形成後；層38沉積於該等閘極結構30、32、34及半導體基板12上面，如第2圖所示。在某些具體實施例中，層38的材料可與覆蓋層24的相同。在第3圖中，通過典型的微影製程(photolithographic process)，形成遮罩40於NFET區18上面。在PFET區16中，蝕刻層38，例如用RIE法，以形成PFET間隔體44。在此蝕刻製程期間，層38厚度可能有點腐蝕，包括覆蓋層24的厚度可能也有點腐蝕，這導致最終閘極結構高度有差異，若是沒有採取以下步驟來克服差異的話。如第3圖所示，層38中覆於覆蓋層24上的部份，以及一部份覆蓋層24已經因蝕刻製程而腐蝕掉。
根據一個具體實施例，如第4圖所示，移除遮罩40以及藉由經由選擇性磊晶製程來成長材料(例如，矽或含矽材料(例如，矽鍺)於半導體基板12上面，形成PFET主動區48。可摻雜或不摻雜磊晶材料。在PFET主動區48形成後，沉積層52於PFET及NFET區16，18上面，如第5圖所示。層52的材料通常與層38的相同，例如氮化矽。然後，通過典型的微影製程步驟形成遮罩54於PFET區16上面，如第6圖所示。然後，蝕刻層38、52，例如用RIE法，以形成NFET間隔體56。在此蝕刻製程期間，層38及52的厚度可能有點腐蝕，包括覆蓋層24的厚度可能也有點腐蝕，這導致最終閘極結構高度有差異，若是沒有採取以下步驟來克服差異的話。如第6圖所示，層38中覆於 覆蓋層24上的部份，以及一部份覆蓋層24已經因蝕刻製程而腐蝕掉。
在第7圖中，移除遮罩54以及例如藉由經由選擇性磊晶製程成長材料(例如，矽或含矽材料，例如Si：C)，形成NFET主動區60於半導體基板12上面。可摻雜或不摻雜磊晶材料。為了利用該等主動區48、60中未摻雜或未充分摻雜的材料，依序沉積及蝕刻間隔體層62(例如，氮化矽(SiN))以形成間隔體於該等閘極結構30、32、34四周，如第8圖所示。在此製程期間，依序執行各區16、18的離子植入製程以提供充分的摻雜給該等主動區48、60。或者，間隔體層62也可為氧化物，在離子植入完成後可移除它。這些製程在現代加工常見因而不需在此詳述。在形成有充分摻雜磊晶材料的該等主動區48、60時，可排除這些步驟。
在第9圖中，沉積絕緣體層66於半導體基板12上面及蝕刻它，如圖示。這可用以下步驟達成：首先用間隙填充材料(如氧化物)過度填充(over-fill)該空間，用化學機械平坦化法(CMP)平坦化該間隙填充材料，以及經由適當的定向蝕刻或濕蝕刻使該間隙填充材料凹回。然後，移除覆蓋層24以及該等層38、52、62之一部份以暴露臨時多晶矽閘極22，如第10圖所示。在有視需要之硬遮罩層位於多晶矽閘極22上的具體實施例中，在覆蓋層24及該等層38、52、62之一部份移除後，硬遮罩層仍會覆蓋多晶矽閘極22。在間隔體及帽蓋材料為SiN的情形下，可用等向性SiN乾蝕刻製程或使用磷酸的濕蝕刻製程來進行蝕刻。由 於誘發厚度差異的層已被移除，閘極結構不再遭受差異，這由第10圖可明白。
第11圖圖示一種在用共形製程(conformal process，例如原子層沉積法(ALD))沉積均勻內襯70(例如，氮化矽)之前移除絕緣體層66的示範方法。或者，絕緣體層66可留下以及可沉積均勻內襯70於絕緣體層66上面。在示範具體實施例中，均勻內襯70的厚度約有3奈米(nm)至約8奈米，以及均勻內襯為K值約有7的氮化矽。第12圖圖示在均勻內襯70正面上形成附加內襯72的視需要步驟。例如，可使用利用氣體團簇離子束沉積法(GCIB)的定向電介質沉積製程以定向形成附加內襯72。在第12圖顯而易見，PFET多晶矽閘極結構30和NFET多晶矽閘極結構32各自與磊晶材料的間隔是用PFET間隔體44(由層38形成)及NFET間隔體56(由層38及52形成)建立，而不是藉由均勻內襯70之垂直部份的厚度。另外，是均勻內襯70及隨後所沉積之材料的電介質常數(K值)對於最終閘極結構與接觸栓塞之間的電容影響最大，而不是PFET間隔體44及NFET間隔體56的K值。
在第13圖中，沉積絕緣體層76(例如，可流動的氧化矽(SiO2 ))於半導體基板12上面，以及加以平坦化至附加內襯72(或至均勻內襯70，如果沒有使用視需要的附加內襯72)。示範絕緣體層76有約5.5或以下的K值。示範平坦化製程使用CMP製程。然後，視需要，可使絕緣體層76陷到附加內襯72(或均勻內襯70)的位準以下，如第14圖 所示。之後，沉積絕緣體層80於絕緣體層76上面以及也加以平坦化至附加內襯72(或均勻內襯70)。在示範具體實施例中，絕緣體層80為用高密度電漿(HDP)沉積法所沉積的氧化物。示範絕緣體層80有約3.9的K值。
在第15圖中，蝕刻該等內襯70、72中在多晶矽閘極22上面的部份，例如，用RIE。在蝕刻該等內襯部份後，蝕刻半導體裝置10的多晶矽閘極22，從而形成閘極溝槽84。在視需要之硬遮罩層仍然覆蓋多晶矽閘極22的具體實施例中，在蝕刻多晶矽閘極22以形成閘極溝槽84之前，移除該硬遮罩層。通過典型的沉積、蝕刻及平坦化步驟，在閘極溝槽84中形成取代金屬閘極結構88。沉積高k值介電材料(例如，二氧化鉿)於在金屬閘極下面的閘極溝槽84內。在第16圖中，沉積層間電介質材料92於半導體基板12上面。然後，形成穿過層間電介質材料92、絕緣體層76及80、和該等內襯72及70至PFET主動區48及NFET主動區60的通孔溝槽(via trench)94，如第17圖所示。然後，沉積金屬於通孔溝槽94內以按需要形成建立至該等主動區48、60之電氣連接的接觸栓塞96。視需要的矽化製程(silicide process)可在第8圖後馬上進行，或在以第17圖描述的步驟，在金屬填充之前穿過通孔溝槽94。
如第17圖所示，半導體裝置10經形成其係具有被有下半部98及上半部99之間隔體97包圍的取代金屬閘極結構88。在上半部99只由均勻內襯70形成時，下半部98由該等層38、52、62形成。結果，下半部98的厚度均大 於上半部99的厚度。例如，該等下半部可有約10奈米至約20奈米的厚度，以及上半部可有約3奈米至約8奈米的厚度。此外，與習知閘極結構加工法不同的是，本發明方法不應用應力內襯(stress liner)，而是應用K值有3.9的正常氧化物膜或k值更低的電介質材料。在各種具體實施例中，該方法可繼續以及包括製程步驟，例如附加層的沉積或成形，附加接觸件及互連結構(例如，線路及通孔)，金屬層，以及層間電介質材料，以提供至含有已成形取代金屬閘極結構88之裝置的電氣互連。
總之，具體實作一種半導體裝置製造方法以形成具有改良高度均勻性的金屬閘極結構。具體言之，該方法由臨時閘極結構移除閘極帽蓋、內襯及間隔體。該等帽蓋、內襯及間隔體已經受導致厚度不均勻的各種蝕刻製程。在移除不均勻的帽蓋、內襯及間隔體後，形成均勻內襯於臨時閘極結構上以及在形成取代金屬閘極結構之前用作平坦化終止物。該均勻平坦化終止物提供高度均勻性給取代金屬閘極結構。此外，寄生電容也減少，從而可改善裝置效能。
描述於本文的製造方法導致半導體裝置的金屬閘極結構具有改良高度均勻性。儘管以上詳細說明已陳述至少一個示範具體實施例，然而應瞭解，仍有有許多變體。也應瞭解，描述於本文的示範具體實施例或實施例並非旨在以任何方式限制本發明的範疇、適用性或組構。反而，上述詳細說明是要讓熟諳此藝者有個方便的發展藍圖用來具體實作該等具體實施例。應瞭解，元件的功能及配置可做出 不同的改變而不脫離由申請專利範圍定義的範疇，此範疇包括在申請本專利申請案時已知及可預見的等效物。
10‧‧‧半導體裝置
38‧‧‧層
48‧‧‧PFET主動區
52‧‧‧層
60‧‧‧NFET主動區
62‧‧‧間隔體層
70‧‧‧均勻內襯
72‧‧‧附加內襯
76‧‧‧絕緣體層
80‧‧‧絕緣體層
88‧‧‧取代金屬閘極結構
92‧‧‧層間電介質材料
94‧‧‧通孔溝槽
96‧‧‧接觸栓塞
97‧‧‧間隔體
98‧‧‧下半部
99‧‧‧上半部

Claims (17)

  1. 一種製造半導體裝置的方法，包括：在半導體基板之表面上形成包含多晶矽閘極及覆蓋層的臨時閘極結構；形成間隔體於該臨時閘極結構四周；移除該覆蓋層以及該間隔體之一部份，其係藉由：沉積間隙填充材料於該半導體基板上方；平坦化該間隙填充材料；回蝕該間隙填充材料，以暴露該覆蓋層及該間隔體之該一部份；以及蝕刻該覆蓋層以及該間隔體的該暴露部份；沉積覆於該多晶矽閘極上的均勻內襯；移除覆於該多晶矽閘極上之該均勻內襯的一部份以及該多晶矽閘極，以形成閘極溝槽；以及在該閘極溝槽中形成取代金屬閘極。
  2. 如申請專利範圍第1項所述之方法，復包括：形成與該間隔體毗鄰的數個主動區；沉積絕緣體於該均勻內襯上方；沉積層間電介質材料於該取代金屬閘極及該絕緣體上方；蝕刻穿過該層間電介質材料、該絕緣體及該內襯的數個通孔，以暴露該等主動區；以及用金屬填充該等通孔，以形成該等主動區的數個接觸件。
  3. 如申請專利範圍第2項所述之方法，其中，沉積該絕緣體包括沉積具有K值不超過約5.5的材料於該均勻內襯上方。
  4. 如申請專利範圍第1項所述之方法，復包括：形成與該間隔體毗鄰的數個主動區；沉積絕緣體於該均勻內襯上方；在移除該均勻內襯之該一部份與該多晶矽閘極以形成該閘極溝槽之前，平坦化該絕緣體至該均勻內襯；沉積層間電介質材料於該取代金屬閘極及該絕緣體上方；蝕刻穿過該層間電介質材料、該絕緣體及該內襯的數個通孔，以接觸該等主動區；以及用金屬填充該等通孔，以形成該等主動區的數個接觸。
  5. 如申請專利範圍第1項所述之方法，復包括：沉積第一絕緣體於該均勻內襯上方；在移除該均勻內襯之該一部份與該多晶矽閘極以形成該閘極溝槽之前，平坦化該第一絕緣體至該均勻內襯；使經平坦化之該第一絕緣體凹陷；沉積第二絕緣體於該已凹陷之第一絕緣體上方；以及平坦化該第二絕緣體至該均勻內襯。
  6. 如申請專利範圍第1項所述之方法，其中，在該閘極 溝槽中形成該取代金屬閘極包括：使該取代金屬閘極的下半部位於具有第一厚度的間隔體部份之間，以及使該取代金屬閘極的上半部位於具有小於該第一厚度之第二厚度的均勻內襯部份之間。
  7. 如申請專利範圍第1項所述之方法，其中，沉積該均勻內襯包括：藉由原子層沉積法沉積覆於該多晶矽閘極上的均勻氮化物層至有約3奈米至約8奈米的厚度。
  8. 如申請專利範圍第1項所述之方法，其中，沉積該均勻內襯包括：沉積覆於該多晶矽閘極上的均勻氮化物層，且其中該方法復包括定向沉積氮化物附加層於該均勻氮化物層上方。
  9. 一種製造半導體裝置的方法，包括：在半導體表面上形成數個臨時閘極結構；在該等臨時閘極結構四周形成主動區；移除覆於該等臨時閘極結構上且毗鄰該等臨時閘極結構的材料，以暴露該等臨時閘極結構，其係藉由：沉積間隙填充材料；平坦化該間隙填充材料；回蝕該間隙填充材料，以暴露該覆蓋層以及與該等臨時閘極結構毗鄰之該材料的一部份；移除該覆蓋層以及該材料之該暴露部份；以及移除該間隙填充材料；沉積覆於該等臨時閘極結構上的均勻內襯； 沉積絕緣體材料於該均勻內襯上方；平坦化該絕緣體材料至該均勻內襯，並暴露覆於該等臨時閘極結構上之該均勻內襯的數個部份；移除覆於該等臨時閘極結構上之該均勻內襯的該等部份以及該等臨時閘極結構，以形成數個閘極溝槽；以及在該等閘極溝槽中形成取代金屬閘極。
  10. 如申請專利範圍第9項所述之方法，其中，形成臨時閘極結構包括：形成NFET臨時閘極結構於該半導體表面之NFET區上，以及形成PFET臨時閘極結構於該半導體表面之PFET區上；以及其中形成主動區包括形成數個NFET主動區及數個PFET主動區。
  11. 如申請專利範圍第10項所述之方法，其中，形成PFET主動區包括：沉積PFET間隔體層於該等臨時閘極結構及該半導體表面上方；形成NFET遮罩於該NFET區上方；蝕刻在該PFET區中的該PFET間隔體層，以形成與該PFET臨時閘極毗鄰的第一PFET間隔體；移除該NFET遮罩；以及磊晶成長與該第一PFET間隔體毗鄰的材料。
  12. 如申請專利範圍第11項所述之方法，其中，形成NFET主動區包括：沉積NFET間隔體層於該NFET區及PFET區上方； 形成PFET遮罩於該PFET區上方；蝕刻在該NFET區中的該等間隔體層，以形成與該NFET臨時閘極毗鄰的第一NFET間隔體；以及移除該PFET遮罩；以及磊晶成長與該第一NFET間隔體毗鄰的材料。
  13. 如申請專利範圍第9項所述之方法，其中，沉積該均勻內襯包括：藉由原子層沉積法沉積覆於該等臨時閘極結構及數個主動區上的均勻氮化物層至約有3奈米至約8奈米的厚度。
  14. 如申請專利範圍第9項所述之方法，其中，沉積該均勻內襯包括：沉積覆於該等臨時閘極結構及數個主動區上的均勻氮化物層，且其中該方法復包括定向沉積附加氮化物層於該均勻氮化物層上方。
  15. 如申請專利範圍第9項所述之方法，其中，沉積該均勻內襯包括：沉積覆於該等臨時閘極結構及數個主動區上且具有K值約為7的均勻氮化物層，以及其中沉積該絕緣體材料包括：沉積K值不超過約5.5的氧化物於該均勻內襯上方。
  16. 一種半導體裝置，包括：半導體基板；形成於該半導體基板上具有均勻高度及側面的數個取代金屬閘極結構；與該等取代金屬閘極結構之該側面毗鄰且包含頂部及底部的間隔體，其中，每個頂部由均勻的氮化物 內襯形成並具有頂厚度，以及其中，每個底部具有大於該頂厚度的底厚度；與該間隔體之該底部毗鄰的數個主動區；位於該主動區之上的氮化矽內襯；位於該主動區之上的接觸栓塞；以及位於該間隔體與該接觸栓塞之間且k值小於約5.5的絕緣體材料。
  17. 如申請專利範圍第16項所述之半導體裝置，其中，該頂厚度為約3奈米至約8奈米。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9299781B2 (en) * 2014-04-01 2016-03-29 Globalfoundries Inc. Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material
US9941388B2 (en) * 2014-06-19 2018-04-10 Globalfoundries Inc. Method and structure for protecting gates during epitaxial growth
US9397003B1 (en) * 2015-05-27 2016-07-19 Globalfoundries Inc. Method for forming source/drain contacts during CMOS integration using confined epitaxial growth techniques
US9793407B2 (en) * 2015-12-15 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor
US10163704B2 (en) 2015-12-29 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and a method for fabricating the same
DE102016116026B4 (de) 2015-12-29 2024-02-01 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleitervorrichtung und Herstellungsverfahren
US9837535B2 (en) * 2016-03-03 2017-12-05 International Business Machines Corporation Directional deposition of protection layer
CN108493159A (zh) * 2018-04-13 2018-09-04 上海华力集成电路制造有限公司 栅极的制造方法
CN109037053B (zh) * 2018-07-13 2021-02-02 上海华力集成电路制造有限公司 栅极的制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201009959A (en) * 2008-08-18 2010-03-01 Ibm Self-aligned borderless contacts for high density electronic and memory device integration
TW201011837A (en) * 2008-09-11 2010-03-16 United Microelectronics Corp Metal gate transistor and method for fabricating the same
TW201123448A (en) * 2009-12-21 2011-07-01 Taiwan Semiconductor Mfg Gate electrode for field effect transistor and field effect transistor
TW201123355A (en) * 2009-12-18 2011-07-01 United Microelectronics Corp Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse
TW201203383A (en) * 2010-03-29 2012-01-16 Globalfoundries Us Inc Method of manufacturing a finned semiconductor device structure
TW201212231A (en) * 2010-09-07 2012-03-16 Nanya Technology Corp Semiconductor device and fabrications thereof

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7723192B2 (en) * 2008-03-14 2010-05-25 Advanced Micro Devices, Inc. Integrated circuit long and short channel metal gate devices and method of manufacture
US8084824B2 (en) * 2008-09-11 2011-12-27 United Microelectronics Corp. Metal gate transistor and method for fabricating the same
DE102009015747B4 (de) * 2009-03-31 2013-08-08 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung von Transistoren mit Metallgateelektrodenstrukturen und Gatedielektrikum mit großem ε und einer Zwischenätzstoppschicht
DE102009031146B4 (de) * 2009-06-30 2012-01-26 Globalfoundries Dresden Module One Llc & Co. Kg Abtrag einer Deckschicht in einem Metallgatestapel mit großem ε unter Anwendung eines Ätzprozesses
US8487354B2 (en) * 2009-08-21 2013-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving selectivity of epi process
DE102009039521B4 (de) * 2009-08-31 2018-02-15 Globalfoundries Dresden Module One Llc & Co. Kg Verbesserte Füllbedingungen in einem Austauschgateverfahren unter Anwendung einer zugverspannten Deckschicht
US8227890B2 (en) * 2009-12-18 2012-07-24 United Microelectronics Corporation Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse
DE102010001406B4 (de) * 2010-01-29 2014-12-11 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Austausch-Gate-Verfahren auf der Grundlage eines früh aufgebrachten Austrittsarbeitsmetalls
DE102010003451B4 (de) * 2010-03-30 2013-12-24 Globalfoundries Dresden Module One Llc & Co. Kg Austauschgateverfahren für Metallgatestapel mit großem ε durch Vermeiden eines Polierprozesses zum Freilegen des Platzhaltermaterials
DE102010030756B4 (de) * 2010-06-30 2013-06-06 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Austauschgateverfahren für Metallgatestapel mit großem ε auf der Grundlage eines nicht-konformen Zwischenschichtdielektrikums
US8358012B2 (en) * 2010-08-03 2013-01-22 International Business Machines Corporation Metal semiconductor alloy structure for low contact resistance
KR20120051915A (ko) * 2010-11-15 2012-05-23 삼성전자주식회사 반도체 소자 제조 방법
US8426300B2 (en) * 2010-12-02 2013-04-23 International Business Machines Corporation Self-aligned contact for replacement gate devices
DE102011004320B4 (de) * 2011-02-17 2016-02-04 Globalfoundries Dresden Module One Llc & Co. Kg Verfahren zur Herstellung komplementärer Transistoren mit Metallgateelektrodenstrukturen mit großem ε und epitaktisch hergestellten Halbleitermaterialien in den Drain- und Sourcebereichen
US20120306026A1 (en) * 2011-05-31 2012-12-06 International Business Machines Corporation Replacement gate electrode with a tungsten diffusion barrier layer
US8846513B2 (en) * 2011-09-23 2014-09-30 Globalfoundries Inc. Semiconductor device comprising replacement gate electrode structures and self-aligned contact elements formed by a late contact fill
US8975672B2 (en) * 2011-11-09 2015-03-10 United Microelectronics Corp. Metal oxide semiconductor transistor and manufacturing method thereof
US9012277B2 (en) * 2012-01-09 2015-04-21 Globalfoundries Inc. In situ doping and diffusionless annealing of embedded stressor regions in PMOS and NMOS devices
US8927407B2 (en) * 2012-01-20 2015-01-06 Globalfoundries Inc. Method of forming self-aligned contacts for a semiconductor device
US8841181B2 (en) * 2012-03-07 2014-09-23 United Microelectronics Corp. Method for fabricating semiconductor device and PMOS device fabricated by the method
US8828813B2 (en) * 2012-04-13 2014-09-09 Taiwan Semiconductor Manufacturing Co., Ltd. Replacement channels
US8629511B2 (en) * 2012-05-15 2014-01-14 International Business Machines Corporation Mask free protection of work function material portions in wide replacement gate electrodes

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201009959A (en) * 2008-08-18 2010-03-01 Ibm Self-aligned borderless contacts for high density electronic and memory device integration
TW201011837A (en) * 2008-09-11 2010-03-16 United Microelectronics Corp Metal gate transistor and method for fabricating the same
TW201123355A (en) * 2009-12-18 2011-07-01 United Microelectronics Corp Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse
TW201123448A (en) * 2009-12-21 2011-07-01 Taiwan Semiconductor Mfg Gate electrode for field effect transistor and field effect transistor
TW201203383A (en) * 2010-03-29 2012-01-16 Globalfoundries Us Inc Method of manufacturing a finned semiconductor device structure
TW201212231A (en) * 2010-09-07 2012-03-16 Nanya Technology Corp Semiconductor device and fabrications thereof

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