CN103489784B - 具有改良的栅极高度均匀性的半导体装置及其制造方法 - Google Patents
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Abstract
本发明涉及一种具有改良的栅极高度均匀性的半导体装置及其制造方法,其中,提供数种半导体装置以及用于制造半导体装置的方法。在一具体实施例中,一种用于制造半导体装置的方法包括:在半导体表面上形成包含多晶硅栅极及帽盖的临时栅极结构。形成间隔体于该临时栅极结构四周。移除该帽盖与该间隔体的一部分。沉积覆于该多晶硅栅极上的均匀衬板。该方法移除覆于该多晶硅栅极上的该均匀衬板的一部分以及该多晶硅栅极以形成栅极沟槽。然后,在该栅极沟槽中形成取代金属栅极。
Description
技术领域
本揭示内容大体涉及半导体装置及半导体装置的制造方法,且更特别的是,涉及具有改良的栅极高度均匀性的半导体装置以及具有改良的栅极高度均匀性的半导体装置的制造方法。
背景技术
随着技术节点缩短,有些集成电路设计一直企图排除使用多晶硅栅极以及用减少的特征尺寸来改善装置效能。解决方案之一是用金属栅极结构取代多晶硅栅极结构。取代金属栅极结构(replacement metalgate structure)可提供优异的Tinv(反转层厚度)-Vt(临界电压)效能。不过,习知制造方法难以控制取代金属栅极结构高度。具体言之,多个间隔体蚀刻和源极/漏极预外延清洗工艺(pre epi clean proces)导致覆盖临时多晶硅栅极的硬掩模(hardmask)有厚度差异。习知上,在取代金属栅极制备期间,硬掩模用作平坦化工艺的终止物(stop)。因此,硬掩模厚度的变异导致取代金属栅极结构高度的变异。最好排除取代金属栅极结构高度的变异以改善装置效能。
此外,随着栅极间距减少,栅极与接触栓塞(contact plug)之间的寄生电容分量变得愈来愈重要。因此,最好在栅极与接触件之间实现较低的K介电值以减少电容。
因此,最好提供具有均匀高度的金属栅极结构的半导体装置以及具有均匀高度的金属栅极结构的半导体装置制造方法。此外,最好提供寄生电容减少的半导体装置及其制造方法。此外,阅读以下结合附图的【具体实施方式】及【权利要求书】的详细说明和以上【技术领域】及【背景技术】可明白其它合意的特征及特性。
发明内容
提供数种半导体装置及其制造方法。根据一个具体实施例,半导体装置的制造方法包括下列步骤:在半导体表面上形成包含多晶硅栅极及帽盖的临时栅极结构。形成间隔体于该临时栅极结构四周。移除该帽盖与该间隔体的一部分。沉积覆于该多晶硅栅极上的均匀衬板(uniform liner)。该方法移除覆于该多晶硅栅极上的该均匀衬板的一部分以及该多晶硅栅极以形成栅极沟槽。然后,在该栅极沟槽中形成取代金属栅极。
在另一具体实施例中,提供半导体装置的制造方法,其包括在半导体表面上形成数个临时栅极结构。该方法进一步包括在所述临时栅极结构四周形成主动区。移除覆于所述临时栅极结构上及相邻所述临时栅极结构的材料以暴露所述临时栅极结构。然后,沉积覆于所述临时栅极结构上的均匀衬板。在该均匀衬板上面沉积绝缘体材料。平坦化该绝缘体材料至该均匀衬板以暴露覆于所述临时栅极结构上的该均匀衬板的数个部分。移除该均匀衬板的暴露部分与该临时栅极结构以形成数个栅极沟槽。然后,在所述栅极沟槽中形成取代金属栅极。
根据另一具体实施例,提供一种半导体装置,其包含半导体衬底与形成于该半导体衬底上的数个取代金属栅极结构。所述取代金属栅极结构有均匀高度及侧面。安置与所述取代金属栅极结构的侧面相邻的间隔体。每个间隔体包含顶部与底部。每个顶部由均匀的氮化物衬板形成以及有顶厚度,以及每个底部有大于该顶厚度的底厚度。
附图说明
以下用附图描述具有改良的取代金属栅极结构高度均匀性的半导体装置的具体实施例以及所述半导体装置的制造方法,其中类似的组件用相同的组件符号表示,且其中:
图1以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图2以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图3以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图4以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图5以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图6以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图7以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图8以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图9以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图10以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图11以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图12以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图13以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图14以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图15以横截面图标部分半导体装置以及制造半导体装置的方法步骤;
图16以横截面图标部分半导体装置以及制造半导体装置的方法步骤;以及
图17以横截面图标部分半导体装置以及制造半导体装置的方法步骤。
符号说明
10 半导体装置
12 半导体衬底
16 P型信道场效晶体管(PFET)区
18 N型信道FET(NFET)区
20 临时栅极氧化物层
22 临时多晶硅层
24 临时覆盖层
30 PFET临时栅极结构
32 NFET临时栅极结构
34 过渡临时栅极结构
38 层
40 掩模
44 PFET间隔体
48 PFET主动区
52 层
54 掩模
56 NFET间隔体
60 NFET主动区
62 间隔体层
66 绝缘体层
70 均匀衬板
72 附加衬板
76 绝缘体层
80 绝缘体层
84 栅极沟槽
88 取代金属栅极结构
92 层间电介质材料
94 通孔沟槽
96 接触栓塞
97 间隔体
98 下半部
99 上半部。
具体实施方式
以下的详细说明在本质上只是用来示范说明而非旨在限制如本发明权利要求书所述的半导体装置或所述半导体装置的制造方法。此外,希望不受【技术领域】、【背景技术】、或【发明内容】或以下【具体实施方式】之中明示或暗示的理论约束。
根据本文的各种具体实施例,提供有具改良栅极高度均匀性的取代金属栅极结构的半导体装置以及具改良栅极高度均匀性的半导体装置的制造方法。在一示范具体实施例中,该半导体装置制造方法包括由临时栅极结构移除包含衬板及帽盖的硬掩模层以暴露多晶硅栅极。在习知方法中,硬掩模层在经历各种蚀刻工艺后有可变厚度。在此,在移除可变的硬掩模层后,沉积均匀衬板于多晶硅栅极上面。随后的平坦化步骤用该均匀衬板作为终止物。由于均匀衬板在平坦化之前不能忍受蚀刻工艺而保有实质均匀的厚度。结果,均匀衬板的平坦化及后续蚀刻产生深度实质不变的栅极沟槽,以及随后,形成于栅极沟槽之中的取代金属栅极结构有实质均匀的高度。
图1至图17根据本文的各种具体实施例依序图标用于制造具有均匀高度的取代金属栅极结构的半导体装置的方法。设计及构造半导体装置的各种步骤为众所周知,因此,为简洁起见,本文只简述或完全省略掉许多习知步骤而不提供众所周知的加工细节。此外,应注意,半导体装置含有数量不同的组件而图中的单一组件可能代表多个组件。再者,尽管以平面型装置图解说明,然而方法及半导体装置可应用于finFET装置。
此时翻到图1,半导体装置10的示范制造方法由以下步骤开始:提供其上可形成浅沟槽隔离(STI)结构、源极/漏极区、源极/漏极延伸区、栅极电介质、接触件、间隔体、硬掩模层、及其它特征的半导体衬底12。半导体衬底12通常为硅晶圆以及包含本技艺所习知的各种掺杂配置(doping configuration)以定义P型信道场效晶体管(PFET)区16和N型信道FET(NFET)区18。半导体衬底12也可包含其它初级半导体材料,例如锗。或者,衬底12可包含化合物半导体,例如碳化硅、砷化镓、砷化铟、锑化铟、或磷化铟。此外,衬底12视需要可包含外延层(epi layer),可赋予应变用以增强效能及/或可包含绝缘体上硅(SOI)结构。如图标,在半导体衬底12上沉积临时栅极氧化物层20。此外,在临时栅极氧化物层20上面沉积临时多晶硅层22及临时覆盖层24,例如氮化硅。在某些具体实施例中,使硬掩模层(例如,由氧化硅、氧化铪或氧化铝构成约3纳米的薄层)位在临时多晶硅层22上,也就是说,在临时多晶硅层22与临时覆盖层24之间。蚀刻层20、22及24(以及任何附加层,例如视需要的硬掩模层),例如用反应离子蚀刻法(RIE),以形成PFET临时栅极结构30、NFET临时栅极结构32,以及视需要,形成过渡临时栅极结构34。
在栅极结构30、32、34形成后;层38沉积于结构30、32、34及半导体衬底12上面,如图2所示。在某些具体实施例中,层38的材料可与覆盖层24的相同。在图3中,通过典型的微影工艺(photolithographic process),形成掩模40于NFET区18上面。在PFET区16中,蚀刻层38,例如用RIE法,以形成PFET间隔体44。在此蚀刻工艺期间,层38厚度可能有点腐蚀,包括覆盖层24的厚度可能也有点腐蚀,这导致最终栅极结构高度有差异,若是没有采取以下步骤来克服差异的话。如图3所示,层38中覆于覆盖层24上的部分,以及一部分覆盖层24已经因蚀刻工艺而腐蚀掉。
根据一个具体实施例,如图4所示,移除掩模40以及通过经由选择性外延工艺来成长材料(例如,硅或含硅材料(例如,硅锗)于衬底12上面,形成PFET主动区48。可掺杂或不掺杂外延材料48。在PFET主动区48形成后,沉积层52于PFET及NFET区16,18上面,如图5所示。层52的材料通常与层38的相同,例如氮化硅。然后,通过典型的微影工艺步骤形成掩模54于PFET区16上面,如图6所示。然后,蚀刻层38、52,例如用RIE法,以形成NFET间隔体56。在此蚀刻工艺期间,层38及52的厚度可能有点腐蚀,包括帽盖层24的厚度可能也有点腐蚀,这导致最终栅极结构高度有差异,若是没有采取以下步骤来克服差异的话。如图6所示,层38中覆于覆盖层24上的部分,以及一部分覆盖层24已经因蚀刻工艺而腐蚀掉。
在图7中,移除掩模54以及例如通过经由选择性外延工艺成长材料(例如,硅或含硅材料,例如Si:C),形成NFET主动区60于衬底12上面。可掺杂或不掺杂外延材料60。为了利用主动区48、60中未掺杂或未充分掺杂的材料,依序沉积及蚀刻间隔体层62(例如,氮化硅(SiN))以形成间隔体于栅极结构30、32、34四周,如图8所示。在此工艺期间,依序执行各区16、18的离子植入工艺以提供充分的掺杂给主动区48、60。或者,间隔体层62也可为氧化物,在离子植入完成后可移除它。这些工艺在现代加工常见因而不需在此详述。在形成有充分掺杂外延材料的主动区48、60时,可排除这些步骤。
在图9中,沉积绝缘体层66于半导体衬底12上面及蚀刻它,如图标。这可用以下步骤达成:首先用氧化物过度填充(over-fill)该空间,用化学机械平坦化法(CMP)平坦化该氧化物,以及经由适当的定向蚀刻或湿蚀刻使氧化物凹回。然后,移除帽盖24以及层38、52、62的一部分以暴露临时多晶硅栅极22,如图10所示。在有视需要的硬掩模层位于多晶硅栅极22上的具体实施例中,在帽盖24及层38、52、62的一部分移除后,硬掩模层仍会覆盖多晶硅栅极22。在间隔体及帽盖材料为SiN的情形下,可用等向性SiN干蚀刻工艺或使用磷酸的湿蚀刻工艺来进行蚀刻。由于诱发厚度差异的层已被移除,栅极结构不再遭受差异,这由图10可明白。
图11图标一种在用共形工艺(conformal process,例如原子层沉积法(ALD))沉积均匀衬板70(例如,氮化硅)之前移除绝缘体层66的示范方法。或者,绝缘体层66可留下以及可沉积均匀衬板70于绝缘体层66上面。在示范具体实施例中,均匀衬板70的厚度约有3纳米(nm)至约8纳米,以及均匀衬板为K值约有7的氮化硅。图12图标在均匀衬板70正面上形成附加衬板72的视需要步骤。例如,可使用利用气体团簇离子束沉积法(GCIB)的定向电介质沉积工艺以定向形成附加衬板72。在图12显而易见,PFET、NFET多晶硅栅极结构30、32各自与外延材料48、60的间隔是用间隔体44(由层38形成)及56(由层38及52形成)建立,而不是通过均匀衬板70的垂直部分的厚度。另外,是均匀衬板70及随后所沉积的材料的电介质常数(K值)对于最终栅极结构与接触栓塞之间的电容影响最大,而不是间隔体44及56的K值。
在图13中,沉积绝缘体层76(例如,可流动的氧化硅(SiO2))于半导体衬底12上面,以及加以平坦化至衬板72(或至衬板70,如果没有使用视需要的衬板72)。示范绝缘体层76有约5.5或以下的K值。示范平坦化工艺使用CMP工艺。然后,视需要,可使绝缘体层76陷到衬板72(或70)的位准(level)以下,如图14所示。之后,沉积绝缘体层80于层76上面以及也加以平坦化至衬板72(或70)。在示范具体实施例中,绝缘体层80为用高密度等离子(HDP)沉积法所沉积的氧化物。示范绝缘体层80有约3.9的K值。
在图15中,蚀刻衬板70、72中在多晶硅栅极22上面的部分,例如,用RIE。在蚀刻所述衬板部分后,蚀刻半导体装置10的多晶硅栅极22,从而形成栅极沟槽84。在视需要的硬掩模层仍然覆盖多晶硅栅极22的具体实施例中,在蚀刻多晶硅栅极22以形成栅极沟槽84之前,移除该硬掩模层。通过典型的沉积、蚀刻及平坦化步骤,在栅极沟槽84中形成取代金属栅极结构88。沉积高k值介电材料(例如,二氧化铪)于在金属栅极下面的栅极沟槽84内。在图16中,沉积层间电介质材料92于半导体衬底12上面。然后,形成穿过层间电介质材料92、绝缘体76及80、和衬板72及70至主动区48及60的通孔沟槽(viatrench)94,如图17所示。然后,沉积金属于通孔沟槽94内以按需要形成建立至主动区48、60的电气连接的接触栓塞96。视需要的硅化工艺(silicide process)可在图8后马上进行,或在以图17描述的步骤,在金属填充之前穿过通孔沟槽94。
如图17所示,半导体装置10经形成其具有被有下半部98及上半部99的间隔体97包围的取代金属栅极结构88。在上半部99只由均匀衬板70形成时,下半部98由层38、52、62形成。结果,下半部98的厚度均大于上半部99的厚度。例如,所述下半部可有约10纳米至约20纳米的厚度,以及上半部可有约3纳米至约8纳米的厚度。此外,与习知栅极结构加工法不同的是,本发明方法不应用应力衬板(stressliner),而是应用K值有3.9的正常氧化物膜或k值更低的电介质材料。在各种具体实施例中,该方法可继续以及包括工艺步骤,例如附加层的沉积或成形,附加接触件及互连结构(例如,线路及通孔),金属层,以及层间电介质材料,以提供至含有已成形金属栅极结构88的装置的电气互连。
总之,具体实作一种半导体装置制造方法以形成具有改良高度均匀性的金属栅极结构。具体言之,该方法由临时栅极结构移除栅极帽盖、衬板及间隔体。所述帽盖、衬板及间隔体已经受导致厚度不均匀的各种蚀刻工艺。在移除不均匀的帽盖、衬板及间隔体后,形成均匀衬板于临时栅极结构上以及在形成取代金属栅极结构之前用作平坦化终止物。该均匀平坦化终止物提供高度均匀性给取代金属栅极结构。此外,寄生电容也减少,从而可改善装置效能。
描述于本文的制造方法导致半导体装置的金属栅极结构具有改良高度均匀性。尽管以上详细说明已陈述至少一个示范具体实施例,然而应了解,仍有有许多变体。也应了解,描述于本文的示范具体实施例或实施例并非旨在以任何方式限制本发明的范畴、适用性或配置。反而,上述详细说明是要让熟谙此艺者有个方便的发展蓝图用来具体实作所述具体实施例。应了解,组件的功能及配置可做出不同的改变而不脱离由权利要求书定义的范畴,此范畴包括在申请本专利申请案时已知及可预见的等效物。
Claims (14)
1.一种制造半导体装置的方法,包括:
在半导体表面上方形成包含栅极及帽盖的临时栅极结构;
形成间隔体于该栅极四周;
移除该帽盖以及该间隔体的一部分以定义该栅极的暴露表面;
在该栅极的该暴露表面上沉积均匀衬板;
在该均匀衬板上方沉积第一绝缘体;
平坦化该第一绝缘体至该均匀衬板;
使经平坦化的该第一绝缘体凹陷;
沉积第二绝缘体于该已凹陷的第一绝缘体上方;
平坦化该第二绝缘体至该均匀衬板;
移除覆于该栅极上的该均匀衬板的一部分以及该栅极,以形成栅极沟槽;以及
在该栅极沟槽中形成取代金属栅极。
2.根据权利要求1所述的方法,进一步包括:
形成与该间隔体相邻的数个主动区;
沉积绝缘体于该均匀衬板上方;
沉积层间电介质材料于该取代金属栅极及该绝缘体上方;
蚀刻穿过该层间电介质材料、该绝缘体及该均匀衬板的数个通孔,以暴露所述主动区;以及
用金属填充所述通孔,以形成所述主动区的数个接触件。
3.根据权利要求2所述的方法,其中,沉积该绝缘体包括沉积具有K值为等于或小于5.5的材料于该均匀衬板上方。
4.根据权利要求1所述的方法,其中,移除该帽盖及该间隔体的该一部分包括:
沉积间隙填充材料于该半导体衬底上方;
平坦化该间隙填充材料;
回蚀该间隙填充材料,以暴露该帽盖及该间隔体的该一部分;以及
蚀刻该帽盖以及该间隔体的该暴露部分。
5.根据权利要求1所述的方法,其中,在该栅极沟槽中形成该取代金属栅极包括:使该取代金属栅极的下半部位于具有第一厚度的间隔体部分之间,以及使该取代金属栅极的上半部位于具有小于该第一厚度的第二厚度的均匀衬板部分之间。
6.根据权利要求1所述的方法,其中,沉积该均匀衬板包括:沉积覆于该栅极上的均匀氮化物层,且其中,该方法进一步包括定向沉积氮化物附加层于该均匀氮化物层上方。
7.一种制造半导体装置的方法,包括:
在半导体表面上方形成数个临时栅极;
形成至少一临时材料相邻且覆于所述临时栅极;
在该半导体表面上方沉积间隙填充材料;
在回蚀该间隙填充材料以暴露该至少一临时材料的一部分之前,平坦化该间隙填充材料;
在移除该至少一临时材料的该暴露部分之后,移除该间隙填充材料;
沉积覆于所述临时栅极上的均匀衬板;
沉积绝缘体材料于该均匀衬板上方;
平坦化该绝缘体材料至该均匀衬板,并暴露覆于所述临时栅极上的该均匀衬板的数个部分;
移除覆于所述临时栅极上的该均匀衬板的所述部分,以形成数个栅极沟槽;以及
在所述栅极沟槽中形成取代金属栅极。
8.根据权利要求7所述的方法,进一步包括在所述临时栅极四周形成主动区。
9.根据权利要求8所述的方法,其中,形成临时栅极包括:形成NFET临时栅极结构于该半导体表面的NFET区上,以及形成PFET临时栅极结构于该半导体表面的PFET区上;以及其中,形成主动区包括形成数个NFET主动区及数个PFET主动区。
10.根据权利要求9所述的方法,其中,形成PFET主动区包括:
沉积PFET间隔体层于所述临时栅极及该半导体表面上方;
形成NFET掩模于该NFET区上方;
蚀刻在该PFET区中的该PFET间隔体层,以形成与该PFET临时栅极相邻的第一PFET间隔体;
移除该NFET掩模;以及
外延成长与该第一PFET间隔体相邻的材料。
11.根据权利要求8所述的方法,其中,沉积该均匀衬板包括:通过原子层沉积法沉积覆于所述临时栅极及数个主动区上的均匀氮化物层直到3纳米至8纳米的厚度。
12.根据权利要求8所述的方法,其中,沉积该均匀衬板包括:沉积覆于所述临时栅极及数个主动区上的均匀氮化物层,且其中,该方法进一步包括定向沉积附加氮化物层于该均匀氮化物层上方。
13.根据权利要求8所述的方法,其中,沉积该均匀衬板包括:沉积覆于所述临时栅极及数个主动区上且具有K值为7的均匀氮化物层,以及其中,沉积该绝缘体材料包括:沉积K值为等于或小于5.5的氧化物于该均匀衬板上方。
14.一种制造半导体装置的方法,包括:
在半导体表面上形成数个临时栅极结构,其中,形成临时栅极结构包括:形成NFET临时栅极结构于该半导体表面的NFET区上,以及形成PFET临时栅极结构于该半导体表面的PFET区上;以及其中,形成主动区包括形成数个NFET主动区及数个PFET主动区,其中,形成PFET主动区包括:
沉积PFET间隔体层于所述临时栅极结构及该半导体表面上方;
形成NFET掩模于该NFET区上方;
蚀刻在该PFET区中的该PFET间隔体层,以形成与该PFET临时栅极相邻的第一PFET间隔体;
移除该NFET掩模;以及
外延成长与该第一PFET间隔体相邻的材料;
其中,形成NFET主动区包括:
沉积NFET间隔体层于该NFET区及PFET区上方;
形成PFET掩模于该PFET区上方;
蚀刻在该NFET区中的所述间隔体层,以形成与该NFET临时栅极相邻的第一NFET间隔体;
移除该PFET掩模;以及
外延成长与该第一NFET间隔体相邻的材料;
在所述临时栅极结构四周形成主动区;
移除覆于所述临时栅极结构上且相邻所述临时栅极结构的材料,以暴露所述临时栅极结构;
沉积覆于所述临时栅极结构上的均匀衬板;
沉积绝缘体材料于该均匀衬板上方;
平坦化该绝缘体材料至该均匀衬板,并暴露覆于所述临时栅极结构上的该均匀衬板的数个部分;
移除覆于所述临时栅极结构上的该均匀衬板的所述部分以及所述临时栅极结构,以形成数个栅极沟槽;以及
在所述栅极沟槽中形成取代金属栅极。
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