TW201123355A - Method of forming an electrical fuse and a metal gate transistor and the related electrical fuse - Google Patents

Abstract

The present invention provides a method of integrating an electrical fuse process into a high-k/metal gate process. The method can simultaneously form a dummy gate stack of a transistor and a dummy gate stack of an e-fuse through the same processes; simultaneously removes the polysilicon of the dummy gate stack in the transistor region and the polysilicon of the dummy gate stack in the e-fuse region; next removes the work function metal layer disposed in the opening of the e-fuse region; and thereafter simultaneously fills the opening in the transistor region and the opening in the e-fuse region with metal conductive structures through the same processes to form an e-fuse and a metal gate of a transistor.

Description

201123355 VI. Description of the Invention: [Technical Field] The present invention relates to a method of forming an electrical fuse (e-fuse) component and a metal gate transistor and an electrical fuse component thereof, and in particular It relates to a method for integrating an electric fuse process into a high dielectric constant material and a high-k/metal gate (HK/MG) process. [Prior Art] Generally, the fuse is connected to a redundant circuit (redundancy φ drcuit), which can be used to repair or replace a defective circuit once the circuit is found to be defective. . Taking the structure of memory (mem〇ry) as an example, the conventional process will make some fuse structures on the uppermost layer of the structure, and its function is to complete some memory cells and word lines when the memory is completed. When the function of the 〇rd line) or the wire is problematic, it can be replaced by another redundant memory cell, word line or wire. In addition, the eye-catching design of the wire can provide stylized Qjr〇gramming). For example, in order to save R&D and manufacturing costs, the fab can use metal wires to connect to each transistor in the memory array and add a stylized connectivity component to the cable. After the semiconductor wafer is fabricated, Data input is performed externally to uniqueize each standard wafer into a variety of product wafers. When a programmable read only memory (PROM) is used for data input, if a higher voltage is used, the connected line is burned, and an open circuit is generated, that is, the input is ''transfer; , the unburned wire-electric crystal connection line still exists and forms a conduction state (〇n_state), which is equivalent to depositing, 〇". This (four), pressure burned _-) fuse is a stylized process啊聪呦, and the stylized touch wire will permanently form a disconnected state. By stylized through the 201123355 process, the fuses that are stylized to form a disconnected state and the fuses that are not programmed to form a path state can be The digital filament is stored in the form of a digital bit. The conventional filament unit 10 is shown in Fig. 1 'which comprises a polycrystalline silicon fuse element 12 and a control element 14, and the control element 14 is, for example, a transistor element. One end of the element 14 is electrically connected to the polysilicon electrical fuse element 12, and the other end is electrically connected to the grounding point GND. In general, the 'solving unit 1' is ready for use, only for the integrated circuit - block redundancy Remaining circuit. When needed When repairing or programming, a gate voltage Vg is applied to the gate of the control element 14 to turn on the control element 14. At this time, an appropriate current Ids is generated between the wire operating voltage Vfs and the ground point GND. The polycrystalline celestial element 12 is such that polycrystalline; the Wei wire element 12 produces electromigration. Although the current Ids continues to pass through the polycrystalline 矽 electrolyzed element 12, the polycrystalline 矽 electric fuse element 12 of the polycrystalline material will The phenomenon of moving along the grain boundary of the material itself in the direction of electron flow leads to the disconnection, thereby achieving the purpose of repairing and stylizing.

The gentleman suspected & the size of a semiconductor piece continued to shrink, and the multi- (10) multifilament component was tested. This is because polycrystalline Dreamliner components are prone to enthalpy when burned, which leads to damage to adjacent structures. In order to reduce the chance of particulate sweat damage = the opportunity of 冓, the precision of the components must be reduced between the crystal 7 electrical components and the surrounding components. . In addition, for the polycrystalline silicon fused S t , it is necessary to pass the electric wire to heat it so that the electrolysis filament tends to give a considerable voltage. = more =: = control of the operating voltage of the piece is difficult, 201123355 In view of this 'polycrystalline silicon fuse element will become a limitation of size reduction, how to form an electric fuse component suitable for miniature size, is currently the technical field One of the big topics. SUMMARY OF THE INVENTION Accordingly, the present invention provides a method of forming an electric fuse element and a metal gate transistor and an electric fuse element thereof, which facilitates integration of an electric fuse process into a ΗΚ/MG process, thereby solving the aforementioned conventional knowledge. problem.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of forming an electrical fuse element and a metal gate, a transistor, comprising the following steps. First, a substrate is provided defining at least one electrical fuse region and at least one active region on the substrate. Next, a dummy gate stack is formed in both the active region and the electroformed wire region. Each dummy_stack includes a gate dielectric layer, a first work function metal layer, and a polysilicon layer. Thereafter, a source/drain region is formed in each of the opposite sides of the dummy gate stack of the active region, and then an active region and an electrolyzed saddle-shaped wire-interlayer dielectric layer are formed. [The layer is located in the polycrystalline layer in the active area and the electric_area. Next, the moving area and the area of the electric area will be sold, and the time will be opened. Subsequently, a second work function metal layer is formed in the active region, covering the bottom of the opening of the active region, and then forming a metal conductive structure to fill the opening, and (10) forming a metal gate electrode and an electrical fuse element. % 201123355 Contact the surface of a metal conductive structure. According to this, the hair riding process can not only provide small size and gold crystals, but also the electric fuse process can be used for the production of two nanometers.

[Embodiment] Hereinafter, the electrolysis wire element and the metal gate transistor according to the present invention and the method for manufacturing the metal are specifically described in detail, but the embodiments are provided to limit the colors covered by the present invention. The method flow step description is not used to limit the order of the eight executions. Any execution process that is recombined by the method steps, and the method with equal effect is the one covered by the ride. The towel pattern is for illustrative purposes only and is not drawn to the original size. Referring to FIG. 2 to FIG. 9 , FIG. 2 to FIG. 9 are schematic diagrams showing a method for forming an electric fuse element and a metal gate transistor according to a preferred embodiment of the present invention, and FIG. 8 and FIG. 9 are the electricity formed by the present invention. ;tg: structure of the wire element and the metal gate transistor. The same elements or parts in the drawings are denoted by the same symbols. As shown in Fig. 2, a substrate m', for example, a substrate, a -cut substrate, or an insulating layer, a slilc〇n-〇n-insuiator (S0I) substrate or the like is provided. At least one active region 114 and at least a -electrolytic filament region ιι6 may be defined on the substrate 112. The active region ι14 can be used to form a Ni metal oxide semiconductor (N_type metal 〇xide semie〇nduct〇r, electric 201123355 crystal, P-type metal oxide semicxmduetor (PMOS) transistor and/or complementary metal An active device such as an oxide semiconductor (CMOS) transistor or the like, for example, an active region 114 of the present embodiment can simultaneously fabricate a nm〇s transistor and a PM〇s transistor, and the electrical fuse The region 116 is used to fabricate an electrical fuse element, and then fabricated in the active region ii4 and the substrate 112 of the electrical fuse region 116 by processes such as local oxidation (LOCOS) or shallow trench isolation (STI). A plurality of isolation structures 118, such as a fieid oxide iayer or shallow trench isolation structure, surround and isolate the active components of the active region 114, and may be used to isolate the electrical fuse formed in the φ electrical fuse region 116. Next, a gate dielectric layer 122' is formed on the surface of the active region 114 and the substrate 112 of the electrical fuse region 116. For example, in the present embodiment, the gate dielectric layer 122 The fabrication may include first forming an oxide layer on the active region 14 and the substrate 112 of the electrical fuse region 116 by a process such as thermal oxidative or chemical vapor deposition (CVD). 122a, for example, may include a dielectric material such as a ruthenium dioxide layer or a ruthenium oxynitride layer, and then form a high-k mateml layer on the active region 114 and the oxide layer 122a of the electro-dissolved filament region 116. L22b, for example, may include bismuth ruthenate (Congxuan), anthraquinone acid (HfSiON), oxidation to _), oxidized (La 〇), lyic acid & (La^lO), A south dielectric constant dielectric layer or a combination thereof, such as an oxidized hammer (Zr〇), a bismuth acid oxy-compound (ZrSi〇), a bismuth acid ring. In other embodiments, the gate dielectric layer (2) may also comprise only a single layer structure or a structure of three or more layers, and may include any kind of dielectric material. In addition, the present invention also needs to cover the gate dielectric layer 122 on the gate dielectric layer (for example, it can be shown), for example, after the cover layer is completely removed, the mask layer located in the PM〇s transistor region can be removed. So that the 201123355 NMOS transistor region and the electric fuse region have a cover layer. Please continue with Figure 2, followed by a process such as CVD process, physical vapor deposition (PVD) process, atomic layer deposition (ALD) process, sputtering process or A plasma enhanced chemical vapor deposition (PECVD) process, etc., to form a first work function metal layer 126' on the gate dielectric layer 22, wherein the first work function metal layer 126 can include One of the N-type work function metal and the p-type work function metal, and the first work function φ metal layer 126 may be a single layer structure or a multilayer structure. For the material selection of the first work function metal layer 126, the first work function metal layer 126 may comprise a material having a resistance value of less than 100 micro ohms (Ll〇hm_cm), such as a pure metal, a metal alloy, a metal oxide, a metal nitrogen. a compound, a metal oxynitride, a metal halide, a metal carbide or other metal compound. In the case of fabricating a CMOS transistor or the like having an NM0S transistor and a PMOS transistor, the fermi level of the metal gate is preferably close to the intermediate level (mid_gap) of the germanium to facilitate adjustment of the NMOS transistor. The threshold voltage (vth) of the PMOS transistor is matched with the threshold voltage of the PMOS transistor. In addition, the metal gate material of the present invention preferably has good thermal stability, barrier properties and adhesion, so that the gate material itself does not easily penetrate into the substrate or the dielectric layer to cause pollution, and it is difficult for the impurities to penetrate and spread, and is not easily peeled off. . For example, the first work function metal layer 126 may preferably include titanium nitride (TiN), a nitride button (TaN), a carbonization button (Ta〇 or tungsten nitride (WN). Next, as shown in FIG. 3, A plurality of b-stone layers 128 and a mask layer 13〇 are formed on the first work function metal layer 126 by a single-time or successive-step process to cover the 201123355 cover layer 130, the polysilicon layer 128, and the first work function. The metal layer 126 and the gate dielectric layer 122 are patterned to form two dummy gate stacks (dummy gates) of the NMOS transistor and the PMOS cell body in the active region 114, At the same time, the dummy gate stack 132 required for the electrical fuse element is formed in the electrical melting region 116. Further, this embodiment can form an offset spacer 134 on the sidewall of each dummy gate stack 132. Optionally performing a light doping process in the active region 114, selectively forming a plurality of sidewalls around each dummy gate stack 132, for example, including a first hafnium oxide layer 136, a tantalum nitride cladding layer 138, and a first The sidewall structure of the germanium dioxide layer 14〇 forms the source/drain region 143a of the NM〇S transistor, selectively Forming the source/" and the pole trench of the PM0S electric body, and forming the source/drain region 143b of the PMOS transistor in the source/polarization trench, and forming the source/drain region 143b of the PMOS transistor. The region 114 is subjected to a self-aligned metal salicide process to form a metal lithium 148 on the source/drain region 143a and the source/no-polar region 143b. Then, a selective formation-stop layer is formed. 154, covering the substrate 112, the source/depolarization regions 143a, 143b, the dummy gate stack 132 and the second ruthenium oxide layer 14 。 surface. Then forming a first interlayer dielectric layer 156 and overlying the etch Stopping the sound 154. It should be noted that the order of description of the foregoing process steps is not intended to limit the order of execution thereof, that is, the order of execution of each process step may be determined according to actual needs. For example, this embodiment can be used in the first A nitriding layer 138 is deposited on the first sidewall formed by the oxidized rhyme 136, and then the nitride sidewall 138 is etched back to form a second sidewall, and then other processes such as implanting the source/drain Region 143a 盥 forms source/pole region excitation, and then sinks The second oxidized stone layer is 14 〇, and the third side wall is formed on the back side. In other embodiments, the source/drain region 14 may be first formed to form the source/drain region 143a; or Forming the first side of the first ruthenium oxide layer 136, the 201123355 wall, and then performing a light doping process. Multi-aa = 128 gamma as a sacrificial layer, which may include no, and the layer 13G may contain dioxin. Cut ((10) 2), nitrogen ° In addition, the nitride blanket 138 1 stretches the stress as a stress sidewall. _Stop layer of money = as 彳i continued to carry out the flat stop and the surname of the job plug

^ Force overlay. The first interlayer dielectric layer 156 may comprise one or a combination of nitride, oxide==, low-k material. Thereafter, as shown in FIG. 4, a planarization process is performed on the first interlayer dielectric layer 156, for example, a chemical mechanical polishing (chemical job_咄_-process or dry side process to remove part of the first layer) The dielectric layer (9), a portion of the etch stop layer 54 and the mask layer 13 〇, and the top of the polycrystalline material 128 is approximately tangentially exposed to the surface of the dielectric layer 156. 'Next, as shown in FIG. 5 A selective dry side or wet etch process, for example, using an ammonia hydroxide (ΝΗβΗ) or tetramethylammonium hydroxide (TMAH) etching solution to remove the active, domain 114 and The polycrystalline (tetra) 128 in the electroformed wire region 116 may be roughly etched into the inter-layer dielectric layer 15 6 ' to open in the active region 1 i 4 and the electric snaking region j 6; into three openings 158, At the same time, the j metal layer 126 disposed at the bottom of each opening 158 is exposed. 201123355 Next, as shown in FIG. 6, 'a second work portion and a sidewall are formed, and then the electrode layer 160 is replaced by the electric melting layer == f. First work function metal layer (3). More specifically ^ first CVD process, PVD process, fly case Can

劁程, to bring this flute-mountain ~ 贱 ore process or PECVD 2 field into the first - work function metal layer 16G, then form a patterned photoresist 162 on the second work function gold, and expose the Weisi area ιΐ6 Open: 158 're-surface dry _ process or difficult erroneous Wei wire area ... 158 side of the side of the crane at the bottom of the second work function metal layer (10) and the third = (3) to expose the opening 158 of the Wei wire region 116 Dielectric layer = layer According to this, the first work function metal may also be disposed only in the active region. The first work function metal layer 16A may include (4) another of the work function metal and the p-type work function metal, and may also be a single layer structure or a multilayer structure, and preferably may include TiN TaN or WN. In addition, in order to better meet the required work function value or other desired characteristics of different _ transistors, the present invention may also perform value setting, surface treatment, changing process conditions, or increase or decrease the work function metal layer of the work function metal layer. The number of material layers. Thereafter, as shown in FIG. 7, a conductive layer 164' formed of a low-resistance material such as metal is formed over the second work-function metal layer 16A of the active region 114 and fills the openings 158' such that the conductive layer 164 is The gate dielectric layer 122 is directly contactable within the opening 158 of the electrical fuse region 116. In the present embodiment, the conductive layer 164 may be composed of a low-resistance material such as aluminum, tungsten, titanium alloy (TiAl) or c〇balt tungsten phosphide (CoWP). Thereafter, as shown in FIG. 8, another CMP process is performed to remove portions of the conductive layer 164 to form a metal conductive structure 165' in each opening 158 to form an electrical fuse element 168 and a metal gate. s transistors 166a, 166b. The metal conductive structure 165 is disposed on the surface of the gate dielectric layer 122 instead of the dummy gate stack 132, and the sidewall substructure is disposed on the sidewall of the conductive structure 165 of the metal 12 201123355. Furthermore, as shown in FIG. 9, the active region 114 and the electric fuse region Π6 may be formed - the second interlayer dielectric layer 17'' covers the first dielectric layer 156, the M s transistors 166a, 166b and the electric Above the fuse element 168, a plurality of contact plugs are formed in the first and second interlayer dielectric layers 156, 170, respectively electrically connected to the M〇s transistor 166a, the secret metal conductive structure 165, and the N-type source. / drain region ·, P-type source / drain region 143b and electrical fuse element 168.

In summary, the present invention can effectively integrate the electric fuse process into the hk/mg process 'especially the HK/MG process of 32/28 nm or less and can provide a small size and well-structured electric fuse element = ' Mm makes the circuit and materialization reduction, and the effect of the component® precision. Dimensions are effective Although the present invention has been disclosed in a preferred embodiment, any familiarity with this technique (4) is in the form of a divergence; although the book can be modified and run, the patent application is defined. The warranty is attached to the following [Simplified Description of the Drawings] ® 1 is a schematic diagram of the Xi Lai. 2 to 9 are schematic views showing a method of a crystal according to the present invention. [Main components and symbols illustrate preferred embodiments for forming an electric fuse component and a metal crucible] Gate electric power 201123355 ίο : Fuse unit 12: polycrystalline germanium electric fuse element 14 : Control Element 112: substrate 114: active region 116: electrosex region 118: isolation structure 122: gate dielectric layer 122a: oxide layer | 122b: high-k material layer 126: first work function metal layer 128: polysilicon layer 130: mask layer 132: dummy gate stack 134: pad layer 136: first hafnium oxide layer 138: tantalum nitride cap layer 140: second hafnium oxide layer 143a: N-type source/drain region 143b : P-type source/drain region 148: metal telluride 154: button stop layer 156: first interlayer dielectric layer 158: opening 160: second work function metal layer 162: patterned photoresist 201123355 164: conductive Layer 165: metal conductive structure 168: electrical fuse element 166a, 166b: MOS transistor 170: second interlayer dielectric layer 172: contact plug GND: ground point

Vg: gate voltage

Vfs : fuse operating voltage

Ids: current

Claims (1)

201123355 VII. Patent application scope: 1. A method for forming an electric fuse element and a metal gate transistor, comprising: providing a substrate to define at least an electrostimulus region and at least one active region on the substrate; The region and the sharp domain (4) form a dielectric layer, a first work function metal layer and a poly crystal 7 layer dummy stack gate stack; the dummy stack in the ahai active region Forming a source/no-polar region in each of the opposite sides of the substrate; Forming a first interlayer dielectric between the active region and the electrolysis filament region, and exposing the interlayer layer to the polysilicon layer in the main secret domain and the electrolysis filament region; Forming an opening in the region and the electric fuse region respectively; forming a second work function metal layer covering the active work region, covering a bottom portion and a sidewall of the opening of the active region; and forming a metal conductive structure filling The openings are filled to form a metal open transistor and an electrolysis element. 2. The method of claim 2, wherein the substrate comprises at least one isolation structure and the WEI element is formed on a surface of the entanglement structure. 3. The method of claim 4, wherein the step of forming the gate comprises: forming an oxide layer on the active region and the substrate in the electrical fuse region; and in the active region A high 201123355 high-k material layer is formed on the oxide layer in the electric fuse region. 如4. The method of claim, wherein the first work function layer comprises one of an N-type work function metal and a p-type work function metal, and the first work function metal layer comprises a work function metal and a p-type work function metal 5. The method of claim 5, wherein the step of forming the first electrical layer comprises: 'an electrical product', an electrical layer covering the substrate, the source/j: and The polar region is now on the imaginary interlayer: and a gradual process is performed on the inter-layer dielectric layer until the polycrystalline layer is exposed. 6. The method of claim 2, further comprising forming a sidewall substructure on a sidewall of each of the dummy interposer stacks. The method of claim 1, wherein before forming the inter-layer dielectric layer, the method further comprises: forming an etch stop layer overlying the substrate, the source/drain regions, The dummy gates are on the side wall substructures. The method of applying the patent 翻 叙 叙 method, in the axial scaly/wave region, comprises: forming a wormhole region in the substrate on opposite sides of the dummy gate of the active region. 17 201123355 9. After applying for the Wei Wei 丨 丨 green and the electric fuse element, the following further includes: ^ _ the polar crystal in the active region and the electric fuse region cover the first interlayer dielectric layer, Above the body member; and the mantle body and the electrospark element are electrically connected to the metal layer of the metal layer in the first and second dielectric layers respectively Structure, 兮 = pole / drain region and the electrical fuse element. Mu Temple, original 10. The method of claim i, wherein the second layer of work is formed only in the opening of the active region. 11. The method of claim 1, wherein the forming the second work function metal layer comprises: causing the functional metal to form the second work layer over the first work function metal layer; Removing the second and the first work function metal layer ' located on the sidewall and the bottom of the opening of the electrical fuse region to expose the gate dielectric layer in the opening. The method includes: a substrate; a gate dielectric layer disposed over the substrate; a metal conductive structure disposed on the surface of the gate dielectric layer; an interlayer dielectric layer overlying the substrate; and 201123355 At least - a plug, penetrating the interlayer dielectric layer to contact the surface of the metal conductive structure. 13. The electric fuse element of claim 12, wherein the enamel bottom comprises a clever-isolated structure, and the dielectric material is electrically connected to the isolation structure. 14 Ray = The electrical component of claim 12, wherein the interposer dielectric layer comprises an oxide layer and a high dielectric constant material layer. Wherein the metal conductor 15. The electrical fuse element electrical structure as recited in claim 12 includes aluminum metal. 16. The electric typhoon tree of claim 12, further comprising a side structure disposed on a side wall of the metal conductive structure. The wire component of claim 16, wherein the side structure comprises: a first oxide layer covering a sidewall of the metal conductive structure; - a nitride cap layer covering a sidewall of the first oxide layer; a second oxide layer 'covers the sidewalls of the nitride cap layer. ^ The electrofusion member according to claim 12, further comprising a first stop layer covering the substrate and the metal conductive structure.