CN103681465B - The forming method of semiconductor devices - Google Patents
The forming method of semiconductor devices Download PDFInfo
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- CN103681465B CN103681465B CN201210348126.9A CN201210348126A CN103681465B CN 103681465 B CN103681465 B CN 103681465B CN 201210348126 A CN201210348126 A CN 201210348126A CN 103681465 B CN103681465 B CN 103681465B
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- fuse
- layer
- dielectric layer
- forming method
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- 238000000034 method Methods 0.000 title claims abstract description 125
- 239000004065 semiconductor Substances 0.000 title claims abstract description 122
- 229910052751 metal Inorganic materials 0.000 claims abstract description 110
- 239000002184 metal Substances 0.000 claims abstract description 110
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 73
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 73
- 238000002955 isolation Methods 0.000 claims abstract description 46
- 239000010410 layer Substances 0.000 claims description 397
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 55
- 230000008569 process Effects 0.000 claims description 54
- 229920005591 polysilicon Polymers 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 230000015572 biosynthetic process Effects 0.000 claims description 21
- 150000002500 ions Chemical class 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 239000004411 aluminium Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- BRGOCSWOKBOIOJ-UHFFFAOYSA-N N.[O-2].[Hf+4] Chemical compound N.[O-2].[Hf+4] BRGOCSWOKBOIOJ-UHFFFAOYSA-N 0.000 claims description 3
- DBOSZDMILYIJNB-UHFFFAOYSA-M N.[O-2].[O-2].[O-2].[O-2].[OH-].O.[Hf+4].[Ta+5] Chemical compound N.[O-2].[O-2].[O-2].[O-2].[OH-].O.[Hf+4].[Ta+5] DBOSZDMILYIJNB-UHFFFAOYSA-M 0.000 claims description 3
- GSZNHRGXAVYPDE-UHFFFAOYSA-N N.[O-2].[Zr+4] Chemical compound N.[O-2].[Zr+4] GSZNHRGXAVYPDE-UHFFFAOYSA-N 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 claims description 3
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 3
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 claims description 3
- OPZZBWHYLNRIQZ-UHFFFAOYSA-N [Si]=O.[Zr].[N] Chemical compound [Si]=O.[Zr].[N] OPZZBWHYLNRIQZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- 229910052716 thallium Inorganic materials 0.000 claims description 3
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 3
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 2
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 claims description 2
- 239000002210 silicon-based material Substances 0.000 claims description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 2
- 238000011065 in-situ storage Methods 0.000 claims 1
- 238000000151 deposition Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 239000013078 crystal Substances 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- GDYLQKCXCRZSRS-UHFFFAOYSA-N N.[O-2].[Si+4].[Hf+4] Chemical compound N.[O-2].[Si+4].[Hf+4] GDYLQKCXCRZSRS-UHFFFAOYSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of semiconductor devices, including: there is in Semiconductor substrate fleet plough groove isolation structure；Forming dummy grid at semiconductor substrate surface, form fuse-wires structure at surface of shallow trench isolation structure, the height of fuse-wires structure is less than the height of dummy grid；Forming stressor layers in the Semiconductor substrate of dummy grid both sides, stressor layers surface less than fuse-wires structure surface or flushes with fuse-wires structure surface；Forming dielectric layer at fuse-wires structure, stressor layers, Semiconductor substrate and surface of shallow trench isolation structure, the surface of dielectric layer flushes with the top of dummy grid, and dielectric layer covers fuse-wires structure surface；Afterwards, remove dummy grid, form grid structure；Afterwards, remove stressor layers and the dielectric layer on fuse-wires structure surface, form the first opening and second opening on fuse-wires structure surface on stressor layers surface；Metal silicide layer is formed on stressor layers surface and fuse-wires structure surface；Afterwards, in the first opening, the first conductive plunger is formed.The performance of semiconductor device that the present invention is formed is good.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the forming method of a kind of semiconductor devices.
Background technology
Along with microminiaturization and the raising of complexity of semiconductor technology, semiconductor devices also becomes easier to
Affected by various defects or impurity institute, and the inefficacy of single metal connecting line, diode or transistor etc. is often
I.e. constitute the defect of whole chip.Therefore to solve this problem, prior art will be at integrated circuit
The connecting line (fusible links) of middle some fusible of formation, namely fuse (fuse), to guarantee collection
Become the utilizability of circuit.
In prior art, fuse is for connecting the redundant circuit in integrated circuit, when detection discovery circuit tool
Time defective, the connecting line of these fusible can be used for repairing or replace defective circuit；Additionally, it is molten
Silk can also provide the function of sequencing, the most first by circuit, device array and programmed circuit at chip
On process, then carried out data input by outside, by programmed circuit fusing fuse to complete circuit
Design；Such as, at programmable read only memory (Programmable Read Only Memory, PROM)
In, produce open circuit by fusing fuse, be state " 1 ", and the fuse not disconnected keeps connection status,
It is state " 0 ".
In the several frequently seen fuse-wires structure of prior art, polysilicon fuse structure is typically at CMOS
(Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)) crystal
In the forming process of pipe, concurrently form with polysilicon gate electrode layer；In existing small-scale integrated circuit,
In order to reduce the size of transistor, not affecting device performance, described transistor is frequently with high-K metal gate simultaneously
Pole (HKMG, High K Metal Gate) structure, during forming transistor, described polysilicon
Fuse concurrently forms with the dummy gate layer with polysilicon as material.
But, the existing fuse-wires structure poor-performing concurrently formed with CMOS transistor, and formation process
Complicated.
More fuse-wires structures and forming method thereof refer to the U.S. of Publication No. US 2006/0157819 A1
Patent document.
Summary of the invention
The problem that the present invention solves is to provide the forming method of a kind of semiconductor devices, improves same with transistor
Time the performance of fuse-wires structure that formed.
For solving the problems referred to above, the present invention provides the forming method of a kind of semiconductor devices, including: provide
Semiconductor substrate, has fleet plough groove isolation structure, described fleet plough groove isolation structure in described Semiconductor substrate
Surface flush with the surface of Semiconductor substrate；Dummy grid is formed, in institute at described semiconductor substrate surface
Stating surface of shallow trench isolation structure and form fuse-wires structure, the height of described fuse-wires structure is less than dummy gate pole
Height；Forming stressor layers in the Semiconductor substrate of both sides, dummy gate pole, described stressor layers surface is low
Flush in described fuse-wires structure surface or with described fuse-wires structure surface；At described fuse-wires structure, stress
Layer, Semiconductor substrate and surface of shallow trench isolation structure form dielectric layer, and the surface of described dielectric layer is with pseudo-
The top of grid flushes, and described dielectric layer covers described fuse-wires structure surface and the sidewall of dummy grid；?
After forming dielectric layer, remove dummy gate pole, form grid structure in the position of dummy gate pole；In shape
After becoming grid structure, remove described stressor layers and the dielectric layer on fuse-wires structure surface, form stressor layers table
First opening in face and second opening on fuse-wires structure surface；Stressor layers table in described first open bottom
The fuse-wires structure surface of face and the second open bottom forms metal silicide layer；Forming described metal silication
After nitride layer, formed and fill full described first opening and the second opening, and cover described dielectric layer and grid
The conductive layer of structure；Remove the conductive layer higher than dielectric layer surface, in the first opening, form the first conduction
Connector.
Alternatively, low 10 nanometer-50 nanometers of the height of the aspect ratio dummy gate pole of described fuse-wires structure.
Alternatively, the material of dummy gate pole and fuse-wires structure is polysilicon.
Alternatively, the forming method of dummy gate pole and fuse-wires structure is: in described Semiconductor substrate and shallow
Groove isolation construction surface deposit polycrystalline silicon layer；It is etched back to the polysilicon layer of surface of shallow trench isolation structure,
Make the polysilicon layer polysilicon layer less than semiconductor substrate surface of surface of shallow trench isolation structure；Carve returning
After etching technique, etched portions polysilicon layer is until exposing Semiconductor substrate and fleet plough groove isolation structure is
Only, dummy grid and fuse-wires structure are formed.
Alternatively, the polycrystalline silicon material of described fuse-wires structure has Doped ions, described Doped ions bag
Include: boron, phosphorus or arsenic.
Alternatively, described Doped ions uses original position doping process or ion implantation technology at described polysilicon
Interior formation.
Alternatively, also include: before forming stressor layers, in dummy gate pole and fuse-wires structure both sides shape
Become side wall；Stressor layers is formed in the Semiconductor substrate of dummy gate pole and side wall both sides.
Alternatively, the sidewall of described stressor layers and semiconductor substrate surface are in " Σ " shape, described stressor layers
Sidewall Semiconductor substrate below dummy gate structure in extend.
Alternatively, the material of described stressor layers is SiGe or carborundum.
Alternatively, described grid structure includes: be positioned at semiconductor substrate surface high-K dielectric layer and
It is positioned at the metal gate layers on described high-K dielectric layer surface.
Alternatively, also include: silicon oxide layer between described Semiconductor substrate and high-K dielectric layer,
And the protective layer between described high-K dielectric layer and metal gate layers.
Alternatively, one or both combinations in the material titanium nitride of described protective layer and tantalum nitride.
Alternatively, the forming method of described grid structure includes: etching dummy gate pole exposing partly is led
Body substrate surface, forms the 3rd opening；High-K dielectric layer is formed in the bottom of described 3rd opening；Institute
State high-K dielectric layer surface and form the metal gate layers filling full described 3rd opening.
Alternatively, the material of described high-K dielectric layer is: for hafnium oxide, hafnium silicon oxide, nitrogen hafnium oxide,
Nitrogen hafnium silicon oxide, nitrogen hafnium oxide tantalum, zirconium oxide, nitrogen zirconium oxide, nitrogen zirconium silicon oxide, zirconium silicon oxide, oxygen
Change lanthanum, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminum oxide.
Alternatively, the material of described metal gate layers is: aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt,
One or more combinations in thallium, tantalum and tungsten.
Alternatively, the material of described metal silicide layer is nisiloy, titanium silicon or cobalt silicon.
Alternatively, the forming method of described metal silicide layer is: at the stressor layers table of the first open bottom
Face, the fuse-wires structure surface of the second open bottom and dielectric layer surface deposition metal level, described metal level
Material is nickel, titanium or cobalt；After forming metal level, carry out thermal annealing, make the metal in metal level and answer
Silicon in power layer and fuse-wires structure combines, and forms metal silicide layer；Remove metal silicide layer surface
Remaining metal level.
Alternatively, described removal is CMP process higher than the technique of the conductive layer of dielectric layer surface.
Alternatively, also include: after removing the conductive layer higher than dielectric layer surface, use and be etched back to technique
Remaining conductive layer in removing the second opening.
Alternatively, the material of described conductive plunger is copper, tungsten or aluminium.
Alternatively, the material of described dielectric layer is silica.
Alternatively, the surface of described stressor layers is less than described fuse-wires structure surface 5 nanometer-10 nanometer, is higher than
Surface 10 nanometer-50 nanometer of Semiconductor substrate.
Alternatively, also include: form second Jie on described dielectric layer, grid structure and fuse-wires structure surface
Matter layer, has the 4th opening in described second dielectric layer, described 4th opening exposes the first conductive plunger
Surface and the surface at described fuse-wires structure two ends；In described 4th opening, form the second conduction insert
Plug.
Compared with prior art, technical scheme has the advantage that
It is formed at the dummy grid of semiconductor substrate surface higher than the fuse being formed at surface of shallow trench isolation structure
Structure, it is possible to make the metal silicide layer being formed at fuse-wires structure surface less than the grid structure being subsequently formed；
Therefore, the dielectric layer flushed with dummy grid height can cover described fuse-wires structure surface, it is possible to is removing
Dummy grid also forms the technique of grid structure, protects fuse-wires structure surface；Additionally, lead being subsequently formed
During electric plug, owing to needing to remove the conductive layer higher than dielectric layer surface, therefore work as fuse-wires structure
When the metal silicide layer on surface is less than described dielectric layer, it is possible to avoid in the technique removing conductive layer,
Described metal silicide layer sustains damage, thus ensure that the stable performance of fuse-wires structure.
Further, owing to the dielectric layer of stressor layers and fuse-wires structure surface is removed simultaneously, and stressor layers
The metal silicide on surface and fuse-wires structure surface is formed in same processing step, thus simplifies technique
Step, has saved cost.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the cross-sectional view of the forming process of fuse-wires structure in prior art；
Fig. 5 to Figure 16 is that the cross-section structure of the forming process of the semiconductor devices described in the embodiment of the present invention shows
It is intended to.
Detailed description of the invention
As stated in the Background Art, the existing fuse-wires structure poor-performing concurrently formed with transistor, and shape
Become complex process.
The cross-section structure of the fuse-wires structure of prior art includes: be positioned at described surface of shallow trench isolation structure
Polysilicon layer, and it is positioned at the metal silicide layer on described polysilicon layer surface, described polysilicon layer and gold
Belong to silicide layer include fuse area and be positioned at the contact zone at fuse area two ends；Wherein, due to described metal
The resistance of silicide layer is relatively low, when applying high-voltage pulse to the contact zone at described metal silicide layer two ends,
Transient Currents can be produced in described metal silicide layer, the fuse area of described metal silicide layer is fused；
Meanwhile, the heat that described Transient Currents produces, make to be positioned at the polysilicon below metal silicide layer fuse area
Layer recrystallization, and impurity rearrangement, so that the resistance of the contact zone at described polysilicon layer two ends is notable
Increase.Additionally, in prior art, described fuse-wires structure concurrently forms with transistor, walk with Simplified flowsheet
Suddenly.
But, the present inventor finds through research, in prior art, concurrently forms with transistor
The performance of fuse-wires structure the best.Concrete, the section knot of the forming process of fuse-wires structure in prior art
Structure schematic diagram, as shown in Figures 1 to 4, including:
Refer to Fig. 1, it is provided that Semiconductor substrate 100, have in described Semiconductor substrate 100 shallow trench every
From structure 101；Described Semiconductor substrate 100 surface has dummy grid 102, both sides, dummy gate pole 102
There is side wall 103, in the Semiconductor substrate 100 of dummy gate pole 102 and side wall 103 both sides, there is stress
Layer 104；Described fleet plough groove isolation structure 101 surface has fuse-wires structure 105, dummy gate pole 102 He
The material of fuse-wires structure 105 is polysilicon；Described Semiconductor substrate 100, fleet plough groove isolation structure 101 and
Stressor layers 104 surface has dielectric layer 106, the top of described dielectric layer 106 and dummy grid 102 and fuse
Structure 105 flushes.
Refer to Fig. 2, form mask layer 107, institute at described dielectric layer 106 and fuse-wires structure 105 surface
State mask layer 107 and expose dummy grid 102(as shown in Figure 1) surface；With described mask layer 1 07 for covering
Film removes dummy gate layer 102, and forms metal gate 108, described metal gate in the position of former dummy grid 102
108 flush with dielectric layer 106.
Refer to Fig. 3, remove described mask layer 107(as shown in Figure 2), and at described fuse-wires structure 105
Surface forms the first metal silicide layer 109.
Refer to Fig. 4, after forming the first metal silicide layer 109, formed on described stressor layers 104 surface
Opening (not shown), forms the second metal silicide layer 110 on stressor layers 104 surface of described open bottom,
And the conduction of the full described opening of filling is formed on the second metal silicide layer 110 surface of described open bottom
Layer (not shown)；CMP process is used to remove the conductive layer higher than dielectric layer 106 surface, shape
Become conductive plunger 111.
The present inventor studies discovery, owing to described fuse-wires structure 105 flushes with dielectric layer 106,
Therefore described fuse-wires structure 105 surface formed the first metal silicide layer 109 also with described dielectric layer
106 flush；But, during owing to forming conductive plunger 111, need to use CMP process to remove
Higher than the conductive layer on dielectric layer 106 surface, and described CMP process is with described dielectric layer 106
As polishing stop layer, the most described CMP process can damage and flush with described dielectric layer 106
The first metal silicide layer 109, and then cause the performance of described fuse-wires structure 105 bad.
Being additionally, since when forming the opening above stressor layers 104, the surface of fuse-wires structure 105 covers
There is mask layer 107, and described mask layer 107 has continued to protect during being subsequently formed conductive plunger 111
Protect effect；Therefore, prior art is when forming the second metal silicide layer 110, it is impossible to simultaneously at fuse
The surface of structure 105 forms the first metal silicide layer 109；Thus need to increase processing step, at fuse
Structure 105 surface forms the first metal silicide layer 109, makes processing step complicated, and the process time extends.
The present inventor after further research, makes to be formed at the dummy grid of semiconductor substrate surface
Highly, higher than the height of the fuse-wires structure being formed at surface of shallow trench isolation structure, make to be formed at fuse
The metal silicide layer of body structure surface is also below dielectric layer surface；Thus ensure that and forming conductive plunger
During, CMP process will not damage the metal silicide layer on described fuse-wires structure surface, makes
The stable performance of the fuse-wires structure formed；Additionally, make the height of described formed dielectric layer and dummy grid
Spending identical, and described fuse-wires structure is less than dummy gate pole, the most described dielectric layer covers described fuse knot
Structure；During removing dummy grid and substituting with grid structure, described fuse-wires structure can be by described
Dielectric layer be protected against damage；And, the dielectric layer on described fuse-wires structure and stressor layers surface is simultaneously
It is removed, and the metal silicide layer on fuse-wires structure and stressor layers surface concurrently forms, and not necessarily form
Extra mask layer such that it is able to save processing step, saves the process time, and reduces cost.
Understandable, below in conjunction with the accompanying drawings for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from
The detailed description of the invention of the present invention is described in detail.
Fig. 5 to Figure 16 is that the cross-section structure of the forming process of the semiconductor devices described in the embodiment of the present invention shows
It is intended to.
Refer to Fig. 5, it is provided that Semiconductor substrate 200, have in described Semiconductor substrate 200 shallow trench every
From structure 201, the surface of described fleet plough groove isolation structure 201 flushes with the surface of Semiconductor substrate 200；
At described Semiconductor substrate 200 and fleet plough groove isolation structure 201 surface deposit polycrystalline silicon layer 202.
Described Semiconductor substrate 200 is for providing workbench, described Semiconductor substrate 200 for subsequent technique
Material be silicon or silicon-on-insulator；In the present embodiment, the crystal face on described Semiconductor substrate 200 surface refers to
Number is (100).
The material of described fleet plough groove isolation structure 201 is silica, described fleet plough groove isolation structure 201
Surface is used for forming fuse-wires structure in subsequent technique；The formation process of described fleet plough groove isolation structure 201
Being well known to those skilled in the art, therefore not to repeat here.
Described Semiconductor substrate 200 surface is used for forming transistor, including: PMOS transistor, NMOS
Transistor or CMOS transistor；Described fuse-wires structure is formed during forming described transistor；
When described transistor is high-K metal gate (HKMG, High-k Metal Gate) structure, described molten
Fuse layer in silk structure concurrently forms with the dummy gate structure of transistor；In the present embodiment, described half
Conductor substrate 200 surface forms the transistor with high-K dielectric layer and metal gates in subsequent technique.
Described polysilicon layer 202 is for forming fuse-wires structure and the dummy grid of transistor in subsequent technique；
The formation process of described polysilicon layer 202 is depositing operation, it is preferred that selective epitaxial depositing operation；
When having Doped ions in described polysilicon layer 202, the resistivity of described polysilicon layer 202 becomes
Change；To be removed owing to being subsequently formed the dummy grid in Semiconductor substrate 200 surface, and by grid structure
Replacing, the ion adulterated in the most described polysilicon layer 202 is without the Gate Electrode Conductive class by transistor
The restriction of type；And then, in described polysilicon layer 202, Doped ions is with the technique meeting fuse-wires structure 202
Requirement is advisable, and the conduction type of the transistor being subsequently formed without consideration.
Described Doped ions includes: boron, phosphorus or arsenic；In one embodiment, described polysilicon layer is being deposited
After 202, use ion implantation technology Doped ions in above-mentioned polysilicon layer 202；In another embodiment
In, during forming described polysilicon layer 202, use original position doping process at polysilicon layer 202
Interior Doped ions.
Refer to Fig. 6, be etched back to the polysilicon layer 202 on fleet plough groove isolation structure 201 surface, make shallow trench
The polysilicon layer 202 on isolation structure 201 surface is less than the polysilicon layer 202 on Semiconductor substrate 200 surface.
The polysilicon layer 202 on described fleet plough groove isolation structure 201 surface is less than Semiconductor substrate 200 surface
Polysilicon layer 202, it is possible to make to be subsequently formed the height of the fuse-wires structure in fleet plough groove isolation structure 201 surface
Degree, less than the height of the dummy grid being formed at Semiconductor substrate 200 surface；Therefore, it is subsequently formed in molten
The top of the metal silicide layer of silk body structure surface is also below the top of grid structure；And then, make follow-up shape
Become CMP process during conductive plunger will not damage the metal silicide layer on fuse-wires structure surface,
Make the performance of follow-up formed fuse-wires structure more preferably.
Additionally, due to be subsequently formed the height of the fuse-wires structure in fleet plough groove isolation structure 201 surface, low
In the height of the dummy grid being formed at Semiconductor substrate 200 surface, make to be subsequently formed with dummy grid top
The dielectric layer flushed covers the fuse-wires structure surface being subsequently formed, and described dielectric layer can remove puppet follow-up
Described fuse-wires structure surface is protected during grid, and formation grid structure；And, it is subsequently formed
During first opening on stressor layers surface, it is possible to remove the dielectric layer on fuse-wires structure surface simultaneously, thus without
Extra mask layer can concurrently form stressor layers and the metal silicide layer on fuse-wires structure surface；Therefore,
The forming method of semiconductor devices described in the present embodiment is simple, saves process time and cost.
The described technique that is etched back to is: at described polysilicon layer 202(as shown in Figure 5) surface formation photoresist
Layer；Described photoresist layer is exposed development, makes described photoresist layer expose fleet plough groove isolation structure
The correspondence position of 201；With the photoresist layer after exposure as mask, it is etched back to described polysilicon layer 202, makes
The polysilicon layer 202 on fleet plough groove isolation structure 201 surface is less than the polysilicon on Semiconductor substrate 200 surface
Layer 202, described in be etched back to technique be dry etching；After being etched back to technique, remove described photoresist layer.
It should be noted that the polysilicon layer 202 on described fleet plough groove isolation structure 201 surface, compare semiconductor
The distance of low 10 nanometer-50 nanometers of polysilicon layer 202 on substrate 200 surface, it is possible to ensure to be subsequently formed
The top of the metal silicide layer in fuse-wires structure surface, than the grid structure formed and the top of dielectric layer
Portion is low, so that the CMP process during being subsequently formed conductive plunger will not destroy fuse knot
The metal silicide layer on structure surface.
Refer to Fig. 7, after being etched back to technique, etched portions polysilicon layer 202(is as shown in Figure 6),
Till exposing Semiconductor substrate 200 and fleet plough groove isolation structure 201, form dummy grid 203 He
Fuse-wires structure 204, the height of described fuse-wires structure 204 is less than the height of dummy gate pole 203.
Dummy gate pole 203 takes up space for the grid structure for being subsequently formed；Described fuse-wires structure 204
Contact zone (not shown) including fuse area (not shown) and fuse area two ends；The width of described fuse area
The narrow width of more described contact zone, described contact zone is used for being electrically interconnected；When fuse-wires structure 204 liang
After the contact zone of end accesses Transient Currents, owing to described fuse area is narrower, easily it is blown after being heated,
Thus realize the function of fuse-wires structure 204.
The formation process of dummy gate pole 203 and fuse-wires structure 204 is: at described polysilicon layer 202 table
Face forms mask layer 220, and described mask layer 220 covers to be needed to form dummy grid 203 and fuse-wires structure 204
Correspondence position；Anisotropic dry etch process is used to etch described polysilicon layer 202, until exposing
Till going out Semiconductor substrate 200 and fleet plough groove isolation structure 201.
Owing to the technique that is etched back to before makes the polysilicon layer 202 on fleet plough groove isolation structure 201 surface be less than
The polysilicon layer 202 on Semiconductor substrate 200 surface, the height of the fuse-wires structure 204 therefore formed is less than
The height of dummy gate pole 203, and described fuse-wires structure 204 less than the distance of dummy gate pole 203 is
10 nanometer-50 nanometers.
Described fuse-wires structure 204, less than dummy gate pole 203, makes be subsequently formed to flush with dummy grid 203
Dielectric layer can cover described fuse-wires structure, thus at follow-up removal dummy grid 203 and form grid knot
During structure, protect described fuse-wires structure surface；Additionally, described fuse-wires structure 204 is less than dummy gate pole 203
Distance be 10 nanometer-50 nanometers, it is ensured that be subsequently formed in the metal silicide layer on fuse-wires structure surface
Less than grid structure and dielectric layer, thus during avoiding and being subsequently formed conductive plunger, chemical machinery
The glossing damage to the metal silicide on fuse-wires structure 204 surface.
Refer to Fig. 8, form side wall 205 in dummy gate pole 203 and fuse-wires structure 204 both sides.
Described side wall 205 include being positioned at dummy grid 203 and the first side wall of fuse-wires structure 204 both sides, with
And the pseudo-side wall outside described first side wall；The material of described first side wall is silica, described pseudo-side wall
Material be silicon nitride, described pseudo-side wall is subsequently formed in dummy grid 203 and side wall 205 liang for definition
The position of the stressor layers of side, it is to avoid produce short-channel effect.
The formation process of described side wall 205 is: at described Semiconductor substrate 200, fleet plough groove isolation structure
201, dummy grid 203 and fuse-wires structure 204 surface form silicon oxide layer and the nitridation on silicon oxide layer surface
Silicon layer；It is etched back to described silicon oxide layer and silicon nitride layer, at dummy gate pole 203 and fuse-wires structure 204
Both sides form the first side wall and pseudo-side wall；In the present embodiment, described first side wall and pseudo-side wall constitute side
Wall 205.
In another embodiment, after being subsequently formed stressor layers, remove described pseudo-side wall and form second
Side wall, the material of described second side wall is one or both combinations in silicon nitride and silica；Due to
During being subsequently formed stressor layers, described pseudo-side wall can be thinned, it is therefore desirable to forms size the most smart
The second true side wall replaces described pseudo-side wall, is more beneficial for the stable performance of formed transistor；At this
In embodiment, described side wall 205 is made up of the first side wall and the second side wall.
Refer to Fig. 9, being formed in the Semiconductor substrate 200 of dummy gate pole 203 and side wall 205 both sides should
Power layer 206, described stressor layers 206 surface less than described fuse-wires structure 204 surface or with described fuse-wires structure
204 surfaces flush.
The material of described stressor layers 206 is SiGe or carborundum；When the transistor formed is PMOS,
The material of described stressor layers 206 is SiGe, provides compression to the channel region of transistor；When the crystalline substance formed
When body pipe is NMOS tube, the material of described stressor layers 206 is carborundum, provides to the channel region of transistor
Tension.
The sidewall of described stressor layers 206 and the surface of Semiconductor substrate 200 are in " Σ " (Sigma, Sigma)
Type；In the present embodiment, the surface of described stressor layers 206 is less than surface 5 nanometer of described fuse-wires structure 204
-10 nanometers, higher than surface 10 nanometer-50 nanometer of Semiconductor substrate 200；In another embodiment, described
Stressor layers 206 flushes with the surface of described fuse-wires structure 204, and the most described stressor layers 206 is less than dummy gate pole
The distance of 203 is 10 nanometer-50 nanometers.
Lattice mismatch is there is between material and the material of Semiconductor substrate 200 of described stressor layers 206, and institute
The stress stating lattice mismatch generation can apply to give the channel region of formed transistor；And, described should
The sidewall of power layer 206 extends in Semiconductor substrate 200, makes between the stressor layers 206 of dummy grid 203 both sides
Distance closer to, thus it is bigger to put on the stress of channel region, is more beneficial for the migration of carrier.
The formation process of described stressor layers 206 is: in dummy grid 203 and the Semiconductor substrate of side wall 205 both sides
The surface of opening (not shown), the sidewall of described opening and Semiconductor substrate 200 is formed in " Σ " in 200
Type；Epitaxial deposition process is used to form stressor layers 206 in described opening；After forming stressor layers 206,
Implanting p-type ion or N-type ion in described stressor layers 206, form source region and drain region.
Wherein, the formation process of described opening is: use anisotropic dry etch process in described puppet
Form sidewall in the Semiconductor substrate 200 of grid 203 and side wall 205 both sides to hang down with Semiconductor substrate 100 surface
Straight opening (not shown)；After described anisotropic dry etch process, use anisotropy
Wet-etching technology etch described opening, make the drift angle on described opening sidewalls below dummy grid 203
Extend in Semiconductor substrate 200, form the opening of " Σ " shape.
When the crystal face on described Semiconductor substrate 200 surface is (100), and described anisotropic wet method is carved
Erosion is being perpendicular to Semiconductor substrate 200 surface and is being parallel on the direction on Semiconductor substrate 200 surface
Etch rate is very fast, and the etch rate when etching crystal face (111) is the slowest, so that described opening
Sidewall and Semiconductor substrate 200 surface are in " Σ " shape；After forming stressor layers 206 in described opening,
The spacing of adjacent stressor layers 206 is less, then the stress putting on transistor channel region is bigger.
It should be noted that in one embodiment, after forming described stressor layers 206, remove described
Pseudo-side wall, forms the second side wall in dummy gate pole 203 and the first side wall both sides, described second side wall
Material is one or both combinations in silicon nitride and silica；In this embodiment, described side wall 205 by
First side wall and the second side wall are constituted, and the size of described side wall 205 is easily controlled.
Refer to Figure 10, at described fuse-wires structure 204, stressor layers 206, Semiconductor substrate 200 and shallow trench
Isolation structure 201 surface forms dielectric layer 207, the surface of described dielectric layer 207 and the top of dummy grid 203
Flush, and described dielectric layer 207 covers described fuse-wires structure 204 surface and the sidewall of dummy grid 203.
The material of described dielectric layer 207 is silica, and described dielectric layer 207 is used for making to be formed at semiconductor lining
The device electric isolution on surface, the end 200；The formation process of described dielectric layer 207 is: use chemical gaseous phase deposition
Technique in dummy gate pole 203, fuse-wires structure 204, stressor layers 206, Semiconductor substrate 200 and shallow trench
Isolation structure 201 surface forms dielectric film；CMP process is used to planarize described medium thin
Film, till exposing dummy grid 203, forms dielectric layer 207.
Owing to described fuse-wires structure 204 is less than dummy gate pole 203, therefore described neat with dummy grid 203 top
Flat dielectric layer 207 still covers described fuse-wires structure 204, thus at follow-up removal dummy grid 203 and formed
During grid structure, protect described fuse-wires structure 204 surface；Additionally, in subsequent technique, fuse
The dielectric layer 207 on structure 204 and stressor layers 206 surface can be removed simultaneously, and with remaining dielectric layer
207 is mask, it is possible to form metal silicide layer at fuse-wires structure 204 and stressor layers 206 surface simultaneously, from
And Simplified flowsheet, save process time and cost.
It should be noted that when the dielectric film using CMP process to remove dummy grid 203 surface
Afterwards, remove the mask layer 220 on dummy grid 203 surface, and expose dummy grid 203 surface.
Refer to Figure 11, after forming dielectric layer 207, remove dummy gate pole 203(as shown in Figure 10),
Grid structure 208 is formed in the position of dummy gate pole 203.
The formation process of described grid structure 208 is: use dry etching or wet-etching technology to remove pseudo-grid
Pole layer 203, and expose Semiconductor substrate 200, form the 3rd opening；Formed in described 3rd opening
Grid structure；Described grid structure 208 includes: be positioned at the high-K dielectric layer on Semiconductor substrate 200 surface (not
Illustrate) and the metal gate layers (not shown) on high-K dielectric layer surface.
The material of described high-K dielectric layer includes: for hafnium oxide, hafnium silicon oxide, nitrogen hafnium oxide, nitrogen hafnium oxide
Silicon, nitrogen hafnium oxide tantalum, zirconium oxide, nitrogen zirconium oxide, nitrogen zirconium silicon oxide, zirconium silicon oxide, lanthana, oxygen
Change titanium, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminum oxide；Described metal gates
The material of layer includes: one in aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum and tungsten or
Multiple combination.
It should be noted that protective layer can also be formed between described high-K dielectric layer and metal gate layers
(not shown), described protective layer can have the described high-K dielectric layer of isolation and metal gate layers, and keep away
Exempt from metal to spread in high-K dielectric layer and cause device performance unstable；The material of described protective layer includes:
One or both combinations in titanium nitride and tantalum nitride；Additionally, in described high-K dielectric layer and Semiconductor substrate
Can form silicon oxide layer between 200, described silicon oxide layer is used for being bonded described high-K dielectric layer and semiconductor
Substrate 200, it is to avoid produce leakage current.
The formation process of described grid structure 208 is well known to those skilled in the art, and therefore not to repeat here；
Owing to the dummy grid 203 removed and dielectric layer 207 are higher than fuse-wires structure 204, and described grid structure 208
Flushing with dielectric layer 207, the most described grid structure 208 is higher than fuse-wires structure 204 top.
Refer to Figure 12, after forming grid structure 208, remove described stressor layers 206 and fuse-wires structure
The dielectric layer 207 on 204 surfaces, forms the first opening 209 and fuse-wires structure 204 surface on stressor layers 206 surface
The second opening 210.
The formation process of described first opening 209 and the second opening 210 is: at described dielectric layer 207 and grid
Structure 208 surface forms photoresist layer；Graphical described photoresist layer, making described photoresist layer expose should
Dielectric layer 207 surface of power layer and fuse-wires structure correspondence position；The photoresist layer graphically changed is mask, adopts
Form the first opening 209 by dry etch process on stressor layers 206 surface, formed on fuse-wires structure 204 surface
Second opening 210.
Described first opening 209 and the second opening 2 10 concurrently form, and cause follow-up at described first opening 209
Can concurrently form with the metal silicide layer bottom the second opening 210；Avoid as described in the prior art,
Fuse-wires structure 105(is as shown in Figure 4) surface forms the first metal silicide layer 109(as shown in Figure 4), and
Stressor layers 104(is as shown in Figure 4) surface forms the second metal silicide layer 110(as shown in Figure 4) pass through
Twice technique is formed；Therefore, the forming method technique of semiconductor devices described in the present embodiment simplifies, it is possible to
Save process time and cost.
Described first opening 209 is used for forming conductive plunger in subsequent technique, the crystal formed with realization
The electrical interconnection of pipe；Described second opening 210 is used for being formed the gold on fuse-wires structure 204 surface in subsequent technique
Belong to silicide layer, owing to described fuse-wires structure 204 is less than dielectric layer 207, therefore, be subsequently formed and fuse
The metal silicide layer on structure 204 surface, also below dielectric layer 207, thus avoid and forms conductive plunger
During, the flatening process damage to the metal silicide layer on fuse-wires structure 204 surface.
It should be noted that after removing the dielectric layer 207 on fuse-wires structure 204 surface, remove fuse knot
The mask layer 220(on structure 204 surface is as shown in figure 11).
Refer to Figure 13, stressor layers 206 surface bottom described first opening 209 and second opening 210 end
Fuse-wires structure 204 surface in portion forms metal silicide layer 2 11.
The material of described metal silicide layer 211 is titanium silicon, nisiloy or cobalt silicon；The gold on stressor layers 206 surface
Belong to silicide layer 211 and be used for the source region as the transistor formed and the electrode in drain region；Described fuse-wires structure
The metal silicide layer 211 on 204 surfaces is for as low resistivity layer, when connecing to described fuse-wires structure 204 two ends
When touching district's applying high-voltage pulse, in the metal silicide layer 211 on described fuse-wires structure 204 surface, wink can be produced
The big electric current of state, and produce high heat, thus the fuse area of fuse-wires structure 204 is fused.
The formation process of described metal silicide layer 211 is: at stressor layers 206, fuse-wires structure 204, medium
Layer 207 and grid structure 208 surface deposition metal level, the material of described metal level is titanium, nickel or cobalt；?
After forming metal level, carry out thermal annealing, make the metallic atom in described metal level diffuse into stressor layers 206 He
In fuse-wires structure 204, form metal silicide layer 211；After thermal annealing, remove metal silicide layer
The metal level of 211 surface residual.
Owing to the top of described fuse-wires structure 204 is less than dielectric layer 207 and grid structure 208, the most described molten
The surface of the metal silicide layer 211 that silk structure 204 surface is formed is also below described dielectric layer 207 and grid
Structure；And then, during being subsequently formed conductive plunger, CMP process will not damage,
The thinning metal silicide layer 211 even removing fuse-wires structure 204 surface, makes formed fuse-wires structure 204
Stable performance.
Refer to Figure 14, after forming described metal silicide layer 211, formed to fill and completely described first open
Mouth 209(is as shown in figure 13) and the second opening 210(is as shown in figure 13) and cover described dielectric layer 207
Conductive layer 212 with grid structure 208.
The material of described conductive layer 212 is copper, tungsten or aluminium, and described conductive layer 212 is used for forming conductive plunger,
The formation process of described conductive layer 212 is depositing operation, it is preferred that physical gas-phase deposition.
Owing to described conductive layer 212 fills full second opening 210, therefore remove higher than medium at subsequent technique
During the conductive layer 212 on layer 207 surface, there is in described second opening 210 conductive layer 212 of remnants, and institute
Remaining conductive layer 212 can protect the metal silicide layer 211 on fuse-wires structure 204 surface to destroy.
Refer to Figure 15, remove and be higher than the conductive layer 212(on dielectric layer 207 surface as shown in figure 14),
The first conductive plunger 213 is formed in the first opening 209.
Described removal is CMP process higher than conductive layer 212 technique on dielectric layer 207 surface,
And described CMP process is using dielectric layer as stop-layer；When removing higher than dielectric layer 207 surface
Conductive layer after, in described first opening 209 and the second opening 20, there is remaining conductive layer 212；Institute
In stating the first opening 209, remaining conductive layer 212 forms the first conductive plunger 213；Described second opening
In 210, remaining conductive layer 212 is in described CMP process, protects fuse-wires structure 204 surface
Metal silicide layer 211 be not damaged, thinning or remove completely, so that the fuse-wires structure formed
204 stable performances.
It should be noted that after removing the conductive layer 212 higher than dielectric layer 207 surface, use back
Etching technics is remaining conductive layer 212 in removing the second opening 210；Described due to described conductive layer 212
Material is different from the material of metal silicide layer 211, is therefore etched back in technical process described, conduction
Between layer 212 and metal silicide layer 211, there is selectivity, while removing conductive layer 212, difficult
So that metal silicide layer 211 is caused damage.
Refer to Figure 16, in described dielectric layer 207, grid structure 208 and fuse-wires structure 204 surface shape
Become second dielectric layer 214, there is in described second dielectric layer 214 the 4th opening (not shown), described the
Four openings expose the surface of the first conductive plunger 213, grid structure 208 and fuse-wires structure 204 liang
The surface of end；The second conductive plunger 215 is formed in described 4th opening.
The material of described second dielectric layer 214 is silica, and formation process is depositing operation, it is preferred that
Chemical gaseous phase deposition work technique；The formation process of described 4th opening is anisotropic dry etch process；
The material of described second conductive plunger 215 is copper, tungsten or aluminium, formation process and the first conductive plunger 213
Technique identical, do not repeat.
The second conductive plunger 215 and fuse-wires structure 204 table that 204 liang of end surfaces of described fuse-wires structure are formed
The metal silicide layer 211 in face connects, for the metal silicide layer to described fuse-wires structure 204 surface
211 input high-voltage pulses, with the fuse area of the described fuse-wires structure 204 that fuses；Described first conductive plunger
213 and second conductive plunger 215 on grid structure 208 surface for realizing the electrical interconnection of transistor.
In the present embodiment, the polysilicon layer 202(on fleet plough groove isolation structure 201 surface is as shown in Figure 6) low
In the polysilicon layer 202 on Semiconductor substrate 200 surface, make formed fuse-wires structure 204 less than described puppet
Grid 203；And the dielectric layer 207 being used for isolating device flushes with dummy grid 203, the most described dielectric layer
207 cover described fuse-wires structure 204, protect described fuse-wires structure surface 204 in subsequent technique；Secondly,
The dielectric layer 207 of described fuse-wires structure 204 surface and stressor layers 206 is removed simultaneously, with remaining medium
Layer 207 is mask, it is possible to form metal silicide at fuse-wires structure 204 and stressor layers 206 surface simultaneously
Layer 211, thus save process time and cost；Again, due to the metal silication on fuse-wires structure 204 surface
Nitride layer 211 is less than dielectric layer 207 surface, therefore during forming the first conductive plunger 213, changes
Learn mechanical polishing process and will not destroy the metal silicide layer 211 on fuse-wires structure 204 surface, make to be formed
Fuse-wires structure is functional.
In sum, the dummy grid of semiconductor substrate surface it is formed at higher than being formed at fleet plough groove isolation structure
The fuse-wires structure on surface, it is possible to make the metal silicide layer being formed at fuse-wires structure surface less than being subsequently formed
Grid structure；Therefore, the dielectric layer flushed with dummy grid height can cover described fuse-wires structure surface,
Fuse-wires structure surface can be protected in removal dummy grid the technique forming grid structure；Additionally,
During being subsequently formed conductive plunger, owing to needing to remove the conductive layer higher than dielectric layer surface, therefore
When the metal silicide layer on fuse-wires structure surface is less than described dielectric layer, it is possible to avoid removing conductive layer
Technique in, described metal silicide layer sustains damage, thus ensure that the stable performance of fuse-wires structure.
Further, owing to the dielectric layer of stressor layers and fuse-wires structure surface is removed simultaneously, and stressor layers
The metal silicide on surface and fuse-wires structure surface is formed in same processing step, thus simplifies technique
Step, has saved cost.
Although the present invention is open as above with preferred embodiment, but it is not for limiting the present invention, appoints
What those skilled in the art without departing from the spirit and scope of the present invention, may be by the disclosure above
Technical solution of the present invention is made possible variation and amendment by method and technology contents, therefore, every does not takes off
From the content of technical solution of the present invention, it is any that above example is made by the technical spirit of the foundation present invention
Simple modification, equivalent variations and modification, belong to the protection domain of technical solution of the present invention.
Claims (21)
1. the forming method of a semiconductor devices, it is characterised in that including:
Thering is provided Semiconductor substrate, have fleet plough groove isolation structure in described Semiconductor substrate, the surface of described fleet plough groove isolation structure flushes with the surface of Semiconductor substrate；
Forming dummy grid at described semiconductor substrate surface, form fuse-wires structure at described surface of shallow trench isolation structure, the height of described fuse-wires structure is less than the height of dummy gate pole；
Forming stressor layers in the Semiconductor substrate of both sides, dummy gate pole, described stressor layers surface less than described fuse-wires structure surface or flushes with described fuse-wires structure surface；
Forming dielectric layer at described fuse-wires structure, stressor layers, Semiconductor substrate and surface of shallow trench isolation structure, the surface of described dielectric layer flushes with the top of dummy grid, and described dielectric layer covers described fuse-wires structure surface and the sidewall of dummy grid；
After forming dielectric layer, remove dummy gate pole, form grid structure in the position of dummy gate pole；
After formation of the gate structure, remove described stressor layers and the dielectric layer on fuse-wires structure surface, form the first opening and second opening on fuse-wires structure surface on stressor layers surface；
Metal silicide layer is formed on the fuse-wires structure surface of the stressor layers surface of described first open bottom and the second open bottom；
After forming described metal silicide layer, formed and fill full described first opening and the second opening and cover the conductive layer of described dielectric layer and grid structure；
Remove the conductive layer higher than dielectric layer surface, in the first opening, form the first conductive plunger；
Wherein, the forming method of described semiconductor devices also includes: before forming stressor layers, forms side wall in dummy gate pole and fuse-wires structure both sides；Stressor layers is formed in the Semiconductor substrate of dummy gate pole and side wall both sides；
Wherein, described side wall includes being positioned at the pseudo-side wall outside dummy gate pole and the first side wall of described fuse-wires structure both sides and described first side wall；Wherein, described pseudo-side wall is subsequently formed in dummy gate pole and the position of the stressor layers of described side wall both sides for definition；
Wherein, the forming method of dummy gate pole and fuse-wires structure is: at described Semiconductor substrate and surface of shallow trench isolation structure deposit polycrystalline silicon layer；It is etched back to the polysilicon layer of surface of shallow trench isolation structure, makes the polysilicon layer polysilicon layer less than semiconductor substrate surface of surface of shallow trench isolation structure；After being etched back to technique, etched portions polysilicon layer, till exposing Semiconductor substrate and fleet plough groove isolation structure, forms dummy grid and fuse-wires structure.
2. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that low 10 nanometer-50 nanometers of height of the aspect ratio dummy gate pole of described fuse-wires structure.
3. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the material of dummy gate pole and fuse-wires structure is polysilicon.
4. the forming method of semiconductor devices as claimed in claim 3, it is characterised in that having Doped ions in the polycrystalline silicon material of described fuse-wires structure, described Doped ions includes: boron, phosphorus or arsenic.
5. the forming method of semiconductor devices as claimed in claim 4, it is characterised in that described Doped ions uses doping process or ion implantation technology in situ to be formed in described polysilicon.
6. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the sidewall of described stressor layers and semiconductor substrate surface, in " Σ " shape, extend in the sidewall of described stressor layers Semiconductor substrate below dummy gate structure.
7. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the material of described stressor layers is SiGe or carborundum.
8. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that described grid structure includes: is positioned at the high-K dielectric layer of semiconductor substrate surface and is positioned at the metal gate layers on described high-K dielectric layer surface.
9. the forming method of semiconductor devices as claimed in claim 8, it is characterised in that also include: the silicon oxide layer between described Semiconductor substrate and high-K dielectric layer and the protective layer between described high-K dielectric layer and metal gate layers.
10. the forming method of semiconductor devices as claimed in claim 9, it is characterised in that one or both combinations in the material titanium nitride of described protective layer and tantalum nitride.
The forming method of 11. semiconductor devices as claimed in claim 8, it is characterised in that the forming method of described grid structure includes: etching dummy gate pole also exposes semiconductor substrate surface, forms the 3rd opening；High-K dielectric layer is formed in the bottom of described 3rd opening；The metal gate layers filling full described 3rd opening is formed on described high-K dielectric layer surface.
The forming method of 12. semiconductor devices as claimed in claim 8, it is characterized in that, the material of described high-K dielectric layer is: hafnium oxide, hafnium silicon oxide, nitrogen hafnium oxide, nitrogen hafnium silicon oxide, nitrogen hafnium oxide tantalum, zirconium oxide, nitrogen zirconium oxide, nitrogen zirconium silicon oxide, zirconium silicon oxide, lanthana, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminum oxide.
The forming method of 13. semiconductor devices as claimed in claim 8, it is characterised in that the material of described metal gate layers is: one or more combinations in aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum and tungsten.
The forming method of 14. semiconductor devices as claimed in claim 1, it is characterised in that the material of described metal silicide layer is nisiloy, titanium silicon or cobalt silicon.
The forming method of 15. semiconductor devices as claimed in claim 1, it is characterized in that, the forming method of described metal silicide layer is: on the stressor layers surface of the first open bottom, the fuse-wires structure surface of the second open bottom and dielectric layer surface deposition metal level, the material of described metal level is nickel, titanium or cobalt；After forming metal level, carry out thermal annealing, make the metal in metal level combine with the silicon in stressor layers and fuse-wires structure, form metal silicide layer；Remove the metal level of metal silicide layer surface residual.
The forming method of 16. semiconductor devices as claimed in claim 1, it is characterised in that described removal is CMP process higher than the technique of the conductive layer of dielectric layer surface.
The forming method of 17. semiconductor devices as claimed in claim 1, it is characterised in that also include: after removing the conductive layer higher than dielectric layer surface, uses and is etched back to remaining conductive layer in technique removes the second opening.
The forming method of 18. semiconductor devices as claimed in claim 1, it is characterised in that the material of described conductive plunger is copper, tungsten or aluminium.
The forming method of 19. semiconductor devices as claimed in claim 1, it is characterised in that the material of described dielectric layer is silica.
The forming method of 20. semiconductor devices as claimed in claim 1, it is characterised in that the surface of described stressor layers is less than described fuse-wires structure surface 5 nanometer-10 nanometer, higher than surface 10 nanometer-50 nanometer of Semiconductor substrate.
The forming method of 21. semiconductor devices as claimed in claim 1, it is characterized in that, also include: form second dielectric layer on described dielectric layer, grid structure and fuse-wires structure surface, having the 4th opening in described second dielectric layer, described 4th opening exposes surface and the surface at described fuse-wires structure two ends of the first conductive plunger；The second conductive plunger is formed in described 4th opening.
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| CN107978556A (en) * | 2017-11-21 | 2018-05-01 | 长江存储科技有限责任公司 | A kind of preparation method of 3D nand flash memories wordline connection structure |
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| TW201101422A (en) * | 2009-06-18 | 2011-01-01 | United Microelectronics Corp | Metal gate transistor and resistor and method for fabricating the same |
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| TW201101422A (en) * | 2009-06-18 | 2011-01-01 | United Microelectronics Corp | Metal gate transistor and resistor and method for fabricating the same |
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