CN104183543B - Electrical fuse structure and formation method thereof and semiconductor device - Google Patents
Electrical fuse structure and formation method thereof and semiconductor device Download PDFInfo
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- CN104183543B CN104183543B CN201310193706.XA CN201310193706A CN104183543B CN 104183543 B CN104183543 B CN 104183543B CN 201310193706 A CN201310193706 A CN 201310193706A CN 104183543 B CN104183543 B CN 104183543B
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Abstract
The invention provides an electrical fuse structure and a formation method thereof and a semiconductor device. The formation method of the electrical fuse structure comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is provided with raised fin portions, the fin portions being made of semiconductor materials, and the fin portions being subjected to first type of doping; carrying out second type of doping, and the fin portion tops being subjected to the second type of doping serving as a fuse; or carrying out second type of doping on the fin portion tops, and then, forming metal silicide on the fin portions, the fin portion tops being subjected to the second type of doping and the metal silicide jointly serving as the fuse, wherein the second type of doping is opposite to the first type of doping, and the doping dosage of the second type of doping is larger than that of the first type of doping; forming an inter-layer dielectric layer covering the fuse and the substrate; and forming conductive plugs in the inter-layer dielectric layer, the conductive plugs being at the two ends of the fuse respectively. The invention provides the method for forming the electrical fuse structure on the fin portions so as to realize diversity of the method for forming the electrical fuse structure on the semiconductor device.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly to a kind of electric fuse structure and forming method thereof, semiconductor device
Part.
Background technology
In integrated circuit fields, fuse（Fuse）Refer to that some resistance being formed in integrated circuits can occur significantly
Change（Changed from low resistance state to high-impedance state）Or the connecting line that can fuse.Initially, fuse is for connecting in integrated circuit
Redundant circuit, once detection find integrated circuit there is defect, just using fuse reparation or replacement defective circuit.Molten
Silk is generally laser fuse（Laser Fuse）And electric fuse（Electrical Fuse, hereinafter referred to as E-fuse）Two kinds.With
The development of semiconductor technology, E-fuse gradually instead of laser fuse.
General, electric fuse structure can use metal（Aluminium, copper etc.）Or silicon makes, with reference to Fig. 1, a kind of allusion quotation in prior art
The electric fuse structure of type forms fleet plough groove isolation structure in the semiconductor substrate（STI）On 100, it includes anode 101 and the moon
Pole 103, and it is located at the fuse 102 of the fine strip shape being connected between anode 101 and negative electrode 103, its Anodic 101 He with both
Negative electrode 103 surface has conductive plunger 104.When passing through larger immediate current between anode 101 and negative electrode 103, fuse 102
Resistance can significantly alter or can be blown.Wherein, if fuse 102 is blown, the state that fuse 102 is not blown
Under, it is low resistance state at electric fuse structure（If resistance is R）, after fuse 102 is blown in the state of, at electric fuse structure be height
Resistance state（If resistance is infinity）.Because it has, the characteristic that low-resistance converts to high resistant, electric fuse structure be can achieve by electric current
Except in addition to the application in redundant circuit, also having wider application, such as：Built-in self-test（Build in self test, letter
Claim BIST）Technology, self-repair technology, one-time programming（One Time Program, abbreviation OTP）Chip, on-chip system（System
On Chip, abbreviation SoC）Etc..
In prior art, with reference to Fig. 1, the forming method of electric fuse structure is as follows：
First, Semiconductor substrate is provided, forms fleet plough groove isolation structure 100 in described Semiconductor substrate；
Then, form polysilicon layer on described fleet plough groove isolation structure 100 surface, form figure on the surface of polysilicon layer
The mask layer changed, with described patterned mask layer for mask etching polysilicon layer, formation two ends are roomy, and are connected with two ends
The semiconductor structure of the intermediate elongated connecing.Wherein, the roomy place in two ends is anode 101 and negative electrode 103, is fuse at intermediate elongated
102.Form conductive plunger 104 on the surface of described anode 101 and negative electrode 103.
The invention provides a kind of method that electric fuse structure is formed on fin, to realize being formed on the semiconductor device
The diversity of electric fuse structure method.
Content of the invention
The problem that the present invention solves has been to provide a kind of method forming electric fuse structure on fin, to realize half
The diversity of electric fuse structure method is formed on conductor device.
For solving the above problems, the invention provides a kind of forming method of electric fuse structure, including：
There is provided Semiconductor substrate, described Semiconductor substrate has the fin of projection, and the material of described fin is semiconductor material
Material, described fin has carried out first kind doping；
Second Type doping is carried out to the top of described fin, the fin top having carried out Second Type doping is as molten
Silk, described Second Type is contrary with the first kind, and the dopant dose of described Second Type doping is more than first kind doping
Dopant dose；Or,
Second Type doping is carried out to the top of described fin, afterwards, described fin forms metal silicide, carries out
The fin top of Second Type doping and described metal silicide collectively as fuse,
Described Second Type is contrary with the first kind, and the dopant dose of described Second Type doping is mixed more than the first kind
Miscellaneous dopant dose；
Form interlayer dielectric layer and form conductive plunger, described conductive plunger is at the two ends of described fuse.
In described interlayer dielectric layer, the two ends of described fuse form conductive plunger respectively.
Optionally, before the top of described fin is carried out with Second Type doping step, or the top to described fin
After carrying out Second Type doping, also comprise the following steps before the step that metal silicide is formed on described fin：
Form groove in described fin, described groove is located at the two ends of described fin；
Form semi-conducting material in described groove；
The surface of the semi-conducting material in described groove forms silicon layer；
Described conductive plunger is located on described silicon layer.
Optionally, when Second Type is doped to p-type, described semi-conducting material is germanium silicon, and described groove is that sigma shape is recessed
Groove；
When Second Type is doped to N-type, described semi-conducting material is carborundum, and described groove is U-shaped groove.
Optionally, when Second Type is doped to p-type, the forming method of described fin includes：
Form p-type doped region in described Semiconductor substrate, above described p-type doped region, carry out first kind doping
Form N-type well region；
Etch the fin that described N-type well region forms projection.
Optionally, when Second Type is doped to N-type, the forming method of described fin includes：
Form p-type doped region in described Semiconductor substrate, form n-type doping area above described p-type doped region,
Carry out first kind doping above described n-type doping area and form P type trap zone；Etch the fin that described P type trap zone forms projection.
Optionally, also comprise the following steps before the step that the top of described fin is carried out with Second Type doping：
Form silicon layer at the top of described fin；
When described fin top is carried out with Second Type doping, also Second Type doping is carried out to described silicon layer.
Optionally, described Semiconductor substrate has first area and second area, and described first area is used for forming fin
Field-effect transistor, described fuse is formed at described second area, the fin of described fin and described fin formula field effect transistor
Same processing step is formed.
Optionally, when the fin two ends of described second area have groove, there is in described groove semi-conducting material, institute
State that the described groove of second area and the source of described first area, the groove shapes in drain electrode are identical, described second area institute
State the source of the semi-conducting material in groove and described first area, semi-conducting material is identical in drain electrode.
Optionally, the Second Type doping step top of the fin of second area being carried out, with formation first area
Source in described fin formula field effect transistor, the doping step of drain electrode are same step.
Optionally, the source electrode in the fin formula field effect transistor in the forming step of described conductive plunger, with first area,
The forming step of the conductive plunger in drain electrode is same step.
Optionally, the forming method of described conductive plunger includes：
Form patterned mask layer on the surface of described interlayer dielectric layer；
With described patterned mask layer as mask, etch described interlayer dielectric layer, formed in described interlayer dielectric layer
Opening, described fuse is exposed in the bottom of described opening；
Described opening is filled using conductive layer, forms conductive plunger.
The present invention also provides a kind of electric fuse structure, including：
There is the Semiconductor substrate of the fin of projection, the material of described fin is semi-conducting material；
Described fin has first kind doped region；
On described first kind doped region and be located at described fin top Second Type doped region, fuse be described
The described Second Type doped region at fin top；Or,
On described first kind doped region and be located at described fin top Second Type doped region, positioned at described fin
The metal silicide at portion top, described fuse is the described Second Type doped region at described fin top and described metal silication
Thing；
The described first kind and described Second Type is contrary and dopant dose of the doping of described Second Type is more than the first kind
The dopant dose of type doping；
Cover the interlayer dielectric layer of described fuse；
Conductive plunger, in described interlayer dielectric layer and be located at described fuse two ends.
Optionally, described fin has the groove of the full semi-conducting material of filling, and described groove is located at the two ends of described fuse,
Described conductive plunger is located on described semi-conducting material.
Optionally, the upper surface of described fin has the silicon layer being doped with impurity, the dopant type of doping in described silicon layer
Identical with the doping type of described Second Type doped region；
When the top of fin has metal silicide, have between described fin and described metal silicide be doped with miscellaneous
The silicon layer of matter, in described silicon layer, impurity type is identical with the doping type of the doped region of described Second Type.
The present invention also provides a kind of semiconductor devices it is characterised in that including：
Fin formula field effect transistor；
The electric fuse structure being formed by said method, described fin formula field effect transistor and described electric fuse structure are located at same
In semi-conductive substrate.
Compared with prior art, technical scheme has advantages below：
The invention provides a kind of method that electric fuse structure is formed on fin, to realize being formed on the semiconductor device
The diversity of electric fuse structure method.
Further, the step that is integrally formed of the electric fuse structure of the present invention colonizes in same Semiconductor substrate
Among the forming step of fin formula field effect transistor, therefore, the method for the present invention is simple.
Brief description
Fig. 1 is a kind of schematic perspective view of electric fuse structure of the prior art；
Fig. 2 is the schematic flow sheet of the electric fuse structure forming method in the embodiment of the present invention；
Fig. 3 is the perspective view of the intermediate structure of the electric fuse structure in the embodiment of the present invention one；
Fig. 4 is the cross-sectional view along AA direction for the Fig. 3；
Fig. 5 to Figure 12 is the cross-sectional view of the electric fuse structure forming method in the embodiment of the present invention one；
Figure 13 and Figure 14 is the cross-sectional view of the electric fuse structure forming method in the embodiment of the present invention two.
Specific embodiment
The invention provides a kind of method that electric fuse structure is formed on fin formula field effect transistor, to realize partly leading
The diversity of electric fuse structure method is formed on body device.
Understandable for enabling the above objects, features and advantages of the present invention to become apparent from, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Embodiment one
Fig. 2 is the schematic flow sheet of the electric fuse structure forming method in the embodiment of the present invention.Fig. 3 is the embodiment of the present invention
The perspective view of the intermediate structure of the electric fuse structure in.Fig. 4 is the cross-sectional view along AA direction for the Fig. 3.
Fig. 5 to Figure 12 is the cross-sectional view of the electric fuse structure forming method in the embodiment of the present invention one.
With reference first to Fig. 3 and Fig. 4, execute step S11 in Fig. 2, Semiconductor substrate 200, described Semiconductor substrate are provided
200 fins 204 with projection, the material of described fin 204 is semi-conducting material, and described fin 204 has carried out the first kind
Doping.
In the present embodiment, the step that is integrally formed of electric fuse structure is the fin field colonizing in same Semiconductor substrate
Among the forming step of effect transistor, therefore, in order to clearly describe the present invention, in conjunction with reference Fig. 3 and Fig. 4, this
Semiconductor substrate 200 is divided into first area Ι and second area Ι Ι by embodiment, and first area Ι is used for forming fin field effect crystalline substance
Body pipe, second area Ι Ι is used for forming electric fuse structure.
Semiconductor substrate 200 can be silicon substrate or germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate.
Semiconductor substrate 200 in the present embodiment more preferably selects silicon substrate because on a silicon substrate implement the present invention than above-mentioned its
The low cost of the present invention is implemented on his Semiconductor substrate.Especially than the low cost that the present invention is implemented on silicon substrate on insulator.
In the present embodiment, etch the fin 204 that described silicon semiconductor substrate 200 forms projection, this fin 204 has first
Type is adulterated, and the fin 204 of the fin 204 of described first area Ι and second area Ι Ι is formed in same processing step.Its
In, first kind doping is contrary with the follow-up Second Type doping being formed at the top of second area fin 204.
In the present embodiment, the Second Type subsequently carrying out at the top of the fin 204 of second area Ι Ι is doped to p-type, then
The forming method of the fin 204 of first area Ι and second area Ι Ι is specially：With reference to Fig. 4, first in Semiconductor substrate 200
P-type doped region 201 is formed on bottom, then forms N-type well region 202 above p-type doped region 201.Etch described N-type well region
202 form raised fin 204, and now the doping type of the entirety of fin 204 is N-type.Certainly, in other embodiments,
N-type doping area can be formed in the bottom of Semiconductor substrate, specifically, after forming n-type doping area, above n-type doping area
Form p-type doped region, form N-type well region on p-type doped region.Why so adulterate, be because between Semiconductor substrate
Isolation effect relatively good, can preferably block bottom interference.Then, etching N-type well region forms the fin of projection, now fin
The overall doping type in portion is also N-type.
It should be noted that the Second Type subsequently carrying out at the top of the fin 204 of second area Ι Ι is doped to p-type
When, resistivity when forming p-type doped region in the bottom of Semiconductor substrate is mixed with respect in the bottom of Semiconductor substrate formation N-type
Resistivity during miscellaneous area is low.Those skilled in the art can select first area Ι and second area Ι Ι according to the needs of oneself
Fin method.
In other embodiment, when the Second Type subsequently carrying out at the top of the fin of second area is doped to N-type, then
The forming method of the fin of first area Ι and second area Ι Ι is specially：Form n-type doping in the bottom of Semiconductor substrate first
Area, then forms P type trap zone above n-type doping area.Etching P type trap zone forms the fin of projection, and now fin is overall
Doping type is p-type.In other embodiments it is also possible to form p-type doped region in the bottom of Semiconductor substrate, then in p-type
Form n-type doping area above doped region, form P type trap zone on n-type doping area.Why so adulterate, be because half
Isolation between conductor substrate is relatively good, can preferably block bottom interference, and form p-type in the bottom of Semiconductor substrate
Resistivity during doped region is low with respect to resistivity when forming n-type doping area in the bottom of Semiconductor substrate.Then, etch P
Type well region forms the fin of projection, and now the overall doping type of fin is p-type.
In other embodiments, Semiconductor substrate can also be silicon-on-insulator substrate, described silicon-on-insulator substrate bag
Include bottom silicon layer, the insulating barrier being located on bottom silicon layer, the top silicon layer being located on insulating barrier.Etching top silicon layer forms fin
Portion, then carries out first kind doping to fin, and silicon-on-insulator substrate can also be divided into first area and second area, and first
Region is used for being formed fin formula field effect transistor, and second area is used for being formed electric fuse structure, and, described first area Ι
The fin of fin and second area Ι Ι is formed in same processing step.Fin to first area Ι and the fin of second area Ι Ι
After portion carries out first kind doping, in order to form fuse, follow-up needs carry out Second Type at the top of the fin of second area
Doping, wherein Second Type doping is contrary with first kind doping.Fall within protection scope of the present invention.
In the present embodiment, Semiconductor substrate 200 also includes between each fin 204 and less than fin 204 shallow ridges
Recess isolating structure 203（STI）.Described fleet plough groove isolation structure 203 is used for the different fins in described Semiconductor substrate 200
204 isolation, the material of described fleet plough groove isolation structure 203 is silica, and the forming method of described fleet plough groove isolation structure is this
Skilled person knows technology, will not be described here.
In the present embodiment, Second Type doping is carried out to the top of fin 204, the step forming fuse 216 is second
Region Ι Ι is carried out, with the described fin formula field effect transistor of first area Ι in source, drain electrode in doping step be same step
Suddenly.Specific as follows：
Continuing with reference to Fig. 3 and Fig. 4, step S12 in execution Fig. 2, grid are formed on the fin 204 of first area Ι
Pole structure 205, the top of fin 204 and side wall described in described grid structure 205 covering part.
In the present embodiment, described grid structure 205 includes gate dielectric layer 206 and is formed at the grid above gate dielectric layer 206
Pole 207.The material of gate dielectric layer 206 is high-k gate dielectric layer, and the material of high-k gate dielectric layer is HfO2、Al2O3、ZrO2、HfSiO、
HfSiON, HfTaO and HfZrO.Grid 207 is dummy grid, and the material of dummy grid is polysilicon.
Referring next to Fig. 5, execute step S13 in Fig. 2, formation side wall 208 around grid structure 205, with side wall
208 is the fin 204 of mask etching first area Ι, forms groove 209, second area Ι Ι fin in the fin of side wall 208 both sides
The groove 209 in portion and the groove 209 of first area Ι are formed in same etch step, the fin of first area Ι and second area Ι Ι
After portion 204 forms described groove 209, filling semiconductor material 210 in described groove 209.
In the present embodiment, the type of the fin formula field effect transistor being subsequently formed is p-type, and this groove is preferably sigma type
Groove, in the range of effective dimensions, the sharp corner of sigma type groove, closer to channel region, is conducive to subsequently in channel region shape
Become larger compression, to improve the carrier mobility of channel region, improve the property of the fin formula field effect transistor being subsequently formed
Energy.In other embodiments, this groove can also be other shapes, such as rectangle.After forming sigma type groove, in sigma type
Filling semiconductor material 210 in groove, in the present embodiment, semi-conducting material is germanium silicon material.Concrete formation process is this area
Technical staff knows technology, will not be described here.
Certainly, in other embodiments, when the type of the fin formula field effect transistor being subsequently formed is N-type, this groove
Preferably U-shaped groove, in the range of effective dimensions, U-shaped groove is conducive to subsequently forming larger tension in channel region, to carry
The carrier mobility of high channel region, improves the performance of the fin formula field effect transistor being subsequently formed.After forming U-shaped groove, in U
In type groove, the semi-conducting material of filling is carborundum.
It should be noted that with continued reference to Fig. 5, in the present embodiment, forming groove 209 in the fin 204 of first area Ι
Meanwhile, the fin 204 in second area Ι Ι also forms groove 209.The position of the fin 204 in second area Ι Ι for the groove 209 with
The position of this fin in first area Ι for the groove 209 is identical.The shape of second area Ι Ι groove 209, packing material and the firstth area
The shape of groove 209 of domain Ι, packing material are identical.Formed in groove 209 and groove 209 in the fin 204 of second area Ι Ι
Semi-conducting material so that the contact between the follow-up conductive plunger in the fuse-wires structure that second area Ι Ι is formed and fuse
Resistance reduces.Further, when the groove 209 being formed in second area Ι Ι fin 204 is sigma type or when U-shaped, can drop
Contact resistance between the conductive plunger of low fuse-wires structure and fuse.Further, in second area Ι Ι with first area Ι
Inside form groove 209 and its interior semi-conducting material simultaneously, the now groove structure similarity highest in this two regions, thus can
So that the contact resistance between conductive plunger in second area Ι Ι and fuse is preferably minimized.
In other embodiments, groove can be formed in the fin of first area and second area by substep.
In other embodiments it is also possible to not form described groove in the fin of second area.
With reference to Fig. 6, step S14 in execution Fig. 2, on semi-conducting material 210 surface of first area Ι and second area Ι Ι
Form silicon layer 211（Si Cap）.
The concrete grammar forming described silicon layer 211 knows technology for those skilled in the art, will not be described here.First
Semi-conducting material 210 surface of region I and second area II forms silicon layer 211, and this silicon layer 211 can prevent subsequently in semiconductor
Second Type doping diffusion in material 210, and then can ensure that source electrode, the resistance of drain electrode being subsequently formed in the I of first area
Rate is low, but also can ensure that the semi-conducting material 210 subsequently carrying out Second Type doping in second area II resistivity low.
Then, with reference to Fig. 7, execute step S15 in Fig. 2, after forming silicon layer 211, to first area Ι and second area Ι Ι
Fin 204 in semi-conducting material 210, the silicon layer 211 on semi-conducting material 210 surface and second area Ι Ι fin top
Carry out Second Type doping, form doped region 214, described Second Type is contrary with the first kind, and the doping of described Second Type
Dopant dose be more than the first kind doping dopant dose.
This Second Type doping step forms doped region 214, this Second Type doping step in the fin 204 of second area Ι Ι
The rapid source electrode 212 forming fin formula field effect transistor in the Ι of first area and drain electrode 213.In second area Ι Ι, Second Type is mixed
The contrary meeting that is to say, that Second Type doping and the first kind are adulterated of miscellaneous and original in fin 204 first kind doping type
Form P-N junction, this P-N junction has buffer action to fuse.
The forming step of the P-N junction in the present embodiment is also the formation of the fin formula field effect transistor colonizing in first area
Among step, therefore, almost nil cost.And, the present embodiment just can form the isolation to fuse simply by doping,
Therefore, method is simple.In addition, also being started using the method that the P-N junction on fin in the second area is isolated to fuse
Directly form the precedent of fuse on the active area.Reason is as follows：Fuse of the prior art be can not be formed directly into active
In area, active area belongs to large-area semiconductor structure, the especially very big semiconductor structure of width, even if having on fuse
There is larger immediate current, the substantial amounts of heat that this electric current produces also can shed from large-area active area, therefore, existing skill
In art, need insulating barrier and fleet plough groove isolation structure to be provided below in fuse.And the P-N junction below the fuse of the present invention is just permissible
The technique realizing forming fuse on the active area.
With reference to Fig. 8, step S16 in execution Fig. 2, after forming doped region 214, first area Ι's and second area Ι Ι
Silicon layer 211, on the doped region 214 at the fin top of second area Ι Ι formed metal silicide layer 215.Wherein, on silicon layer
Metal silicide layer 215 can reduce the contact resistance between silicon layer 211 and the conductive plunger being subsequently formed.Need explanation
It is that metal silicide layer 215, then this metal silicide layer 215 are formed on the doped region 214 at the fin top of second area Ι Ι
Collectively form fuse 216 with the doped region 214 at the fin top of second area Ι Ι, when subsequent technique formed anode and negative electrode it
Between when there is larger immediate current, fuse 216 has two kinds by the situation that low resistance state changes into high-impedance state：（1）Metal silicide
The resistivity of layer 215 is less than doped region 214, and therefore, between anode and negative electrode, larger immediate current can be preferentially from metal silication
Flow through in 215 layers of nitride layer, so that the inside of metal silicide layer 215 occurs electromigration（Electromigration, EM）
Phenomenon that is to say, that the metal ion great majority in metal silicide layer 215 all migrate to negative electrode or anode so that
The inside of metal silicide layer 215 produces cavity so that the resistance of metal silicide layer 215 increases considerably, and then makes molten
The resistance of silk 216 increases considerably, and changes into high-impedance state by low resistance state.（2）Larger immediate current between anode and negative electrode
Substantial amounts of heat energy can be produced, metal silicide layer 215 can be fused together with doped region 214 by this substantial amounts of heat energy, so that
The resistance of fuse 216 increases considerably, and changes into high-impedance state by low resistance state.Certainly, in other embodiments, in second area Ι Ι
The doped region 214 at fin top on can not also form metal silicide layer 215, also can implement the present invention.Fuse now
It is only doped region 214, when there is larger immediate current between the anode that subsequent technique is formed and negative electrode, in doped region 214
Impurity also can migrate, migrate to male or female, thus the resistance of doped region 214 can be made to increase considerably,
High-impedance state is changed into by low resistance state.
In other embodiment, the semiconductor material surface in the groove of first area and second area forms silicon layer（Si
Cap）While, silicon layer can also be formed in the upper surface of the fin of second area.Therefore, the fin top of second area is entered
While the doping of row Second Type forms doped region, the silicon layer that also upper surface of the fin of second area can be formed carries out second
Type is adulterated, and forms fuse together.The silicon layer that fuse includes being formed in second area fin upper surface has following benefit：Can in case
Only the Second Type doping diffusion at the fin top of second area is so that the Second Type doping at the fin top of second area
Distribution is narrow, thus reducing the resistivity of the doped region at fin top of second area so that the condition of fuse failure is more held
Easy to control, and then improve the utility ratio of fuse.When the fuse at the fin top in second area has a plurality of, above-mentioned benefit meeting
Become apparent from.
In other embodiments, when the upper surface in the fin of second area has silicon layer, on the fin of second area
Metal silicide layer be formed on silicon layer.
Then, with reference to Fig. 9, execute step S17 in Fig. 2, form interlayer dielectric layer 217, cover described fuse 216.
In the present embodiment, form interlayer dielectric layer 217, cover Semiconductor substrate, fleet plough groove isolation structure 203, the firstth area
Metal silicide layer 215 on domain Ι and second area Ι Ι fin, the grid structure 205 in the Ι of first area and side wall 208.So
Afterwards, interlayer dielectric layer 217 higher than grid structure is removed using the method for chemically mechanical polishing so that interlayer dielectric layer 217
Surface is equal with the surface of grid structure 205.
It should be noted that when fuse 216 has larger immediate current, substantial amounts of heat, inter-level dielectric can be produced
Layer 217 covering fuse 216 can make this heat cannot Quick diffusing go out, and is more beneficial for the fusing of fuse 216.
In the present embodiment, with reference to Fig. 4, in grid structure 205, grid 207 is dummy grid, continues with reference to reference 9 and Figure 10,
After forming interlayer dielectric layer 217, need to remove the grid 207 in the Ι of first area, be internally formed grid in interlayer dielectric layer 217
Pole groove 218, high-k gate dielectric layer is exposed in the bottom of gate recess 218.With reference to Figure 11, form metal gate in gate recess 218
Pole 219.Remove grid 207 and form that the technique of metal gates 219 broadly falls into those skilled in the art know technology, here is not
Repeat again.
With reference to Figure 12, in the present embodiment, after forming metal gates 219, interlayer is continuously formed on interlayer dielectric layer 217 and is situated between
Matter layer 220.
Then, with continued reference to Figure 12, execute step S18 in Fig. 2, in described interlayer dielectric layer 217, described fuse
216 two ends form conductive plunger 221 respectively.
Fin field in the present embodiment, in the forming step of the conductive plunger at fuse two ends being subsequently formed and first area
The forming step of the conductive plunger on source electrode 212 and drain electrode 213 in effect transistor is same step.Specifically include：
Then, the surface in interlayer dielectric layer 220 forms patterned mask layer（Not shown）, patterned covered with described
Film layer is mask, etches described interlayer dielectric layer 217 and 220, forms several openings in interlayer dielectric layer 217 and 220,
First area Ι, the metal silicide layer 215 in described source electrode 212 and drain electrode 213 is exposed in the bottom of this opening；In second area Ι
Ι, the metal silicide layer 215 at described fuse 216 two ends is exposed in the bottom of this opening.After forming opening, using conductive layer filling
Described opening, forms conductive plunger 221, wherein conductive layer is metal, can be metallic copper or tungsten in the present embodiment.
In other embodiments, after the top of the fin of second area is carried out with Second Type doping formation doped region, can
Inter-level dielectric is formed with the surface of the directly silicon layer on Semiconductor substrate, semi-conducting material, grid structure, side wall and doped region
Layer, after forming interlayer dielectric layer, removes dummy grid, forms metal gates in high-k gate dielectric layer surface, then, in inter-level dielectric
Layer be internally formed opening, the silicon layer of semiconductor material surface is exposed in the bottom of described opening, then in the silicon layer of open bottom
Upper formation metal silicide layer, after forming metal silicide layer, filling opening forms conductive plunger.It should be noted that this is real
Apply example and cannot form metal silicide layer on doped region, or, when silicon layer is had on doped region, also cannot on silicon layer shape
Become metal silicide layer.Therefore, this doped region is fuse.
The present invention provide not only a kind of method forming electric fuse structure on fin, to realize on the semiconductor device
Form the diversity of electric fuse structure method, and the step that is integrally formed of the electric fuse structure in this method is to colonize in together
Among the forming step of fin formula field effect transistor in one Semiconductor substrate, therefore, the method for the present invention simple and
Process costs are almost nil.
Second embodiment
In the present invention, the technique of the fin formula field effect transistor in the Ι of first area is divided into high-k gate dielectric layer in front formation work
Skill（HK First）With high-k gate dielectric layer in rear formation process（HK Last）.Electric fuse structure in first embodiment is in height
K gate dielectric layer is formed during front formation process.Electric fuse structure in second embodiment is rear in high-k gate dielectric layer
Formed during formation process.
With reference to Figure 13 and Figure 14, the difference with first embodiment is：
（1）With reference to Figure 13, grid structure 305 is formed on the fin 304 of the first area Ι of Semiconductor substrate 300.Grid
Structure 305 includes gate dielectric layer 306 and is formed at the grid 307 above gate dielectric layer 306.Wherein, the material of gate dielectric layer 306
For silica, grid 307 remains as dummy grid.When removal dummy grid forms pseudo- grid recess, also remove gate dielectric layer 306.
（2）With reference to Figure 14, in high-k gate dielectric layer in rear formation process, the high-k gate dielectric layer 314 of formation covers grid
The bottom of groove and side wall.
It should be noted that this technique be high-k gate dielectric layer in rear formation process, need forming high-k gate dielectric layer 314
After metal gates 315, metal silicide layer 320 could be formed on silicon layer 311 in first area Ι and second area Ι Ι.
Reason is as follows：If forming high-k gate dielectric layer, moving back in high-k gate dielectric layer formation process after forming metal silicide layer
The resistance of the metal silicide layer being formed before can be increased considerably by ignition technique, thus destroying the performance of metal silicide layer.
In a second embodiment, in order to form high-k gate dielectric layer 314 and metal gates 315, subsequent technique has formation interlayer dielectric layer
317 and 318 step, the silicon layer 311 that this interlayer dielectric layer 317 and 318 covers in first area Ι and second area Ι Ι is worked as in layer
Between when forming the opening exposing silicon layer 311 in dielectric layer 317 and 318, metal silicide layer 320 could be formed in this opening,
Then form conductive plunger 321 with constitutive promoter.Therefore, in high-k gate dielectric layer in rear formation process it is impossible to doping
Form metal silicide in area 316, or, when there is silicon layer 311 on doped region 316, gold also cannot be formed on silicon layer 311
Belong to silicide.Therefore, this doped region 316 is fuse.
It should be noted that the formation process of the fuse-wires structure of the present invention is applicable not only to rear grid formation process, but also
It is applied to front grid technique.
3rd embodiment
3rd embodiment is distinguished as with first, second embodiment：
In the first embodiment of the present invention and second embodiment, electric fuse structure be integrally formed step be colonize in same
Among the forming step of the fin formula field effect transistor in individual Semiconductor substrate, in the third embodiment, electric fuse structure
It is integrally formed among the forming step of fin formula field effect transistor that step does not colonize in same Semiconductor substrate, Ke Yidan
Electric fuse structure is formed on only fin on a semiconductor substrate.
With reference to Figure 12, the present invention also provides a kind of electric fuse structure, including：
There is the Semiconductor substrate 200 of the fin 204 of projection, the material of described fin 204 is semi-conducting material；
Described fin 204 has first kind doped region；
On described first kind doped region and be located at described fin 204 top doped region 214, described doped region
214 is Second Type, and fuse is the described doped region 214 at described fin 204 top；Or,
On described first kind doped region and be located at described fin 204 top doped region 214, positioned at described fin
The metal silicide 215 at 204 tops, described fuse is the described doped region 214 at described fin 204 top and described metal silication
Thing 215；
The described first kind and described Second Type is contrary and dopant dose of the doping of described Second Type is more than the first kind
The dopant dose of type doping；
Cover the interlayer dielectric layer of described fuse；
Conductive plunger 221, in described interlayer dielectric layer, the two ends of described fuse.
In the present embodiment, described fin 204 has a groove 209 of the full semi-conducting material 210 of filling, described groove 209
In the two ends of described fuse, the surface of described semi-conducting material 210 has silicon layer 211, and the surface of described silicon layer 211 has metal
Silicide layer 215, described conductive plunger 221 is located on described metal silicide layer 215.
In other embodiments, described fin 204 can also not have described groove 209.
In other embodiments, the upper surface of described fin has the silicon layer of doping type identical with described doped region, institute
State fuse and include described silicon layer.
In other embodiments, the upper surface of described fin has the silicon layer of doping type identical with described doped region, institute
State fuse and include described silicon layer.And, the upper surface of described silicon layer has metal silicide.
In first embodiment of the invention, the content with regard to structure, material can be incorporated herein, and will not be described here.
The present invention also provides a kind of semiconductor devices, including：
Fin formula field effect transistor；
Above-described electric fuse structure, described fin formula field effect transistor and described electric fuse structure are located at and lead with half
On body substrate.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, without departing from this
In the spirit and scope of invention, all can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope limiting is defined.
Claims (15)
1. a kind of forming method of electric fuse structure is it is characterised in that include：
There is provided Semiconductor substrate, described Semiconductor substrate has the fin of projection, and the material of described fin is semi-conducting material, institute
State fin and carry out first kind doping；
Grid structure, the top of fin and side wall described in described grid structure covering part are formed on the fin of first area；
Formation side wall around grid structure；
With side wall for the fin of mask etching first area, in the fin of side wall both sides, form groove, second area fin
Groove is formed in same etch step with the groove of first area；
Filling semiconductor material in described groove；
Form silicon layer in the semiconductor material surface of first area and second area；
To the semi-conducting material in the fin of first area and second area, the silicon layer of semiconductor material surface and second area
The top of fin carry out Second Type doping, form doped region；
Form metal silicide on silicon layer in first area and second area, the doped region at fin top in second area,
Carried out Second Type doping fin top and described metal silicide collectively as fuse,
Described Second Type is contrary with the first kind, and the dopant dose of described Second Type doping is more than first kind doping
Dopant dose；
Form interlayer dielectric layer, cover described fuse and described Semiconductor substrate；
Form conductive plunger in described interlayer dielectric layer, described conductive plunger is at the two ends of described fuse.
2. electric fuse structure according to claim 1 forming method it is characterised in that
Before the top of described fin is carried out with Second Type doping step, or Second Type is carried out to the top of described fin
After doping, also comprise the following steps before the step that metal silicide is formed on described fin：
Form groove in described fin, described groove is located at the two ends of described fin；
Form semi-conducting material in described groove；
The surface of the semi-conducting material in described groove forms silicon layer；
Described conductive plunger is located on described silicon layer.
3. electric fuse structure according to claim 2 forming method it is characterised in that
When Second Type is doped to p-type, described semi-conducting material is germanium silicon, and described groove is sigma connected in star；
When Second Type is doped to N-type, described semi-conducting material is carborundum, and described groove is U-shaped groove.
4. the forming method of electric fuse structure according to claim 1 is it is characterised in that when Second Type is doped to p-type
When, the forming method of described fin includes：
Form p-type doped region in described Semiconductor substrate, carry out first kind doping above described p-type doped region and formed
N-type well region；
Etch the fin that described N-type well region forms projection.
5. the forming method of electric fuse structure according to claim 1 is it is characterised in that when Second Type is doped to N-type
When, the forming method of described fin includes：
Form p-type doped region in described Semiconductor substrate, form n-type doping area above described p-type doped region, described
Carry out first kind doping above n-type doping area and form P type trap zone；Etch the fin that described P type trap zone forms projection.
6. the forming method of electric fuse structure according to claim 1 is it is characterised in that carry out to the top of described fin
Also comprise the following steps before the step of Second Type doping：
Form silicon layer at the top of described fin；
When described fin top is carried out with Second Type doping, also Second Type doping is carried out to described silicon layer.
7. the forming method of electric fuse structure according to claim 1 is it is characterised in that described Semiconductor substrate has
One region and second area, described first area is used for forming fin formula field effect transistor, and described fuse is formed at described second
Region, the fin of described fin and described fin formula field effect transistor is formed in same processing step.
8. the forming method of electric fuse structure according to claim 7 is it is characterised in that work as the fin of described second area
When two ends have groove, there is in described groove semi-conducting material, the described groove of described second area and described first area
Source, the groove shapes in drain electrode identical, semi-conducting material in the described groove of described second area and described first area
Source, drain electrode in semi-conducting material identical.
9. the forming method of electric fuse structure according to claim 7 is it is characterised in that the top of fin to second area
Source in Second Type that portion is carried out doping step, with the described fin formula field effect transistor forming first area, the mixing of drain electrode
Miscellaneous step is same step.
10. the forming method of electric fuse structure according to claim 7 is it is characterised in that the formation of described conductive plunger
The forming step of the conductive plunger on the source electrode in fin formula field effect transistor in step, with first area, drain electrode is same
Step.
The forming method of 11. electric fuse structures according to claim 1 is it is characterised in that the formation of described conductive plunger
Method includes：
Form patterned mask layer on the surface of described interlayer dielectric layer；
With described patterned mask layer as mask, etch described interlayer dielectric layer, in described interlayer dielectric layer, form opening,
Described fuse is exposed in the bottom of described opening；
Described opening is filled using conductive layer, forms conductive plunger.
A kind of 12. electric fuse structures are it is characterised in that adopt the electric fuse structure as any one of claim 1 to 11
Forming method being formed, described electric fuse structure includes：
There is the Semiconductor substrate of the fin of projection, the material of described fin is semi-conducting material；
Described fin has first kind doped region；
On described first kind doped region and be located at described fin top Second Type doped region, fuse be described fin
The described Second Type doped region at top；Or,
On described first kind doped region and be located at described fin top Second Type doped region, positioned at described fin top
The metal silicide in portion, described fuse is the described Second Type doped region at described fin top and described metal silicide；
The described first kind and described Second Type is contrary and dopant dose of the doping of described Second Type is mixed more than the first kind
Miscellaneous dopant dose；
Cover the interlayer dielectric layer of described fuse；
Conductive plunger, in described interlayer dielectric layer and be located at described fuse two ends.
13. electric fuse structures according to claim 12 are it is characterised in that described fin has the full semi-conducting material of filling
Groove, described groove be located at described fuse two ends, described conductive plunger be located at described semi-conducting material on.
14. electric fuse structures according to claim 12 it is characterised in that the upper surface of described fin have be doped with miscellaneous
The silicon layer of matter, in described silicon layer, the dopant type of doping is identical with the doping type of described Second Type doped region；
When the top of fin has metal silicide, have between described fin and described metal silicide and be doped with impurity
Silicon layer, in described silicon layer, impurity type is identical with the doping type of the doped region of described Second Type.
A kind of 15. semiconductor devices are it is characterised in that include：
Fin formula field effect transistor；
Electric fuse structure described in any one of claim 12～14, described fin formula field effect transistor and described electric fuse structure
It is located at in semi-conductive substrate.
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| CN106206691B (en) * | 2015-04-29 | 2019-04-26 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN106328645B (en) * | 2015-07-01 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
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| CN101312191A (en) * | 2007-05-25 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semi-conductor construction and forming method thereof |
| US7888771B1 (en) * | 2007-05-02 | 2011-02-15 | Xilinx, Inc. | E-fuse with scalable filament link |
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| US8946064B2 (en) * | 2011-06-16 | 2015-02-03 | International Business Machines Corporation | Transistor with buried silicon germanium for improved proximity control and optimized recess shape |
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| US7888771B1 (en) * | 2007-05-02 | 2011-02-15 | Xilinx, Inc. | E-fuse with scalable filament link |
| CN101312191A (en) * | 2007-05-25 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semi-conductor construction and forming method thereof |
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