CN104183543A - Electrical fuse structure and formation method thereof and semiconductor device - Google Patents
Electrical fuse structure and formation method thereof and semiconductor device Download PDFInfo
- Publication number
- CN104183543A CN104183543A CN201310193706.XA CN201310193706A CN104183543A CN 104183543 A CN104183543 A CN 104183543A CN 201310193706 A CN201310193706 A CN 201310193706A CN 104183543 A CN104183543 A CN 104183543A
- Authority
- CN
- China
- Prior art keywords
- fin
- type
- doping
- area
- fuse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides an electrical fuse structure and a formation method thereof and a semiconductor device. The formation method of the electrical fuse structure comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate is provided with raised fin portions, the fin portions being made of semiconductor materials, and the fin portions being subjected to first type of doping; carrying out second type of doping, and the fin portion tops being subjected to the second type of doping serving as a fuse; or carrying out second type of doping on the fin portion tops, and then, forming metal silicide on the fin portions, the fin portion tops being subjected to the second type of doping and the metal silicide jointly serving as the fuse, wherein the second type of doping is opposite to the first type of doping, and the doping dosage of the second type of doping is larger than that of the first type of doping; forming an inter-layer dielectric layer covering the fuse and the substrate; and forming conductive plugs in the inter-layer dielectric layer, the conductive plugs being at the two ends of the fuse respectively. The invention provides the method for forming the electrical fuse structure on the fin portions so as to realize diversity of the method for forming the electrical fuse structure on the semiconductor device.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly a kind of electric fuse structure and forming method thereof, semiconductor device.
Background technology
In integrated circuit fields, fuse (Fuse) refers to that the connecting line that significantly changes (being changed to high-impedance state by low resistance state) or can fuse can occur some resistance that form in integrated circuit.At first, fuse is the redundant circuit for connecting integrated circuit, finds that integrated circuit has defect once detect, and just utilizes fuse reparation or replaces defective circuit.Fuse is generally two kinds of laser fuse (Laser Fuse) and electric fuses (Electrical Fuse, hereinafter to be referred as E-fuse).Along with the development of semiconductor technology, E-fuse has replaced laser fuse gradually.
General, electric fuse structure can be made with metal (aluminium, copper etc.) or silicon, with reference to figure 1, in prior art, a kind of typical electric fuse structure is formed on the fleet plough groove isolation structure (STI) 100 in Semiconductor substrate, it comprises anode 101 and negative electrode 103, and the fuse 102 of the fine strip shape being connected with both between anode 101 and negative electrode 103, its Anodic 101 and negative electrode 103 surfaces have conductive plunger 104.In the time passing through larger immediate current between anode 101 and negative electrode 103, the resistance of fuse 102 can occur significantly to change or can be fused.Wherein, if fuse 102 is fused, under the state that fuse 102 is not fused, electric fuse structure place is low resistance state (if resistance is R), and under the state after fuse 102 is by fusing, electric fuse structure place is high-impedance state (if resistance is for infinitely great).Because having by electric current, it can realize the characteristic that low-resistance transforms to high resistant, electric fuse structure is except the application in redundant circuit, also there is application widely, as: built-in self-test (Build in self test, be called for short BIST) technology, self-repair technology, one-time programming (One Time Program, be called for short OTP) chip, SOC (system on a chip) (System On Chip is called for short SoC) etc.
In prior art, with reference to figure 1, the formation method of electric fuse structure is as follows:
First, provide Semiconductor substrate, in described Semiconductor substrate, form fleet plough groove isolation structure 100;
Then, form polysilicon layer on described fleet plough groove isolation structure 100 surfaces, form patterned mask layer on the surface of polysilicon layer, taking described patterned mask layer as mask etching polysilicon layer, formation two ends are roomy, and the semiconductor structure of the intermediate elongated being connected with two ends.Wherein, roomy place, two ends is anode 101 and negative electrode 103, and intermediate elongated place is fuse 102.Surface at described anode 101 and negative electrode 103 forms conductive plunger 104.
The invention provides a kind of method that forms electric fuse structure on fin, to realize the diversity that forms electric fuse structure method on semiconductor device.
Summary of the invention
The problem that the present invention solves is to provide a kind of method that forms electric fuse structure on fin, to realize the diversity that forms electric fuse structure method on semiconductor device.
For addressing the above problem, the invention provides a kind of formation method of electric fuse structure, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has protruding fin, and the material of described fin is semi-conducting material, and described fin has carried out first kind doping;
Second Type doping is carried out in the top of described fin, carried out the fin top of Second Type doping as fuse, described Second Type is contrary with the first kind, and the dopant dose of described Second Type doping is greater than the dopant dose of first kind doping; Or,
Second Type doping carried out in the top of described fin, afterwards, on described fin, form metal silicide, carried out the fin top of Second Type doping and described metal silicide jointly as fuse,
Described Second Type is contrary with the first kind, and the dopant dose of described Second Type doping is greater than the dopant dose of first kind doping;
Form interlayer dielectric layer and form conductive plunger, described conductive plunger is at the two ends of described fuse.
In described interlayer dielectric layer, the two ends of described fuse form respectively conductive plunger.
Optionally, before Second Type doping step is carried out in the top of described fin, or after Second Type doping is carried out in the top of described fin, also comprise the following steps: form the step of metal silicide on described fin before
In described fin, form groove, described groove is positioned at the two ends of described fin;
In described groove, form semi-conducting material;
The surface of the semi-conducting material in described groove forms silicon layer;
Described conductive plunger is positioned on described silicon layer.
Optionally, in the time that Second Type is doped to P type, described semi-conducting material is germanium silicon, and described groove is sigma connected in star;
In the time that Second Type is doped to N-type, described semi-conducting material is carborundum, and described groove is U-shaped groove.
Optionally, in the time that Second Type is doped to P type, the formation method of described fin comprises:
In described Semiconductor substrate, form P type doped region, on described P type doped region, carry out first kind doping and form N-type well region;
Described in etching, N-type well region forms protruding fin.
Optionally, in the time that Second Type is doped to N-type, the formation method of described fin comprises:
In described Semiconductor substrate, form P type doped region, on described P type doped region, form N-type doped region, on described N-type doped region, carry out first kind doping and form P type well region; Described in etching, P type well region forms protruding fin.
Optionally, the top of described fin is carried out also comprising the following steps: before the step of Second Type doping
Silicon layer is formed on the top at described fin;
When Second Type doping is carried out in described fin top, also described silicon layer is carried out to Second Type doping.
Optionally, described Semiconductor substrate has first area and second area, described first area is used to form fin formula field effect transistor, and described fuse is formed on described second area, and the fin of described fin and described fin formula field effect transistor forms in same processing step.
Optionally, in the time that the fin two ends of described second area have groove, in described groove, there is semi-conducting material, groove shapes in the described groove of described second area and the source of described first area, drain electrode is identical, the source of semi-conducting material in the described groove of described second area and described first area, drain in semi-conducting material identical.
Optionally, the Second Type that carries out at the top of the fin to second area doping step, with form the source in the described fin formula field effect transistor of first area, the doping step of drain electrode is same step.
Optionally, the formation step of described conductive plunger, with the formation step of the source electrode in fin formula field effect transistor in first area, the conductive plunger in drain electrode be same step.
Optionally, the formation method of described conductive plunger comprises:
Form patterned mask layer on the surface of described interlayer dielectric layer;
Taking described patterned mask layer as mask, interlayer dielectric layer described in etching forms opening in described interlayer dielectric layer, and described fuse is exposed in the bottom of described opening;
Adopt conductive layer to fill described opening, form conductive plunger.
The present invention also provides a kind of electric fuse structure, comprising:
Have the Semiconductor substrate of protruding fin, the material of described fin is semi-conducting material;
Described fin has first kind doped region;
Be positioned on described first kind doped region and be positioned at the Second Type doped region at described fin top, fuse is the described Second Type doped region at described fin top; Or,
Be positioned on described first kind doped region and be positioned at the Second Type doped region at described fin top, being positioned at the metal silicide at described fin top, described fuse is described Second Type doped region and the described metal silicide at described fin top;
Described first kind dopant dose contrary with described Second Type and described Second Type doping is greater than the dopant dose of first kind doping;
Cover the interlayer dielectric layer of described fuse;
Conductive plunger, is positioned at described interlayer dielectric layer and is positioned at the two ends of described fuse.
Optionally, described fin has the groove of filling full semi-conducting material, and described groove is positioned at the two ends of described fuse, and described conductive plunger is positioned on described semi-conducting material.
Optionally, the upper surface of described fin has the silicon layer of the impurity that adulterated, and in described silicon layer, the dopant type of doping is identical with the doping type of described Second Type doped region;
In the time that the top of fin has metal silicide, between described fin and described metal silicide, there is the silicon layer of the impurity that adulterated, in described silicon layer, impurity type is identical with the doping type of the doped region of described Second Type.
The present invention also provides a kind of semiconductor device, it is characterized in that, comprising:
Fin formula field effect transistor;
The electric fuse structure being formed by said method, described fin formula field effect transistor and described electric fuse structure are positioned in same semi-conductive substrate.
Compared with prior art, technical scheme of the present invention has the following advantages:
The invention provides a kind of method that forms electric fuse structure on fin, to realize the diversity that forms electric fuse structure method on semiconductor device.
Further, it is to colonize among the formation step of the fin formula field effect transistor in same Semiconductor substrate that the entirety of electric fuse structure of the present invention forms step, and therefore, method of the present invention is simple.
Brief description of the drawings
Fig. 1 is the schematic perspective view of a kind of electric fuse structure of the prior art;
Fig. 2 is the schematic flow sheet of the electric fuse structure formation method in the embodiment of the present invention;
Fig. 3 is the perspective view of the intermediate structure of the electric fuse structure in the embodiment of the present invention one;
Fig. 4 is the cross-sectional view of Fig. 3 along AA direction;
Fig. 5 to Figure 12 is the cross-sectional view of the electric fuse structure formation method in the embodiment of the present invention one;
Figure 13 and Figure 14 are the cross-sectional view of the electric fuse structure formation method in the embodiment of the present invention two.
Embodiment
The invention provides a kind of method that forms electric fuse structure on fin formula field effect transistor, to realize the diversity that forms electric fuse structure method on semiconductor device.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Embodiment mono-
Fig. 2 is the schematic flow sheet of the electric fuse structure formation method in the embodiment of the present invention.Fig. 3 is the perspective view of the intermediate structure of the electric fuse structure in the embodiment of the present invention one.Fig. 4 is the cross-sectional view of Fig. 3 along AA direction.Fig. 5 to Figure 12 is the cross-sectional view of the electric fuse structure formation method in the embodiment of the present invention one.
First with reference to figure 3 and Fig. 4, the step S11 in execution graph 2, provides Semiconductor substrate 200, and described Semiconductor substrate 200 has protruding fin 204, and the material of described fin 204 is semi-conducting material, and described fin 204 has carried out first kind doping.
In the present embodiment, it is to colonize among the formation step of the fin formula field effect transistor in same Semiconductor substrate that the entirety of electric fuse structure forms step, therefore, in order clearly to describe the present invention, in conjunction with reference to figure 3 and Fig. 4, Semiconductor substrate 200 is divided into first area Ι and second area Ι Ι by the present embodiment, and first area Ι is used to form fin formula field effect transistor, and second area Ι Ι is used to form electric fuse structure.
Semiconductor substrate 200 can be silicon substrate, can be also germanium, germanium silicon, gallium arsenide substrate or silicon-on-insulator substrate.Semiconductor substrate 200 in the present embodiment is more preferably selected silicon substrate, because it is lower than implement cost of the present invention in above-mentioned other Semiconductor substrate to implement the present invention on silicon substrate.Especially lower than implement cost of the present invention in silicon-on-insulator substrate.
In the present embodiment, silicon semiconductor substrate 200 forms protruding fin 204 described in etching, and this fin 204 has first kind doping, and the fin 204 of the fin 204 of described first area Ι and second area Ι Ι forms in same processing step.Wherein, the Second Type doping that first kind doping forms with the follow-up top at second area fin 204 is contrary.
In the present embodiment, the Second Type that carry out at the top of the follow-up fin 204 at second area Ι Ι is doped to P type, the formation method of the fin 204 of first area Ι and second area Ι Ι is specially: with reference to figure 4, first form P type doped region 201 in the bottom of Semiconductor substrate 200, then on P type doped region 201, form N-type well region 202.Described in etching, N-type well region 202 forms protruding fin 204, and now the overall doping type of fin 204 is N-type.Certainly, in other embodiments, also can form N-type doped region in the bottom of Semiconductor substrate, be specially, form behind N-type doped region, on N-type doped region, form P type doped region, on P type doped region, form N-type well region.Why like this doping, be because the isolation effect between Semiconductor substrate is relatively good, can better block bottom and disturb.Then, etching N type well region forms protruding fin, and now the doping type of fin entirety is also N-type.
It should be noted that, when the Second Type that carry out at the top of the follow-up fin 204 at second area Ι Ι is doped to P type, the resistivity of the resistivity while forming P type doped region in the bottom of Semiconductor substrate when forming N-type doped region in the bottom of Semiconductor substrate is low.Those skilled in the art can select according to the needs of oneself method of the fin of first area Ι and second area Ι Ι.
In other embodiment, when the Second Type carrying out when the top of the follow-up fin at second area is doped to N-type, the formation method of the fin of first area Ι and second area Ι Ι is specially: first form N-type doped region in the bottom of Semiconductor substrate, then on N-type doped region, form P type well region.Etching P type well region forms protruding fin, and now the doping type of fin entirety is P type.In other embodiments, also can form P type doped region in the bottom of Semiconductor substrate, then on P type doped region, form N-type doped region, on N-type doped region, form P type well region.Why like this doping, because the isolation ratio between Semiconductor substrate is better, can better block bottom and disturb, and resistivity while forming P type doped region in the bottom of the Semiconductor substrate resistivity when forming N-type doped region in the bottom of Semiconductor substrate is low.Then, etching P type well region forms protruding fin, and now the doping type of fin entirety is P type.
In other embodiments, Semiconductor substrate can also be silicon-on-insulator substrate, and described silicon-on-insulator substrate comprises bottom silicon layer, be positioned at insulating barrier on bottom silicon layer, be positioned at the top silicon layer on insulating barrier.Etching top silicon layer forms fin, then fin is carried out to first kind doping, silicon-on-insulator substrate also can be divided into first area and second area, first area is used to form fin formula field effect transistor, second area is used to form electric fuse structure, and the fin of the fin of described first area Ι and second area Ι Ι forms in same processing step.The fin of fin to first area Ι and second area Ι Ι carries out after first kind doping, in order to form fuse, follow-uply need to carry out Second Type doping at the top of the fin of second area, and wherein Second Type doping is adulterated contrary with the first kind.Also belong to protection scope of the present invention.
In the present embodiment, Semiconductor substrate 200 also comprise between each fin 204 and lower than the fleet plough groove isolation structure 203(STI of fin 204).Described fleet plough groove isolation structure 203 is for isolating the different fins 204 in described Semiconductor substrate 200, the material of described fleet plough groove isolation structure 203 is silica, the formation method of described fleet plough groove isolation structure, for those skilled in the art know technology, does not repeat them here.
In the present embodiment, Second Type doping is carried out in the top of fin 204, forms the step of fuse 216 and carry out at second area Ι Ι, with the source in the described fin formula field effect transistor of first area Ι, the doping step in drain electrode be same step.Specific as follows:
Continue in conjunction with reference to figure 3 and Fig. 4, the step S12 in execution graph 2 forms grid structure 205 on the fin 204 of first area Ι, top and the sidewall of fin 204 described in described grid structure 205 cover parts.
In the present embodiment, described grid structure 205 comprises gate dielectric layer 206 and is formed on gate dielectric layer 206 grid 207 above.The material of gate dielectric layer 206 is high-k gate dielectric layer, and the material of high-k gate dielectric layer is HfO
2, Al
2o
3, ZrO
2, HfSiO, HfSiON, HfTaO and HfZrO.Grid 207 is dummy grid, and the material of dummy grid is polysilicon.
Then with reference to figure 5, step S13 in execution graph 2, formation side wall 208 around grid structure 205, fin 204 taking side wall 208 as mask etching first area Ι, in the fin of side wall 208 both sides, form groove 209, the groove 209 of second area Ι Ι fin forms in same etch step with the groove 209 of first area Ι, and the fin 204 of first area Ι and second area Ι Ι forms after described groove 209, at the interior filling semiconductor material 210 of described groove 209.
In the present embodiment, the type of the fin formula field effect transistor of follow-up formation is P type, this groove is preferably sigma type groove, within the scope of effective dimensions, the sharp corner of sigma type groove is more near channel region, be conducive to the follow-up larger compression that forms in channel region, to improve the carrier mobility of channel region, improve the performance of the fin formula field effect transistor of follow-up formation.In other embodiments, this groove can also be other shapes, for example rectangle.Form after sigma type groove, filling semiconductor material 210 in sigma type groove, in the present embodiment, semi-conducting material is germanium silicon material.The concrete technique that forms, for those skilled in the art know technology, does not repeat them here.
Certainly, in other embodiments, in the time that the type of the fin formula field effect transistor of follow-up formation is N-type, this groove is preferably U-shaped groove, within the scope of effective dimensions, U-shaped groove is conducive to the follow-up larger tension stress that forms in channel region, to improve the carrier mobility of channel region, improves the performance of the fin formula field effect transistor of follow-up formation.Form after U-shaped groove, the semi-conducting material of filling in U-shaped groove is carborundum.
It should be noted that, continue with reference to figure 5, in the present embodiment, when the fin 204 of first area Ι forms groove 209, also form groove 209 at the fin 204 of second area Ι Ι.Groove 209 is identical in the position of the fin of first area Ι with this groove 209 in the position of the fin 204 of second area Ι Ι.Shape, the packing material of second area Ι Ι groove 209 are identical with shape, the packing material of the groove 209 of first area Ι.Semi-conducting material in the interior formation groove 209 of fin 204 and the groove 209 of second area Ι Ι, can make the contact resistance between follow-up conductive plunger and the fuse of fuse-wires structure forming at second area Ι Ι reduce.Further, in the time that the groove 209 of second area Ι Ι fin 204 interior formation is sigma type or when U-shaped, can reduce the contact resistance between conductive plunger and the fuse of fuse-wires structure.Further, form groove 209 and interior semi-conducting material thereof at second area Ι Ι with in the Ι of first area simultaneously, now the groove structure similarity in these two regions is the highest, thereby can make conductive plunger in second area Ι Ι and the contact resistance between fuse drop to minimum.
In other embodiments, can form groove at the fin of first area and second area by substep.
In other embodiments, also can in the fin of second area, not form described groove.
With reference to figure 6, the step S14 in execution graph 2, forms silicon layer 211(Si Cap on semi-conducting material 210 surfaces of first area Ι and second area Ι Ι).
Form the concrete grammar of described silicon layer 211 for those skilled in the art know technology, do not repeat them here.Semi-conducting material 210 surfaces at first area I and second area II form silicon layer 211, this silicon layer 211 can prevent follow-up Second Type doping diffusion in semi-conducting material 210, and then the resistivity of source electrode, drain electrode that can ensure follow-up formation in the I of first area is low, but also can ensure that the resistivity of the follow-up semi-conducting material 210 that carries out Second Type doping in second area II is low.
Then, with reference to figure 7, step S15 in execution graph 2, form after silicon layer 211, Second Type doping is carried out at silicon layer 211 to the semi-conducting material 210 in the fin 204 of first area Ι and second area Ι Ι, semi-conducting material 210 surfaces and the fin top of second area Ι Ι, form doped region 214, described Second Type is contrary with the first kind, and the dopant dose of described Second Type doping is greater than the dopant dose of first kind doping.
This Second Type doping step forms doped region 214 at the fin 204 of second area Ι Ι, and this Second Type doping step forms source electrode 212 and the drain electrode 213 of fin formula field effect transistor in the Ι of first area.In second area Ι Ι, Second Type doping is contrary with original first kind doping type in fin 204, that is to say, Second Type doping can form P-N with first kind doping and tie, and this P-N fuse of becoming a partner has buffer action.
The formation step of P-N in the present embodiment knot is also to colonize among the formation step of fin formula field effect transistor of first area, therefore, and almost nil cost.And the present embodiment just just can form the isolation to fuse by doping, therefore, method is simple.In addition, method that fuse isolates has also been started the precedent that directly forms fuse on active area to utilize P-N on fin in second area to become a partner.Reason is as follows: fuse of the prior art can not be formed directly on active area, active area belongs to large-area semiconductor structure, especially the very large semiconductor structure of width, even if there is larger immediate current on fuse, a large amount of heat that this electric current produces also can shed from large-area active area, therefore,, in prior art, insulating barrier and fleet plough groove isolation structure need to be set below fuse.And P-N below fuse of the present invention knot just can be realized the technique that forms fuse on active area.
With reference to figure 8, the step S16 in execution graph 2, forms behind doped region 214, on the silicon layer 211 of first area Ι and second area Ι Ι, doped region 214 at the fin top of second area Ι Ι, forms metal silicide layer 215.Wherein, the metal silicide layer 215 on silicon layer can reduce the contact resistance between silicon layer 211 and the conductive plunger of follow-up formation.It should be noted that, on the doped region 214 at the fin top of second area Ι Ι, form metal silicide layer 215, this metal silicide layer 215 forms fuse 216 jointly with the doped region 214 at the fin top of second area Ι Ι, between anode that subsequent technique forms and negative electrode while thering is larger immediate current, the situation that fuse 216 changes into high-impedance state by low resistance state has two kinds: the resistivity of (1) metal silicide layer 215 is lower than doped region 214, therefore, between anode and negative electrode, larger immediate current can be preferentially flows through from 215 layers of metal silicide layers, thereby make the inside of metal silicide layer 215 that electromigration (electromigration occur, EM) phenomenon, that is to say, metal ion great majority in metal silicide layer 215 all migrate to negative electrode or anode, thereby make the inside of metal silicide layer 215 produce cavity, the resistance of metal silicide layer 215 is increased considerably, and then the resistance of fuse 216 is increased considerably, change into high-impedance state by low resistance state.(2) the larger immediate current between anode and negative electrode can produce a large amount of heat energy, and this large amount of heat energy can fuse metal silicide layer 215 together with doped region 214, thereby the resistance of fuse 216 is increased considerably, and changes into high-impedance state by low resistance state.Certainly, in other embodiments, on the doped region 214 at the fin top of second area Ι Ι, also can not form metal silicide layer 215, also can implement the present invention.Fuse is now only doped region 214, between anode that subsequent technique forms and negative electrode while thering is larger immediate current, impurity in doped region 214 also can move, migrate to male or female, thereby can make the resistance of doped region 214 increase considerably, change into high-impedance state by low resistance state.
In other embodiment, in semiconductor material surface in the groove of first area and second area forms silicon layer (Si Cap), also can form silicon layer at the upper surface of the fin of second area.Therefore,, when Second Type doping formation doped region is carried out in the fin top of second area, the silicon layer that also can form the upper surface of the fin of second area carry out Second Type doping, forms together fuse.The silicon layer that fuse is included in the formation of second area fin upper surface has following benefit: can prevent the Second Type doping diffusion at the fin top of second area, the distribution that the Second Type at the fin top of second area is adulterated is narrow, thereby reduce the resistivity of the doped region at the fin top of second area, the condition of fuse failure is more easily controlled, and then improved the utility ratio of fuse.When in the time that the fuse at the fin top of second area has many, above-mentioned benefit can be more obvious.
In other embodiments, in the time that the upper surface of the fin of second area has silicon layer, the metal silicide layer on the fin of second area is formed on silicon layer.
Then,, with reference to figure 9, the step S17 in execution graph 2, forms interlayer dielectric layer 217, covers described fuse 216.
In the present embodiment, form interlayer dielectric layer 217, cover the metal silicide layer 215 on Semiconductor substrate, fleet plough groove isolation structure 203, first area Ι and second area Ι Ι fin, grid structure 205 and the side wall 208 in the Ι of first area.Then, adopt the method for chemico-mechanical polishing to remove the interlayer dielectric layer 217 higher than grid structure, make the surface of interlayer dielectric layer 217 equal with the surface of grid structure 205.
It should be noted that, in the time that fuse 216 has larger immediate current, can produce a large amount of heats, interlayer dielectric layer 217 covers fuse 216 and can make this heat to go out by Quick diffusing, is more conducive to the fusing of fuse 216.
In the present embodiment, with reference to figure 4, in grid structure 205, grid 207 is dummy grid, continue in conjunction with reference 9 and Figure 10, form after interlayer dielectric layer 217, need to remove the grid 207 in the Ι of first area, form grid groove 218 in the inside of interlayer dielectric layer 217, high-k gate dielectric layer is exposed in the bottom of grid groove 218.With reference to Figure 11, at the interior formation metal gates 219 of grid groove 218.The technique of removing grid 207 and formation metal gates 219 all belongs to those skilled in the art's the technology of knowing, and does not repeat them here.
With reference to Figure 12, in the present embodiment, form after metal gates 219, on interlayer dielectric layer 217, continue to form interlayer dielectric layer 220.
Then, continue with reference to Figure 12, the step S18 in execution graph 2, in described interlayer dielectric layer 217, the two ends of described fuse 216 form respectively conductive plunger 221.
In the present embodiment, the formation step of the conductive plunger in source electrode 212 and drain electrode 213 in the fin formula field effect transistor in formation step and the first area of the conductive plunger at the fuse two ends of follow-up formation is same step.Specifically comprise:
Then, form patterned mask layer (not shown) on the surface of interlayer dielectric layer 220, taking described patterned mask layer as mask, interlayer dielectric layer 217 and 220 described in etching, at interlayer dielectric layer 217 and 220 several openings of interior formation, at first area Ι, the metal silicide layer 215 in described source electrode 212 and drain electrode 213 is exposed in the bottom of this opening; At second area Ι Ι, the metal silicide layer 215 at described fuse 216 two ends is exposed in the bottom of this opening.Form after opening, adopt conductive layer to fill described opening, form conductive plunger 221, wherein conductive layer is metal, can be metallic copper or tungsten in the present embodiment.
In other embodiments, the top of the fin to second area is carried out Second Type doping and is formed behind doped region, can be directly in Semiconductor substrate, silicon layer on semi-conducting material, grid structure, the surface of side wall and doped region forms interlayer dielectric layer, form after interlayer dielectric layer, remove dummy grid, form metal gates on high-k gate dielectric layer surface, then, inside at interlayer dielectric layer forms opening, the silicon layer of semiconductor material surface is exposed in the bottom of described opening, then on the silicon layer of open bottom, form metal silicide layer, form after metal silicide layer, filling opening forms conductive plunger.It should be noted that, this embodiment cannot form metal silicide layer on doped region, or, in the time thering is silicon layer on doped region, also cannot on silicon layer, form metal silicide layer.Therefore, this doped region is fuse.
The present invention not only provides a kind of method that forms electric fuse structure on fin, to realize the diversity that forms electric fuse structure method on semiconductor device, and the entirety of electric fuse structure in this method to form step be to colonize among the formation step of the fin formula field effect transistor in same Semiconductor substrate, therefore, method of the present invention is simple and process costs is almost nil.
The second embodiment
In the present invention, the technique of the fin formula field effect transistor in the Ι of first area be divided into high-k gate dielectric layer at front formation technique (HK First) and high-k gate dielectric layer at rear formation technique (HK Last).Electric fuse structure in the first embodiment forms in front formation technical process at high-k gate dielectric layer.Electric fuse structure in the second embodiment forms in rear formation technical process at high-k gate dielectric layer.
With reference to Figure 13 and Figure 14, with the difference of the first embodiment be:
(1), with reference to Figure 13, on the fin 304 of the first area of Semiconductor substrate 300 Ι, form grid structure 305.Grid structure 305 comprises gate dielectric layer 306 and is formed on gate dielectric layer 306 grid 307 above.Wherein, the material of gate dielectric layer 306 is silicon dioxide, and grid 307 is still dummy grid.In the time that removal dummy grid forms pseudo-grid recess, also remove gate dielectric layer 306.
(2) with reference to Figure 14, at high-k gate dielectric layer in rear formation technique, bottom and the sidewall of the high-k gate dielectric layer 314 cover gate grooves of formation.
It should be noted that, this technique be high-k gate dielectric layer in rear formation technique, need to, after forming high-k gate dielectric layer 314 and metal gates 315, could in first area Ι and second area Ι Ι, on silicon layer 311, form metal silicide layer 320.Reason is as follows: if form high-k gate dielectric layer after forming metal silicide layer, the annealing process that high-k gate dielectric layer forms in technique can increase considerably the resistance of the metal silicide layer forming before, thereby destroys the performance of metal silicide layer.In a second embodiment, in order to form high-k gate dielectric layer 314 and metal gates 315, subsequent technique has the step that forms interlayer dielectric layer 317 and 318, this interlayer dielectric layer 317 and 318 covers silicon layer 311 in first area Ι and second area Ι Ι when in the time that the opening of silicon layer 311 is exposed in interlayer dielectric layer 317 and 318 interior formation, could in this opening, form metal silicide layer 320, then form conductive plunger 321 with metal filled opening.Therefore, in rear formation technique, cannot on doped region 316, form metal silicide at high-k gate dielectric layer, or, in the time thering is silicon layer 311 on doped region 316, also cannot on silicon layer 311, form metal silicide.Therefore, this doped region 316 is fuse.
It should be noted that, the formation technique of fuse-wires structure of the present invention is not only applicable to rear grid and forms technique, but also is applicable to front grid technique.
The 3rd embodiment
The difference of the 3rd embodiment and first, second embodiment is:
In the first embodiment of the present invention and the second embodiment, it is to colonize among the formation step of the fin formula field effect transistor in same Semiconductor substrate that the entirety of electric fuse structure forms step, in the 3rd embodiment, the entirety of electric fuse structure forms step and does not colonize among the formation step of the fin formula field effect transistor in same Semiconductor substrate, on the fin in Semiconductor substrate that can be independent, forms electric fuse structure.
With reference to Figure 12, the present invention also provides a kind of electric fuse structure, comprising:
Have the Semiconductor substrate 200 of protruding fin 204, the material of described fin 204 is semi-conducting material;
Described fin 204 has first kind doped region;
Be positioned on described first kind doped region and be positioned at the doped region 214 at described fin 204 tops, described doped region 214 is Second Type, and fuse is the described doped region 214 at described fin 204 tops; Or,
Be positioned on described first kind doped region and be positioned at the doped region 214 at described fin 204 tops, being positioned at the metal silicide 215 at described fin 204 tops, described fuse is described doped region 214 and the described metal silicide 215 at described fin 204 tops;
Described first kind dopant dose contrary with described Second Type and described Second Type doping is greater than the dopant dose of first kind doping;
Cover the interlayer dielectric layer of described fuse;
Conductive plunger 221, is positioned at the two ends of described interlayer dielectric layer, described fuse.
In the present embodiment, described fin 204 has the groove 209 of filling full semi-conducting material 210, described groove 209 is positioned at the two ends of described fuse, the surface of described semi-conducting material 210 has silicon layer 211, the surface of described silicon layer 211 has metal silicide layer 215, and described conductive plunger 221 is positioned on described metal silicide layer 215.
In other embodiments, described fin 204 can not have described groove 209 yet.
In other embodiments, the upper surface of described fin has the silicon layer with the identical doping type in described doped region, and described fuse comprises described silicon layer.
In other embodiments, the upper surface of described fin has the silicon layer with the identical doping type in described doped region, and described fuse comprises described silicon layer.And the upper surface of described silicon layer has metal silicide.
Content about structure, material in first embodiment of the invention can be incorporated herein, and does not repeat at this.
The present invention also provides a kind of semiconductor device, comprising:
Fin formula field effect transistor;
Above-described electric fuse structure, described fin formula field effect transistor and described electric fuse structure are positioned in same semi-conductive substrate.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (15)
1. a formation method for electric fuse structure, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has protruding fin, and the material of described fin is semi-conducting material, and described fin has carried out first kind doping;
Second Type doping is carried out in the top of described fin, carried out the fin top of Second Type doping as fuse; Or,
Second Type doping carried out in the top of described fin, afterwards, on described fin, form metal silicide, carried out the fin top of Second Type doping and described metal silicide jointly as fuse,
Described Second Type is contrary with the first kind, and the dopant dose of described Second Type doping is greater than the dopant dose of first kind doping;
Form interlayer dielectric layer, cover described fuse and described Semiconductor substrate;
In described interlayer dielectric layer, form conductive plunger, described conductive plunger is at the two ends of described fuse.
2. the formation method of electric fuse structure according to claim 1, is characterized in that,
Before Second Type doping step is carried out in the top of described fin, or after Second Type doping is carried out in the top of described fin, also comprise the following steps: form the step of metal silicide on described fin before
In described fin, form groove, described groove is positioned at the two ends of described fin;
In described groove, form semi-conducting material;
The surface of the semi-conducting material in described groove forms silicon layer;
Described conductive plunger is positioned on described silicon layer.
3. the formation method of electric fuse structure according to claim 2, is characterized in that,
In the time that Second Type is doped to P type, described semi-conducting material is germanium silicon, and described groove is sigma connected in star;
In the time that Second Type is doped to N-type, described semi-conducting material is carborundum, and described groove is U-shaped groove.
4. the formation method of electric fuse structure according to claim 1, is characterized in that, in the time that Second Type is doped to P type, the formation method of described fin comprises:
In described Semiconductor substrate, form P type doped region, on described P type doped region, carry out first kind doping and form N-type well region;
Described in etching, N-type well region forms protruding fin.
5. the formation method of electric fuse structure according to claim 1, is characterized in that, in the time that Second Type is doped to N-type, the formation method of described fin comprises:
In described Semiconductor substrate, form P type doped region, on described P type doped region, form N-type doped region, on described N-type doped region, carry out first kind doping and form P type well region; Described in etching, P type well region forms protruding fin.
6. the formation method of electric fuse structure according to claim 1, is characterized in that, the step of the top of described fin being carried out to Second Type doping also comprises the following steps: before
Silicon layer is formed on the top at described fin;
When Second Type doping is carried out in described fin top, also described silicon layer is carried out to Second Type doping.
7. the formation method of electric fuse structure according to claim 1, it is characterized in that, described Semiconductor substrate has first area and second area, described first area is used to form fin formula field effect transistor, described fuse is formed on described second area, and the fin of described fin and described fin formula field effect transistor forms in same processing step.
8. the formation method of electric fuse structure according to claim 7, it is characterized in that, in the time that the fin two ends of described second area have groove, in described groove, there is semi-conducting material, the described groove of described second area is identical with the groove shapes in the source of described first area, drain electrode, and the semi-conducting material in the described groove of described second area is identical with the semi-conducting material in the source of described first area, drain electrode.
9. the formation method of electric fuse structure according to claim 7, it is characterized in that, the Second Type that carries out at the top of the fin to second area doping step, with form the source in the described fin formula field effect transistor of first area, the doping step of drain electrode is same step.
10. the formation method of electric fuse structure according to claim 7, is characterized in that, the formation step of described conductive plunger, with the formation step of the source electrode in fin formula field effect transistor in first area, the conductive plunger in drain electrode be same step.
The formation method of 11. electric fuse structures according to claim 1, is characterized in that, the formation method of described conductive plunger comprises:
Form patterned mask layer on the surface of described interlayer dielectric layer;
Taking described patterned mask layer as mask, interlayer dielectric layer described in etching forms opening in described interlayer dielectric layer, and described fuse is exposed in the bottom of described opening;
Adopt conductive layer to fill described opening, form conductive plunger.
12. 1 kinds of electric fuse structures, is characterized in that, comprising:
Have the Semiconductor substrate of protruding fin, the material of described fin is semi-conducting material;
Described fin has first kind doped region;
Be positioned on described first kind doped region and be positioned at the Second Type doped region at described fin top, fuse is the described Second Type doped region at described fin top; Or,
Be positioned on described first kind doped region and be positioned at the Second Type doped region at described fin top, being positioned at the metal silicide at described fin top, described fuse is described Second Type doped region and the described metal silicide at described fin top;
Described first kind dopant dose contrary with described Second Type and described Second Type doping is greater than the dopant dose of first kind doping;
Cover the interlayer dielectric layer of described fuse;
Conductive plunger, is positioned at described interlayer dielectric layer and is positioned at the two ends of described fuse.
13. electric fuse structures according to claim 12, is characterized in that, described fin has the groove of filling full semi-conducting material, and described groove is positioned at the two ends of described fuse, and described conductive plunger is positioned on described semi-conducting material.
14. electric fuse structures according to claim 12, is characterized in that, the upper surface of described fin has the silicon layer of the impurity that adulterated, and in described silicon layer, the dopant type of doping is identical with the doping type of described Second Type doped region;
In the time that the top of fin has metal silicide, between described fin and described metal silicide, there is the silicon layer of the impurity that adulterated, in described silicon layer, impurity type is identical with the doping type of the doped region of described Second Type.
15. 1 kinds of semiconductor device, is characterized in that, comprising:
Fin formula field effect transistor;
Electric fuse structure described in claim 12～14 any one, described fin formula field effect transistor and described electric fuse structure are positioned in same semi-conductive substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310193706.XA CN104183543B (en) | 2013-05-22 | 2013-05-22 | Electrical fuse structure and formation method thereof and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310193706.XA CN104183543B (en) | 2013-05-22 | 2013-05-22 | Electrical fuse structure and formation method thereof and semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104183543A true CN104183543A (en) | 2014-12-03 |
| CN104183543B CN104183543B (en) | 2017-02-22 |
Family
ID=51964488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310193706.XA Active CN104183543B (en) | 2013-05-22 | 2013-05-22 | Electrical fuse structure and formation method thereof and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104183543B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106206691A (en) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN106328645A (en) * | 2015-07-01 | 2017-01-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and formation method thereof |
| CN106605285A (en) * | 2014-08-22 | 2017-04-26 | 丰田自动车株式会社 | Current interrupting device |
| US10056329B1 (en) | 2017-05-02 | 2018-08-21 | International Business Machines Corporation | Programmable buried antifuse |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101312191A (en) * | 2007-05-25 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semi-conductor construction and forming method thereof |
| US20090098689A1 (en) * | 2006-10-19 | 2009-04-16 | International Business Machines Corporation | Electrical fuse and method of making |
| US20100244144A1 (en) * | 2009-03-31 | 2010-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical fuse and related applications |
| US7888771B1 (en) * | 2007-05-02 | 2011-02-15 | Xilinx, Inc. | E-fuse with scalable filament link |
| US20120319166A1 (en) * | 2011-06-16 | 2012-12-20 | International Business Machines Corporation | Transistor with buried silicon germanium for improved proximity control and optimized recess shape |
-
2013
- 2013-05-22 CN CN201310193706.XA patent/CN104183543B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090098689A1 (en) * | 2006-10-19 | 2009-04-16 | International Business Machines Corporation | Electrical fuse and method of making |
| US7888771B1 (en) * | 2007-05-02 | 2011-02-15 | Xilinx, Inc. | E-fuse with scalable filament link |
| CN101312191A (en) * | 2007-05-25 | 2008-11-26 | 台湾积体电路制造股份有限公司 | Semi-conductor construction and forming method thereof |
| US20100244144A1 (en) * | 2009-03-31 | 2010-09-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical fuse and related applications |
| US20120319166A1 (en) * | 2011-06-16 | 2012-12-20 | International Business Machines Corporation | Transistor with buried silicon germanium for improved proximity control and optimized recess shape |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106605285A (en) * | 2014-08-22 | 2017-04-26 | 丰田自动车株式会社 | Current interrupting device |
| CN106605285B (en) * | 2014-08-22 | 2018-06-22 | 丰田自动车株式会社 | Failure of current device |
| CN106206691A (en) * | 2015-04-29 | 2016-12-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN106206691B (en) * | 2015-04-29 | 2019-04-26 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN106328645A (en) * | 2015-07-01 | 2017-01-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and formation method thereof |
| CN106328645B (en) * | 2015-07-01 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| US10056329B1 (en) | 2017-05-02 | 2018-08-21 | International Business Machines Corporation | Programmable buried antifuse |
| US10541202B2 (en) | 2017-05-02 | 2020-01-21 | International Business Machines Corporation | Programmable buried antifuse |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104183543B (en) | 2017-02-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI733704B (en) | Semiconductor and manufacturing method thereof | |
| TWI593103B (en) | Methods of forming stressed layers on finfet semiconductor devices and the resulting devices | |
| CN104183542B (en) | Electric fuse structure and forming method thereof, semiconductor devices and forming method thereof | |
| KR101218479B1 (en) | A metal gate structure of a field effect transistor | |
| TWI531043B (en) | Transistor devices having an anti-fuse configuration and methods of forming the same | |
| US10050036B2 (en) | Semiconductor structure having common gate | |
| US9716177B2 (en) | Semiconductor device comprising a multi-layer channel region | |
| US20160163863A1 (en) | Channel cladding last process flow for forming a channel region on a finfet device | |
| CN107516668B (en) | Semiconductor device and method for manufacturing the same | |
| CN104752428A (en) | Semiconductor device and fabricating method thereof | |
| KR102449211B1 (en) | Semiconductor devices including field effect transistors | |
| TW201729347A (en) | Semiconductor device | |
| CN104183543A (en) | Electrical fuse structure and formation method thereof and semiconductor device | |
| US20160020215A1 (en) | Semiconductor structure | |
| TWI619250B (en) | Semiconductor structures and methods for forming the same | |
| CN106486362B (en) | Test structure, forming method thereof and test method | |
| US10811520B2 (en) | Semiconductor device and method for manufacturing same | |
| TWI588991B (en) | Trench power semiconductor device | |
| CN210092094U (en) | Semiconductor structure | |
| US9515155B2 (en) | E-fuse design for high-K metal-gate technology | |
| CN104681422B (en) | The forming method of semiconductor devices | |
| CN103681465B (en) | The forming method of semiconductor devices | |
| WO2020228334A1 (en) | Semiconductor structure and method for forming same | |
| CN112701042A (en) | Replacement metal gate integration | |
| CN109285841B (en) | Memory and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |