CN103681465A - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- CN103681465A CN103681465A CN201210348126.9A CN201210348126A CN103681465A CN 103681465 A CN103681465 A CN 103681465A CN 201210348126 A CN201210348126 A CN 201210348126A CN 103681465 A CN103681465 A CN 103681465A
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- fuse
- layer
- dielectric layer
- semiconductor substrate
- semiconductor device
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- 238000000034 method Methods 0.000 title claims abstract description 133
- 239000004065 semiconductor Substances 0.000 title claims abstract description 125
- 229910052751 metal Inorganic materials 0.000 claims abstract description 113
- 239000002184 metal Substances 0.000 claims abstract description 113
- 239000000758 substrate Substances 0.000 claims abstract description 86
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 75
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 75
- 238000002955 isolation Methods 0.000 claims abstract description 49
- 239000010410 layer Substances 0.000 claims description 397
- 230000015572 biosynthetic process Effects 0.000 claims description 75
- 230000008569 process Effects 0.000 claims description 53
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 52
- 229920005591 polysilicon Polymers 0.000 claims description 50
- 239000000463 material Substances 0.000 claims description 42
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 21
- 238000005498 polishing Methods 0.000 claims description 18
- 239000000126 substance Substances 0.000 claims description 17
- 150000002500 ions Chemical class 0.000 claims description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 12
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 9
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 239000004411 aluminium Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 239000011241 protective layer Substances 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
- 239000010941 cobalt Substances 0.000 claims description 6
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 6
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 6
- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- BRGOCSWOKBOIOJ-UHFFFAOYSA-N N.[O-2].[Hf+4] Chemical compound N.[O-2].[Hf+4] BRGOCSWOKBOIOJ-UHFFFAOYSA-N 0.000 claims description 3
- DBOSZDMILYIJNB-UHFFFAOYSA-M N.[O-2].[O-2].[O-2].[O-2].[OH-].O.[Hf+4].[Ta+5] Chemical compound N.[O-2].[O-2].[O-2].[O-2].[OH-].O.[Hf+4].[Ta+5] DBOSZDMILYIJNB-UHFFFAOYSA-M 0.000 claims description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- WUNIMIODOAGQAW-UHFFFAOYSA-N [O-2].[Ba+2].[Ti+4] Chemical compound [O-2].[Ba+2].[Ti+4] WUNIMIODOAGQAW-UHFFFAOYSA-N 0.000 claims description 3
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 claims description 3
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 claims description 3
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 claims description 3
- OPZZBWHYLNRIQZ-UHFFFAOYSA-N [Si]=O.[Zr].[N] Chemical compound [Si]=O.[Zr].[N] OPZZBWHYLNRIQZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- 229910052716 thallium Inorganic materials 0.000 claims description 3
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 3
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 claims description 3
- 239000002210 silicon-based material Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000012545 processing Methods 0.000 description 8
- 238000011010 flushing procedure Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 230000001052 transient effect Effects 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
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- 239000013078 crystal Substances 0.000 description 2
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- 230000006870 function Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a method for forming a semiconductor device. The method comprises the following steps: providing a shallow trench isolation structure in a semiconductor substrate; forming a dummy gate on the surface of the semiconductor substrate, and forming a fuse structure on the surface of the shallow trench isolation structure, wherein the height of the fuse structure is smaller than the height of the dummy gate; forming a stress layer inside the semiconductor substrate on two sides of the dummy gate, wherein the surface of the stress layer is lower than the surface of the fuse structure or aligned with the surface of the fuse structure; forming a dielectric layer on the surfaces of the fuse structure, the stress layer, the semiconductor substrate and the shallow trench isolation structure, wherein the surface of the dielectric layer is aligned with the top of the dummy gate and the dielectric layer covers the surface of the fuse structure; then removing the dummy gate to form a gate structure; subsequently removing the dielectric layer from the surfaces of the stress layer and the fuse structure to form a first opening on the surface of the stress layer and a second opening on the surface of the fuse structure; forming a metal silicide layer on the surfaces of the stress layer and the fuse structure; then forming a first conducting inserter in the first opening. The semiconductor device formed by the method provided in the invention is good in performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of semiconductor device.Background technology
Along with the microminiaturization of semiconductor technology and the raising of complexity, semiconductor device also becomes and affected by various defects or impurity, and the inefficacy of single metal connecting line, diode or transistor etc. often forms the defect of whole chip.Therefore in order to address this problem, prior art just can form the connecting line (fusible links) of some fusible in integrated circuit, and fuse (fuse) namely, to guarantee the utilizability of integrated circuit.
In prior art, fuse is for connecting the redundant circuit of integrated circuit, and when detection finds that circuit has defect, the connecting line of these fusible can be used for repairing or replacing defective circuit; In addition, fuse can also provide the function of sequencing, first circuit, device array and programmed circuit is processed on chip, then carries out data input by outside, the design by programmed circuit blow out fuse with completing circuit; For example, in programmable read only memory (Programmable Read Only Memory, PROM), by blow out fuse, produce and open circuit, be state " 1 ", and the fuse not disconnecting keeps connection status, is state " 0 ".
In the several frequently seen fuse-wires structure of prior art, polysilicon fuse structure is generally at CMOS(Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors (CMOS)), in transistorized forming process, form with polygate electrodes layer simultaneously; In existing small-scale integrated circuit, in order to dwindle transistorized size, do not affect device performance simultaneously, described transistor often adopts high-K metal grid (HKMG, High K Metal Gate) structure, in forming transistorized process, the dummy gate layer that described polysilicon fuse and the polysilicon of take are material forms simultaneously.
Yet, the existing fuse-wires structure poor-performing simultaneously forming with CMOS transistor, and form complex process.
More fuse-wires structures and forming method thereof please refer to the U.S. patent documents that publication number is US 2006/0157819 A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of semiconductor device, improves the performance of the fuse-wires structure simultaneously forming with transistor.
For addressing the above problem, the invention provides a kind of formation method of semiconductor device, comprising: Semiconductor substrate is provided, in described Semiconductor substrate, there is fleet plough groove isolation structure, the surface of described fleet plough groove isolation structure and the flush of Semiconductor substrate; At described semiconductor substrate surface, form dummy grid, at described surface of shallow trench isolation structure, form fuse-wires structure, the height of described fuse-wires structure is lower than the height of described dummy grid; In the Semiconductor substrate of described dummy grid both sides, form stressor layers, described stressor layers surface lower than described fuse-wires structure surface or with described fuse-wires structure flush; At described fuse-wires structure, stressor layers, Semiconductor substrate and surface of shallow trench isolation structure, form dielectric layer, the surface of described dielectric layer flushes with the top of dummy grid, and described dielectric layer covers the sidewall of described fuse-wires structure surface and dummy grid; After forming dielectric layer, remove described dummy grid, in the position of described dummy grid, form grid structure; After forming grid structure, remove the dielectric layer on described stressor layers and fuse-wires structure surface, form first opening on stressor layers surface and second opening on fuse-wires structure surface; On the stressor layers surface of described the first open bottom and the fuse-wires structure surface of the second open bottom, form metal silicide layer; After forming described metal silicide layer, form and fill full described the first opening and the second opening, and cover the conductive layer of described dielectric layer and grid structure; Removal, higher than the conductive layer on dielectric layer surface, forms the first conductive plunger in the first opening.
Alternatively, low 10 nanometer-50 nanometers of the height of dummy grid described in the aspect ratio of described fuse-wires structure.
Alternatively, the material of described dummy grid and fuse-wires structure is polysilicon.
Alternatively, the formation method of described dummy grid and fuse-wires structure is: at described Semiconductor substrate and surface of shallow trench isolation structure deposit spathic silicon layer; The polysilicon layer that returns etching surface of shallow trench isolation structure, makes the polysilicon layer of surface of shallow trench isolation structure lower than the polysilicon layer of semiconductor substrate surface; After returning etching technics, etched portions polysilicon layer is until expose Semiconductor substrate and fleet plough groove isolation structure, formation dummy grid and fuse-wires structure.
Alternatively, have doping ion in the polycrystalline silicon material of described fuse-wires structure, described doping ion comprises: boron, phosphorus or arsenic.
Alternatively, described doping ion adopts in-situ doped technique or ion implantation technology to form in described polysilicon.
Alternatively, also comprise: before forming stressor layers, at described dummy grid and fuse-wires structure both sides, form side wall; In the Semiconductor substrate of described dummy grid and side wall both sides, form stressor layers.
Alternatively, sidewall and the semiconductor substrate surface of described stressor layers is " Σ " shape, and the sidewall of described stressor layers extends in the Semiconductor substrate of dummy gate structure below.
Alternatively, the material of described stressor layers is SiGe or carborundum.
Alternatively, described grid structure comprises: the metal gate layers that is positioned at the high K dielectric layer of semiconductor substrate surface and is positioned at described high K dielectric layer surface.
Alternatively, also comprise: at the silicon oxide layer between described Semiconductor substrate and high K dielectric layer and the protective layer between described high K dielectric layer and metal gate layers.
Alternatively, the material titanium nitride of described protective layer and one or both combinations in tantalum nitride.
Alternatively, the formation method of described grid structure comprises: dummy grid expose semiconductor substrate surface described in etching, forms the 3rd opening; High K dielectric layer is formed on the bottom at described the 3rd opening; On described high K dielectric layer surface, form the metal gate layers of filling full described the 3rd opening.
Alternatively, the material of described high K dielectric layer is: be hafnium oxide, hafnium silicon oxide, nitrogen hafnium oxide, nitrogen hafnium silicon oxide, nitrogen hafnium oxide tantalum, zirconia, nitrogen zirconia, nitrogen zirconium silicon oxide, zirconium silicon oxide, lanthana, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide.
Alternatively, the material of described metal gate layers is: one or more combinations in aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum and tungsten.
Alternatively, the material of described metal silicide layer is nisiloy, titanium silicon or cobalt silicon.
Alternatively, the formation method of described metal silicide layer is: at the stressor layers surface of the first open bottom, fuse-wires structure surface and the dielectric layer surface deposition metal level of the second open bottom, the material of described metal level is nickel, titanium or cobalt; After forming metal level, carry out thermal annealing, the metal in metal level is combined with the silicon in stressor layers and fuse-wires structure, form metal silicide layer; Remove the remaining metal level in metal silicide layer surface.
Alternatively, described removal is CMP (Chemical Mechanical Polishing) process higher than the technique of the conductive layer on dielectric layer surface.
Alternatively, also comprise: after removing the conductive layer higher than dielectric layer surface, adopt back etching technics to remove remaining conductive layer in the second opening.
Alternatively, the material of described conductive plunger is copper, tungsten or aluminium.
Alternatively, the material of described dielectric layer is silica.
Alternatively, the surface of described stressor layers is lower than described fuse-wires structure surface 5 nanometer-10 nanometers, higher than surface 10 nanometer-50 nanometers of Semiconductor substrate.
Alternatively, also comprise: on described dielectric layer, grid structure and fuse-wires structure surface, form second medium layer, in described second medium layer, have the 4th opening, described the 4th opening exposes the surface of the first conductive plunger and the surface at described fuse-wires structure two ends; In described the 4th opening, form the second conductive plunger.
Compared with prior art, technical scheme of the present invention has the following advantages:
Be formed at the dummy grid of semiconductor substrate surface higher than the fuse-wires structure that is formed at surface of shallow trench isolation structure, can make to be formed at the metal silicide layer on fuse-wires structure surface lower than the grid structure of follow-up formation; Therefore, the dielectric layer flushing with dummy grid height can cover described fuse-wires structure surface, can remove dummy grid and form in the technique of grid structure, protection fuse-wires structure surface; In addition, in the process of follow-up formation conductive plunger, because needs are removed the conductive layer higher than dielectric layer surface, therefore when the metal silicide layer on fuse-wires structure surface is during lower than described dielectric layer, can avoid in removing the technique of conductive layer, described metal silicide layer sustains damage, thereby has guaranteed the stable performance of fuse-wires structure.
Further, because the dielectric layer on stressor layers and fuse-wires structure surface is removed simultaneously, and the metal silicide on stressor layers surface and fuse-wires structure surface forms in same processing step, thereby simplified processing step, saved cost.
Accompanying drawing explanation
Fig. 1 to Fig. 4 is the cross-sectional view of the forming process of fuse-wires structure in prior art;
Fig. 5 to Figure 16 is the cross-sectional view of the forming process of the semiconductor device described in the embodiment of the present invention.
Embodiment
As stated in the Background Art, the existing fuse-wires structure poor-performing simultaneously forming with transistor, and form complex process.
The cross-section structure of the fuse-wires structure of prior art comprises: the polysilicon layer that is positioned at described surface of shallow trench isolation structure, and the metal silicide layer that is positioned at described polysilicon layer surface, the contact zone that described polysilicon layer and metal silicide layer comprise fuse area and be positioned at fuse area two ends; Wherein, because the resistance of described metal silicide layer is lower, when the contact zone to described metal silicide layer two ends applies high-voltage pulse, in described metal silicide layer, can produce Transient Currents, by the fuse area fusing of described metal silicide layer; Meanwhile, the heat that described Transient Currents produces, makes to be positioned at the polysilicon layer recrystallization of metal silicide layer fuse area below, and impurity arranges again, thereby the resistance of the contact zone at described polysilicon layer two ends is significantly increased.In addition, in prior art, described fuse-wires structure and transistor form simultaneously, to simplify processing step.
Yet the present inventor finds through research, in prior art, the performance of the fuse-wires structure simultaneously forming with transistor is not good.Concrete, the cross-sectional view of the forming process of fuse-wires structure in prior art, as shown in Figures 1 to 4, comprising:
Please refer to Fig. 1, Semiconductor substrate 100 is provided, in described Semiconductor substrate 100, there is fleet plough groove isolation structure 101; Described Semiconductor substrate 100 surfaces have dummy grid 102, and described dummy grid 102 both sides have side wall 103, in the Semiconductor substrate 100 of described dummy grid 102 and side wall 103 both sides, have stressor layers 104; Described fleet plough groove isolation structure 101 surfaces have fuse-wires structure 105, and the material of described dummy grid 102 and fuse-wires structure 105 is polysilicon; Described Semiconductor substrate 100, fleet plough groove isolation structure 101 and stressor layers 104 surfaces have dielectric layer 106, and the top of described dielectric layer 106 flushes with dummy grid 102 and fuse-wires structure 105.
Please refer to Fig. 2, at described dielectric layer 106 and fuse-wires structure 105 surfaces, form mask layer 107, described mask layer 107 exposes dummy grid 102(as shown in Figure 1) surface; Take described mask layer 1 07 as mask removal dummy gate layer 102, and form metal gate 108 in the position of former dummy grid 102, described metal gate 108 flushes with dielectric layer 106.
Please refer to Fig. 3, remove described mask layer 107(as shown in Figure 2), and form the first metal silicide layer 109 on described fuse-wires structure 105 surfaces.
Please refer to Fig. 4, form after the first metal silicide layer 109, on described stressor layers 104 surfaces, form opening (not shown), stressor layers 104 surfaces in described open bottom form the second metal silicide layer 110, and form the conductive layer (not shown) of filling full described opening on the second metal silicide layer 110 surfaces of described open bottom; Adopt CMP (Chemical Mechanical Polishing) process to remove the conductive layer higher than dielectric layer 106 surfaces, form conductive plunger 111.
The present inventor studies discovery, and because described fuse-wires structure 105 flushes with dielectric layer 106, the first metal silicide layer 109 therefore forming on described fuse-wires structure 105 surfaces also flushes with described dielectric layer 106; Yet, during due to formation conductive plunger 111, need to adopt CMP (Chemical Mechanical Polishing) process to remove the conductive layer higher than dielectric layer 106 surfaces, and described CMP (Chemical Mechanical Polishing) process is usingd described dielectric layer 106 as polishing stop layer, therefore described CMP (Chemical Mechanical Polishing) process can be damaged the first metal silicide layer 109 flushing with described dielectric layer 106, and then causes the performance of described fuse-wires structure 105 bad.
And during due to opening above forming stressor layers 104, the surface coverage of fuse-wires structure 105 has mask layer 107, and described mask layer 107 continues to shield in the process of follow-up formation conductive plunger 111; Therefore, prior art, when forming the second metal silicide layer 110, can not form the first metal silicide layer 109 simultaneously on the surface of fuse-wires structure 105; Thereby need to increase processing step, on fuse-wires structure 105 surfaces, form the first metal silicide layer 109, make processing step complicated, and extend the process time.
The present inventor after further research, make to be formed at the height of the dummy grid of semiconductor substrate surface, higher than the height of fuse-wires structure that is formed at surface of shallow trench isolation structure, make the metal silicide layer that is formed at fuse-wires structure surface also lower than dielectric layer surface; Thereby guaranteed that CMP (Chemical Mechanical Polishing) process can not damaged the metal silicide layer on described fuse-wires structure surface, makes the stable performance of formed fuse-wires structure in forming the process of conductive plunger; In addition, make described formed dielectric layer identical with the height of dummy grid, and described fuse-wires structure is lower than described dummy grid, therefore described dielectric layer covers described fuse-wires structure; Removing dummy grid and with grid structure in alternative process, described fuse-wires structure can be subject to the protection of described dielectric layer and avoid damage; And the dielectric layer on described fuse-wires structure and stressor layers surface is removed simultaneously, and the metal silicide layer on fuse-wires structure and stressor layers surface forms simultaneously, and without forming extra mask layer, thereby can save processing step, save the process time, and reduce cost.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Fig. 5 to Figure 16 is the cross-sectional view of the forming process of the semiconductor device described in the embodiment of the present invention.
Please refer to Fig. 5, Semiconductor substrate 200 is provided, in described Semiconductor substrate 200, there is fleet plough groove isolation structure 201, the flush of the surface of described fleet plough groove isolation structure 201 and Semiconductor substrate 200; At described Semiconductor substrate 200 and fleet plough groove isolation structure 201 surface deposition polysilicon layers 202.
Described Semiconductor substrate 200 is used to subsequent technique that workbench is provided, and the material of described Semiconductor substrate 200 is silicon or silicon-on-insulator; In the present embodiment, the indices of crystallographic plane on described Semiconductor substrate 200 surfaces are (100).
The material of described fleet plough groove isolation structure 201 is silica, and the surface of described fleet plough groove isolation structure 201 is used to form fuse-wires structure in subsequent technique; The formation technique of described fleet plough groove isolation structure 201 is well known to those skilled in the art, and therefore not to repeat here.
Described Semiconductor substrate 200 surfaces are used to form transistor, comprising: PMOS transistor, nmos pass transistor or CMOS transistor; Described fuse-wires structure is formed in forming described transistorized process; When described transistor is high-K metal grid (HKMG, High-k Metal Gate) structure, the fuse layer in described fuse-wires structure and transistorized dummy gate structure form simultaneously; In the present embodiment, described Semiconductor substrate 200 surfaces form the transistor with high K dielectric layer and metal gates in subsequent technique.
Described polysilicon layer 202 is for forming fuse-wires structure and transistorized dummy grid at subsequent technique; The formation technique of described polysilicon layer 202 is depositing operation, preferably selective epitaxial depositing operation; While having doping ion in described polysilicon layer 202, the resistivity of described polysilicon layer 202 changes; Because the follow-up dummy grid that is formed at Semiconductor substrate 200 surfaces will be removed, and replaced by grid structure, therefore interior the adulterated ion of described polysilicon layer 202 is without the restriction that is subject to transistorized grid conduction type; And then the interior doping ion of described polysilicon layer 202 is advisable to meet the technological requirement of fuse-wires structure 202, and without the transistorized conduction type of considering follow-up formation.
Described doping ion comprises: boron, phosphorus or arsenic; In one embodiment, after the described polysilicon layer 202 of deposition, adopt ion implantation technology at the interior doping ion of above-mentioned polysilicon layer 202; In another embodiment, in forming the process of described polysilicon layer 202, adopt in-situ doped technique at the interior doping ion of polysilicon layer 202.
Please refer to Fig. 6, return the polysilicon layer 202 on etching fleet plough groove isolation structure 201 surfaces, make the polysilicon layer 202 on fleet plough groove isolation structure 201 surfaces lower than the polysilicon layer 202 on Semiconductor substrate 200 surfaces.
The polysilicon layer 202 on described fleet plough groove isolation structure 201 surfaces is lower than the polysilicon layer 202 on Semiconductor substrate 200 surfaces, can make the follow-up height that is formed at the fuse-wires structure on fleet plough groove isolation structure 201 surfaces, lower than the height that is formed at the dummy grid on Semiconductor substrate 200 surfaces; Therefore, the top of the follow-up metal silicide layer that is formed at fuse-wires structure surface is also lower than the top of grid structure; And then the CMP (Chemical Mechanical Polishing) process while making follow-up formation conductive plunger can not damaged the metal silicide layer on fuse-wires structure surface, make the performance of follow-up formed fuse-wires structure better.
In addition, due to the follow-up height that is formed at the fuse-wires structure on fleet plough groove isolation structure 201 surfaces, lower than the height that is formed at the dummy grid on Semiconductor substrate 200 surfaces, make the dielectric layer flushing with dummy grid top of follow-up formation cover the fuse-wires structure surface of follow-up formation, described dielectric layer can be at follow-up removal dummy grid, and forms in the process of grid structure and protect described fuse-wires structure surface; And, during first opening on follow-up formation stressor layers surface, can remove the dielectric layer on fuse-wires structure surface simultaneously, thereby without extra mask layer, can form the metal silicide layer on stressor layers and fuse-wires structure surface simultaneously; Therefore, the formation method of semiconductor device is simple described in the present embodiment, saves process time and cost.
Described time etching technics is: at described polysilicon layer 202(as shown in Figure 5) surface formation photoresist layer; Described photoresist layer is carried out to exposure imaging, make described photoresist layer expose the correspondence position of fleet plough groove isolation structure 201; The photoresist layer of take after exposure is mask, returns polysilicon layer 202 described in etching, makes the polysilicon layer 202 on fleet plough groove isolation structure 201 surfaces lower than the polysilicon layer 202 on Semiconductor substrate 200 surfaces, and described time etching technics is dry etching; After returning etching technics, remove described photoresist layer.
It should be noted that, the polysilicon layer 202 on described fleet plough groove isolation structure 201 surfaces, than the distance of low 10 nanometer-50 nanometers of polysilicon layer 202 on Semiconductor substrate 200 surfaces, can guarantee the follow-up top that is formed at the metal silicide layer on fuse-wires structure surface, lower than the top of formed grid structure and dielectric layer, thereby make the CMP (Chemical Mechanical Polishing) process in follow-up formation conductive plunger process can not destroy the metal silicide layer on fuse-wires structure surface.
Please refer to Fig. 7, after returning etching technics, etched portions polysilicon layer 202(as shown in Figure 6), until expose Semiconductor substrate 200 and fleet plough groove isolation structure 201, form dummy grid 203 and fuse-wires structure 204, the height of described fuse-wires structure 204 is lower than the height of described dummy grid 203.
Described dummy grid 203 is used to the grid structure of follow-up formation to take up space; Described fuse-wires structure 204 comprises the contact zone (not shown) at fuse area (not shown) and fuse area two ends; The width of the more described contact zone of width of described fuse area is narrow, and described contact zone is used for carrying out electrical interconnection; After the contact zone access Transient Currents at fuse-wires structure 204 two ends, because described fuse area is narrower, after being heated, easily fused, thereby realized the function of fuse-wires structure 204.
The formation technique of described dummy grid 203 and fuse-wires structure 204 is: on described polysilicon layer 202 surfaces, form mask layer 220, described mask layer 220 covers the correspondence position that need to form dummy grid 203 and fuse-wires structure 204; Adopt polysilicon layer 202 described in anisotropic dry etch process etching, until expose Semiconductor substrate 200 and fleet plough groove isolation structure 201.
Because the etching technics that returns before makes the polysilicon layer 202 on fleet plough groove isolation structure 201 surfaces lower than the polysilicon layer 202 on Semiconductor substrate 200 surfaces, therefore the height of formed fuse-wires structure 204 is lower than the height of described dummy grid 203, and described fuse-wires structure 204 is 10 nanometer-50 nanometers lower than the distance of described dummy grid 203.
Described fuse-wires structure 204, lower than described dummy grid 203, makes the dielectric layer flushing with dummy grid 203 of follow-up formation can cover described fuse-wires structure, thereby at follow-up removal dummy grid 203 and while forming grid structure, protects described fuse-wires structure surface; In addition, described fuse-wires structure 204 is 10 nanometer-50 nanometers lower than the distance of described dummy grid 203, guaranteed that the follow-up metal silicide layer that is formed at fuse-wires structure surface is lower than grid structure and dielectric layer, thereby avoided in the process of follow-up formation conductive plunger the damage of CMP (Chemical Mechanical Polishing) process to the metal silicide on fuse-wires structure 204 surfaces.
Please refer to Fig. 8, at described dummy grid 203 and fuse-wires structure 204 both sides, form side wall 205.
Described side wall 205 comprises and is positioned at the first side wall of dummy grid 203 and fuse-wires structure 204 both sides and the pseudo-side wall in described the first side wall outside; The material of described the first side wall is silica, and the material of described pseudo-side wall is silicon nitride, and described pseudo-side wall, for defining the follow-up position that is formed at the stressor layers of dummy grid 203 and side wall 205 both sides, avoids producing short-channel effect.
The formation technique of described side wall 205 is: the silicon nitride layer that forms silicon oxide layer and silicon oxide layer surface on described Semiconductor substrate 200, fleet plough groove isolation structure 201, dummy grid 203 and fuse-wires structure 204 surfaces; Return silicon oxide layer and silicon nitride layer described in etching, at described dummy grid 203 and fuse-wires structure 204 both sides, form the first side wall and pseudo-side wall; In the present embodiment, described the first side wall and pseudo-side wall form side wall 205.
In another embodiment, after follow-up formation stressor layers, remove described pseudo-side wall and form the second side wall, the material of described the second side wall is one or both combinations in silicon nitride and silica; In the process in follow-up formation stressor layers, described pseudo-side wall can be thinned, and therefore need to form more accurate the second side wall of size and replace described pseudo-side wall, is more conducive to formed transistorized stable performance; In this embodiment, described side wall 205 consists of the first side wall and the second side wall.
Please refer to Fig. 9, the interior formation stressor layers 206 of Semiconductor substrate 200 in described dummy grid 203 and side wall 205 both sides, described stressor layers 206 surfaces lower than described fuse-wires structure 204 surfaces or with described fuse-wires structure 204 flush.
The material of described stressor layers 206 is SiGe or carborundum; When formed transistor is PMOS pipe, the material of described stressor layers 206 is SiGe, to transistorized channel region, provides compression; When formed transistor is NMOS pipe, the material of described stressor layers 206 is carborundum, to transistorized channel region, provides tension stress.
The surface of the sidewall of described stressor layers 206 and Semiconductor substrate 200 is " Σ " (Sigma, Sigma) type; In the present embodiment, the surface of described stressor layers 206 is lower than surface 5 nanometer-10 nanometers of described fuse-wires structure 204, higher than surface 10 nanometer-50 nanometers of Semiconductor substrate 200; In another embodiment, the flush of described stressor layers 206 and described fuse-wires structure 204, described stressor layers 206 is 10 nanometer-50 nanometers lower than the distance of described dummy grid 203.
Between the material of the material of described stressor layers 206 and Semiconductor substrate 200, have lattice mismatch, and the stress that described lattice mismatch produces can apply and gives formed transistorized channel region; And the sidewall of described stressor layers 206 is to the interior extension of Semiconductor substrate 200, make the distance between the stressor layers 206 of dummy grid 203 both sides nearer, thereby it is larger to put on the stress of channel region, is more conducive to the migration of charge carrier.
The formation technique of described stressor layers 206 is: at the interior formation opening of Semiconductor substrate 200 (not shown) of dummy grid 203 and side wall 205 both sides, the surface of the sidewall of described opening and Semiconductor substrate 200 is " Σ " type; In described opening, adopt epitaxial deposition process to form stressor layers 206; After forming stressor layers 206, at the interior injection of described stressor layers 206 P type ion or N-type ion, form source region and drain region.
Wherein, the formation technique of described opening is: adopt the Semiconductor substrate 200 interior formation sidewall of anisotropic dry etch process in described dummy grid 203 and the side wall 205 both sides opening (not shown) vertical with Semiconductor substrate 100 surfaces; After described anisotropic dry etch process, adopt opening described in anisotropic wet-etching technology etching, make drift angle on described opening sidewalls to the interior extension of Semiconductor substrate 200 of dummy grid 203 belows, form the opening of " Σ " shape.
Crystal face when described Semiconductor substrate 200 surfaces is (100), and described anisotropic wet etching is very fast perpendicular to Semiconductor substrate 200 surface and the etch rate that is parallel in the direction on Semiconductor substrate 200 surfaces, and etch rate when etching crystal face (111) is the slowest, thereby make the sidewall of described opening and Semiconductor substrate 200 surfaces be " Σ " shape; When forming in described opening after stressor layers 206, between adjacent stressor layers 206, distance is less, and the stress that puts on transistor channel region is larger.
It should be noted that, in one embodiment, after forming described stressor layers 206, remove described pseudo-side wall, at described dummy grid 203 and the first side wall both sides, form the second side wall, the material of described the second side wall is one or both combinations in silicon nitride and silica; In this embodiment, described side wall 205 consists of the first side wall and the second side wall, and the size of described side wall 205 is easily controlled.
Please refer to Figure 10, on described fuse-wires structure 204, stressor layers 206, Semiconductor substrate 200 and fleet plough groove isolation structure 201 surfaces, form dielectric layer 207, the surface of described dielectric layer 207 flushes with the top of dummy grid 203, and described dielectric layer 207 covers the sidewall of described fuse-wires structure 204 surfaces and dummy grid 203.
The material of described dielectric layer 207 is silica, and described dielectric layer 207 is for making to be formed at the device electricity isolation on Semiconductor substrate 200 surfaces; The formation technique of described dielectric layer 207 is: adopt chemical vapor deposition method to form dielectric film on described dummy grid 203, fuse-wires structure 204, stressor layers 206, Semiconductor substrate 200 and fleet plough groove isolation structure 201 surfaces; Dielectric film described in the planarization of employing CMP (Chemical Mechanical Polishing) process, until expose dummy grid 203, forms dielectric layer 207.
Because described fuse-wires structure 204 is lower than described dummy grid 203, therefore the described dielectric layer 207 flushing with dummy grid 203 tops still covers described fuse-wires structure 204, thereby at follow-up removal dummy grid 203 and form in the process of grid structure, protect described fuse-wires structure 204 surfaces; In addition, in subsequent technique, the dielectric layer 207 on fuse-wires structure 204 and stressor layers 206 surfaces can be removed simultaneously, and to take remaining dielectric layer 207 be mask, can at fuse-wires structure 204 and stressor layers 206 surfaces, form metal silicide layer simultaneously, thereby simplification technique, saves process time and cost.
It should be noted that, after adopting the dielectric film on CMP (Chemical Mechanical Polishing) process removal dummy grid 203 surfaces, remove the mask layer 220 on dummy grid 203 surfaces, and expose dummy grid 203 surfaces.
Please refer to Figure 11, after forming dielectric layer 207, remove described dummy grid 203(as shown in figure 10), in the position of described dummy grid 203, form grid structure 208.
The formation technique of described grid structure 208 is: adopt dry etching or wet-etching technology to remove dummy gate layer 203, and expose Semiconductor substrate 200, form the 3rd opening; In described the 3rd opening, form grid structure; Described grid structure 208 comprises: be positioned at the high K dielectric layer (not shown) on Semiconductor substrate 200 surfaces and the metal gate layers (not shown) on high K dielectric layer surface.
The material of described high K dielectric layer comprises: be hafnium oxide, hafnium silicon oxide, nitrogen hafnium oxide, nitrogen hafnium silicon oxide, nitrogen hafnium oxide tantalum, zirconia, nitrogen zirconia, nitrogen zirconium silicon oxide, zirconium silicon oxide, lanthana, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide; The material of described metal gate layers comprises: one or more combinations in aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum and tungsten.
It should be noted that, between described high K dielectric layer and metal gate layers, can also form protective layer (not shown), described protective layer can have isolation described high K dielectric layer and metal gate layers, and avoids metal to cause that to diffusion in high K dielectric layer device performance is unstable; The material of described protective layer comprises: one or both combinations in titanium nitride and tantalum nitride; In addition, between described high K dielectric layer and Semiconductor substrate 200, can form silicon oxide layer, described silicon oxide layer, for high K dielectric layer and Semiconductor substrate 200 described in bonding, avoids producing leakage current.
The formation technique of described grid structure 208 is well known to those skilled in the art, and therefore not to repeat here; Because removed dummy grid 203 and dielectric layer 207 are higher than fuse-wires structure 204, and described grid structure 208 flushes with dielectric layer 207, and therefore described grid structure 208 is higher than fuse-wires structure 204 tops.
Please refer to Figure 12, after forming grid structure 208, remove the dielectric layer 207 on described stressor layers 206 and fuse-wires structure 204 surfaces, form first opening 209 on stressor layers 206 surfaces and second opening 210 on fuse-wires structure 204 surfaces.
The formation technique of described the first opening 209 and the second opening 210 is: at described dielectric layer 207 and grid structure 208 surfaces, form photoresist layer; Graphical described photoresist layer, makes described photoresist layer expose dielectric layer 207 surfaces of stressor layers and fuse-wires structure correspondence position; Take patterned photoresist layer as mask, adopt dry etch process to form the first opening 209 on stressor layers 206 surfaces, on fuse-wires structure 204 surfaces, form the second opening 210.
Described the first opening 209 and the second opening 2 10 form simultaneously, cause the follow-up metal silicide layer in described the first opening 209 and the second opening 210 bottoms to form simultaneously; Avoided as described in the prior art, fuse-wires structure 105(is as shown in Figure 4) surface forms the first metal silicide layer 109(as shown in Figure 4), and stressor layers 104(is as shown in Figure 4) surface forms the second metal silicide layer 110(as shown in Figure 4) by twice technique, form; Therefore, the formation method work simplification of semiconductor device, can save process time and cost described in the present embodiment.
Described the first opening 209 is used to form conductive plunger in subsequent technique, to realize formed transistorized electrical interconnection; Described the second opening 210 is used to form the metal silicide layer on fuse-wires structure 204 surfaces in subsequent technique, because described fuse-wires structure 204 is lower than dielectric layer 207, therefore, the metal silicide layer on follow-up formation and fuse-wires structure 204 surfaces is also lower than dielectric layer 207, avoided thus forming in the process of conductive plunger the damage of flatening process to the metal silicide layer on fuse-wires structure 204 surfaces.
It should be noted that, after removing the dielectric layer 207 on fuse-wires structure 204 surfaces, remove the mask layer 220(on fuse-wires structure 204 surfaces as shown in figure 11).
Please refer to Figure 13, on stressor layers 206 surfaces of described the first opening 209 bottoms and fuse-wires structure 204 surfaces of the second opening 210 bottoms, form metal silicide layer 2 11.
The material of described metal silicide layer 211 is titanium silicon, nisiloy or cobalt silicon; The metal silicide layer 211 on stressor layers 206 surfaces is for the electrode as formed transistorized source region and drain region; The metal silicide layer 211 on described fuse-wires structure 204 surfaces is for as low resistivity layer, when the contact zone to described fuse-wires structure 204 two ends applies high-voltage pulse, the interior meeting of metal silicide layer 211 on described fuse-wires structure 204 surfaces produces Transient Currents, and produce high heat, thereby by the fuse area fusing of fuse-wires structure 204.
The formation technique of described metal silicide layer 211 is: at stressor layers 206, fuse-wires structure 204, dielectric layer 207 and grid structure 208 surface deposition metal levels, the material of described metal level is titanium, nickel or cobalt; After forming metal level, carry out thermal annealing, the metallic atom in described metal level is diffused in stressor layers 206 and fuse-wires structure 204, form metal silicide layer 211; After thermal annealing, remove the surperficial remaining metal level of metal silicide layer 211.
Because the top of described fuse-wires structure 204 is lower than dielectric layer 207 and grid structure 208, the surface of the metal silicide layers 211 that therefore described fuse-wires structure 204 surfaces form is also lower than described dielectric layer 207 and grid structure; And then in the process of follow-up formation conductive plunger, CMP (Chemical Mechanical Polishing) process can not damaged, attenuate is even removed the metal silicide layer 211 on fuse-wires structure 204 surfaces, make formed fuse-wires structure 204 stable performances.
Please refer to Figure 14, after forming described metal silicide layer 211, form and fill full described the first opening 209(as shown in figure 13) and the second opening 210(is as shown in figure 13) and cover the conductive layer 212 of described dielectric layer 207 and grid structure 208.
The material of described conductive layer 212 is copper, tungsten or aluminium, and described conductive layer 212 is used to form conductive plunger, and the formation technique of described conductive layer 212 is depositing operation, preferably physical gas-phase deposition.
Because described conductive layer 212 is filled full the second opening 210; therefore when subsequent technique is removed the conductive layer 212 higher than dielectric layer 207 surfaces; in described the second opening 210, there is remaining conductive layer 212, and remaining conductive layer 212 can protect the metal silicide layer 211 on fuse-wires structure 204 surfaces can not destroy.
Please refer to Figure 15, remove higher than the conductive layer 212(on dielectric layer 207 surfaces as shown in figure 14), at interior formation the first conductive plunger 213 of the first opening 209.
Described removal is CMP (Chemical Mechanical Polishing) process higher than conductive layer 212 techniques on dielectric layer 207 surfaces, and described CMP (Chemical Mechanical Polishing) process is usingd dielectric layer as stop-layer; After the conductive layer of removing higher than dielectric layer 207 surfaces, in described the first opening 209 and the second opening 20, there is remaining conductive layer 212; The interior remaining conductive layer 212 of described the first opening 209 forms the first conductive plunger 213; The interior remaining conductive layer 212 of described the second opening 210 is in described CMP (Chemical Mechanical Polishing) process, and the metal silicide layer 211 on protection fuse-wires structure 204 surfaces is not damaged, attenuate or remove completely, thereby makes formed fuse-wires structure 204 stable performances.
It should be noted that, after the conductive layer 212 of removing higher than dielectric layer 207 surfaces, adopt back etching technics to remove the interior remaining conductive layer 212 of the second opening 210; The described material due to described conductive layer 212 is different from the material of metal silicide layer 211, therefore in described time etching process, between conductive layer 212 and metal silicide layer 211, there is selectivity, when removing conductive layer 212, be difficult to metal silicide layer 211 to cause damage.
Please refer to Figure 16, on described dielectric layer 207, grid structure 208 and fuse-wires structure 204 surfaces, form second medium layer 214, in described second medium layer 214, have the 4th opening (not shown), described the 4th opening exposes the surface at surface, grid structure 208 and fuse-wires structure 204 two ends of the first conductive plunger 213; In described the 4th opening, form the second conductive plunger 215.
The material of described second medium layer 214 is silica, and formation technique is depositing operation, preferably chemical vapour deposition (CVD) work technique; The formation technique of described the 4th opening is anisotropic dry etch process; The material of described the second conductive plunger 215 is copper, tungsten or aluminium, forms technique identical with the technique of the first conductive plunger 213, does not again repeat.
The second conductive plunger 215 that 204 liang of end surfaces of described fuse-wires structure form is connected with the metal silicide layer 211 on fuse-wires structure 204 surfaces, for the metal silicide layer 211 input high-voltage pulses to described fuse-wires structure 204 surfaces, with the fuse area of the described fuse-wires structure 204 that fuses; Second conductive plunger 215 on described the first conductive plunger 213 and grid structure 208 surfaces is for realizing transistorized electrical interconnection.
In the present embodiment, the polysilicon layer 202(on fleet plough groove isolation structure 201 surfaces is as shown in Figure 6) lower than the polysilicon layer 202 on Semiconductor substrate 200 surfaces, make formed fuse-wires structure 204 lower than described dummy grid 203; And flush with dummy grid 203 for the dielectric layer 207 of isolating device, therefore described dielectric layer 207 covers described fuse-wires structure 204, protects described fuse-wires structure surface 204 in subsequent technique; Secondly, the dielectric layer 207 of described fuse-wires structure 204 surfaces and stressor layers 206 is removed simultaneously, and the remaining dielectric layer 207 of take is mask, can at fuse-wires structure 204 and stressor layers 206 surfaces, form metal silicide layer 211 simultaneously, thereby save process time and cost; Again, because the metal silicide layer 211 on fuse-wires structure 204 surfaces is lower than dielectric layer 207 surfaces, therefore in forming the process of the first conductive plunger 213, CMP (Chemical Mechanical Polishing) process can not destroyed the metal silicide layer 211 on fuse-wires structure 204 surfaces, makes formed fuse-wires structure functional.
In sum, be formed at the dummy grid of semiconductor substrate surface higher than the fuse-wires structure that is formed at surface of shallow trench isolation structure, can make to be formed at the metal silicide layer on fuse-wires structure surface lower than the grid structure of follow-up formation; Therefore, the dielectric layer flushing with dummy grid height can cover described fuse-wires structure surface, can remove dummy grid and form in the technique of grid structure, protection fuse-wires structure surface; In addition, in the process of follow-up formation conductive plunger, because needs are removed the conductive layer higher than dielectric layer surface, therefore when the metal silicide layer on fuse-wires structure surface is during lower than described dielectric layer, can avoid in removing the technique of conductive layer, described metal silicide layer sustains damage, thereby has guaranteed the stable performance of fuse-wires structure.
Further, because the dielectric layer on stressor layers and fuse-wires structure surface is removed simultaneously, and the metal silicide on stressor layers surface and fuse-wires structure surface forms in same processing step, thereby simplified processing step, saved cost.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (23)
1. a formation method for semiconductor device, is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, there is fleet plough groove isolation structure, the surface of described fleet plough groove isolation structure and the flush of Semiconductor substrate;
At described semiconductor substrate surface, form dummy grid, at described surface of shallow trench isolation structure, form fuse-wires structure, the height of described fuse-wires structure is lower than the height of described dummy grid;
In the Semiconductor substrate of described dummy grid both sides, form stressor layers, described stressor layers surface lower than described fuse-wires structure surface or with described fuse-wires structure flush;
At described fuse-wires structure, stressor layers, Semiconductor substrate and surface of shallow trench isolation structure, form dielectric layer, the surface of described dielectric layer flushes with the top of dummy grid, and described dielectric layer covers the sidewall of described fuse-wires structure surface and dummy grid;
After forming dielectric layer, remove described dummy grid, in the position of described dummy grid, form grid structure;
After forming grid structure, remove the dielectric layer on described stressor layers and fuse-wires structure surface, form first opening on stressor layers surface and second opening on fuse-wires structure surface;
On the stressor layers surface of described the first open bottom and the fuse-wires structure surface of the second open bottom, form metal silicide layer;
After forming described metal silicide layer, form the conductive layer of filling full described the first opening and the second opening and covering described dielectric layer and grid structure;
Removal, higher than the conductive layer on dielectric layer surface, forms the first conductive plunger in the first opening.
2. the formation method of semiconductor device as claimed in claim 1, is characterized in that, low 10 nanometer-50 nanometers of height of dummy grid described in the aspect ratio of described fuse-wires structure.
3. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the material of described dummy grid and fuse-wires structure is polysilicon.
4. the formation method of semiconductor device as claimed in claim 3, is characterized in that, the formation method of described dummy grid and fuse-wires structure is: at described Semiconductor substrate and surface of shallow trench isolation structure deposit spathic silicon layer; The polysilicon layer that returns etching surface of shallow trench isolation structure, makes the polysilicon layer of surface of shallow trench isolation structure lower than the polysilicon layer of semiconductor substrate surface; After returning etching technics, etched portions polysilicon layer is until expose Semiconductor substrate and fleet plough groove isolation structure, formation dummy grid and fuse-wires structure.
5. the formation method of semiconductor device as claimed in claim 3, is characterized in that in the polycrystalline silicon material of described fuse-wires structure, having doping ion, and described doping ion comprises: boron, phosphorus or arsenic.
6. the formation method of semiconductor device as claimed in claim 5, is characterized in that, described doping ion adopts in-situ doped technique or ion implantation technology to form in described polysilicon.
7. the formation method of semiconductor device as claimed in claim 1, is characterized in that, also comprises: before forming stressor layers, at described dummy grid and fuse-wires structure both sides, form side wall; In the Semiconductor substrate of described dummy grid and side wall both sides, form stressor layers.
8. the formation method of semiconductor device as claimed in claim 1, is characterized in that, sidewall and the semiconductor substrate surface of described stressor layers is " Σ " shape, and the sidewall of described stressor layers extends in the Semiconductor substrate of dummy gate structure below.
9. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the material of described stressor layers is SiGe or carborundum.
10. the formation method of semiconductor device as claimed in claim 1, is characterized in that, described grid structure comprises: the metal gate layers that is positioned at the high K dielectric layer of semiconductor substrate surface and is positioned at described high K dielectric layer surface.
The 11. formation methods of semiconductor device as claimed in claim 10, is characterized in that, also comprise: at the silicon oxide layer between described Semiconductor substrate and high K dielectric layer and the protective layer between described high K dielectric layer and metal gate layers.
The 12. formation methods of semiconductor device as claimed in claim 11, is characterized in that the material titanium nitride of described protective layer and one or both combinations in tantalum nitride.
The 13. formation methods of semiconductor device as claimed in claim 10, is characterized in that, the formation method of described grid structure comprises: dummy grid expose semiconductor substrate surface described in etching, forms the 3rd opening; High K dielectric layer is formed on the bottom at described the 3rd opening; On described high K dielectric layer surface, form the metal gate layers of filling full described the 3rd opening.
The 14. formation methods of semiconductor device as claimed in claim 10, it is characterized in that, the material of described high K dielectric layer is: be hafnium oxide, hafnium silicon oxide, nitrogen hafnium oxide, nitrogen hafnium silicon oxide, nitrogen hafnium oxide tantalum, zirconia, nitrogen zirconia, nitrogen zirconium silicon oxide, zirconium silicon oxide, lanthana, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide.
The 15. formation methods of semiconductor device as claimed in claim 10, is characterized in that, the material of described metal gate layers is: one or more combinations in aluminium, copper, silver, gold, platinum, nickel, titanium, cobalt, thallium, tantalum and tungsten.
The 16. formation methods of semiconductor device as claimed in claim 1, is characterized in that, the material of described metal silicide layer is nisiloy, titanium silicon or cobalt silicon.
The 17. formation methods of semiconductor device as claimed in claim 1, it is characterized in that, the formation method of described metal silicide layer is: at the stressor layers surface of the first open bottom, fuse-wires structure surface and the dielectric layer surface deposition metal level of the second open bottom, the material of described metal level is nickel, titanium or cobalt; After forming metal level, carry out thermal annealing, the metal in metal level is combined with the silicon in stressor layers and fuse-wires structure, form metal silicide layer; Remove the remaining metal level in metal silicide layer surface.
The 18. formation methods of semiconductor device as claimed in claim 1, is characterized in that, described removal is CMP (Chemical Mechanical Polishing) process higher than the technique of the conductive layer on dielectric layer surface.
The 19. formation methods of semiconductor device as claimed in claim 1, is characterized in that, also comprise: after removing the conductive layer higher than dielectric layer surface, adopts back etching technics to remove the interior remaining conductive layer of the second opening.
The 20. formation methods of semiconductor device as claimed in claim 1, is characterized in that, the material of described conductive plunger is copper, tungsten or aluminium.
The 21. formation methods of semiconductor device as claimed in claim 1, is characterized in that, the material of described dielectric layer is silica.
The 22. formation methods of semiconductor device as claimed in claim 1, is characterized in that, the surface of described stressor layers is lower than described fuse-wires structure surface 5 nanometer-10 nanometers, higher than surface 10 nanometer-50 nanometers of Semiconductor substrate.
The 23. formation methods of semiconductor device as claimed in claim 1, it is characterized in that, also comprise: on described dielectric layer, grid structure and fuse-wires structure surface, form second medium layer, in described second medium layer, have the 4th opening, described the 4th opening exposes the surface of the first conductive plunger and the surface at described fuse-wires structure two ends; In described the 4th opening, form the second conductive plunger.
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