CN103779198B - Semiconductor device and forming method thereof - Google Patents

Semiconductor device and forming method thereof Download PDF

Info

Publication number
CN103779198B
CN103779198B CN201210406263.3A CN201210406263A CN103779198B CN 103779198 B CN103779198 B CN 103779198B CN 201210406263 A CN201210406263 A CN 201210406263A CN 103779198 B CN103779198 B CN 103779198B
Authority
CN
China
Prior art keywords
layer
work
dielectric layer
grid structure
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210406263.3A
Other languages
Chinese (zh)
Other versions
CN103779198A (en
Inventor
洪中山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201210406263.3A priority Critical patent/CN103779198B/en
Publication of CN103779198A publication Critical patent/CN103779198A/en
Application granted granted Critical
Publication of CN103779198B publication Critical patent/CN103779198B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A kind of semiconductor device and forming method thereof, wherein, semiconductor device, comprising: Semiconductor substrate, and Semiconductor substrate comprises adjacent first area and second area; Be positioned at the first grid structure of the semiconductor substrate surface of first area, first grid structure comprises: the first high-K gate dielectric layer, be positioned at first work-function layer on the first high-K gate dielectric layer surface and be positioned at the first grid electrode layer on the first work-function layer surface; Be positioned at the second grid structure of second area semiconductor substrate surface, second grid structure comprises: the second high-K gate dielectric layer, be positioned at second work-function layer on the second high-K gate dielectric layer surface and be positioned at the second gate electrode layer on the second work-function layer surface; Be positioned at the second dielectric layer of first grid structure and second grid body structure surface, there is in second dielectric layer the contact through hole exposing part first grid structure and part second grid body structure surface; Be positioned at contact through hole and form the first conductive plunger.Described performance of semiconductor device is good.

Description

Semiconductor device and forming method thereof
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of semiconductor device and forming method thereof.
Background technology
CMOS (Complementary Metal Oxide Semiconductor) pipe (ComplementaryMetal-Oxide-Semiconductor, CMOS) has become semiconductor device conventional in integrated circuit.Described CMOS tube comprises: P-type mos pipe (PMOS) and N-type MOS (metal-oxide-semiconductor) transistor (NMOS).Prior art, in order to control short-channel effect while reduction grid size, adopts high K dielectric material to replace the materials such as conventional silica and forms gate dielectric layer, adopts metal material to replace the materials such as conventional polysilicon and forms gate electrode layer; In addition, in order to regulate the threshold voltage of PMOS and NMOS tube, prior art can form work-function layer (workfunctionlayer) on the gate dielectric layer surface of PMOS and NMOS tube; Wherein, the work-function layer of PMOS needs to have higher work function, and the work-function layer of NMOS tube needs to have lower work function, and therefore PMOS is different with the material of the work-function layer of NMOS tube.
Prior art, in order to improve component density, the raising integrated level of semiconductor device, proposes a kind of CMOS tube of common gate electrode, the gate electrode of PMOS is connected with the gate electrode of NMOS tube, thus reduces the characteristic size of CMOS tube.As depicted in figs. 1 and 2, be the schematic diagram of the CMOS tube of the common gate electrode of prior art, and containing high-K gate dielectric layer and metal gate electrode in described CMOS tube; Wherein, Fig. 1 is the cross-sectional view of described CMOS tube, and Fig. 2 is the plan structure schematic diagram of described CMOS tube.
Please refer to Fig. 1, described CMOS tube comprises: Semiconductor substrate 100, and described Semiconductor substrate 100 comprises adjacent PMOS area I and NMOS area II; Be positioned at the first grid structure 101 on Semiconductor substrate 100 surface of described PMOS area I, described first grid structure 101 comprises: the first high-K gate dielectric layer 110, be positioned at first work-function layer 111 on described first high-K gate dielectric layer 110 surface and be positioned at first metal gate 112 on described first work-function layer 111 surface; Be positioned at the second grid structure 102 on Semiconductor substrate 100 surface of described NMOS area II, described second grid structure 102 comprises: the second high-K gate dielectric layer 120, be positioned at second work-function layer 121 on described second high-K gate dielectric layer 120 surface and be positioned at second metal gate 122 on described second work-function layer 121 surface.It should be noted that, described Semiconductor substrate 100 surface also has the dielectric layer 103 covering described first grid structure 101 and second grid structure 102 sidewall, and the surface of described dielectric layer 103 flushes with the surface of described first grid structure 101 and second grid structure 102.
Please refer to Fig. 2, in PMOS area I, in the Semiconductor substrate 100 that described first grid ties 101 structure both sides, there is the first source region 104 and the first drain region 105; In NMOS area II, there is in the Semiconductor substrate 100 of described second grid structure 102 both sides the second source region 106 and the second drain region 107.
But in prior art, the performance with the common gate electrode CMOS tube of high-K gate dielectric layer and metal gate electrode is not good.
The related data of more CMOS tube please refer to the U.S. patent documents that publication number is US2008/0308872A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of semiconductor device and forming method thereof, improves the performance with the common gate electrode CMOS tube of high-K gate dielectric layer and metal gate electrode.
For solving the problem, the invention provides a kind of formation method of semiconductor device, comprising: provide Semiconductor substrate, described Semiconductor substrate comprises adjacent first area and second area; Semiconductor substrate surface in described first area forms first grid structure, and described first grid structure comprises: the first high-K gate dielectric layer, be positioned at first work-function layer on described first high-K gate dielectric layer surface and be positioned at the first grid electrode layer on described first work-function layer surface; Form second grid structure at described second area semiconductor substrate surface, described second grid structure comprises: the second high-K gate dielectric layer, be positioned at second work-function layer on described second high-K gate dielectric layer surface and be positioned at the second gate electrode layer on described second work-function layer surface; After formation first grid structure and second grid structure, second dielectric layer is formed in described first grid structure and second grid body structure surface, have contact through hole in described second dielectric layer, described contact through hole exposes part first grid structure and part second grid body structure surface; The first conductive plunger is formed in described contact through hole.
Correspondingly, the present invention also provides a kind of semiconductor device, comprising: Semiconductor substrate, and described Semiconductor substrate comprises adjacent first area and second area; Be positioned at the first grid structure of the semiconductor substrate surface of described first area, described first grid structure comprises: the first high-K gate dielectric layer, be positioned at first work-function layer on described first high-K gate dielectric layer surface and be positioned at the first grid electrode layer on described first work-function layer surface; Be positioned at the second grid structure of described second area semiconductor substrate surface, described second grid structure comprises: the second high-K gate dielectric layer, be positioned at second work-function layer on described second high-K gate dielectric layer surface and be positioned at the second gate electrode layer on described second work-function layer surface; Be positioned at the second dielectric layer of described first grid structure and second grid body structure surface, have contact through hole in described second dielectric layer, described contact through hole exposes part first grid structure and part second grid body structure surface; Be positioned at described contact through hole and form the first conductive plunger.
Compared with prior art, technical scheme of the present invention has the following advantages:
After semiconductor substrate surface forms adjacent first grid structure and second grid structure, second dielectric layer is formed in described first grid structure and second grid body structure surface, there is in described second dielectric layer the contact through hole exposing part first grid structure and part second grid body structure surface, and form the first conductive plunger in described contact through hole; Described first conductive plunger can make first grid electrode layer and the electrical connection of second gate electrode layer, thus the resistance that can reduce between first grid electrode layer and second gate electrode layer, avoid in the forming process of described semiconductor device, between described first grid electrode layer and second gate electrode layer, produce the problem of electric isolution; The performance of the semiconductor device formed improves.
Further, after the first grid electrode layer forming high-K dielectric layer at the semiconductor substrate surface of described first area and second area, be positioned at first work-function layer on described high-K dielectric layer surface and be positioned at described first work-function layer surface, first work-function layer of removal second area and first grid electrode layer are till exposing high-K dielectric layer, form the second opening, and form second grid structure in described second opening; Wherein, when removing the first work-function layer and the first grid electrode layer of second area, easily form oxide layer in the first work-function layer of described second opening and the sidewall surfaces of first grid electrode layer side, described oxide layer can improve the resistance between first grid electrode layer and second gate electrode layer, even causes electric isolution; And the first conductive plunger of follow-up formation can make formed first grid electrode layer and the electrical connection of second gate electrode layer, thus reduce the resistance between described first grid electrode layer and second gate electrode layer, improve the performance of the semiconductor device formed.
Further, dummy gate layer is formed at the semiconductor substrate surface of first area and second area; Remove the dummy gate layer of the semiconductor substrate surface of second area, and form second grid structure at the semiconductor substrate surface of described second area; Afterwards, remove the dummy gate layer of the semiconductor substrate surface of first area, and form first grid structure; There is between the first grid structure formed and second grid structure the first high-K gate dielectric layer in first grid structure and the second high-K gate dielectric layer in second grid structure, the resistance between formed first grid electrode layer and second gate electrode layer can be caused to increase, even electric isolution; And the first conductive plunger of follow-up formation can make formed first grid electrode layer and the electrical connection of second gate electrode layer, to reduce the resistance between formed first grid electrode layer and second gate electrode layer, improve the performance of formed semiconductor device.In addition, the formation process step of described semiconductor device is more simple, and is easier to remove due to dummy gate layer, and the dummy gate layer therefore only removing second area is easier to operation, and technique is simple, not easily produces pollution.
Further, in the Semiconductor substrate of first grid structure both sides, the first source region and the first drain region is formed; The second source region and the second drain region is formed in the Semiconductor substrate of second grid structure both sides; And described first source region, the first drain region, the second source region and surface, the second drain region all need the second conductive plunger formed; Described first conductive plunger and described second conductive plunger are formed simultaneously, thus can Simplified flowsheet step, and save the process time.
Described semiconductor structure comprises: be positioned at semiconductor substrate surface and adjacent first grid structure and second grid structure; Described first grid structure and second grid body structure surface have the first conductive plunger, and described first conductive plunger simultaneously with first grid structure and second grid form touch; Therefore, described first conductive plunger can make first grid electrode layer and the electrical connection of second gate electrode layer, thus reduces the resistance between described first grid electrode layer and second gate electrode layer, makes the functional of described semiconductor device.
Accompanying drawing explanation
Fig. 1 is the cross-sectional view of the CMOS tube of the common gate electrode of prior art;
Fig. 2 is the plan structure schematic diagram of the CMOS tube of the common gate electrode of prior art;
Fig. 3 to Fig. 5 is the cross-sectional view that prior art forms the process of common gate electrode CMOS tube;
Fig. 6 to Figure 11 is the cross-sectional view of the forming process of semiconductor device described in first embodiment of the invention;
Figure 12 to Figure 14 is the cross-sectional view of the forming process of semiconductor device described in second embodiment of the invention.
Embodiment
As stated in the Background Art, in prior art, the performance with the common gate electrode CMOS tube of high-K gate dielectric layer and metal gate electrode is not good.
The present inventor finds through research, as described in Figure 1, described first grid structure 101 is for the formation of the grid structure of PMOS, and described second grid structure 102 is for the formation of the grid structure of NMOS tube, therefore, in order to meet the different performance demand of PMOS and NMOS tube, described first work-function layer 111 is different with the material of the second work-function layer 121; Concrete, described first work-function layer 111 needs to have higher work function, described second work-function layer 121 needs to have lower work function, regulates the threshold voltage of formed PMOS and NOMS pipe with this, thus ensures the stable performance of the CMOS tube formed.
In order to form the first different work-function layer 111 and the second work-function layer 121 of material, form the method for described common gate electrode CMOS tube as shown in Figures 3 to 5.
Please refer to Fig. 3, the Semiconductor substrate 100 comprising adjacent PMOS area I and NMOS area II is provided, described Semiconductor substrate 100 surface has dielectric layer 103, there is in described dielectric layer 103 first opening (not shown), described first opening exposes Semiconductor substrate 100 surface of PMOS area I and NMOS area II, have in described first opening and cover the sidewall of described first opening and the high-K gate dielectric layer 130 of lower surface, be positioned at first work-function layer 111 on described high-K gate dielectric layer 130 surface, and be positioned at first metal gate 112 on described first work-function layer 111 surface.
Please refer to Fig. 4, first work-function layer 111 of removal NMOS area II and the first metal gate 112, till exposing high-K gate dielectric layer 130, form the second opening 109.
Please refer to Fig. 5, formed at described second opening 109(as shown in Figure 4) and cover the sidewall of described second opening 109 and the second work-function layer 121 of lower surface, and be positioned at the second metal gate 122 of described second work-function layer 121 surface and full described second opening 109 of filling.Wherein, the high-K gate dielectric layer 130 being positioned at PMOS area I is the first high-K gate dielectric layer 110, and the high-K gate dielectric layer 130 being positioned at NMOS area II is the second high-K gate dielectric layer 120.
But, in the common gate electrode CMOS tube formed with said method, between described first metal gate 112 and the second metal gate 122, easily form oxide layer; Described oxide layer can cause the resistance between described first metal gate 112 and the second metal gate 122 to increase, and even makes electric isolution between described first metal gate 112 and the second metal gate 122, and then makes the degradation of formed CMOS tube.Concrete, because the material of described first metal gate 112 is metal, such as copper, tungsten or aluminium, the material of described first work-function layer 111 is metal or metallic compound, such as titanium nitride or tantalum nitride, and described metal or metallic compound are very easily oxidized; As shown in Figure 4, first work-function layer 111 of described removal NMOS area II and the technique of the first metal gate 112 are anisotropic dry etch process, and the etching gas in described anisotropic dry etch process, or in the cleaning process after described anisotropic dry etch process, very easily make described first metal gate 112 and the first work-function layer 111 be oxidized.Therefore, when forming common gate electrode CMOS tube with said method, the first metal gate 112 of described second opening 109 and the sidewall surfaces of the first work-function layer 111 side form oxide layer; And then after follow-up formation second work-function layer 121 and the second metal gate 122, can be isolated by described oxide layer between described first metal gate 112 and the second metal gate 122, the resistance between described first metal gate 112 and the second metal gate 122 is caused to increase, even be electrically isolated from each other, cause the degradation of formed CMOS tube.
The present inventor after further research, after formation first grid structure and second grid structure, second dielectric layer is formed in described first grid structure and second grid body structure surface, there is in described second dielectric layer the contact through hole exposing part first grid structure and part second grid body structure surface, and form conductive plunger in described contact through hole; Produce electric isolution between described first metal gate and the second metal gate after, described conductive plunger can make to be electrically connected between described first metal gate and the second metal gate, makes the performance improvement of formed common grid CMOS tube.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
First embodiment
Fig. 6 to Figure 11 is the cross-sectional view of the forming process of semiconductor device described in first embodiment of the invention.
Please refer to Fig. 6, provide Semiconductor substrate 300, described Semiconductor substrate 300 comprises adjacent first area I and second area II; Form dummy gate layer 301 on described Semiconductor substrate 300 surface and cover the first medium layer 302 of described dummy gate layer 301 sidewall, described dummy gate layer 301 is positioned at Semiconductor substrate 300 surface of described first area I and second area II, and the surface of described first medium layer 302 flushes with the surface of described dummy gate layer 301.
Described Semiconductor substrate 300 is for providing workbench for subsequent technique; Described Semiconductor substrate 300 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate, glass substrate or III-V substrate (such as silicon nitride or GaAs etc.).
Described first area I and second area II is respectively used to form the contrary transistor of conduction type at subsequent technique.In the present embodiment, Semiconductor substrate 300 surface of described first area I in subsequent technique for the formation of PMOS, Semiconductor substrate 200 surface of described second area II in subsequent technique for the formation of NMOS tube.Because the present embodiment is for the formation of having high-K gate dielectric layer and metal gate electrode, and common gate electrode PMOS and NMOS tube, after the semiconductor device therefore described in the present embodiment adopts, grid (GateLast) technique is formed.
The material of described dummy gate layer 301 is polysilicon; The material of described first medium layer 302 is one or both combinations in silica and silicon nitride; Described dummy gate layer 301 is for defining position and the size of follow-up formed first grid structure and second grid structure, described first medium layer 302, for after the described dummy gate layer 301 of follow-up removal, retains position and size that described dummy gate layer defines.
The formation process of described dummy gate layer 301 and first medium layer 302 is: form dummy grid film on Semiconductor substrate 300 surface; Form photoresist layer at described dummy grid film surface, described photoresist layer covers the correspondence position of described first area I and second area II; With described photoresist layer for mask, adopt anisotropic dry etch process to etch described dummy grid film, form dummy gate layer 301; After formation dummy gate layer 301, form first medium film in described Semiconductor substrate 300 and dummy gate layer 301 surface, in the present embodiment, the material of described first medium film is silica; Adopt first medium film described in CMP (Chemical Mechanical Polishing) process planarization till exposing described dummy gate layer 301, form first medium layer 302.
It should be noted that, in order to make described CMP (Chemical Mechanical Polishing) process more controlled, in other embodiments, before the described first medium film of formation, forming barrier layer in described Semiconductor substrate 300 and dummy gate layer 301 surface; The material on described barrier layer is different from the material of described first medium film, and such as, when the material of described first medium film is silica, the material on described barrier layer is silicon nitride; When carrying out described CMP (Chemical Mechanical Polishing) process, being first polished to and exposing described barrier layer, then carry out certain polishing excessively to expose dummy gate layer 301; Thus avoid the height that described CMP (Chemical Mechanical Polishing) process reduces described dummy gate layer 301, make the size of described dummy gate layer 301 more accurate.
Please refer to Fig. 7, the dummy gate layer 301 removing second area II, till exposing Semiconductor substrate 300, forms the second opening 303.
The technique of the dummy gate layer 301 of described removal second area II is: form at described first medium layer 302 and dummy gate layer 301 surface the photoresist layer exposing second area II relevant position; With described photoresist layer for mask, anisotropic dry etch process is adopted to etch described dummy gate layer 301 till exposing Semiconductor substrate 300, form the second opening 303, the gas of described dry etching comprise in chlorine and hydrogen bromide one or both; Adopt anisotropic dry etch process that the sidewall of described second opening 303 can be made vertical with Semiconductor substrate 300 surface.Described photoresist layer can be removed after described anisotropic dry etch process, also can remove after follow-up formation second gate electrode layer.
Material due to described dummy gate layer 301 is polysilicon, therefore, etching removes the technique of the dummy gate layer 301 of second area II, first work-function layer 111 of NMOS area II and the first metal gate 112(is removed as shown in Figure 4 compared with prior art) more simple, be easy to operation, and can not produce residual and pollute the device formed.
Described second opening 303 for forming second grid structure in subsequent technique; In the present embodiment, described second grid structure is for the formation of NMOS tube, and the material of the second work-function layer in the second grid structure formed can be different from the material of the first work-function layer of follow-up formation, to meet the demand of dissimilar transistor.
Please refer to Fig. 8, second grid structure is formed at described second opening 303(as shown in Figure 7), comprise: cover the sidewall of described second opening 303 and the second high-K gate dielectric layer 304 of lower surface, be positioned at second work-function layer 305 on described second high-K gate dielectric layer 304 surface, and be positioned at the second gate electrode layer 306 of described second work-function layer 305 surface and full described second opening 303 of filling.
The formation process of described second high-K gate dielectric layer 304, second work-function layer 305 and second gate electrode layer 306 is: deposit the second high-K gate dielectric film, the second work function film and second gate electrode film successively at the sidewall of described first medium layer 302 surface, the second opening 303 and lower surface, until fill full described second opening 303, described depositing operation preferably chemical vapor deposition method; Adopt CMP (Chemical Mechanical Polishing) process to remove higher than the second high-K gate dielectric film on described first medium layer 302 surface, the second work function film and second gate electrode film, the second formed high-K gate dielectric layer 304, second work-function layer 305 and second gate electrode layer 306 surface are flushed with described first medium layer 302.
The material of described second gate electrode layer 306 is metal, comprising: copper, tungsten or aluminium; The material of described second high-K gate dielectric layer 304 is for comprising hafnium oxide, zirconia, hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide; Described second high-K gate dielectric layer 304 can improve isolation effect, reduces leakage current, improves device performance.
The material of described second work-function layer 305 comprises one or more combinations in Ti, TiN, Co, TiAl, AlCo, TiAlN, Ta and TaN; And in the present embodiment, described second area II surface is for the formation of NMOS tube, therefore described second work-function layer 305 needs to have lower work function.
But because first area I and second area II is respectively used to form the contrary transistor of conduction type at subsequent technique, the first work-function layer therefore in the follow-up first grid structure being formed at I surface, first area is different from described second work-function layer 305; In the present embodiment, when second area II is for the formation of NMOS tube, described first area I is for the formation of PMOS, then the first work-function layer of follow-up formation needs to have higher work function.
Therefore, in order to the demand of the dissimilar transistor of satisfied formation, need to remove the dummy gate layer 301 on second area II surface in subsequent technique, and first grid electrode layer needed for being formed and the first work-function layer.
It should be noted that, due between the second high-K gate dielectric layer 304 and Semiconductor substrate 300 in conjunction with bad, easy generation leakage current, therefore in embodiments of the invention, also comprise: between described second high-K gate dielectric layer 304 and Semiconductor substrate 300, form the second insulating barrier (not shown), with the second high-K gate dielectric layer 304 and Semiconductor substrate 300 described in bonding, improve the performance of device; The material of described second insulating barrier is silica.
In addition, second gate electrode layer 306 is diffused into from the second high-K gate dielectric layer 304 in order to prevent the impurity produced in technical process, and when preventing formed semiconductor device work, carrier diffusion enters in described second gate electrode layer 306, between described second high-K gate dielectric layer 304 and the second work-function layer 305, form the second protective layer, described second high-K gate dielectric layer 304 and the second work-function layer 305 are isolated; The material of described second protective layer is one or both combinations in titanium nitride and tantalum nitride.
Please refer to Fig. 9, after the described second grid structure of formation, remove the dummy gate layer 301 of first area I till exposing Semiconductor substrate 300, form the 3rd opening 307.
The technique of the 3rd opening 307 of described formation with form the second opening 303(as shown in Figure 7) technique identical, do not repeat them here.
Please refer to Figure 10, first grid structure is formed in described 3rd opening 307, comprise: cover the sidewall of described 3rd opening and the first high-K gate dielectric layer 308 of lower surface, be positioned at first work-function layer 309 on described first high-K gate dielectric layer 308 surface, and be positioned at the first grid electrode layer 310 of described first work-function layer 309 surface and full described 3rd opening 307 of filling.
The technique of the first grid structure of described formation is identical with the technique forming second grid structure, does not repeat them here.
It should be noted that, also comprise in described first grid structure: be formed at the 3rd insulating barrier between the first high-K gate dielectric layer 308 and Semiconductor substrate, and be formed at the first protective layer between the first high-K gate dielectric layer 308 and the first work-function layer 309.
Please refer to Figure 11, after formation first grid structure and second grid structure, second dielectric layer 311 is formed in described first grid structure and second grid body structure surface, have contact through hole (not shown) in described second dielectric layer 311, described contact through hole exposes part first grid structure and part second grid body structure surface; The first conductive plunger 312 is formed in described contact through hole.
Described second dielectric layer 311 also covers described first medium layer 302 surface; The material of described second dielectric layer 311 is one or both combinations in silicon nitride and silica; Described contact through hole is used at follow-up formation first conductive plunger; The formation process of described second dielectric layer 311 and contact through hole is: at described first medium layer 302, first grid structure and second grid body structure surface deposition second medium film; Etching removes the described second medium film of part, and exposes first grid electrode layer 306 and second gate electrode layer 310 surface, forms contact through hole.
The material of described first conductive plunger 312 comprises: copper, tungsten or aluminium; The formation process of described first conductive plunger 312 is: in described second dielectric layer 311 and contact through hole, adopt depositing operation or electroplating technology filled conductive material; Adopt CMP (Chemical Mechanical Polishing) process removal higher than the electric conducting material on described second dielectric layer 311 surface; Described first conductive plunger 312 for being electrically connected first grid electrode layer 306 and second gate electrode layer 310, thus avoiding owing to being formed with oxide layer between described first grid electrode layer 306 and second gate electrode layer 310 and device performance is deteriorated.
It should be noted that, the sidewall of described contact through hole and lower surface are also formed with barrier layer 313, and described first conductive plunger 312 is formed at surface, described barrier layer 313, and fill full described contact through hole; Described barrier layer 313 defines the stop position of described chemico-mechanical polishing; After being polished to described barrier layer 313, carried out polishing, to expose second dielectric layer 311 surface; The material on described barrier layer 313 is titanium nitride or tantalum nitride.
In the present embodiment, before formation first medium layer 302, in the Semiconductor substrate 300 of dummy gate layer 301 both sides of first area I, form the first source region (not shown) and the first drain region (not shown), in the Semiconductor substrate 300 of dummy gate layer 301 both sides of second area II, form the second source region (not shown) and the second drain region (not shown); And described first source region, the first drain region, the second source region and the second surface, drain region need to form conductive plunger, for applying operating voltage to formed semiconductor device; Therefore, while described first conductive plunger 312 of formation, form the second conductive plunger being positioned at described first source region, the first drain region, the second source region and the second surface, drain region, thus technique and time can be saved.
In other embodiments, described first source region, the first drain region, the second source region and the second drain region are in formation first grid structure and second grid structure and formation after removing first medium layer 302, then described second dielectric layer 311 is formed at Semiconductor substrate 300, first grid structure and second grid body structure surface, and forms the first conductive plunger 312 and the second conductive plunger in described second dielectric layer 311.
There is between the first grid electrode layer that the present embodiment is formed and second gate electrode layer the first high-K gate dielectric layer and the second high-K gate dielectric layer, described first high-K gate dielectric layer and the second high-K gate dielectric layer can make electric isolution between described first grid electrode layer and second gate electrode layer, cause the inefficacy of formed semiconductor device; And described first conductive plunger can make described first grid electrode layer and the electrical connection of second gate electrode layer, thus make the stable working state of described semiconductor device, functional; In addition, after the present embodiment removes the dummy gate layer of second area, second grid structure is formed, after removing the dummy gate layer of first area, form first grid structure, avoid the processing step of the metal gate layers of extra etching first area or second area, make technique simple; And the technique removing dummy gate layer is easier to operation, and remove thoroughly, not easily produce residual and pollute device; Again, described first conductive plunger and described second conductive plunger are formed simultaneously, simplify processing step, save the process time.
Accordingly, the present embodiment also provides a kind of semiconductor device, please continue to refer to Figure 11, comprising: Semiconductor substrate 300, and described Semiconductor substrate 300 comprises adjacent first area I and second area II; Be positioned at the first grid structure on Semiconductor substrate 300 surface of described first area I, described first grid structure comprises: the first high-K gate dielectric layer 308, be positioned at first work-function layer 309 on described first high-K gate dielectric layer 308 surface and be positioned at the first grid electrode layer 310 on described first work-function layer 309 surface; Be positioned at the second grid structure on described second area II Semiconductor substrate 300 surface, described second grid structure comprises: the second high-K gate dielectric layer 304, be positioned at second work-function layer 305 on described second high-K gate dielectric layer 304 surface and be positioned at the second gate electrode layer 306 on described second work-function layer 305 surface; Be positioned at the second dielectric layer 311 of described first grid structure and second grid body structure surface, have contact through hole (not shown) in described second dielectric layer 311, described contact through hole exposes part first grid structure and part second grid body structure surface; Be positioned at described contact through hole and form the first conductive plunger 312.
Described Semiconductor substrate 300 surface has the first medium layer 302 covering described first grid structure and second grid structure side wall, the surface of described first medium layer 302 flushes with the surface of described first grid structure and second grid structure, and the material of described first medium layer 202 is silicon nitride or silica.
In the present embodiment, there is between described first grid electrode layer 310 and second gate electrode layer 306 first high-K gate dielectric layer 308 and the second high-K gate dielectric layer 304, the resistance between described first grid electrode layer 310 and second gate electrode layer 306 can be caused to increase, even electric isolution.
The material of described first conductive plunger 312 is copper, tungsten or aluminium, so the electrical connection between described first grid electrode layer 310 and second gate electrode layer 306 of described first conductive plunger 312, avoid the problem that the first high-K gate dielectric layer 308 and the second high-K gate dielectric layer 304 produce electric isolution.
It should be noted that, the sidewall of described contact through hole and lower surface have barrier layer 313, and described first conductive plunger 312 is positioned at surface, described barrier layer 313; The material on described barrier layer 313 is titanium nitride or tantalum nitride.
In the Semiconductor substrate 300 of described first grid structure both sides, there is the first source region (not shown) and the first drain region; There is in the Semiconductor substrate 300 of described second grid structure both sides the second source region (not shown) and the second drain region (not shown); The second conductive plunger (not shown) on described first source region, the first drain region, the second source region and the second surface, drain region.
Described first grid structure also comprises: the first insulating barrier (not shown) between described Semiconductor substrate 300 and the first high-K gate dielectric layer 308, and the material of described first insulating barrier is silica; And the first protective layer between described first high-K gate dielectric layer 308 and the first work-function layer 309, the material of described first protective layer is one or both combinations in titanium nitride and tantalum nitride.
Described second grid structure also comprises: the second insulating barrier between described Semiconductor substrate 300 and the second high-K gate dielectric layer 304, and the material of described second insulating barrier is silica; And the second protective layer between described second high-K gate dielectric layer 304 and the second work-function layer 305, the material of described second protective layer is one or both combinations in titanium nitride and tantalum nitride.
Described in the present embodiment, there is between first grid electrode layer and second gate electrode layer the first high-K gate dielectric layer and the second high-K gate dielectric layer, the resistance between described first grid electrode layer and second gate electrode layer can be caused to increase, even electric isolution; And form the first conductive plunger at described first grid electrode layer and second gate electrode layer surface and can reduce resistance between described first grid electrode layer and second gate electrode layer, make to be electrically connected between described first grid electrode layer and second gate electrode layer, described semiconductor device functional.
Second embodiment
Figure 12 to Figure 14 is the cross-sectional view of the forming process of semiconductor device described in second embodiment of the invention.
Please refer to Figure 12, provide Semiconductor substrate 200, described Semiconductor substrate 200 comprises adjacent first area I and second area II; Form dummy gate layer (not shown) on described Semiconductor substrate 200 surface and cover the first medium layer 202 of described dummy gate layer sidewall, described dummy gate layer is positioned at Semiconductor substrate 200 surface of described first area I and second area II, and the surface of described first medium layer 202 flushes with the surface of described dummy gate layer; Remove described dummy gate layer till exposing Semiconductor substrate 200, form the first opening; Formed in described first opening: cover the high-K dielectric layer 204 of the sidewall of described first opening and lower surface, be positioned at first work-function layer 205 on described high-K dielectric layer 204 surface and be positioned at the first grid electrode layer 206 on described first work-function layer 205 surface, the high-K dielectric layer 204 of described first area I forms the first high-K gate dielectric layer 204a, and the high-K dielectric layer 204 of described second area II forms the second high-K gate dielectric layer 204b; First work-function layer 205 of removal second area II and first grid electrode layer 206, till exposing high-K dielectric layer 204, form the second opening; Formed in described second opening: cover the sidewall of described second opening and the second work-function layer 208 of lower surface, and be positioned at the second gate electrode layer 209 of described second work-function layer 208 surface and full described second opening 207 of filling.
The material of described Semiconductor substrate 200, and the material of described dummy gate layer and first medium layer 202 and formation process identical with described in the first embodiment, do not repeat at this.
In the present embodiment, the technique removing dummy gate layer is etching technics, preferably wet-etching technology, and the wet-etching technology of described removal dummy gate layer is well known to those skilled in the art, and therefore not to repeat here; The first opening formed for forming first grid structure and second grid structure in subsequent technique.
Formation process and the material of described high-K dielectric layer 204, first work-function layer 205, first grid electrode layer 206, second work-function layer 208 and second gate electrode layer 209 are identical with the Design and material that the first embodiment forms first grid structure or second grid structure, and therefore not to repeat here; In the present embodiment, because first area I is for the formation of PMOS, therefore described first work-function layer 205 needs to have higher work function, and second area II is for the formation of NMOS tube, and therefore described second work-function layer 208 needs to have lower work function; Therefore, in order to the demand of the dissimilar transistor of satisfied formation, need to adopt anisotropic dry etch process to remove first grid electrode layer 205 and first work-function layer 204 on second area II surface, and second gate electrode layer needed for being formed and the second work-function layer.
But the material due to described first grid electrode layer 206 is metal, the material of described first work-function layer 204 is metal or metallic compound, and described metal or metallic compound are very easily oxidized; In the dry etch process process of described anisotropic, or in the cleaning process after described dry etch process, very easily in described second opening (in figure nothing), the sidewall surfaces be made up of first grid electrode layer 206 and the first work-function layer 205 forms oxide layer; After follow-up formation second gate electrode layer and the second work-function layer, described oxide layer can cause the resistance between described first grid electrode layer 206 and second gate electrode layer to increase, and even causes electric isolution, makes the degradation of formed semiconductor device; Therefore, this enforcement is after formation second grid structure, form the conductive plunger contacted with second gate electrode layer 209 with first grid electrode layer 206, thus make between described first grid electrode layer 206 and second gate electrode layer 209 can conducting, make formed device performance improvement.
It should be noted that, form insulating barrier between described high-K dielectric layer 204 and Semiconductor substrate 200, the material of described insulating barrier is silica; Between described high-K dielectric layer 204 and the first work-function layer 205, form the first protective layer, the material of described first protective layer is one or both combinations in titanium nitride and tantalum nitride.
The first grid structure that the present embodiment is formed comprises: be positioned at the first high-K gate dielectric layer 204a on I Semiconductor substrate 200 surface, first area, first work-function layer 205 on described first high-K gate dielectric layer 204a surface and the first grid electrode layer 206 on the first work-function layer 205 surface; Described second grid structure comprises: be positioned at the second high-K gate dielectric layer 204b on second area II Semiconductor substrate 200 surface, second work-function layer 208 on described second high-K gate dielectric layer 204b surface and the second gate electrode layer 209 on the second work-function layer 208 surface; Wherein, described first high-K gate dielectric layer 204a is made up of the high-K dielectric layer 204 being positioned at I surface, first area, and described second high-K gate dielectric layer 204b is made up of the high-K dielectric layer 204 being positioned at second area II surface.
Please refer to Figure 13, after formation first grid structure and second grid structure, second dielectric layer 210 is formed in described first grid structure and second grid body structure surface, have contact through hole 211 in described second dielectric layer 210, described contact through hole 211 exposes part first grid structure and part second grid body structure surface.
Described second dielectric layer 210 also covers described first medium layer 202 surface; The material of described second dielectric layer 210 is one or both combinations in silicon nitride and silica; Described contact through hole 211 is at follow-up formation first conductive plunger; The formation process of described second dielectric layer 210 and contact through hole 211 is: at above-mentioned first medium layer 202, first grid structure and second grid body structure surface deposition second medium film; Etching removes the described second medium film of part, and exposes first grid electrode layer 206 and second gate electrode layer 209 surface, forms contact through hole 211.
Please refer to Figure 14, in described contact through hole 211, form the first conductive plunger 212.
The material of described first conductive plunger 212 comprises: copper, tungsten or aluminium; The formation process of described first conductive plunger 212 is: in described second dielectric layer 210 and contact through hole, adopt depositing operation or electroplating technology filled conductive material; Adopt CMP (Chemical Mechanical Polishing) process removal higher than the electric conducting material on described second dielectric layer 210 surface; Described first conductive plunger 212 for being electrically connected first grid electrode layer 206 and second gate electrode layer 209, thus avoiding owing to being formed with oxide layer between described first grid electrode layer 206 and second gate electrode layer 209 and device performance is deteriorated.
Before the described electric conducting material of filling, form barrier layer 213 at the sidewall of described second dielectric layer 210 surface and described contact through hole 211 and lower surface, described barrier layer 213 defines the stop position of described chemico-mechanical polishing; After being polished to described barrier layer 213, carried out polishing, to expose second dielectric layer 210 surface; The material on described barrier layer 213 is titanium nitride or tantalum nitride.
In the present embodiment, before formation first medium layer 202, in the Semiconductor substrate 200 of dummy gate layer 201 both sides of first area I, form the first source region (not shown) and the first drain region (not shown), in the Semiconductor substrate 200 of dummy gate layer 201 both sides of second area II, form the second source region (not shown) and the second drain region (not shown); And described first source region, the first drain region, the second source region and the second surface, drain region need to form conductive plunger, for applying operating voltage to formed semiconductor device; Therefore, while described first conductive plunger 212 of formation, form the second conductive plunger being positioned at described first source region, the first drain region, the second source region and the second surface, drain region, thus technique and time can be saved.
In other embodiments, described first source region, the first drain region, the second source region and the second drain region are in formation first grid structure and second grid structure and formation after removing first medium layer 202, then described second dielectric layer 210 is formed at Semiconductor substrate 200, first grid structure and second grid body structure surface, and forms the first conductive plunger 212 and the second conductive plunger in described second dielectric layer 210.
In the semiconductor device that the present embodiment is formed, between first grid electrode layer and second gate electrode layer, there is oxide layer, described oxide layer can cause the resistance between described first grid electrode layer and second gate electrode layer to increase, and even electric isolution, causes formed performance of semiconductor device bad; And in the present embodiment, the first conductive plunger is formed at described first grid electrode layer and second gate electrode layer surface, thus the resistance reduced between described first grid electrode layer and second gate electrode layer, make to be electrically connected between described first grid electrode layer and second gate electrode layer, solve resistance that described oxide layer causes and increase or the problem of electric isolution; In addition, because the first source region, the first drain region, the second source region and the second surface, drain region need formation second conductive plunger, and described first conductive plunger and described second conductive plunger are formed simultaneously, simplify processing step, save the process time.
Accordingly, the present embodiment also provides a kind of semiconductor device, please continue to refer to Figure 14, comprising: Semiconductor substrate 200, and described Semiconductor substrate 200 comprises adjacent first area I and second area II; Be positioned at the first grid structure on Semiconductor substrate 200 surface of described first area I, described first grid structure comprises: the first high-K gate dielectric layer 204a, be positioned at first work-function layer 205 on described first high-K gate dielectric layer 204a surface and be positioned at the first grid electrode layer 206 on described first work-function layer 205 surface; Be positioned at the second grid structure on described second area II Semiconductor substrate 200 surface, described second grid structure comprises: the second high-K gate dielectric layer 204b, be positioned at second work-function layer 208 on described second high-K gate dielectric layer 204b surface and be positioned at the second gate electrode layer 209 on described second work-function layer 208 surface; Be positioned at the second dielectric layer 210 of described first grid structure and second grid body structure surface, have contact through hole (not shown) in described second dielectric layer 210, described contact through hole 211(is as shown in figure 11) expose part first grid structure and part second grid body structure surface; Be positioned at described contact through hole 211 and form the first conductive plunger 212.
Described semiconductor device is similar to semiconductor device described in the first embodiment, and therefore not to repeat here.
In the present embodiment, between described first grid electrode layer 206 and second gate electrode layer 209, there is the second work-function layer 208; And also there is between described second work-function layer 208 and first grid electrode layer 206 oxide layer, described oxide layer can cause the resistance between described first grid electrode layer 206 and second gate electrode layer 209 to increase, even electric isolution, and described first conductive plunger 212 is electrically connected between described first grid electrode layer 206 and second gate electrode layer 209 for making, solve the problem of electric isolution.
In sum, after semiconductor substrate surface forms the first adjacent insulating barrier structure and second grid structure, second dielectric layer is formed in described first grid structure and second grid body structure surface, there is in described second dielectric layer the contact through hole exposing part first grid structure and part second grid body structure surface, and the first conductive plunger is formed in described contact through hole, described first conductive plunger can make first grid electrode layer and the electrical connection of second gate electrode layer; Thus resistance between first grid electrode layer and second gate electrode layer can be reduced, avoid in the forming process of described semiconductor device, between described first grid electrode layer and second gate electrode layer, form oxide layer, and cause the problem of resistance increase or electric isolution; The performance of the semiconductor device formed improves.
Described semiconductor structure comprises: be positioned at semiconductor substrate surface and adjacent first grid structure and second grid structure; Described first grid structure and second grid body structure surface have the first conductive plunger, and described first conductive plunger simultaneously with first grid structure and second grid form touch; Therefore, described first conductive plunger can make first grid electrode layer and the electrical connection of second gate electrode layer, thus reduces the resistance between described first grid electrode layer and second gate electrode layer, makes the functional of described semiconductor device.
Though the embodiment of the present invention is described above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (16)

1. a formation method for semiconductor device, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises adjacent first area and second area;
Semiconductor substrate surface in described first area forms first grid structure, and described first grid structure comprises: the first high-K gate dielectric layer, be positioned at first work-function layer on described first high-K gate dielectric layer surface and be positioned at the first grid electrode layer on described first work-function layer surface;
Form second grid structure at described second area semiconductor substrate surface, described second grid structure comprises: the second high-K gate dielectric layer, be positioned at second work-function layer on described second high-K gate dielectric layer surface and be positioned at the second gate electrode layer on described second work-function layer surface;
After formation first grid structure and second grid structure, second dielectric layer is formed in described first grid structure and second grid body structure surface, have contact through hole in described second dielectric layer, same described contact through hole exposes part first grid structure and part second grid body structure surface;
The first conductive plunger is formed, for making described first grid electrode layer and the electrical connection of second gate electrode layer in described contact through hole.
2. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the formation method of described first grid structure and second grid structure is:
Form dummy gate layer at described semiconductor substrate surface and cover the first medium layer of described dummy gate layer sidewall, described dummy gate layer is positioned at the semiconductor substrate surface of described first area and second area, and the surface of described first medium layer flushes with the surface of described dummy gate layer;
Remove described dummy gate layer till exposing Semiconductor substrate, form the first opening;
Formed in described first opening: cover the high-K dielectric layer of the sidewall of described first opening and lower surface, be positioned at first work-function layer on described high-K dielectric layer surface and be positioned at the first grid electrode layer on described first work-function layer surface;
First work-function layer of removal second area and first grid electrode layer, till exposing high-K dielectric layer, form the second opening;
Formed in described second opening: cover the sidewall of described second opening and the second work-function layer of lower surface, and be positioned at the second gate electrode layer of described second work-function layer surface and full described second opening of filling, the high-K dielectric layer of described first area forms the first high-K gate dielectric layer, and the high-K dielectric layer of described second area forms the second high-K gate dielectric layer.
3. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the formation method of described first grid structure and second grid structure is:
Form dummy gate layer at described semiconductor substrate surface and cover the first medium layer of described dummy gate layer sidewall, described dummy gate layer is positioned at the semiconductor substrate surface of described first area and second area, and the surface of described first medium layer flushes with the surface of described dummy gate layer;
The dummy gate layer removing second area, till exposing Semiconductor substrate, forms the second opening;
Second grid structure is formed in described second opening, comprise: cover the sidewall of described second opening and the second high-K gate dielectric layer of lower surface, be positioned at second work-function layer on described second high-K gate dielectric layer surface, and be positioned at the second gate electrode layer of described second work-function layer surface and full described second opening of filling;
After the described second grid structure of formation, remove the dummy gate layer of first area till exposing Semiconductor substrate, form the 3rd opening;
First grid structure is formed in described 3rd opening, comprise: cover the described sidewall of the 3rd opening and the first high-K gate dielectric layer of lower surface, be positioned at first work-function layer on described first high-K gate dielectric layer surface, and be positioned at the first grid electrode layer of described first work-function layer surface and full described 3rd opening of filling.
4. the formation method of semiconductor device as described in Claims 2 or 3, it is characterized in that, the material of described dummy gate layer is polysilicon, and the material of described first medium layer is one or both combinations in silica and silicon nitride.
5. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, the material of described first conductive plunger is copper, tungsten or aluminium.
6. the formation method of semiconductor device as claimed in claim 1, is characterized in that, also comprise: before described first conductive plunger of formation, and form barrier layer at the sidewall of described contact through hole and lower surface, the material on described barrier layer is titanium nitride or tantalum nitride.
7. the formation method of semiconductor device as claimed in claim 1, is characterized in that, also comprise: in the Semiconductor substrate of first grid structure both sides, form the first source region and the first drain region; The second source region and the second drain region is formed in the Semiconductor substrate of second grid structure both sides.
8. the formation method of semiconductor device as claimed in claim 7, it is characterized in that, also comprise: in described first source region, the first drain region, the second source region and the second drain region surface formed the second conductive plunger, described second conductive plunger and described first conductive plunger are formed simultaneously.
9. the formation method of semiconductor device as claimed in claim 1, is characterized in that, the material of described first work-function layer or the second work-function layer is one or more combinations in Ti, TiN, Co, TiAl, AlCo, TiAlN, Ta and TaN.
10. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, described first work-function layer is different with the material of the second work-function layer.
The formation method of 11. semiconductor device as claimed in claim 1, it is characterized in that, described first grid structure also comprises: the first insulating barrier between described Semiconductor substrate and the first high-K gate dielectric layer, and the material of described first insulating barrier is silica.
The formation method of 12. semiconductor device as claimed in claim 1; it is characterized in that; described first grid structure also comprises: the first protective layer between described first high-K gate dielectric layer and the first work-function layer, and the material of described first protective layer is one or both combinations in titanium nitride and tantalum nitride.
The formation method of 13. semiconductor device as claimed in claim 1, it is characterized in that, described second grid structure also comprises: the second insulating barrier between described Semiconductor substrate and the second high-K gate dielectric layer, and the material of described second insulating barrier is silica.
The formation method of 14. semiconductor device as claimed in claim 1; it is characterized in that; described second grid structure also comprises: the second protective layer between described second high-K gate dielectric layer and the second work-function layer, and the material of described second protective layer is one or both combinations in titanium nitride and tantalum nitride.
The formation method of 15. semiconductor device as claimed in claim 1, it is characterized in that, the material of described first grid electrode layer and second gate electrode layer is metal, comprising: copper, tungsten or aluminium.
The formation method of 16. 1 kinds of semiconductor device any one of claim 1 to 15 the semiconductor device that formed, it is characterized in that, comprising:
Semiconductor substrate, described Semiconductor substrate comprises adjacent first area and second area;
Be positioned at the first grid structure of the semiconductor substrate surface of described first area, described first grid structure comprises: the first high-K gate dielectric layer, be positioned at first work-function layer on described first high-K gate dielectric layer surface and be positioned at the first grid electrode layer on described first work-function layer surface;
Be positioned at the second grid structure of described second area semiconductor substrate surface, described second grid structure comprises: the second high-K gate dielectric layer, be positioned at second work-function layer on described second high-K gate dielectric layer surface and be positioned at the second gate electrode layer on described second work-function layer surface;
Be positioned at the second dielectric layer of described first grid structure and second grid body structure surface, have contact through hole in described second dielectric layer, same described contact through hole exposes part first grid structure and part second grid body structure surface;
Be positioned at described contact through hole and form the first conductive plunger, for making described first grid electrode layer and the electrical connection of second gate electrode layer.
CN201210406263.3A 2012-10-22 2012-10-22 Semiconductor device and forming method thereof Active CN103779198B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201210406263.3A CN103779198B (en) 2012-10-22 2012-10-22 Semiconductor device and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201210406263.3A CN103779198B (en) 2012-10-22 2012-10-22 Semiconductor device and forming method thereof

Publications (2)

Publication Number Publication Date
CN103779198A CN103779198A (en) 2014-05-07
CN103779198B true CN103779198B (en) 2016-04-20

Family

ID=50571324

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210406263.3A Active CN103779198B (en) 2012-10-22 2012-10-22 Semiconductor device and forming method thereof

Country Status (1)

Country Link
CN (1) CN103779198B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110875184B (en) * 2018-08-29 2023-08-18 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method of forming the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097382A (en) * 2009-12-15 2011-06-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
CN102487048A (en) * 2010-12-03 2012-06-06 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7696036B2 (en) * 2007-06-14 2010-04-13 International Business Machines Corporation CMOS transistors with differential oxygen content high-k dielectrics

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102097382A (en) * 2009-12-15 2011-06-15 中芯国际集成电路制造(上海)有限公司 Method for manufacturing semiconductor device
CN102487048A (en) * 2010-12-03 2012-06-06 中芯国际集成电路制造(上海)有限公司 Method for forming semiconductor device

Also Published As

Publication number Publication date
CN103779198A (en) 2014-05-07

Similar Documents

Publication Publication Date Title
CN107170825B (en) Semiconductor device, fin field effect transistor device and forming method thereof
CN105720058B (en) The boundary scheme of embedded polycrystalline Si ON CMOS or NVM for HKMG CMOS technology
TWI548096B (en) Methods of forming contact structures on finfet semiconductor devices and the resulting devices
CN111653483B (en) Semiconductor device and method for manufacturing the same
CN103915384B (en) Semiconductor structure and forming method thereof
CN103794505B (en) The formation method of transistor
CN104701150A (en) Transistor forming method
CN107403721B (en) Method for manufacturing power metal oxide semiconductor field effect transistor
CN103165429A (en) Formation method of metal gates
CN105513965A (en) Transistor forming method
CN104752215A (en) Transistor forming method
CN111200019B (en) Semiconductor structure and forming method thereof
CN111200017B (en) Semiconductor structure and forming method thereof
CN103779198B (en) Semiconductor device and forming method thereof
KR102611247B1 (en) Semiconducting metal oxide transistors having a patterned gate and methods for forming the same
US11456304B2 (en) Semiconductor structure and forming method thereof
CN111863723B (en) Semiconductor structure and forming method thereof
CN115997275A (en) Semiconductor structure and forming method thereof
CN105336594A (en) Forming method of semiconductor structure
CN103456692A (en) Method for forming complementary metal-oxide-semiconductor tube
CN113097137B (en) Semiconductor structure and forming method thereof
CN103021947A (en) Manufacture method for semiconductor device
CN115714127A (en) Semiconductor structure and forming method thereof
CN114188412A (en) Semiconductor structure and forming method thereof
CN115621249A (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant