JP2002093745A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent detrimental effect on the characteristics of a semiconductor device by preventing contamination and film wear of an insulation film, in formation of a contact between a first conductive film of the lower layer and a second conductive film of the upper layer, which are set apart from each other by an insulation film. SOLUTION: After a resist mask 7 having a hole part 128 in an upper part of a projection part 23 of an island-like Si thin film layer 33 which turns into a source/drain and a channel region, is formed on a polycrystalline Si film 6, implantation of Si ions 10 is carried out and the bonding of atoms of an SiON film constituting a gate insulation film 5 is weakeded. The resist mask 7 is removed, heat treatment is carried out for 3 hours at 1,100 deg.C, for example, in hydrogen atmosphere and a part of the gate insulating film 5 in a part where the bonding of element is weak through ion implantation is reduced. Thereby, an SiON film in a part which is subjected to ion implantation turns into an Si layer containing a very small amount of N, and the projection part 23 of the island-like Si thin-film layer 33 and the polycrystalline Si film 6 for a gate electrode are connected electrically.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for connecting conductor layers to each other without forming a hole by etching in a minute area, or an arbitrary contact portion after forming a contact plug. And a method for manufacturing an element having an arbitrary additional resistance.

[0002]

2. Description of the Related Art Conventionally, as a method for connecting two conductive layers, an insulating film formed on a first conductive layer is provided with an opening by a photomask method and etching, and then a second conductive layer is formed. There has been a method of forming a conductor layer. In recent years, SOI (S
For SOI MOS transistors formed on a silicon on insulator (Silicon On Insulator) substrate, there has been proposed a structure in which a gate and a body of a transistor are connected in order to prevent a body floating effect which is a problem peculiar to SOI MOS transistors (see: May, 1999). Proceedings of the 33rd Ultra Clean Technology Symposium p134). As a method of connecting the gate and the body of the transistor, first, a method of providing a contact hole in each and connecting them with a metal wiring layer can be considered. However, the wiring layer occupies a large area and the wiring layout is free. There is a problem in high integration because the degree is limited. Second, there is a method in which an opening is provided directly in the gate insulating film by a photomask and etching immediately after the formation of the gate insulating film, and then a gate electrode is formed and the gate and the body are connected. Here, the latter method will be described below with reference to the drawings.

FIGS. 24 to 26 show an n-channel SOIM.
FIG. 24 is a process diagram showing a method for manufacturing a conventional semiconductor device in which a gate and a body of a transistor are connected in an OS transistor, and FIG. 24 [A], [B], FIG.
[B], and in each of FIGS. 26A and 26B,
(A) is a plan view, and (b) is a cross-sectional view taken along a dashed-dotted line X shown in (a).

FIG. 24A shows an initial state of an SOI substrate, wherein 1 is a base Si substrate, 2 is a base insulating film, and 3 is an S
i thin film layer. First, as shown in FIG. 24B, the Si thin film layer 3 is separated by a photomask method and a dry etching method, and an island-like Si thin film layer 33 having the protruding portion 23 is formed.
4 B (boron) ions for controlling the threshold voltage are implanted.

Next, as shown in FIG. 25A, after the gate insulating film 5 is formed, at least the island-shaped S
A resist mask 107 having an opening 108 is formed on the protrusion 23 of the i thin film layer 33.

Next, as shown in FIG. 25B, the gate insulating film 5 in the opening 108 is removed by a dry etching method (removed part 118), and then the resist mask 107 is removed.

Next, as shown in FIG. 26A, a polycrystalline Si film 6 for a gate electrode is deposited by a CVD method. At this time, the island-shaped Si thin film layer 33, that is, the transistor body and the polycrystalline Si film 6 for the gate electrode are brought into contact at the removed portion 118 of the gate insulating film 5 and are electrically connected.

Next, FIG. 26B shows that the polycrystalline Si film 6 is separated into a gate electrode 66 shape by a photomask method and a dry etching method. Thereafter, though not shown, the SOI MOS transistor in which the body of the transistor, that is, the island-shaped Si thin film layer 33 and the gate electrode 66 are connected, is completed through source / drain ion implantation, source / drain electrode formation, and the like.

[0009]

However, in the above-mentioned conventional manufacturing method, since the resist mask 107 is formed directly on the gate insulating film 5, contamination occurs and the reliability of the gate insulating film 5 deteriorates. Film reduction due to cleaning at the time of removing 107, and film reduction at the time of removing by hydrofluoric acid a natural oxide film growing on the surface of the island-like Si thin film layer 33 of the removing portion 118 before forming the polycrystalline Si film 6 for the gate electrode. As a result, the finished film thickness of the gate insulating film 5 fluctuates, and there is an adverse effect when the transistor characteristics such as the threshold voltage vary.

As in the above example, two conductive films (33, 6
The method of removing the insulating film at the contact portion using a resist mask in order to electrically connect the two conductive films with the insulating film (5) interposed between the 6) and 6 There has been a problem that the thickness of the insulating film varies, which adversely affects the characteristics of the semiconductor device.

An object of the present invention is to prevent contamination and reduction of an insulating film in forming a contact between a lower first conductive film and an upper second conductive film separated by an insulating film. It is an object of the present invention to provide a method of manufacturing a semiconductor device which does not adversely affect the characteristics of the semiconductor device.

[0012]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising, as a main component, an oxide sandwiched between a lower first conductive film and an upper second conductive film. A step of performing ion implantation on a predetermined portion of the insulating film to weaken a bond between atoms constituting the insulating film, and a step of reducing the insulating film in the ion-implanted portion by performing a heat treatment in a hydrogen atmosphere And

According to this manufacturing method, the contact between the first conductive film and the second conductive film separated by the insulating film is changed to the second conductive film.
Can be formed by reducing a predetermined portion of the insulating film after the formation of the conductive film, and since the insulating film does not come into contact with a resist or a cleaning solution, contamination and reduction of the insulating film can be prevented. Does not adversely affect the characteristics of the device. In particular, this is effective when the thickness of the insulating film needs to be suppressed like a gate insulating film. Further, for example, the body contact of the SOI MOS transistor can be formed without using a wiring layer, and the restriction on the wiring layout can be reduced as compared with the case of using metal wiring.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
2. The method for manufacturing a semiconductor device according to claim 1, wherein a plurality of portions reduce the insulating film, and ion implantation for weakening bonds between atoms forming the insulating film is performed at the plurality of portions at different doses. It is characterized by.

By using this manufacturing method for forming an antifuse, it is possible to form an antifuse having the same mask and structure up to the formation of a contact plug and having a different resistance value by changing the subsequent mask. A multi-value ROM can be formed.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
Forming a first conductive film, forming an insulating film containing an oxide as a main component on the first conductive film, forming a second conductive film on the insulating film, Forming a hydrogen barrier film having an opening in a predetermined portion on the conductive film,
Reducing the insulating film below the opening of the hydrogen barrier film by performing a heat treatment in a hydrogen atmosphere.

According to this manufacturing method, the same effect as the first aspect can be obtained.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
4. The method for manufacturing a semiconductor device according to claim 3, wherein before the heat treatment is performed in a hydrogen atmosphere, ion implantation for weakening a bond between atoms constituting the insulating film is performed on the insulating film below the opening of the hydrogen barrier film. Is carried out.

Thus, the heat treatment in the hydrogen atmosphere is
The same effect can be obtained with a lower heat treatment temperature or a shorter treatment time.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
5. The method for manufacturing a semiconductor device according to claim 4, wherein a plurality of portions reduce the insulating film, and ion implantation for weakening bonds between atoms constituting the insulating film is performed at the plurality of portions at different doses. It is characterized by.

According to this manufacturing method, the same effect as the second aspect can be obtained.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 are process diagrams showing a method for manufacturing a semiconductor device according to the first embodiment of the present invention. In this embodiment, an n-channel SOI MOS
This is described using an example of a method for manufacturing a semiconductor device in which a gate and a body of a transistor are connected in a transistor.
FIG. 1 [A], [B], FIG. 2 [A], [B], FIG.
[A], [B], FIG. 4 [A], [B], FIG. 5 [A],
[B], in each of FIG. 6, (a) is a plan view,
(B) is a sectional view taken along the dashed-dotted line X shown in (a). FIG. 6C is a cross-sectional view taken along the dashed-dotted line Y shown in FIG.

FIG. 1A shows an initial state of an SOI substrate, wherein 1 is a base Si substrate, 2 is a base insulating film, and 3 is a Si substrate.
It is a thin film layer. First, as shown in FIG.
Is separated by a photomask method and a dry etching method to form an island-like Si thin film layer 33, and B (boron) ions 4 for controlling a threshold voltage are implanted. Here, island Si
The projecting portion 23 is provided in a portion of the thin film layer 33 where a body contact of the transistor is taken.

Next, a gate insulating film 5 is formed as shown in FIG. Here, for example, SiO 2 is used as the gate insulating film 5.
The N film is formed to have a thickness of 3 nm.
0 nm or less is desirable. The content of N in the SiON film is 1
0 mol% or less. The gate insulating film 5 may be a SiO ₂ film, but its thickness is also preferably 10 nm or less.

Next, as shown in FIG. 2B, for example, a 100 nm polycrystalline Si film 6 is deposited for a gate electrode.

Next, as shown in FIG. 3A, an opening 1 is formed above the projecting portion 23 of the island-like Si thin film layer 33 by a photomask method.
A resist mask 7 having 28 is formed on the polycrystalline Si film 6, and thereafter, for example, Si ions 10 are implanted here to weaken the bonds between atoms of the SiON film of the gate insulating film 5. The acceleration voltage is 80 keV, and the dose is, for example, 5 × 1.
0 ¹⁵ cm ^-2 .

After the ion implantation, the resist mask 7 is removed, and a heat treatment is performed in a hydrogen atmosphere at, for example, 1100 ° C. for 3 hours to reduce a part of the gate insulating film 5 where the ion is implanted and the element bond is weak. O in the SiON film is combined with hydrogen and gasified as H ₂ O to be released. As a result, the implanted portion of the SiON film becomes a Si layer containing a small amount of N (this Si layer is included in the polycrystalline Si film 6 in FIG. 3B and thereafter), and the island-shaped Si thin film layer 33 is formed. Is electrically connected to the gate electrode polycrystalline Si film 6 (FIG. 3B). Note that O in the SiON film is not necessarily required.
It is not necessary to reduce all of the above. Particularly, in the case of a body contact of a transistor, even if the contact resistance is somewhat high, it is permissible. Therefore, an effect can be obtained if the atomic ratio to Si is 1/4 or less.

Next, as shown in FIG. 4A, the polycrystalline Si film 6 is separated and processed into a gate electrode 66 shape by a photomask method and a dry etching method. Next, if necessary,
Ion implantation is performed, and then a sidewall insulating film 11 is formed by CVD and dry etching over the entire surface.
[B]). Here, the side wall insulating film 11 is made of SiO.
_Two films are used and the film thickness is 80 nm. At the time of the over-etching of the dry etching, the gate insulating film 5 on the region serving as the source / drain portion in the island-like Si thin film layer 33 is also etched,
The island-shaped Si thin film layer 33 is exposed.

Next, as shown in FIG. 5A, after forming a resist mask 12 covering at least the projecting portion 23 by a photomask method, ion implantation for forming a source / drain portion 18 is performed. Here, for example, As ions 13 are
It is assumed that V is implanted at 2 × 10 ¹⁵ cm ⁻² .

Next, after removing the resist mask 12, as shown in FIG. 5B, a resist mask 22 having an opening 138 on the protrusion 23 and covering the source and drain of the transistor is formed by a photomask method. Then, ion implantation is performed. Here, for example, B (boron) ion 43 is 30 ke
4 × 10 ¹⁴ cm ^{−2 is} implanted with V. This ion implantation reduces the contact resistance between the gate electrode 66 and the transistor body.

Next, after removing the resist mask 22, a cobalt silicide film 15, for example, is formed on the surfaces of the gate electrode 66 and the source / drain portion 18 by a self-aligned silicidation process as shown in FIG. 1
6, a contact hole is opened, a metal wiring layer 17 is formed, and the transistor is completed. In FIG. 6, 1
Reference numeral 9 denotes an LDD region.

Returning to the description of FIG. 3A, the implanted ions are Si ions 10, but some effects such as H and C can be obtained, and a plurality of element ions can be implanted. Is also good. In a process where diffusion by heat treatment does not pose a problem, a similar effect can be obtained by implanting a dopant impurity, for example, P, As, BF ₂ , or B according to the contact conductivity type instead of Si. In the case of forming an n-type contact, in particular, As implantation with a large mass can achieve a high effect with a small implantation amount. Regarding dose amount, ion species,
Although the effect differs depending on the thickness of the insulating film and the temperature of the subsequent heat treatment, 1 × 10 ¹⁵ cm ⁻² or more is required. The upper limit of the dose is determined in consideration of the processing time and the resist stripping property. The heat treatment temperature for reducing part of the gate insulating film 5 is 900 ° C. or more and 12
Desirably less than 00 ° C. This is because when the temperature exceeds 1200 ° C., the oxide film (gate insulating film 5) in a portion where ions are not implanted becomes thinner due to a reduction reaction, and the transistor characteristics such as the threshold voltage fluctuate. Also, 9
If the temperature is lower than 00 ° C., almost no reduction reaction occurs, and thus 9
Increase to 00 ° C or higher.

As described above, according to the present embodiment, the contact between the island-like Si thin film layer 33 separated by the gate insulating film 5 and the gate electrode 66 is formed by forming the polycrystalline Si film 6 serving as the gate electrode 66. It can be formed later by reducing a predetermined portion of the gate insulating film 5, and since the gate insulating film 5 does not come into contact with a resist or a cleaning liquid as in the related art,
The contamination of the gate insulating film 5 and the reduction of the film can be prevented,
There is no adverse effect on transistor characteristics such as threshold voltage. Also, compared to the case of using metal wiring, SO
The body contact of the IMOS transistor can be formed without using a wiring layer, so that restrictions on the wiring layout can be reduced. This is because the wiring layer (Al
This is because, when Cu or the like is used, the present embodiment can avoid the necessity of a space for avoiding a bridge between the source and the drain and a wiring layer, which increases the wiring area.

(Second Embodiment) Next, a second embodiment of the present invention will be described. Fig. 1 [A] to Fig. 2
Since the steps up to [B] are exactly the same as those in the first embodiment, the description is omitted. FIG. 7 is a process sectional view showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
In this embodiment, steps different from those of the first embodiment are shown. This FIG. 7 is equivalent to FIG. 1 [A], [B] and FIG.
It is a cross section of the same part as (b) such as [A] and [B], and a plan view is omitted.

After forming the polycrystalline Si film 6 shown in FIG.
As shown in FIG. 7A, a SiN film 8 (hydrogen barrier film) is formed by the CVD method. The SiN film 8 preferably has a thickness of 10 nm or more because it plays a role of a hydrogen barrier in a high-temperature heat treatment in hydrogen in a later step.

Thereafter, as shown in FIG. 7B, a resist mask 7 having an opening 128 above the projecting portion 23 of the island-shaped Si thin film layer 33 is formed by a photomask process, and the resist mask 7 is opened by dry etching. The SiN film 8 below the hole 128 is removed.

Next, after removing the resist mask 7, FIG.
In a hydrogen atmosphere as in [C], for example, at 1200 ° C. for 30 minutes.
A portion of the gate insulating film 5 under the portion from which the SiN film 8 has been removed is reduced,
(This Si layer is made of polycrystalline Si in FIG.
It is shown included in the film 6).

Thereafter, when the SiN film 8 is removed by hot phosphoric acid, the structure shown in FIG. 7D is obtained, which has the same structure as that of the first embodiment shown in FIG. 3B. Thereafter, transistors are formed in the same steps as in the first embodiment (FIGS. 4 to 6), and the transistor as shown in FIG. 6 is completed.

According to the present embodiment, the same effects as in the first embodiment can be obtained. Further, in the present embodiment, the SiN film 8 of the hydrogen barrier is formed so that the SiN film 8 is heat-treated at a high temperature of 1200 ° C. for 30 minutes in a hydrogen atmosphere.
The gate insulating film 5 under the portion covered with the film 8 is not reduced. By performing the heat treatment for 30 minutes in a hydrogen atmosphere at such a high temperature, the gate insulation of the portion where the SiN film 8 is opened can be performed without weakening the bonding of atoms by ion implantation as in the first embodiment. Part of the film 5 can be selectively reduced. As described above, although it is possible without the ion implantation step, lower heat treatment can be achieved by opening the SiN film 8 and then ion-implanting Si or the like into the gate insulating film 5 from the opening 128 using the resist mask 7 as a mask. The same effect can be obtained at a temperature or in a shorter time. When ion implantation is not performed, the heat treatment temperature is 1050 ° C. or higher and 1
Desirably less than 250 ° C. This is because if the temperature is lower than 1050 ° C., it is difficult to reduce, and if the temperature is higher than 1250 ° C., the wafer is liable to become defective due to softening or the like.

According to the present embodiment, the heat treatment for reduction can be performed at a higher temperature than in the first embodiment, so that a lower resistance value can be obtained.

(Third Embodiment) Next, as a third embodiment, a method of forming a multi-value ROM using an antifuse formed by using the present invention will be described. FIG. 8 shows a multi-valued RO having an antifuse manufactured by applying the present invention.
FIG. 4 is an equivalent circuit diagram of an M memory cell unit. In practice, the number of cells is usually on the order of kilos or megas, but here, for simplicity, nine cells are used. 8, reference numeral 80 denotes a cell transistor, W1, W2, and W3 denote gate electrodes or word lines, and B1, B2, and B3 denote bit lines connected to the drain D of each cell transistor 80. R0, R
1, R2, R3, R} are additional resistances between the bit lines B1 to B3 and the drain D of each cell transistor 80. There are five levels here, and the resistances of the respective resistances are the same R0, R1, R
2, R3, R}, R0 <R1 <R2
<R3 <R #, and the additional resistor R # indicates that its resistance is infinite, that is, there is no conduction. The sources S of each cell transistor 80 are all grounded. Bit line B
A current detection circuit (not shown) is connected to the ends of 1, B2 and B3. By applying a voltage to one of the bit lines and one of the word lines, only one of the cell transistors is selectively turned on, but the amount of current varies depending on the resistance of the additional resistor between the bit line and the drain. Here, R means non-conduction
Since there are five stages of additional resistances including ∞, the current amount has five stages including zero, and is converted into a five-stage digital signal by the current detection circuit to function as a multi-value ROM.

FIG. 9 is a perspective plan view of the above-described multi-value ROM when viewed from above. In FIG. 9, reference numeral 52 denotes a drain portion n ⁺
A diffusion layer, 53 a source portion n ⁺ diffusion layer, 54 a substrate contact portion p ⁺ diffusion layer, 57 a conductor contact plug, 6
6 is a gate electrode (word line), 81 is a drain wiring (bit line), 83 is a source wiring, 84 is a substrate contact wiring, and 100 is an anti-fuse part.

FIGS. 10 to 21 are process sectional views showing a method of forming the above-mentioned multi-value ROM to which the present invention is applied. For convenience of description, this process sectional view is not necessarily cut by one straight line. Here, it is assumed that the memory cell transistor is formed only of an n-channel transistor.

FIG. 10 shows a state where a contact plug for a transistor is formed. In FIG.
i-substrate, 51 is an element isolation oxide film, 52 is a drain part n ⁺
A diffusion layer, 53 is a source portion n ⁺ diffusion layer, 54 is a substrate contact portion p ⁺ diffusion layer, 5 is a gate insulating film, 66 is a gate electrode (word line), 55 is an interlayer insulating film, and 56 is a first barrier metal. , 57 indicate conductor contact plugs. The barrier metal 56 is, for example, TiN film, conductive contact plugs 57 have a need to use a material having a 900 ° C. or higher heat resistance, here it is assumed that using WSi film, W film and n ⁺ polycrystalline Si It may be a film or a MoSi film. The contact plug 57 is formed by dry etching, opening a contact hole, depositing a barrier metal 56 over the entire surface, then depositing a WSi film over the entire surface by a CVD method, and then removing the WSi film except inside the contact hole by a CMP or etch-back method. , Are formed so as to be buried only in the contact holes by removing the TiN film.

Next, as shown in FIG.
As 8, for example, a TiN film is formed to a thickness of, for example, 50 nm by a PVD method or a CVD method, and then, a thin film SiO ₂ film 59 is formed to a thickness of 6 nm by, for example, a CVD method, and a resist mask 71 having an opening 701 is formed thereon by a photomask method. Form.

Next, as shown in FIG. 12, using the resist mask 71 as a mask, the thin SiO ₂ film 59 below the opening 701 is removed by dry etching. In this step, on the conductor contact plug 57 on the gate electrode 66, on the conductor contact plug 57 on the source part n ⁺ diffusion layer 53, and on the conductor contact plug 57 on the substrate contact part p ⁺ diffusion layer 54, All thin SiO ₂ film 5
9 is removed, and the target value of the additional resistance value of the conductor contact plug 57 on the drain portion n ⁺ diffusion layer 52 is R0.
The thin-film SiO ₂ film 59 is removed only for the cell.

Next, after removing the resist mask 71, FIG.
For example, n ⁺ containing a high concentration of phosphorus
A polycrystalline Si film 61 is deposited to a thickness of 100 nm by a CVD method.

Next, as shown in FIG. 14, an independent resist mask 72 is formed in the shape of a cushion on all the conductor contact plugs 57 by a photomask method, and a polycrystalline Si film 61 and a thin film SiO ₂ film are formed by a dry etching method. 59,
The second barrier metal 58 is selectively removed.

[0049] Then in Figure 15 that the removal of the resist mask 72, the cushion-shaped n ⁺ polycrystalline 61 / thin SiO ₂
The anti-fuse section 100 is constituted by the three layers of the film 59 and the second barrier metal 58.

Next, as shown in FIG. 16, a resist mask 73 having an opening 703 only on the conductor contact plug 57 on the drain portion n ⁺ diffusion layer 52 where the target value of the added resistance is R1 is formed by a photomask method. After that, for example, Si ions 713 are implanted at 1 × 10 ¹⁶ cm ⁻² at 80 keV aiming at the thin SiO ₂ film 59.

Next, after removing the resist mask 73, as shown in FIG. 17, the target value of the additional resistance is set to a value corresponding to the conductor contact plug 57 on the drains of R1 and R2 by a photomask method.
After forming a resist mask 74 having an opening 704 thereon, for example, Si ions 713 are applied at 1 × 10 ¹⁶ at 80 keV.
Inject cm- ² .

Next, after the resist mask 74 is removed, an opening 705 is formed only on the conductor contact plug 57 on the drains of R1, R2 and R3 with the target value of the added resistance by the photomask method as shown in FIG. Resist mask 7
After the formation of 5, for example, Si ions 713 are added at 80 keV for 1
× 10 ¹⁶ cm ^{-2 is} implanted.

Next, FIG. 19 shows that the resist mask 75 is removed.

Next, a heat treatment is performed in a hydrogen atmosphere at, for example, 1100 ° C. for 1 minute, and the portion of the thin film SiO ₂ film 59 where the bonds between the atoms are weakened by the ion implantation is reduced and converted into a Si film. 61 and the second barrier metal 58 are electrically connected (FIG. 20). Note that FIG.
In the figure, the polycrystalline Si film 61 includes the Si film in which the thin-film SiO ₂ film 59 is reduced, and schematically shows a reduced portion. In the heat treatment here, a clear effect can be obtained as the temperature is higher and the time is longer, but in the present embodiment,
This is a step after high-concentration source / drain implantation of a transistor.
Minutes, and the effect can be obtained even in such a short time.

According to the above-described process, the total Si dose in the portion where the target value of the additional resistance is R1 is 3 × 10 ¹⁶ cm ⁻² ,
R2 part is 2 × 10 ¹⁶ cm ⁻² , R3 part is 1 × 10
¹⁶ cm ^-2, and the oxygen is reduced to contain the Si film is reduced the greater the dose, the resistance value after the heat treatment R1
<R2 <R3. Further, the non-implanted portion remains nonconductive = R∞, and the thin SiO ₂ film 5
The portion where the n ⁺ polycrystalline Si film 61 is formed after the opening portion is provided in 9 has the lowest resistance value R0.

Next, as shown in FIG. 21, for example, an AlCu film is deposited, and wirings are patterned by a photomask method and a dry etching method, and a drain wiring (bit line) 81, a gate wiring (word line) 82, a source wiring 83, The multilevel ROM is completed by forming the substrate contact wiring 84. Note that, in FIG. 9, the gate wiring 82 and its contact portion exist in a region not shown.

The heat treatment temperature in the hydrogen atmosphere in the step of FIG. 20 is 9 as in the first embodiment.
The temperature is desirably from 00 ° C to less than 1200 ° C. In the present embodiment, when the temperature exceeds 1200 ° C., the thinned SiO ₂ film 59 in the portion where the ions are not implanted is reduced in thickness by a reduction reaction,
The resistance of the additional resistor will fluctuate.

The implanted ions in the steps shown in FIGS. 16, 17 and 18 are Si ions 7 as in the first embodiment.
In addition to 13, ions such as H and C and a plurality of element ions thereof may be implanted. Alternatively, a dopant impurity, for example, P, As, BF ₂ , or B may be implanted. Among them, As has a large mass and is effective.

As described above, according to the present embodiment, the same mask is used for each antifuse portion 100 until the formation of the conductive contact plug 57 thereunder.
With the structure, the antifuse portion 100 having a different resistance value can be formed by changing a subsequent mask, and various multi-value ROMs can be formed in a short period of time.

In the third embodiment, FIG.
After the step, the steps of FIGS. 22 and 23 may be added.
As shown in FIG. 22, a 50 nm SiN film 91 is deposited on the entire surface by the CVD method, and then, as shown in FIG. 23, the antifuse portion 1 is formed by the photomask method and the dry etching method.
The opening is provided by removing the SiN film 91 on the uppermost layer. After that, the process is performed in the same manner as the process from FIG. In this case, FIG.
The heat treatment temperature for the reduction performed in step 0 is set to less than 1250 ° C. to prevent wafer defects.

[0061]

As described above, according to the present invention, the contact between the first conductive film and the second conductive film separated by the insulating film is formed after the formation of the second conductive film. The insulating film can be formed by reducing the portion, and since the insulating film does not come into contact with the resist or the cleaning solution, contamination and reduction of the insulating film can be prevented, and the characteristics of the semiconductor device are not adversely affected. . In particular, this is effective when the thickness of the insulating film needs to be suppressed like a gate insulating film. Further, for example, the body contact of the SOI MOS transistor can be formed without using a wiring layer, and the restriction on the wiring layout can be reduced as compared with the case of using metal wiring.

Further, by using the present invention for forming an antifuse, it is possible to form an antifuse having the same mask and structure up to the formation of a contact plug and a different resistance value by changing the subsequent mask. A multi-value ROM can be formed.

[Brief description of the drawings]

FIGS. 1A and 1B are a plan view and a sectional view for each step showing a method for manufacturing a semiconductor device (SOI MOS transistor) according to a first embodiment of the present invention.

2A and 2B are a plan view and a cross-sectional view for each step showing a method for manufacturing a semiconductor device (SOI MOS transistor) according to the first embodiment of the present invention.

3A and 3B are a plan view and a cross-sectional view for each step illustrating a method for manufacturing a semiconductor device (SOI MOS transistor) according to the first embodiment of the present invention.

4A and 4B are a plan view and a cross-sectional view for each step showing a method for manufacturing a semiconductor device (SOI MOS transistor) according to the first embodiment of the present invention.

5A and 5B are a plan view and a cross-sectional view for each step showing a method for manufacturing a semiconductor device (SOI MOS transistor) according to the first embodiment of the present invention.

6A and 6B are a plan view and a cross-sectional view for each step showing a method for manufacturing a semiconductor device (SOI MOS transistor) according to the first embodiment of the present invention.

FIG. 7 is a process sectional view illustrating the method for manufacturing the semiconductor device (SOI MOS transistor) according to the second embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of a semiconductor device (multi-level ROM) according to a third embodiment of the present invention.

FIG. 9 is a perspective plan view of a semiconductor device (multi-level ROM) according to a third embodiment of the present invention.

FIG. 10 is a process sectional view illustrating the method for manufacturing the semiconductor device (multi-level ROM) according to the third embodiment of the present invention.

FIG. 11 is a process sectional view illustrating the method of manufacturing the semiconductor device (multi-value ROM) according to the third embodiment of the present invention.

FIG. 12 is a process sectional view illustrating the method for manufacturing the semiconductor device (multi-level ROM) according to the third embodiment of the present invention.

FIG. 13 is a process sectional view illustrating the method for manufacturing the semiconductor device (multi-level ROM) according to the third embodiment of the present invention.

FIG. 14 is a process sectional view illustrating the method of manufacturing the semiconductor device (multi-level ROM) according to the third embodiment of the present invention.

FIG. 15 is a process sectional view illustrating the method for manufacturing the semiconductor device (multi-level ROM) according to the third embodiment of the present invention.

FIG. 16 is a process sectional view illustrating the method for manufacturing the semiconductor device (multi-level ROM) according to the third embodiment of the present invention.

FIG. 17 is a process sectional view illustrating the method of manufacturing the semiconductor device (multi-value ROM) according to the third embodiment of the present invention.

FIG. 18 is a process sectional view illustrating the method for manufacturing the semiconductor device (multi-level ROM) according to the third embodiment of the present invention.

FIG. 19 is a process sectional view illustrating the method of manufacturing the semiconductor device (multi-level ROM) according to the third embodiment of the present invention.

FIG. 20 is a process sectional view illustrating the method of manufacturing the semiconductor device (multi-level ROM) according to the third embodiment of the present invention.

FIG. 21 is a process sectional view illustrating the method of manufacturing the semiconductor device (multi-value ROM) according to the third embodiment of the present invention.

FIG. 22 is a process cross-sectional view showing another example of the method for manufacturing the semiconductor device (multi-level ROM) according to the third embodiment of the present invention.

FIG. 23 is a process cross-sectional view showing another example of the method for manufacturing the semiconductor device (multi-level ROM) according to the third embodiment of the present invention.

24A and 24B are a plan view and a cross-sectional view for each step showing a conventional method for manufacturing a semiconductor device.

FIG. 25 is a plan view and a cross-sectional view for each step showing a conventional method for manufacturing a semiconductor device.

26A and 26B are a plan view and a cross-sectional view for each step showing a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 1 base Si substrate 2 base insulating film 3 Si thin film layer 4 B ion 5 gate insulating film 6 polycrystalline Si film 7 resist mask 8 SiN film 10 Si ion 11 sidewall insulating film 12 resist mask 13 As ion 15 cobalt silicide film 16 interlayer Insulating film 17 Metal wiring layer 18 Source / drain part 19 LDD region 22 Resist mask 23 Projecting part 33 Island-like Si thin film layer 43 B ion 50 p-type Si substrate 51 Element isolation oxide film 52 Drain part n ⁺ diffusion layer 53 Source part n ⁺ Diffusion layer 54 Substrate contact portion p ⁺ Diffusion layer 55 Interlayer insulating film 56 First barrier metal 57 Conductor contact plug 58 Second barrier metal 59 Thin SiO ₂ film 61 n ⁺ Polycrystalline Si film 66 Gate electrode 71 to 75 Resist Mask 80 Cell transistor 81 Drain arrangement (Bit line) 82 gate line 83 the source wiring 84 substrate contact wiring 91 SiN film 100 antifuse portion 128, 138 opening 701,703,704,705 opening 713 Si ions

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/112 H01L 29/78 617J 29/786 622 626Z F-term (Reference) 4M104 AA01 AA09 BB01 BB02 BB30 CC01 DD06 DD08 DD15 DD17 DD28 DD33 DD43 DD56 DD65 DD73 DD75 DD78 DD82 DD88 EE03 EE15 EE17 GG09 GG10 GG14 GG20 HH14 HH20 5F033 GG03 HH04 HH09 HH25 HH33 JJ04 Q19 KK29 QQ60 QQ61 QQ68 QQ74 RR04 RR08 SS11 VV11 VV15 5F064 BB15 CC10 EE32 FF24 FF28 FF29 FF48 5F083 CR14 CR15 HA02 JA35 JA36 JA37 JA39 JA40 MA05 MA06 PR18 PR33 PR36 PR39 PR40 ZA10 ZA21 5F110 EA12 FF20 AE05 DD12 FF40 GG02 GG23 GG32 GG52 HJ01 HJ04 HJ13 HK05 HK40 HL01 HL04 HL05 HL08 HL11 HL24 HM15 NN62 QQ11

Claims (5)

[Claims] An insulating film mainly composed of an oxide sandwiched between a first conductive film as a lower layer and a second conductive film as an upper layer has a predetermined thickness between atoms constituting the insulating film. A method of manufacturing a semiconductor device, comprising: a step of performing ion implantation for weakening a bond; and a step of performing heat treatment in a hydrogen atmosphere to reduce the insulating film in a portion where the ion implantation has been performed. 2. The method according to claim 1, wherein a plurality of portions reduce the insulating film, and ion implantation for weakening bonds between atoms constituting the insulating film is performed at different doses to the plurality of portions. Item 2. A method for manufacturing a semiconductor device according to Item 1. 3. A step of forming a first conductive film, a step of forming an insulating film mainly containing an oxide on the first conductive film, and a step of forming a second conductive film on the insulating film. Forming, forming a hydrogen barrier film having an opening in a predetermined portion on the second conductive film, and performing heat treatment in a hydrogen atmosphere to form the insulating layer under the opening in the hydrogen barrier film. Reducing the film. 4. A process for performing ion implantation for weakening a bond between atoms constituting the insulating film into an insulating film below an opening of the hydrogen barrier film before performing the heat treatment in a hydrogen atmosphere. 4. The method for manufacturing a semiconductor device according to claim 3, wherein: 5. A method according to claim 1, wherein a plurality of portions reduce the insulating film, and ion implantation for weakening bonds between atoms constituting the insulating film is performed at different doses to the plurality of portions. Item 5. The method for manufacturing a semiconductor device according to Item 4.