TW201123448A - Gate electrode for field effect transistor and field effect transistor - Google Patents

Gate electrode for field effect transistor and field effect transistor Download PDF

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TW201123448A
TW201123448A TW99114020A TW99114020A TW201123448A TW 201123448 A TW201123448 A TW 201123448A TW 99114020 A TW99114020 A TW 99114020A TW 99114020 A TW99114020 A TW 99114020A TW 201123448 A TW201123448 A TW 201123448A
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field effect
effect transistor
metal material
metal
gate
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TW99114020A
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Chinese (zh)
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TWI437708B (en
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Peng-Soon Lim
Da-Yuan Lee
Kuang-Yuan Hsu
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Taiwan Semiconductor Mfg
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/512—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being parallel to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)

Abstract

The invention relates to integrated circuit fabrication, and more particularly to a field effect transistor with a low resistance metal gate electrode. In one embodiment, a gate electrode for a field effect transistor comprises a lower portion formed of a first metal material having a recess and a first resistance; and an upper portion formed of a second metal material having a protrusion and a second resistance, wherein the protrusion extends into the recess, and the second resistance is lower than the first resistance.

Description

201123448 六、發明說明： 【發明所屬之技術領域】 本發明係關於積體電路製作，且特別是關於具有金 屬閘極電極（metal gate electrode)之一種場效應電晶體 (field effect transistor，FET)。 【先前技術】 隨著電晶體尺寸的縮減，便需要降低閘極氧化物 (gate oxide)厚度以維持具有經縮減閘極長度（gate iength) 之表現。然而’為了降低閘極漏電流（gate leakage)，因而 採用了高介電常數(high_k)閘極介電膜層，於維持較大技 術節點中所採用之習知閘極氧化物所具有之相同等效厚 度時其可具有較高之物理厚度。 此外’隨著技術節點縮減，於部份積體電路設計中， 便需要採用金屬閘極電極以取代習知多晶矽閘極電極， 藉以改善具有縮減特徵尺寸之元件的表現。形成金屬閘 極的製程之一係為”後閘極（gate iast)，，製程，其内金屬閘 極係最後製備形成’因而允許了閘極電極免於受到某些 高溫製程的影響’例如是受到源極/汲極回火程序的影響。 第1圖為一剖面圖，顯示了採用，，後閘極，，製程所製 造得到之用於場效應電晶體1〇〇之一習知閘極結構（gate structure)120。在此’場效應電晶體ι〇〇係形成於基底ι〇2 内且鄰近於數個隔離區1〇4之一主動區1〇3之上。場效 應電晶體100包括形成於基底102之主動區103内的數 個源極/没極區106與輕度摻雜區ι〇8、包括依序形成於 0503-A34608TWF/shawnchang 4 201123448 基底120上之一中間層122、一閘極介電層124與多膜層 金屬閘極電極120a之一閘極結構12〇、以及分別形成於 閘極結構120之兩侧側壁上之閘極間隔物11〇。此外，於 基底102之上亦可形成有一接觸蝕刻停止層112與一層 間介電層114。 此多膜層金屬閘極12〇a包括了依序形成於閘極介電 層124上方之一下方部（lower portion) 126以及一上方部 (upper P〇rti〇n)l28。下方部126係由作為功函數金屬層 • (WOrk-function metal hyer)且具有第一電阻值之一第一金 屬材料所構成。上方部128則由作為一内連金屬層 (interconnection metal layer)且具有低於上述第一電阻值 之一第二電阻值的一第二金屬材料所構成。由於具有較 低電阻值之上方部128僅佔據了此多膜層金屬閘極12〇a 區域之小。卩伤，可以觀察到的是此多膜層金屬閘極 120a將表現出較高之閘極電阻值，如此將增加了電路之 阻容延遲（RC delay)且劣化了裝置表現。 > 如此，便需要用於閘極結構之具有較低閘極電阻值 之金屬閘極電極（metal gate electrode)。 【發明内容】 於一實施例中，本發明提供了一種用於場效應電晶 體之閘極電極，包括： 由第一金屬材料形成之一下方部，具有一凹口及一 第一電阻值；以及由第二金屬材料形成之一上方部，具 有一突出部以及一第二電阻值，其中該突出部延伸進^ 5 0503-A34608TWF/shawnchang 201123448 该凹口内，且該第二電阻值低於該第一電阻值。 於另一實施例中，本發明提供了一種場效應電晶 體，包括： 基底，包括一主動區；一閘極結構，設置於該基 閘極介電層與一閘極電BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the fabrication of integrated circuits, and more particularly to a field effect transistor (FET) having a metal gate electrode. [Prior Art] As the size of the transistor is reduced, it is necessary to reduce the gate oxide thickness to maintain the performance of the reduced gate length. However, in order to reduce the gate leakage, a high dielectric constant (high_k) gate dielectric film is used, which is the same as the conventional gate oxide used in maintaining larger technology nodes. It can have a higher physical thickness at equivalent thickness. In addition, as the technology node is reduced, in a part of the integrated circuit design, a metal gate electrode is required to replace the conventional polysilicon gate electrode, thereby improving the performance of the component having the reduced feature size. One of the processes for forming a metal gate is a "gate iast", a process in which the metal gate is finally formed to form 'and thus allows the gate electrode to be protected from certain high temperature processes', for example It is affected by the source/drain tempering process. Figure 1 is a cross-sectional view showing the conventional gate used in the field effect transistor 1 manufactured by the process, the back gate, and the process. A gate structure 120. Here, a 'field effect transistor 〇〇 is formed in the substrate ι2 and adjacent to one of the plurality of isolation regions 1-4. The field effect transistor 100. The plurality of source/nomogram regions 106 and the lightly doped regions ι8 formed in the active region 103 of the substrate 102, including an intermediate layer 122 formed on the 0503-A34608TWF/shawnchang 4 201123448 substrate 120, are sequentially formed. a gate dielectric structure 124 of the gate dielectric layer 124 and the multi-layer metal gate electrode 120a, and gate spacers 11 分别 formed on the side walls of the gate structure 120, respectively. A contact etch stop layer 112 and a layer of dielectric may also be formed over 102. The layer 114. The multi-layer metal gate 12A includes a lower portion 126 and an upper portion (18) formed above the gate dielectric layer 124. The portion 126 is composed of a first metal material having a first resistance value as a work function metal layer (WOrk-function metal hyer). The upper portion 128 is formed as an interconnect metal layer and has A second metal material having a second resistance value lower than one of the first resistance values is formed. The upper portion 128 having a lower resistance value occupies only a small area of the multi-layer metal gate 12a. Injury, it can be observed that the multi-layer metal gate 120a will exhibit a higher gate resistance value, which will increase the circuit's RC delay and degrade the device performance. > There is a need for a metal gate electrode having a lower gate resistance value for a gate structure. SUMMARY OF THE INVENTION In one embodiment, the present invention provides a gate electrode for a field effect transistor , including: by the first gold Forming a lower portion of the material having a notch and a first resistance value; and forming an upper portion of the second metal material, having a protrusion and a second resistance value, wherein the protrusion extends into the ^ 5 0503 - A34608TWF/shawnchang 201123448, the second resistance value is lower than the first resistance value. In another embodiment, the present invention provides a field effect transistor, comprising: a substrate, including an active region; a gate structure disposed on the base gate dielectric layer and a gate

底之上 極’其中㈣極電極包括由―第—金屬材料所構成且具 有一凹口與第一電阻值之一下方部，以及由一第二金屬 ^料所構成且具有—突出部與-第：電阻值之一上方 部=，其中該突出部延伸進人該凹σ且該第二電阻值係低 ^該第—電阻值；以及複數個源極/祕區，位於該閘極 ，，，σ構之相對側之該主動區内。 為讓本發明之上述目的 懂，下文特舉一較佳實施例， 細說明如下： 、特徵及優點能更明顯易 並配合所附第圖式，作詳 L貫施方式】 可以理解的是於下文中提供了用於解說本發明之〉 述:3:不同實施例或範例。為了簡化本發明之击 作為範例之用而非用以限定本發明。舉： 說，於關於第一構件於一第二構 =第一構件與第二構件間之直接接觸方= 开匕隹構件與第二構件之間形成有額外構件之惰 接接=使得第一構件與第二構件之間可能不會產生直 接接觸情形。基於簡單清楚之目@，不_件可能採ΐ 〇5〇3-A34608TWF/shawnchang 6 201123448 不同比例而任意地繪示表現。此外，本發明提供了”後閘 極（gate last)”之金屬閘極製程之範例，然而熟悉此技藝者 可將之應用於其他製程及或採用其他材料。 請參照第2圖至第3H圖並配合下文以解說一方法 200以及一場效應電晶體300。第2圖為一流程圖，顯示 了依據本發明一實施例之製造閘極結構320之方法200。 第3A-3H圖則為一系列示意圖，顯示了依據如第2圖所 示之製造方法之一實施例中閘極結構320於不同階段中 φ 之情形。可以理解的是，部分之場效應電晶體300係由 互補型金氧半導體（CMOS)製造技術製成。如此，可以理 解的是，於第2圖所示之方法200實施之前、之中與之 後可更施行額外製程，且僅於此簡單描述了部分其他製 程。此外，為了較易暸解本發明之發明概念，第2圖至 第3H圖亦經過簡化。舉例來說，雖然以下圖式僅繪示了 用於場效應電晶體300之閘極結構320,可以理解到積體 電路可包括如電阻、電容、電感或熔絲等許多其他裝置。 φ 請參照第2圖與第3A圖，方法200啟始於步驟202, 首先提供包括閘極結構320之一溝槽325之一半導體基 底320。半導體基底302可包括一矽基底。半導體基底 302亦可包括矽鍺、砷化鎵或其他適當半導體材料。半導 體基底302可更包括其他構件，例如多個摻雜區、埋入 膜層及/或一磊晶層。再者，半導體基底302可為一絕緣 層上覆半導體層之基底，例如絕緣層上覆矽（SOI)基底。 於其他實施例中，半導體基底302可包括一經摻雜磊晶 層、一梯度半導體層及/或更包括覆蓋具有不同性質之其 0503-A34608TWF/shawnchang 7 201123448 他半導體層之-半導體層’例如是位於—石夕鍺層上之一 石夕層。於其他範例中，可採用包括—多重膜㈣結構之 =化合物半導體基底或可能具有多重膜層半導體結構之 一梦基底。 半導體基底302可包括—主動區3〇3以及數個 區304。依照習知技術之設計需求，主動區3〇3可包括多 =雜形態。於部份實施例中，主動區3〇3可 磐質。舉例來說，主動區3〇3可能摻雜有p型 切如B或BF2 ’或者是摻雜有N型摻質，例如磷 或坤’及/或其組合。主叙yg· 電曰\ΤΛ 動區303可用於Ν型金氧半導體 電曰曰體（通稱為NMOS)或用於ρ型金 稱為PMOS)。 ϋ氧牛導體電a日體（通 此些隔離區3G4可形成半導體基底搬之上， 離多個主動區303。从此眩雜r~ ^ 物（LOCOS)或淺溝样隔二雜^區綱可利用如局部石夕氧化 G3°於本實施射，隔離區 石夕、氮化石夕此些隔離區304可包括氧化 教入雷钭u氮氧化矽、氟摻雜矽玻璃（FSG)、低介電常 適當材料及/或其組合。此些隔離區二 製程形成。：例槽隔離物可藉由任何適當 302於其内形成— 挪4干等锻泰底 電漿乾_、以及;用一乾姓刻、濕侧及或 jb m. ^ ± 、溝槽内填入一介電材料（例如藉由一 予沈積程序）。於部份實施例中，經回填之溝槽可 0503-A34608TWF/shawnchang 8 201123448 具有一多層結構，例如為包括熱氧化物襯層且由氮化矽 或氧化梦填滿之多層結構。 值得注意的是，場效應電晶體300可採用，，後閑極 (gate last)”製程及其他CM〇s技術製程以形成場效:電 曰^體300之多個構件。如此，在此僅簡短地描述其^之 多個構件。場效應電晶體之此些多個構件係於閘極結構 320形成之前採用一’’前閘極（gate first)”製程而先行形 成。此些不同構件可包括位於主動區303内且位於閘極 •結構320相對側之數個源極/汲極區（以下簡稱為N型^ p 型S/D)306與輕度摻雜源極/汲極區（以下簡稱為n型或p 型LDD)308 〇N型S/D 306以及LDD 308等區域内可播 雜有碟或石申，而P型S/D 306以及LDD 3〇8等區域則可 推雜有删或銦。上述不同構件可更包括位於問極結構細 之對稱側之閘間隔物（gate spacer) 31〇、接觸姓刻停止層 (contact etch stop layer，CESL) 3! 2 以及層間介電層 3! 閘極間隔物3H)可由氧切、氮切或其他適當^料形 ♦成。接觸姓刻停止層312可由氮化石夕、氮氧化石夕、或其 他適當材料所形成。層間介電層314則可包括由高深寬 比製程所形成及/或高密度電漿沈積製程所形成之氧化 後閘極’’製程中，絲行形成如多晶梦材質假 閘極之假閘極結構（未顯示），且可接著採用製程 技術直到完成制介電層314的沈積。接著於層間= f 314上實％化學機械研磨（CMp)以冑出此假閉極結 才。可接著移除此假閉極結構’進而形成—開口。可以 〇503-A34608TWF/shawnchang 9 201123448 理解的疋上述例子並不用於限定用於形成假閘極結構之 I程步驟°可以理解的是，上述假閘極結構可包括額外 之介電層及/或導雷展 守电嘴。舉例來說，假閘極結構可包括硬 罩幕層、中間層、卜定。 上盍層、擴散/阻障層，其他適當膜層 及/或其組合。 請繼續參照第3A圖，接著沈積一閘極介電層324， 口P伤填入於開π内以形成一溝槽325。於料實施例中， 閘介電層324可包扛年 卜 _ ^ 匕括氣化矽、氮化矽、咼介電常數介電 層或其組° n介電常數介電層可包括氧化給(Hf02)、氧 化給石夕（HfSiQ)、氮氧給_(Hfsi〇N)、氧化給鈕（H汀、 氧化給欽（HfTl0)、氧化銓鋅（HfZrO)、金屬氧化物、金屬 氮化物、金屬矽化物、過渡金屬氧化物、過渡金屬氮化 物、過渡金屬碎化物、金屬之氮氧化物、金屬銘酸鹽（metai aluminates)、梦酸錯（zirconium silicate)、銘酸錯（zirconium aluminates)、氮化石夕、II氧化石夕、氧化錯（zirconium oxide)、氧化鈦、氧化紹、二氧化給-氧化紹（Hf02-Al2〇3) 合金、其他適當之高介電常數材料及/或其組合。於部份 之實施例中，於開口内之高介電常數介電材料具有少於 2nm之厚度。閘介電層324可更包括一中間層322，以降 低閘介電層324與半導體基底302間的毀損情形。中間 層322可包括氮化矽、氮氧化矽、氮氧化矽、矽酸铪(Hf silicate)或氧化銘基介電材料（Al2〇3 based dielectric)。 一般來說，溝槽325係接著為多個金屬層所填入， 且可施行金屬圖案化程序以形成場效應電晶體1〇〇内之 適當金屬膜層。可施行一化學機械研磨（CMP)以移除溝槽 0503-A34608TWF/shawnchang 201123448 325外之多個金屬層，並形成場效應電晶體100之多膜層 金屬閘極電極120a。或者，亦可施行乾蝕刻或濕蝕刻製 程。可以觀察到的是場效應電晶體100之多膜層金屬閘 極電極120a内，由於具有較低電阻值之金屬層128僅佔 據了多膜層金屬閘極電極120a區域之一小部份，因此使 得多膜層金屬閘極電極120a具有高閘極電阻值。如此將 增加積體電路之阻容延遲（RC delay)並劣化裝置表現。如 此，於下文中透過第2圖與第3B-3H圖解說一經修改多 φ 膜層金屬閘電極120a以形成一閘極結構320，藉以降低 其閘極電阻值至低於一個次方值。如此可降低積體電路 之阻容延遲並提升元件表現。 請參照第2圖與第3B圖，方法200接著進行步驟 204，將具有第一凹口 326a之第一金屬材料326沈積並 部份填入溝槽325内。第一金屬材料326包括擇自由Ti、 Ta、W、TiAl、Co、其合金與其包括C及/或N之化合物 金屬所組成族群之一材料。第一金屬材料326可由化學 • 氣相沈積（CVD)、物理氣相沈積（PVD)或其他適當技術所 形成。第一金屬材料326具有一第一電阻值。第一金屬 材料326具有介於30〜150埃之一厚度。第一金屬材料326 可包括功函數金屬之一堆疊膜層。於一實施例中，用於 一 NM0S之第一金屬材料326可包括Ti、Ta、TiA卜其 合金或包括C及/或N等功函數金屬之化合物。於另一實 施例中，用於一 PM0S之第一金屬材料326可包括Ti、 Ta、Co、其合金或包括C及/或N等功函數金屬。於某些 實施例中，上述堆疊膜層可包括一阻障金屬（barrier metal) 0503-A34608TWF/shawnchang 11 201123448 層、一襯墊金屬（liner metal)層或一增濕金屬（wetting metal)層。 請參照第2圖與第3C圖，方法200接著進行步驟 206，沈積一犧牲層327於第一金屬材料326之上以填滿 第一凹口 326a與溝槽325。犧牲層327可包括多晶矽、 光阻或旋轉塗佈介電層，但並限定於上述材料。犧牲層 327可藉由化學氣相沈積（CVD)、物理氣相沈積（PVD)、 原子層沈積（ALD)、旋轉塗佈或其他適當技術所形成。犧 牲層327之厚度則依照第一凹口 326a與溝槽325之深度 而決定。如此，犧牲層327係沈積直至大體填滿第一凹 口 326a與溝槽325。 請參照第2圖與第3D圖，方法200接著進行步驟 208，施行一化學機械研磨（CMP)程序以移除溝槽325外 之犧牲層327、第一金屬材料326與閘極介電層324之一 部份。如此，當抵達層間介電層314處此化學機械研磨 程序將停止並因而提供了一大體平坦表面。或者，上述 移除情形亦可由一乾蝕刻及/或濕蝕刻程序所達成。 請參照第2圖與第3E圖，方法200接著進行步驟 210，經由一蝕刻製程移除第一金屬材料326之一上方部 以形成此第一金屬材料326之一第二凹口 326b。蝕刻製 程可包括一乾蝕刻製程及或一濕蝕刻製程。舉例來說， 濕蝕刻化學可包括SC-1或SPM，且可能具有如H202之 氧化劑，且於低於70°C之溫度施行以選擇性移除該第一 金屬材料326之上方部。舉例來說，乾蝕刻所使用之蝕 刻化學品可包括BC13以選擇性地移除該第一金屬材料 0503-A34608TWF/shawnchang 12 201123448 326之上方部。蝕刻製程形成了位於溝槽325之第一金屬 材料326内之第二凹口 326b。位於溝槽325内第一金屬 材料326之第二凹口 326b可具有介於約50〜2700埃之深 度。此深度可透過調整蝕刻製程之不同參數而達成，例 如是時間與蝕刻化學品。 再者，犧牲層327於蝕刻製程中可能不作為保護層 之用，除非其移除率不夠大。於一實施例中，蝕刻化學 品對於第一金屬材料326以及犧牲層327之間之移除率 | 比例較佳地高於10。再者，當閘極介電層324經過餘刻 化學品的毁損後，於後續製程中其將成為一缺陷源（defect source)並進而增加了漏電流之可能性。於一實施例中， 蝕刻化學品對於第一金屬材料326與閘極介電材料324 之移除率比例較佳地高於20。於本實施例中，位於溝槽 327内第一金屬材料326之一剩餘部形成了經修正金屬閘 極320a之一下方部。此下方部大體為U形。 請參照第2圖與第3F圖，方法200接著進行步驟 • 212，經由另一蝕刻製程以移除殘留於溝槽325内之犧牲 層327，以露出第一金屬材料326之第一凹口 326a。並 上述蝕刻製程可包括一乾蝕刻製程及/或一濕蝕刻製程。 舉例來說，用於選擇性地移除殘存於溝槽325内之犧牲 層327之乾/濕蝕刻之蝕刻化學品可包括F、C1及Br基化 學品。當鄰近於第一凹口 326a之第一金屬材料326為蝕 刻化學品所侵蝕時，將改變金屬之功函數，並進而增加 了裝置失敗之可能性。於一實施例中，蝕刻化學品對於 犧牲層327及第一金屬材料326之移除率比例較佳地高 0503-A34608TWF/shawnchang 13 201123448 於ίο。 請參照第2圖與第3G圖 214，沈積第二金屬材料328;^=ΖΪ行步轉 以填入第-金屬材料326之第一凹^屬^料326之上’ 3施内。第—金屬材料之第一凹口 3與第二凹口 於下文中通稱為溝槽325之±“^第實=口 _ 二金屬材地形成阻障層，藉以於第 “Ti'Ta'TiN、TaN__ 成私群之一材料。阻障層之厚 ' 可藉由CVD、PVD、ALD5 50埃。阻障層 份實施例中，由於阻障声術所形成°於部 障層。 障層亦具有南電阻值’故不使用阻 請繼續參照第2圖與第沁圖，於第 之上沈積第二金屬材料328以填滿溝槽325之上方部。 於本實施例中，第二金屬材料328可包括擇自由AH C〇與W所組成族群之一材料。第二金屬材料似可藉由 =D、PVD、電鍍、旋轉塗佈、原子層沈積或其他^當 製知所形成。第二金屬材料328具有第二電阻值。第二 電阻值係低於第-電阻值。舉例來說，A1的電阻值（: 2.65从〇.)係低於1^(約20(^〇,)之電阻值。第二金 屬材料328之厚度可依照溝槽325之上方部深度而:。 如此，第二金屬材料328係沈積直至大體填滿了溝槽325 之上方部。 3 請參照第2圖與第3H圖，方法接著進行步驟 0503-A34608TWF/shawnchang 14 201123448 216’施行一化學機械 外之第二金屬材料32:: 移除位於溝槽325 了叶。如此’此cMp程序 介電層314處將停止，因 序於抵達層間The bottom electrode 'where the (four) pole electrode comprises a lower portion of the first metal-resistance material and having a recess and a first resistance value, and is composed of a second metal material and has a protrusion portion and - a: an upper portion of the resistance value =, wherein the protrusion extends into the concave σ and the second resistance value is lower than the first resistance value; and a plurality of source/secret regions are located at the gate, The active region of the opposite side of the σ structure. In order to make the above objects of the present invention, the following description of the preferred embodiments will be described as follows: Features, advantages and advantages can be more obvious and can be combined with the attached drawings, and can be understood as follows. The following is a description of the invention: 3: different embodiments or examples. The simplification of the invention is intended to be illustrative and not to limit the invention. Lifting: said that the first member is in a second configuration = the direct contact between the first member and the second member = the idle joint formed between the opening member and the second member is made to make the first There may be no direct contact between the component and the second component. Based on the simple and clear purpose @,不_件可能ΐ 〇5〇3-A34608TWF/shawnchang 6 201123448 The performance is arbitrarily drawn in different proportions. In addition, the present invention provides an example of a "gate last" metal gate process, but those skilled in the art can apply it to other processes and or other materials. Referring to Figures 2 through 3H, and in conjunction with the following, a method 200 and a field effect transistor 300 are illustrated. 2 is a flow chart showing a method 200 of fabricating a gate structure 320 in accordance with an embodiment of the present invention. The 3A-3H diagram is a series of diagrams showing the φ of the gate structure 320 in different stages in accordance with an embodiment of the fabrication method as shown in Fig. 2. It will be appreciated that a portion of the field effect transistor 300 is fabricated by complementary metal oxide semiconductor (CMOS) fabrication techniques. As such, it will be appreciated that additional processes may be performed before, during, and after the implementation of the method 200 illustrated in FIG. 2, and only some of the other processes are briefly described herein. Further, in order to facilitate the understanding of the inventive concept of the present invention, FIGS. 2 to 3H are also simplified. For example, although the following figures depict only the gate structure 320 for the field effect transistor 300, it will be appreciated that the integrated circuit can include many other devices such as resistors, capacitors, inductors or fuses. φ Referring to Figures 2 and 3A, method 200 begins at step 202 by first providing a semiconductor substrate 320 comprising one of trenches 325 of gate structure 320. The semiconductor substrate 302 can include a germanium substrate. Semiconductor substrate 302 may also include germanium, gallium arsenide or other suitable semiconductor materials. The semiconductor substrate 302 may further include other components such as a plurality of doped regions, a buried film layer, and/or an epitaxial layer. Furthermore, the semiconductor substrate 302 can be a substrate on which an insulating layer is overlaid on a semiconductor layer, such as a silicon-on-insulator (SOI) substrate. In other embodiments, the semiconductor substrate 302 can include a doped epitaxial layer, a graded semiconductor layer, and/or a semiconductor layer that covers a semiconductor layer having a different property, such as 0503-A34608TWF/shawnchang 7 201123448. Located on the Shishi layer on the Shi Xiyu layer. In other examples, a compound semiconductor substrate comprising a multi-membrane (four) structure or a dream substrate having a multi-layer semiconductor structure may be employed. The semiconductor substrate 302 can include an active region 3〇3 and a plurality of regions 304. According to the design requirements of the prior art, the active area 3〇3 may include multiple = heteromorphic forms. In some embodiments, the active zone 3〇3 can be enamel. For example, active region 3〇3 may be doped with a p-type such as B or BF2' or doped with an N-type dopant, such as phosphorus or kun' and/or combinations thereof. The main yg·electric 曰\ΤΛ movable area 303 can be used for Ν-type MOS semiconductors (known as NMOS) or for ρ-type gold (called PMOS). The neon-negative bovine conductor a-day body (through these isolation regions 3G4 can form a semiconductor substrate on top of the active substrate 303. From then on, the slanting r~^ object (LOCOS) or the shallow groove-like separation It can be used, for example, to locally illuminate G3° in the present embodiment, and the isolation zone 304 can include oxidized teachings of Thunderium bismuth oxynitride, fluorine-doped bismuth glass (FSG), and low-passage. Electrically suitable materials and/or combinations thereof. These isolation zones are formed by two processes.: The trench spacers can be formed by any suitable 302 - forging and drying, etc., and using a dry The surname, the wet side, or the jb m. ^ ±, the trench is filled with a dielectric material (for example, by a deposition process). In some embodiments, the backfilled trench can be 0503-A34608TWF/shawnchang 8 201123448 has a multilayer structure, such as a multilayer structure comprising a thermal oxide liner and filled with tantalum nitride or oxidized dream. It is worth noting that field effect transistor 300 can be used, gate last Process and other CM〇s technology processes to form a field effect: multiple components of the body 300. Here, only a plurality of members of the field effect transistor are briefly described. These plurality of members of the field effect transistor are formed first by a 'gate first' process before the gate structure 320 is formed. The different components may include a plurality of source/drain regions (hereinafter abbreviated as N-type p-type S/D) 306 located in the active region 303 on opposite sides of the gate/structure 320 and a lightly doped source/汲The polar region (hereinafter referred to as n-type or p-type LDD) 308 〇N-type S/D 306 and LDD 308 can be mixed with disc or stone, and P-type S/D 306 and LDD 3〇8 The different components may further include a gate spacer 31 on the symmetric side of the thin pole structure, and a contact etch stop layer (CESL) 3! And the interlayer dielectric layer 3! The gate spacer 3H) may be formed by oxygen cutting, nitrogen cutting or other suitable shape. The contact surname stop layer 312 may be formed of nitride rock, oxynitride, or other suitable material. The interlayer dielectric layer 314 may include a post-oxidation gate formed by a high aspect ratio process and/or a high-density plasma deposition process, and the wire lines form a dummy gate such as a polycrystalline dream material dummy gate. The pole structure (not shown) can then be followed by process techniques until deposition of the dielectric layer 314 is completed. Then, the % chemical mechanical polishing (CMp) is applied to the interlayer = f 314 to extract the pseudo-closed junction. This pseudo-closed pole structure can then be removed to form an opening.疋 503-A34608TWF/shawnchang 9 201123448 It is understood that the above examples are not intended to limit the I steps for forming a dummy gate structure. It will be understood that the above-described dummy gate structure may include an additional dielectric layer and/or Guide the mine to keep the electric nozzle. For example, the dummy gate structure can include a hard mask layer, an intermediate layer, and a setting. Upper layer, diffusion/barrier layer, other suitable film layers and/or combinations thereof. Referring to FIG. 3A, a gate dielectric layer 324 is deposited, and the port P is filled in the opening π to form a trench 325. In the embodiment, the gate dielectric layer 324 may include a vaporized germanium, a tantalum nitride, a germanium dielectric constant dielectric layer or a group thereof. The n-n dielectric layer may include oxidation. (Hf02), oxidation to Shixi (HfSiQ), nitrogen to _ (Hfsi〇N), oxidation button (H-tin, oxidation to Qin (HfTl0), bismuth oxide (HfZrO), metal oxides, metal nitrides Metal halides, transition metal oxides, transition metal nitrides, transition metal fragments, metal oxynitrides, metai aluminates, zirconium silicates, zirconium aluminates , nitrite, II oxidized oxide, zirconium oxide, titanium oxide, oxidized, oxidized-oxidized (Hf02-Al2〇3) alloy, other suitable high dielectric constant materials and/or In some embodiments, the high-k dielectric material within the opening has a thickness of less than 2 nm. The gate dielectric layer 324 may further include an intermediate layer 322 to reduce the gate dielectric layer 324 and the semiconductor. The damage between the substrates 302. The intermediate layer 322 may include tantalum nitride, nitrogen oxide , bismuth oxynitride, Hf silicate or oxidized dielectric material (Al2 〇 3 based dielectric). Generally, the trench 325 is followed by a plurality of metal layers, and a metal pattern can be applied. The process is performed to form a suitable metal film layer in the field effect transistor. A chemical mechanical polishing (CMP) can be performed to remove a plurality of metal layers outside the trench 0503-A34608TWF/shawnchang 201123448 325 and form a field effect. The multi-layer metal gate electrode 120a of the transistor 100. Alternatively, a dry etching or wet etching process may be performed. It can be observed that the multi-layer metal gate electrode 120a of the field effect transistor 100 has a lower The metal layer 128 of the resistance value occupies only a small portion of the region of the multi-layer metal gate electrode 120a, thus causing the multi-layer metal gate electrode 120a to have a high gate resistance value. This will increase the resistance of the integrated circuit. RC delay and degraded device performance. Thus, the modified multi-φ film metal gate electrode 120a is illustrated in FIGS. 2 and 3B-3H to form a gate structure 320, thereby reducing its gate resistance. value Lower than a power value. This can reduce the resistance delay of the integrated circuit and improve the performance of the component. Referring to Figures 2 and 3B, the method 200 then proceeds to step 204 to the first metal having the first recess 326a. Material 326 is deposited and partially filled into trenches 325. First metal material 326 includes a material selected from the group consisting of Ti, Ta, W, TiAl, Co, alloys thereof and their compound metals including C and/or N. The first metal material 326 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable technique. The first metal material 326 has a first resistance value. The first metal material 326 has a thickness of between 30 and 150 angstroms. The first metallic material 326 can include a stacked film layer of one of the work function metals. In one embodiment, the first metal material 326 for an NMOS may include Ti, Ta, TiA, or a compound including a work function metal such as C and/or N. In another embodiment, the first metal material 326 for a PMOS may comprise Ti, Ta, Co, alloys thereof, or work function metals including C and/or N. In some embodiments, the stacked film layer may include a barrier metal 0503-A34608TWF/shawnchang 11 201123448 layer, a liner metal layer or a wetting metal layer. Referring to Figures 2 and 3C, method 200 proceeds to step 206 by depositing a sacrificial layer 327 over first metal material 326 to fill first recess 326a and trench 325. The sacrificial layer 327 may comprise a polysilicon, photoresist or spin-coated dielectric layer, but is also limited to the materials described above. The sacrificial layer 327 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin coating, or other suitable technique. The thickness of the sacrificial layer 327 is determined by the depth of the first recess 326a and the groove 325. As such, the sacrificial layer 327 is deposited until the first recess 326a and the trench 325 are substantially filled. Referring to FIGS. 2 and 3D, the method 200 proceeds to step 208 to perform a chemical mechanical polishing (CMP) process to remove the sacrificial layer 327, the first metal material 326 and the gate dielectric layer 324 outside the trench 325. One part. As such, the CMP process will stop when it reaches the interlayer dielectric layer 314 and thus provide a generally flat surface. Alternatively, the above removal can also be achieved by a dry etch and/or wet etch process. Referring to FIGS. 2 and 3E, the method 200 then proceeds to step 210 to remove an upper portion of the first metal material 326 via an etching process to form a second recess 326b of the first metal material 326. The etching process can include a dry etch process and or a wet etch process. For example, the wet etch chemistry can include SC-1 or SPM, and may have an oxidant such as H202, and is applied at a temperature below 70 °C to selectively remove the upper portion of the first metal material 326. For example, the etch chemistry used in dry etching can include BC 13 to selectively remove the upper portion of the first metal material 0503-A34608TWF/shawnchang 12 201123448 326. The etch process forms a second recess 326b in the first metal material 326 of the trench 325. The second recess 326b of the first metal material 326 located in the trench 325 can have a depth of between about 50 and 2700 angstroms. This depth can be achieved by adjusting different parameters of the etch process, such as time and etch chemistry. Furthermore, the sacrificial layer 327 may not be used as a protective layer in the etching process unless the removal rate is not large enough. In one embodiment, the ratio of the removal rate of the etch chemistry to the first metal material 326 and the sacrificial layer 327 is preferably greater than 10. Moreover, when the gate dielectric layer 324 is destroyed by the residual chemical, it will become a defect source in the subsequent process and thereby increase the possibility of leakage current. In one embodiment, the ratio of removal rates of the etch chemistry to the first metal material 326 and the gate dielectric material 324 is preferably greater than 20. In the present embodiment, the remaining portion of the first metal material 326 located in the trench 327 forms a lower portion of the modified metal gate 320a. This lower part is generally U-shaped. Referring to FIGS. 2 and 3F, the method 200 then proceeds to step 212 to remove the sacrificial layer 327 remaining in the trench 325 via another etching process to expose the first recess 326a of the first metal material 326. . And the etching process may include a dry etching process and/or a wet etching process. For example, the etch chemistry used to selectively remove dry/wet etch of sacrificial layer 327 remaining in trench 325 may include F, C1, and Br based chemistries. When the first metal material 326 adjacent to the first recess 326a is eroded by the etch chemistry, the work function of the metal will be altered and, in turn, the likelihood of device failure will increase. In one embodiment, the ratio of removal rate of the etchant to the sacrificial layer 327 and the first metal material 326 is preferably 0503-A34608TWF/shawnchang 13 201123448 at ίο. Referring to FIG. 2 and FIG. 3G FIG. 214, a second metal material 328 is deposited; and the step is rotated to fill the first recess 326 of the first metal material 326. The first recess 3 and the second recess of the first metal material are hereinafter referred to as the barrier layer 325, and the barrier layer is formed by the "metal" material, thereby forming the barrier layer by the "Ti'Ta'TiN. , TaN__ into a private group of materials. The thickness of the barrier layer can be 50 angstroms by CVD, PVD, and ALD5. In the barrier layer embodiment, the barrier layer is formed due to the barrier acoustics. The barrier layer also has a south resistance value. Therefore, no resistance is used. Continuing to refer to Fig. 2 and the second diagram, a second metal material 328 is deposited on top to fill the upper portion of the trench 325. In this embodiment, the second metal material 328 may comprise a material selected from the group consisting of AH C 〇 and W. The second metallic material may be formed by =D, PVD, electroplating, spin coating, atomic layer deposition, or the like. The second metal material 328 has a second resistance value. The second resistance value is lower than the first resistance value. For example, the resistance value of A1 (: 2.65 from 〇.) is less than 1^ (about 20 (^ 〇,)). The thickness of the second metal material 328 can be according to the depth of the upper portion of the trench 325: Thus, the second metal material 328 is deposited until it substantially fills the upper portion of the trench 325. 3 Refer to Figures 2 and 3H, and then proceed to step 0503-A34608TWF/shawnchang 14 201123448 216' to implement a chemical machine The outer second metal material 32:: removes the leaves located in the trench 325. Thus, the cMp program dielectric layer 314 will stop, due to the arrival of the layers

程序施行之後，位於溝槽325 ；^=Γ。於CMP 剩餘部份形成了經修正金屬閘極電極伽 金屬材料328可包括延伸進入第一金屬材料326之^ 凹口 326a内之-突出部通。第二金屬材料328更After the program is executed, it is located in the groove 325; ^=Γ. Forming the modified metal gate electrode galvanic material 328 over the remainder of the CMP can include a protrusion-through that extends into the recess 326a of the first metal material 326. Second metal material 328

^申進入於第-金屬材们26之第二凹口纖之一金屬 帶狀物328b，且第二金屬材料似此時大體為τ形。 經修正金屬閘極結構32〇a包括由具有第一凹口伽 與第-電阻值之第-金屬材料326所構成之下方部。此 下部大體為U形。可以理解較本發明並非以上述實施 例加以限定。下方部可為大體L形或其他形狀。此下方 部具有介於300〜2900埃之一最大高度326e。經修正金屬 閘極320a更包括由具有突出部328a延伸進入凹口 内以及第二電阻值之第二金屬材料328所構成之上方 部。此上方部可更包括金屬帶狀物328b且大體為τ形。 可以理解的是本發明並非為上述實施例而加以限定。上 方部可大體為L形或其他形狀。上方部具有介於5〇〜27〇〇 埃之一最小高度328c。此外，突出部328a延伸進入凹口 326a。第一電阻值係低於第一電阻值。與如第1圖所示 之習知金屬閘極電極120a相比較，此時於經修正金屬閘 極電極320a内具有較低電阻值之上方部328具有較大區 域比例。如此’經修正金屬閘極電極較習知金屬閘極電 極120a具有較低之閘極電阻值。如此之較低閘極電阻值 0503-A34608TWF/shawnchang 15 201123448 可降低電路之阻容延遲以及提升裝置之表現。 可以理解的是場效應電晶體300可更藉由其他 CMOS製造流程的實施，以形成如接觸物/介層物、内連 金屬層、介電層、保護層等多個構件。可以觀察到的是 採用經修正金屬閘極電極320a作為閘極接觸材料可降低 了 NMOS與PMOS之閘極電阻值。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此項技藝者，在不脫離本發明 之精神和範圍内，當可作更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 0503-A34608TWF/shawnchang 16 201123448 【圖式簡單說明】 顯示了用於場效應電晶體之 第1圖為一剖面圖 習知閘極結構； 第2圖為一流程圖，顯示了依 例之閘極結構之製造方法；以及 ^之不同實施 -第3A-3H圖為一系列剖面圖，顯示了㈣如第 之情形。 I U中之閘極結構於不同製程階段中The metal material 328b enters the second recessed fiber of the first metal member 26, and the second metal material is substantially Tau-shaped at this time. The modified metal gate structure 32A includes a lower portion composed of a first metal material 326 having a first notch gamma and a first resistance value. This lower part is generally U-shaped. It will be understood that the present invention is not limited by the above embodiments. The lower portion can be generally L-shaped or otherwise shaped. The lower portion has a maximum height 326e of between 300 and 2900 angstroms. The modified metal gate 320a further includes an upper portion formed by a second metal material 328 having a protrusion 328a extending into the recess and a second resistance value. This upper portion may further include a metal strip 328b and is generally in the shape of a τ. It is to be understood that the invention is not limited to the embodiments described above. The upper portion can be generally L-shaped or otherwise shaped. The upper portion has a minimum height 328c of between 5 〇 and 27 〇〇 angstroms. In addition, the projection 328a extends into the recess 326a. The first resistance value is lower than the first resistance value. The upper portion 328 having a lower resistance value in the modified metal gate electrode 320a at this time has a larger area ratio than the conventional metal gate electrode 120a as shown in Fig. 1. Thus, the modified metal gate electrode has a lower gate resistance value than the conventional metal gate electrode 120a. Such a lower gate resistance value of 0503-A34608TWF/shawnchang 15 201123448 can reduce the resistance delay of the circuit and the performance of the lifting device. It will be appreciated that the field effect transistor 300 can be implemented by other CMOS fabrication processes to form a plurality of components such as contacts/interlayers, interconnect metal layers, dielectric layers, protective layers, and the like. It can be observed that the use of the modified metal gate electrode 320a as the gate contact material reduces the gate resistance values of the NMOS and PMOS. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached. 0503-A34608TWF/shawnchang 16 201123448 [Simple diagram of the diagram] The first diagram for the field effect transistor is shown as a cross-sectional view of the conventional gate structure; the second diagram is a flow chart showing the gate of the example The manufacturing method of the structure; and the different implementations of the -3A-3H are a series of sectional views showing (4) as in the case of the first. The gate structure in I U is in different process stages

閘極電極120a ; 124〜閘極介電層； 128〜上方部； 【主要元件符號說明】 100〜場效應電晶體； 103〜主動區； 106〜源極/汲極區； 110〜閘極間隔物； 114〜層間介電層； 120a〜多膜層金屬 122〜中間層； 126〜下方部； 200〜方法； 1〇2〜基底； 1〇4〜隔離區； 108〜輕度摻雜區； 112〜接觸餘刻停止層； 120〜閘極結構； 202、204、206、208、210、212、214、216〜步驟 300〜場效應電晶體； 302〜半導體基底； 303〜主動區； 304〜隔離區； 3 06〜源極/汲極區； 308〜輕度摻雜源極/汲極區； 310〜閘極間隔物； 312〜接觸蝕刻停止層； 0503-A34608TWF/shawnchang 17 201123448 314〜層間介電層； 320〜閘極結構； 320a〜經修正金屬閘極電極； 322〜中間層； 325〜溝槽； 324〜閘極介電層； 326〜第一金屬材料； 326a〜第一金屬材料之第一凹口； 326b〜第一金屬材料之第二凹口； 326c〜下方部之最大高度； 327〜犧牲層； 328〜第二金屬材料； 328a〜第二金屬材料之突出部； 328b〜金屬帶狀物； 328c〜上方部之最小高度。 0503-A34608TWF/shawnchang 18Gate electrode 120a; 124~ gate dielectric layer; 128~upper part; [Main component symbol description] 100~ field effect transistor; 103~ active region; 106~ source/drain region; 110~ gate interval 114~ interlayer dielectric layer; 120a~multi-layer metal 122~ intermediate layer; 126~lower part; 200~ method; 1〇2~ substrate; 1〇4~ isolation region; 108~lightly doped region; 112~ contact residual stop layer; 120~ gate structure; 202, 204, 206, 208, 210, 212, 214, 216~ step 300~ field effect transistor; 302~ semiconductor substrate; 303~ active area; Isolation region; 3 06~source/drain region; 308~lightly doped source/drain region; 310~gate spacer; 312~contact etch stop layer; 0503-A34608TWF/shawnchang 17 201123448 314~ Dielectric layer; 320~ gate structure; 320a~ modified metal gate electrode; 322~ intermediate layer; 325~ trench; 324~ gate dielectric layer; 326~ first metal material; 326a~ first metal material a first notch; 326b~ a second recess of the first metal material; 326c~ the lowermost portion Large height; 327~ sacrificial layer; 328~ second metal material; 328a~ protrusion of second metal material; 328b~ metal strip; 328c~ minimum height of upper part. 0503-A34608TWF/shawnchang 18

Claims (1)

201123448 七申5月專利範圍：201123448 Seven patents May patent scope: .種用於場效應電晶體 由第一金屬材料形成之一 電随值；以及 之閘極電極，包括： 下方部’具有一凹口及一 ^第二金屬材料形成之—上方部，具有—突出部以 妨楚_ +電阻值’其中该突出部延伸進人該凹口内，且 該第-電阻值低於該第一電阻值。a gate electrode for forming a field effect transistor with a first metal material; and a gate electrode comprising: a lower portion having a notch and a second metal material forming an upper portion having - The protrusion has a resistance value of + wherein the protrusion extends into the recess, and the first resistance value is lower than the first resistance value. 夕申，專利範圍第1項所述之用於場效應電晶體 之問極電極，其中該下方部為大體U形。 夕= U利範31第1項所述之用於場效應電晶體 ^電極’其中該下方部具有介於300〜29G0埃之最大 尚度。 夕如申請專利範圍第1項所述之用於場效應電晶體 W:T·电極’其中該第-金屬材料包括擇自自Ti、Ta、 1 C〇、其合金與其包括C及/或n之化合物金屬 所組成族群之一材料。 5.如申請專利_第丨項所述之用於場效應電晶體 =電極’其中該第一金屬材料為包括功函數金屬之 一膜層。 ^如巾凊專利範圍第丨項所述之用於場效應電晶體 之間極電極，其中該上方部為大體丁形。 」.如申請專利範圍第1韻述之祕場效應電晶體 之:玉電極’其中该上方部具有介於50〜2700埃之-最 8.如申請專利範圍第1項所述之用於場效應電晶體 050j-A34608TWF/shawnchang 201123448 之間極電極，其中該第二金屬材料包括擇自由A卜Cu、 Co與W所組成族群之一材料。 9‘ ”請專利_第8項所述之㈣場 群之一材料 10. — 之間極電極，其中該第二金屬材料更包括一阻障層，： =^包括擇自由 Ti、Ta、TiN、T_WN__ :場效應電晶體，包括 一基底，包括一主動區 勺衽：=結構’設置於該基底之上，其中該間極結構 二電層與—閘極電極，其中該閘極電極包括 :::-金屬材料所構成且具有一凹口與第一電阻值之 ;與-第P::第ST構成且具有一突出 咳凹口且㈣ 上方和其中該突出部延伸進入 且該第二電阻值係低於該第一電阻值；以及 主動=個源極/祕區，位於該閘極結構之相對側之該 I中兮巾，專利範圍第1G項所述之場效應電晶體， 八肀該下方部為大體ϋ形。 直中，如申凊專㈣圍第1G項所述之場效應電晶體， ’、「下方部具有介於3〇〇〜29〇〇埃之—最大高度。 1中兮笛如申°月專利_第1G項所述之場效應電晶體， 金屬材料包括擇自由Ti、Ta、w、TiAi、c〇、 材i。〜、其包括c及/*N之化合物金屬所組成族群之- 如申δ月專利乾圍f 10項所述之場效應電晶體， 〇5〇3-A346〇8TWF/shawnchang 20 201123448 其中該第—金屬材料為包括功函數金屬之一膜層。 如申請專利範圍第15項所述之場效應曰電晶體， ’、。玄膜層包括一上蓋層，而該上蓋層包括擇自由TiN、 Ta、TaN與WN所組成族群之一材料。 I6·如申請專利範圍第10項所述之場效應電晶體， 其中該上方部為大體T形。 17.如申睛專利範圍第10項所述之場效應電晶體， /、中該上方部具有介於50〜2700埃之一最小高度。Xishen, the problem electrode of the field effect transistor described in claim 1, wherein the lower portion is substantially U-shaped.夕 = U Lifan 31 Item 1 for field effect transistor ^electrode' wherein the lower portion has a maximum of 300 to 29 G0 angstroms. The invention relates to a field effect transistor W:T·electrode as described in claim 1 wherein the first metal material comprises from Ti, Ta, 1 C〇, an alloy thereof and C and/or thereof. A material of a group consisting of the compound metal of n. 5. The field effect transistor=electrode as described in the application of the above-mentioned patent, wherein the first metal material is a film layer comprising a work function metal. For use in the field electrode between the field effect transistors, as described in the scope of the patent specification, wherein the upper portion is substantially butyl. For example, the secret field effect transistor of the first aspect of the patent application scope: the jade electrode 'where the upper portion has a range of 50 to 2700 angstroms - the highest 8. For the field described in the first item of the patent application scope The electrode of the effect transistor 050j-A34608TWF/shawnchang 201123448, wherein the second metal material comprises a material selected from the group consisting of Cu, Co and W. 9' ” Patent _ Item 8 (4) One of the field groups of materials 10. The electrode between the electrodes, wherein the second metal material further comprises a barrier layer, : = ^ includes optional Ti, Ta, TiN , T_WN__: field effect transistor, comprising a substrate comprising an active region scoop: = structure 'on top of the substrate, wherein the interpolar structure two electrical layer and the gate electrode, wherein the gate electrode comprises: ::- metal material and having a notch and a first resistance value; and - P:: ST composition and having a protruding cough notch and (d) above and wherein the protrusion extends into and the second resistance The value is lower than the first resistance value; and the active = one source/secret region, the I in the opposite side of the gate structure, the field effect transistor described in the patent scope 1G, gossip The lower part is generally ϋ. Straight center, such as the field effect transistor described in item 1G of the application (4), ', 'the lower part has a maximum height of 3〇〇~29〇〇. 1 The field effect transistor described in the patent of the 1st GG, the metal material includes the free Ti Ta, w, TiAi, c〇, material i.~, which includes the group of compound metals of c and /*N - such as the field effect transistor described in the patent of δ月月干干围f10, 〇5〇 3-A346〇8TWF/shawnchang 20 201123448 wherein the first metal material is a film layer including a work function metal. The field effect germanium transistor according to claim 15 of the patent application, ', the Xuan film layer includes an upper cover And the upper cap layer comprises a field effect transistor according to claim 10, wherein the upper portion is substantially T-shaped. The field effect transistor according to claim 10, wherein the upper portion has a minimum height of 50 to 2700 angstroms. 農j8.如申請專利範圍第10項所述之場效應電晶體， 其中該第二金屬材料包括擇自由A卜Cu、Co與W所組 成方矢群之一材料。 1 19.如申請專利範圍第18項所述之場效應電晶體， 八中該第一金屬材料更包括一阻障層，而該阻障層包括 擇自由Ti、Ta、TiN、TaN與WN所組成族群之一材料。 20.如申請專利範圍第1〇項所述之場效應電晶體， 八中該閘極介電層包括一高介電常數介電層。 21 〇5〇3-A346〇8TWF/shawnchangThe field effect transistor according to claim 10, wherein the second metal material comprises a material selected from the group consisting of A, Cu, Co and W. 1 19. The field effect transistor according to claim 18, wherein the first metal material further comprises a barrier layer, and the barrier layer comprises Ti, Ta, TiN, TaN and WN. One of the constituent materials. 20. The field effect transistor of claim 1, wherein the gate dielectric layer comprises a high dielectric constant dielectric layer. 21 〇5〇3-A346〇8TWF/shawnchang
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US8779530B2 (en) 2014-07-15
CN102104061A (en) 2011-06-22

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