JP2001267561A - Method of manufacturing for semiconductor device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device, where damages to the substrate layer of an electrode can be prevented and the number of processes can be reduced, and to provide a semiconductor device. SOLUTION: A first insulating film 6, having a trench pattern 6a provided with a sidewall 4, is formed on a substrate 1. A metallic material layer 8, which has a recessed part along the inner wall of the trench pattern 6a, is formed. After the inside of the recessed part of the metal material layer 8 is filled with a second insulating film 9, a first insulating film 6 is exposed through planarization. The upper part of the metal material layer 8 in a trench pattern 6a is eliminated, the metallic material layer 8 is dug, and a gate electrode 8a constituted of the metal material layer 8, whose section has a recessed shape is formed in a bottom part of the trench pattern 6a. After a stopper layer 10 is embedded in the trench pattern 6a in the upper part of the gate electrode 8a, the first insulating film 6 and the second insulating film 9 are removed by etching, using the stopper layer 10 and the sidewall 4 as stoppers, and connection holes 12a, 12b which reach the substrate 1 and the gate electrode 8a, respectively, are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device, and more particularly to a method of manufacturing a semiconductor device including a process of manufacturing a damascene gate transistor and a semiconductor device formed by the method.

[0002]

2. Description of the Related Art As semiconductor devices become more highly integrated and highly functional, finer device structures are required. In order to achieve this, it is necessary to use a metal wiring to prevent the wiring to be thinned from having a high resistance. For example, a semiconductor device using a damascene gate process shown in FIG. 11 is manufactured.

In this method, first, as shown in FIG. 11A, a dummy gate electrode 103 is formed on a substrate 101 via a dummy gate insulating film 102, and sidewalls 104 made of silicon nitride are formed on these side walls. To form
After that, the dummy gate electrode 103 and the side wall 1
A source / drain (not shown) is formed on the surface layer of the substrate 1 by performing ion implantation and heat treatment using the mask 04 as a mask. Next, the dummy gate electrode 103 and the side wall 104 are buried with the first insulating film 106, and this is flattened. Next, as shown in FIG. 11B, by removing the dummy gate electrode (103) and the dummy gate insulating film (102), a groove pattern 106a having a sidewall 104 in the first insulating film 106 is formed. I do.

After that, as shown in FIG. 11C, the gate insulating film 10 is covered with the inner wall of the groove pattern 106a.
After the formation of 7, the metal material layer 108 is formed so as to fill the groove pattern 106a, and the metal material layer 108 and the gate insulating film 107 are planarized and polished until the first insulating film 106 is exposed.

Next, as shown in FIG. 11D, a so-called recess step is performed in which the metal material layer 108 and the gate insulating film 107 above the groove pattern 106a are etched away and dug down to form an electrode made of the metal material layer 108. 108a
To form Thereafter, as shown in FIG. 11E, a silicon nitride film 109 is buried in the recess, and the second insulating film 1 is formed on the silicon nitride film 109 and the first insulating film 106.
After forming 10, the first insulating film 106 and the second insulating film 110 are etched using the silicon nitride film 109 and the sidewalls 104 as stoppers to form connection holes 111 reaching the substrate 101. Next, as shown in FIG. 11F, the second insulating film 110 and the silicon nitride film 109 are etched to form a connection hole 112 reaching the gate electrode 108a.
To form

According to the above method, when forming the connection hole 111 reaching the substrate 101, the silicon nitride film 109 is formed.
And the sidewall 104 serves as a stopper. For this reason, the alignment margin of the mask used at the time of etching can be increased, and the connection hole 1 is self-aligned.
11 can be formed. At this time, the shoulder of the gate electrode 108a can be protected by the silicon nitride film 109 and the sidewall 104.

[0007]

However, in such a method of manufacturing a semiconductor device, as described with reference to FIG. 11E, when the connection hole 111 reaching the substrate 101 is formed, the silicon nitride film 109 is formed. And sidewall 104
Is used as a stopper at the time of etching. Therefore, in this step, etching for forming the connection hole 112 reaching the gate electrode 108a cannot be performed at the same time. Therefore, in order to form the connection hole 112 reaching the gate electrode 108a, it is necessary to form a new etching mask and etch the silicon nitride film 109.

In the step described with reference to FIG. 11C, a metal material layer 108 is formed in a state where the inside of the groove pattern 106a is buried. For this reason, FIG.
As shown in FIG. 3, the metal material layer 10 in the groove pattern 106a
At 8, a seam (that is, a joint of the metal material layers 108) A is formed.

Therefore, as shown in FIG. 12D ', in the recess step of etching and digging down the metal material layer 108, the etching easily proceeds at the seam A portion. When the etching of the seam A portion progresses and the seam A expands, the etching reaches the gate insulating film 107 below the gate electrode 108a, and the gate insulating film 107 is damaged. For this reason, the reliability of the gate insulating film 107 decreases, and desired transistor characteristics cannot be obtained.

Therefore, the present invention can reduce the number of steps by simultaneously forming each connection hole reaching the substrate and the electrode while protecting the shoulder of the electrode while preventing damage to the underlying layer of the electrode. It is an object of the present invention to provide a method for manufacturing a semiconductor device and a semiconductor device which are possible.

[0011]

According to a method of manufacturing a semiconductor device of the present invention for achieving the above object, first, a first insulating film having a groove pattern having a sidewall is formed on a substrate. A metal material layer having a concave portion along the inner wall of the groove pattern is formed on the first insulating film. Next, after filling the concave portion of the metal material layer with the second insulating film, the second insulating film and the metal material layer are flattened to expose the first insulating film. Next, an upper portion of the metal material layer in the groove pattern is selectively removed with respect to the first insulating film and the second insulating film and dug down to form an electrode made of a metal material layer having a concave cross section at the bottom in the groove pattern. I do. Then, after the stopper layer is embedded in the groove pattern above the electrode, the first insulating film and the second insulating film are removed by etching using the stopper layer and the sidewalls as stoppers, whereby each connection reaching the substrate and the electrode, respectively. Form a hole.

According to such a manufacturing method, an electrode is formed by digging the metal material layer after embedding the second insulating film in the concave portion of the metal material layer along the inner wall of the groove pattern. By forming the stopper layer, the stopper layer is provided only on the upper ends on both sides of the electrode having a concave cross section. Therefore, the bottom surface in the concave portion of the electrode is not covered with the stopper layer. Therefore, each connection hole reaching the electrode and the substrate is formed by the same etching process while protecting the shoulder of the electrode using the stopper layer and the sidewall as stoppers.

Further, since the metal material layer is formed so as to have a concave portion along the inner wall of the groove pattern, no seam is formed in the metal material layer. For this reason, in the etching when the metal material layer is dug down, the influence of the etching on the base of the electrode due to the expansion of the seam is prevented.

Further, the semiconductor device of the present invention is a semiconductor device formed by such a manufacturing method, and includes an electrode provided on a substrate in a concave cross section having a groove on an upper portion, and both sides of the electrode. A stopper layer provided on the upper end,
A sidewall provided on the outer wall of the stopper layer and the electrode, an insulating film formed on the substrate in a state of covering these, a connection hole formed in the insulating film using the stopper layer and the sidewall as a stopper. Have. These connection holes are provided so as to reach the bottom surface in the concave portion of the electrode and the substrate, respectively.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a method for manufacturing a semiconductor device according to the present invention and a semiconductor device formed by this manufacturing method will be described below in detail with reference to the drawings.

(First Embodiment) A first embodiment of the present invention will be described with reference to FIG. Here, M
An embodiment in the case of forming an OS transistor will be described.

First, as shown in FIG. 1A, a dummy gate electrode 3 is patterned on a substrate 1 with a dummy gate insulating film 2 interposed therebetween, and sidewalls 4 made of silicon nitride are formed on these side walls. . Thereafter, ion implantation and heat treatment are performed using the dummy gate electrode 3 and the side wall 4 as a mask, so that the source / drain 5
To form When an LDD portion is provided in the source / drain 5, ion implantation using the dummy gate electrode 3 as a mask is performed before forming the sidewall 4.

Next, with the dummy gate electrode 3 and the side wall 4 buried, a first silicon oxide
The surface of the dummy gate electrode 3 and the side wall 4 is exposed by forming the insulating film 6 and polishing and flattening it.

Next, as shown in FIG. 1B, by removing the dummy gate electrode (3) and the dummy gate insulating film (2), a groove pattern 6a is formed in the first insulating film 6, and the groove pattern is formed. The substrate 1 is exposed on the bottom of the pattern 6a. Thus, the first insulating film 6 having the groove pattern 6a having the sidewall 4 is formed on the substrate 1.

Thereafter, as shown in FIG. 1C, the gate insulating film 7 is formed on the first insulating film 6 while covering the inner wall of the groove pattern 6a (that is, the substrate 1 and the side wall 4 at the bottom of the groove pattern 6a). Is formed, a metal material layer 8 having a concave portion along the inner wall of the groove pattern 6a is formed on the gate insulating film 7. At this time, the groove pattern 6 is formed by the metal material layer 8.
The thickness of the metal material layer 8 is set such that a recess is formed in the metal material layer 8 without filling the inside of the metal material layer 8.

Next, a second insulating film 9 made of silicon oxide is formed so as to fill the recesses of the metal material layer 8.
Thereafter, the second insulating film 9, the metal material layer 8, and the gate insulating film 7 on the first insulating film 6 are polished and removed by a flattening method such as a CMP (Chemical Mechanical Polishing) method, and the inside of the groove pattern 6a is removed. The first insulating film 6 is exposed except for the second insulating film 9, the metal material layer 8, and the gate insulating film 7.

Next, as shown in FIG. 1D, the metal material layer 8 is selectively etched with respect to the first insulating film 6, the second insulating film 9, and the side wall 4, thereby forming the inside of the groove pattern 6a. A recess step of removing and digging out the upper metal material layer 8 is performed. As a result, a gate electrode 8a made of the metal material layer 8 having a concave cross section is formed at the bottom in the groove pattern 6a. At this time, the gate insulating film 7 may remain without being dug depending on the material.

Thereafter, as shown in FIG. 1E, a stopper layer 10 made of silicon nitride is buried in the groove pattern 6a above the gate electrode 8a. Next, the third insulating film 11 is formed above the first insulating film 6 so as to cover them.
To form

Next, a resist pattern (not shown) is formed on the third insulating film 11, and this resist pattern is used as a mask, and the stopper layer 10 made of silicon nitride and the sidewalls 4 are used as stoppers. Then, the third insulating film 11, the first insulating film 6, and the second insulating film 9 are etched to form a connection hole 12a reaching the source / drain 5 on the surface of the substrate 1 and a connection hole 12b reaching the gate electrode 8a. Are simultaneously formed.

After the above, although not shown here, by forming a wiring connected to the source / drain 5 and the gate electrode 8a through the respective connection holes 12a and 12b, M
The OS transistor is completed.

According to the manufacturing method described above, the gate electrode 8a is formed by digging the metal material layer 8 after filling the recess of the metal material layer 8 along the inner wall of the groove pattern 6a with the second insulating film 9. By forming the stopper layer 10 above the gate electrode 8a, the gate electrode 8 having a concave cross section is formed.
The stopper layer 10 is provided only on the upper end portions on both sides of “a”. Therefore, the bottom surface in the concave portion of the gate electrode 8a is not covered with the stopper layer 10. Therefore, the connection holes 12a and 12b reaching the gate electrode 8a and the substrate 1, respectively, can be formed by the same etching process while protecting the shoulder of the gate electrode 8a using the stopper layer 10 and the sidewalls 4 as stoppers. Will be possible.

As a result, the number of steps of forming a resist pattern serving as a mask at the time of etching can be reduced as compared with the case where the respective connection holes 12a and 12b are formed in separate steps, and the manufacturing steps of the semiconductor device can be simplified. It becomes possible to do.

Moreover, since the metal material layer 8 is formed such that a concave portion is formed along the inner wall of the groove pattern 6a, no seam is formed in the metal material layer 8. Therefore, the etching resistance of the metal material layer 8 is improved, and the influence of the etching on the underlying gate insulating film 7 in the etching at the time of the recess step of digging the metal material layer 8 to form the gate electrode 8a is reduced. Can be prevented. Therefore, the reliability of the gate insulating film 7 can be ensured, and a semiconductor device having desired characteristics can be obtained.

(Second Embodiment) FIGS. 2 to 10 show the present invention.
FIG. 9 is a sectional process view of a second embodiment applied to a DRAM in LOGIC process.
0 is formed in the memory area 20a of the peripheral area 2a.
A method for forming a logic circuit and other peripheral circuits at 0b will be described.

First, as shown in FIG. 2A, an element isolation region 21 is formed on the surface side of a substrate 20 made of silicon, and then, an ion separation region 21 is formed on the surface side of the substrate 20 separated by the element isolation region 21. A P-well layer 22 and an N-well layer 23 are formed by diffusing impurities by an implantation method. At this time, for example, in the memory region 20a, the P well layer 22 is provided on the surface layer of the N well layer 23, and in the peripheral region 20b, the P well layer 22 and the N well layer 23 are provided independently.

Thereafter, a dummy gate insulating film 24 is formed on the surface of the substrate 20 separated by the element isolation region 21.
At this time, the dummy gate insulating films 24 having different profiles may be formed in the memory region 20a and the peripheral region 20b.

Next, as shown in FIG.
A dummy gate electrode 25 made of polysilicon is formed thereon via a dummy gate insulating film 24. At this time, a polysilicon film containing no impurities (or a non-crystalline silicon film) having a thickness of 150 nm is formed on the substrate 20, and a silicon oxide film (not shown) is further formed on the polysilicon film as necessary. After the formation, the dummy gate electrode 25 is formed by patterning the silicon oxide film and the polysilicon film. Further, if necessary, the gate end of the dummy gate electrode 25 is oxidized.

Thereafter, as shown in FIG. 3C, the diffusion layer 26 of a desired conductivity type is formed in a predetermined region by ion implantation using the dummy gate electrode 25 and a resist pattern (not shown) as a mask. 27 are formed. For example, phosphorus (P) is introduced into the memory region 20a to form the n-type diffusion layer 26. Further, an n-type diffusion layer 26 is formed on the surface layer of the P well 22 layer in the peripheral region 20b, and a p-type diffusion layer 27 is formed on the surface layer of the N well layer 23. In the memory region 20a, these n-type diffusion layers 26 become source / drain (S / D) 26. In the logic circuit in the peripheral region 20b, these n-type diffusion layers 26 and p-type diffusion layers 2
7 is the so-called LDD (Lightly Doped Drain) extensio
It becomes n. Note that a heat treatment for suppressing the accelerated diffusion due to defects is performed during the series of these steps.

Next, as shown in FIG. 3D, a silicon nitride film 28 having a predetermined thickness is formed on the substrate 20 so as to cover the dummy gate electrode 25. Here, the thickness of the silicon nitride film 28 is about 50 nm, and the above-mentioned LDD width is determined by this thickness.

Next, as shown in FIG. 4E, while the memory region 20a is covered with a resist mask (not shown), the silicon nitride film 28 in the peripheral region 20b is anisotropically etched to form a dummy gate electrode 25. A sidewall spacer (hereinafter, referred to as a sidewall) 28a leaving the silicon nitride film 28 only on the side wall of is formed. The anisotropic etching here is performed using, for example, a parallel plate type etching apparatus and using an etching gas such as methane tetrafluoride (CF4) or methane trifluoride (CHF3).

At this time, since the substrate surface of the memory area 20a is protected, the substrate area of the memory area 20a is protected.
Good S / D without digging and etching damage (so-called sub-oxide formation and carbon hammering)
26 can be maintained, so that excellent data retention characteristics can be realized.

Next, S / Ds 29, 30 of a desired conductivity type are formed in a predetermined region in the peripheral region 20b by ion implantation using the resist mask, the dummy gate electrode 25, and the sidewalls 28a as masks. On this occasion,
Arsenic (As) ions are implanted into the surface layer of the P well layer 22 to form an n-type S / D 29, and boron (B) ions are implanted into the surface layer of the N well layer 23 to form a p-type S / D 30. Form. After the impurity ions are implanted, each S / D 29,
RTP (Rapid Thermal proc)
ess).

Next, using the SALICIDE technology,
Cobalt silicide (Co) is applied to the surface layer of S / D29,30.
A silicide layer 31 such as Si2) is formed by self-alignment. In the SALICIDE process, conditions that are normally performed can be applied as they are.
At this time, as described with reference to FIG. 2B, when the dummy gate electrode 25 is not covered with the silicon oxide film, a silicide layer is also formed on the surface layer of the dummy gate electrode 25. Will be done.

When a region in which a silicide layer is not formed is provided in addition to the memory region 20a, this region is also covered with the resist mask. by this,
For example, the electrostatic breakdown strength of these elements can be improved without forming a silicide layer in a region where a protection element of an input / output circuit, a high-resistance element, and the like are arranged.

Next, as shown in FIG.
CVD (high density plasma-chemical vapor deposi
The first insulating film 32 made of silicon oxide is deposited so as to bury the dummy gate electrode 25 by a low-temperature film forming process such as a method of forming a thin film or a spin on glass (SOG) coating method. Then, CMP (Chemical Mechanical Polishin)
g), the first insulating film 32 is polished,
The silicon nitride film 28 on the dummy gate electrode 25 in the memory region 20a is removed by (reactive ion etching) to expose the dummy gate electrode 25. At this time, if the salicide layer described above is present on the dummy gate electrode 25, this is also removed at the same time. Thus, the sidewall 28a made of silicon nitride is also formed on the dummy gate electrode 25 in the memory region 20a.

Thereafter, as shown in FIG. 5G, the dummy gate electrode (25) is removed by, for example, isotropic etching to form a groove pattern 33. Next, impurities may be introduced into the predetermined region from the bottom surface of the groove pattern 33 to the surface layer (that is, the channel region) of the substrate 20 as necessary. Thereby, the S / D diffusion layers 26, 29,
It is possible to reduce the junction capacitance by lowering the impurity concentration of the 30 junction.

Next, as shown in FIG. 5 (h), isotropic etching is performed in a state where the memory area 20a is covered and protected by a resist mask (not shown), and one of the dummy gate insulating films 24 in the peripheral area 20b is formed. Part or a fixed thickness.

Next, after removing the resist mask covering the memory region 20a, 1n of silicon nitride having a high dielectric property and a barrier property of silicon is removed by a CVD method or the like.
After forming with a film thickness of about m, tantalum oxide (Ta2O5)
The high dielectric film 35 made of a high dielectric material such as
It is formed with a film thickness of about. Incidentally, the high dielectric film 35 is shown as a line having no thickness.

As a result, a gate insulating film 36 composed of the dummy gate insulating film 24 and the high dielectric film 35 (and silicon nitride) is formed in the memory region 20a, and the high dielectric film 35 (and nitride) is formed in the peripheral region 20b. A gate insulating film 35 made of (silicon) is formed. And memory area 2
0a and the peripheral region 20b are provided with gate insulating films 35 and 35a having different thicknesses.

Here, the Ta 2 O 5 may be subjected to a heat treatment for guaranteeing oxidation defects, removing carbon, and further, for crystallization. However, this heat treatment is applied to the silicide layer 31.
Is performed at such a temperature as not to deteriorate the characteristics described above, and is preferably performed at a temperature lower than 600 ° C., for example.

Next, a metal material layer 37 is formed on the gate insulating films 35 and 35a along the inner wall of the groove pattern 33. here. The metal material layer 37 is formed in a shape having a recess along the inner wall of the groove pattern 33 without filling the inside of the groove pattern 33 with the metal material layer 37.
It is important to set the thickness of the metal material layer 37. However, depending on the pattern, the inside of the groove pattern 33 may be buried. For example, in a portion where the gate electrode has a minimum line width and no connection hole is formed on the gate electrode, such as a word line of a DRAM memory cell, The inside may be filled with a metal material layer 37. At least in the portion having the connection hole on the gate electrode, the groove pattern 33 is formed.
The inside is not filled with the metal material layer 37. Further, a film forming condition having different coverage depending on the width of the groove pattern 33 may be used.

The metal material layer 37 is made of, for example, tungsten (W), tungsten nitride (WN), ruthenium (R)
u), ruthenium oxide (RuO2), titanium nitride (Ti
N) or the like.

Next, as shown in FIG.
A second insulating film 38 made of silicon oxide is formed by a low-temperature film forming process such as a CVD method or an SOG coating method so as to fill the concave portions on the surface of the metal material layer 37; afterwards,
By the CMP method, the second insulating film 38 is polished and removed until the metal material layer 37 is exposed, and the metal material layer 37 and the high dielectric film 35 on the first insulating film 32 are polished and removed. Thus, the surface of the first insulating film 32 is exposed and the metal material layer 37 is separated.

Thereafter, as shown in FIG. 6 (j), the metal material layer 37 is selectively different from the first insulating film 32, the second insulating film 38 made of silicon oxide, and the sidewall 28a made of silicon nitride. Perform isotropic etching. As a result, the metal material layer 37 in the groove pattern 33 is dug down to a certain depth in the groove pattern 33 to form the gate electrode 37a.
To form At this time, the high dielectric film 35 may be dug down simultaneously with the metal material layer 37 or may be left.

Thereafter, a silicon nitride film is formed so as to cover the gate electrode 37a, and the silicon nitride film on the first insulating film 32 and the second insulating film 38 is removed by polishing or etching by the CMP method. Gate electrode 37
The silicon nitride film is left only in the dug portion on a.
Thereby, the stopper layer 40 made of silicon nitride is formed on both upper ends of the gate electrode 37a.

Next, as shown in FIG. 7K, a third insulating film 41 is formed so as to cover the first insulating film 32, the second insulating film 38, the stopper layer 40, and the sidewalls 28a. A connection hole 43 reaching the S / D 26 on the surface of the substrate 1 is formed in 20a.

At this time, first, a resist pattern not shown here is formed, this resist pattern is used as a mask, and the stopper layer 4 made of silicon nitride is used.
The third insulating film 41 and the first insulating film 32 made of silicon oxide are selectively etched using the 0 and the sidewall 28a as stoppers. For this etching, for example, 8
Fluorocyclobutane (C4 F8) / Carbon monoxide (CO)
/ Argon (Ar) / Oxygen (O2).

Thereafter, the bottom of the silicon nitride film 28 connected to the side wall 28a is etched using a gas system such as CHF 3 / CO, thereby forming the substrate 20.
Is formed.

Here, the gate electrode 3 is formed by the stopper layer 40 made of silicon nitride and the sidewall 28a.
Since the shoulder portion 7a is protected, the margin for positioning the resist pattern serving as an etching mask can be increased, and the connection hole 43 is formed in a self-aligned manner.

After the above, embedded in the connection hole 43,
/ D26 is formed.

Next, as shown in FIG. 7L, a fourth insulating film 46 made of silicon oxide is formed on the poly plug 44 and the third insulating film 41, and is formed on the fourth insulating film 46 in the memory region 20a. A connection hole 47 reaching the poly plug 44 is formed. Thereafter, titanium nitride (TiN) is formed on titanium (Ti).
A tungsten (W) film is formed on the adhesion layer on which is laminated, and a silicon nitride film is further formed. Then, these are patterned to form a bit line 48 with an offset made of silicon nitride. This bit line 48
Is formed so as to be connected to the poly plug 44 via the connection hole 47.

Next, a side wall 49 made of silicon nitride is formed on the side wall of the bit line 48.

After the above, as shown in FIG. 8 (m), a first interlayer insulating film 50 made of silicon oxide is formed so as to cover the bit line 48, and then a poly plug 44 is formed on the first interlayer insulating film 50. A connection hole 50a that reaches is formed. On this occasion,
Etching is performed using an offset made of silicon nitride covering the periphery of the bit line 48 and a sidewall as a stopper.

Next, a tungsten plug is formed in the connection hole 50a and used as a node contact 51. Thereafter, a second interlayer insulating film 52 made of silicon oxide is formed to a thickness of about 100 nm so as to cover the node contact 51.

Next, a connection hole 54 reaching the silicide layer 31 on the surface of the substrate 1 and a gate electrode 3 are formed in the peripheral region 20b.
A connection hole 55 reaching 7a is formed at the same time. Here, a resist pattern not shown here is formed on the second interlayer insulating film 52, and this resist pattern is used as a mask, and the stopper layer 40 made of silicon nitride and the sidewall 28a are used as stoppers. , Second interlayer insulating film 52, first interlayer insulating film 50, fourth insulating film 4
6, the third insulating film 41 and the first insulating film 32 or the second insulating film 38 are etched. Thus, a connection hole 54 reaching the silicide layer 31 on the surface of the substrate 20 and a connection hole 55 reaching the gate electrode 37a are formed simultaneously.

For this etching, for example, C4 F8 / C
A gas system such as O / Ar / O2 is used. At this time, since the gate electrode 37a is protected by the stopper layer 40 and the sidewall 28a made of silicon nitride, the resist pattern serving as an etching mask may be formed by rough alignment, and the connection holes 54 and 55 are formed in a self-aligned manner. And can be formed simultaneously.
At this time, the shoulder of the gate electrode 37a is
0 and are protected by the sidewalls 28a.

Next, a heat treatment is performed in a hydrogen atmosphere at a temperature of about 400 ° C.
5, a tungsten plug 56 using TiN as an adhesion layer is formed. At this time, a rapid thermal process (RTP) is performed at a high temperature of about 650 ° C. to densify the adhesion layer.
By this RTP, the interface with the poly plug 44 is silicided at the node contact 51 made of a tungsten plug formed in the memory region 20a, and a good connection is ensured. In addition, these heat treatment and RTP
Can be performed before the DRAM capacitor is formed in the memory region 20a, so that a process in which the capacitor is not exposed to a high-temperature hydrogen atmosphere can be realized.

After the above, a first wiring 57 connected to the tungsten plug 56 in the peripheral region 20b is formed on the second interlayer insulating film 52. The first wiring 57 is formed of TiN / Al-Cu (aluminum-copper) / TiN / T in order from the upper layer.
It is assumed that i = 50 nm / 400 nm / 20 nm / 20 nm is stacked. As described above, the connection holes 54 and 55 and the first wiring 57 can be formed before the step is formed by the DRAM capacitor.

Next, as shown in FIG. 9N, a third interlayer insulating film 58 made of silicon oxide is formed on the second interlayer insulating film 52 so as to cover the first wiring 57. Thereafter, a hole 58 reaching the node contact 51 of the memory region 20a
a is formed on the second interlayer insulating film 52 and the third interlayer insulating film 58, and a metal having excellent oxidation resistance such as WN or TiN, or a metal having an oxide such as Ru or iridium (Ir) exhibiting conductivity. 50n of the lower electrode layer 60 made of
m of the lower electrode layer 6 so as to cover the inner wall of the hole 58a and leave the lower electrode layer 60 only on the inner wall of the hole 58a.
Process 0. Here, after forming the lower electrode layer 60, a resist material or BPSG (boro phospho silicate) is formed.
glass) or SOG (spin on glass),
After the inside of the hole 58a is filled with a filling material that can be selectively removed from the third interlayer insulating film 58 made of silicon oxide, the lower electrode layer 60 on the third interlayer insulating film 58 is formed by performing CMP or etch back. Remove parts,
Thereby, the lower electrode layer 60 is processed. Lower electrode layer 6
After the processing of No. 0, the filling material layer is removed.

After the above, while covering the lower electrode layer 60,
A dielectric film 61 is formed. Here, Ta2 O5 is formed to a thickness of 10 nm as the dielectric film 61, and ozone (O3
) 400 ° C. while irradiating with ultraviolet light in an atmosphere
Anneal for about 10 minutes with Ta2O
5 is maintained in an amorphous state, the internal oxygen vacancies are eliminated, and the residual carbon is removed to form a good capacitor dielectric film 61.

Next, TiN or WN having a thickness of about 100 nm is deposited on the dielectric film 61, and if necessary, a hydrogen blocking layer such as Ti is deposited thereon, followed by patterning. By doing so, the cell plate 62
To form At this time, the dielectric film 61 is also patterned at the same time. Thus, a DRAM capacitor having the dielectric film 61 sandwiched between the lower electrode layer 60 and the cell plate 62 is formed.

Next, as shown in FIG. 10 (o), after a fourth interlayer insulating film 64 made of silicon oxide is formed on the third interlayer insulating film 58 so as to cover the cell plate 62, the memory region 20a and the periphery are formed. In the region 20b, the cell plate 6
A connection hole 65 reaching each of the second and first wirings 57 is formed. After that, plugs 66 are formed in the connection holes 65, and then a second wiring 67 connected to the plugs 66 is formed on the fourth interlayer insulating film 64.

The second wiring 67 is formed on a flat fourth interlayer insulating film 64 in which a step due to the DRAM capacitor can be ignored. Also, the formation of the first wiring 57 and the second wiring 67
To form a DRAM capacitor during the formation of
The depth of the connection hole 67 may be the same as the depth of the Logic process.

After the above, although illustration is omitted here, an interlayer insulating film, a connection hole, a plug, and a wiring are further formed as necessary to achieve a multilayer wiring.

As described above, a DRAM process having good consistency with the logic process is realized.

According to the manufacturing method of the second embodiment, as described with reference to FIGS. 5 (h) to 6 (j),
A metal material layer 37 having a recess along the inner wall of the groove pattern 33 is formed, and the recess is filled with a second insulating film 38, and then the metal material layer 37 is dug down to form a gate electrode 37a. Stopper layer 40 on top of
Is formed, the stopper layer 40 is provided only on the upper ends on both sides of the gate electrode 37a having a concave cross section. Therefore, the bottom surface in the recess of the gate electrode 37 a is not covered with the stopper layer 40. Therefore, in the step described with reference to FIG. 8M, as in the first embodiment, the stopper layer 40 and the sidewall 28a are used as stoppers to protect the shoulder of the gate electrode 37a, and the same etching step is used. The connection holes 54 and 55 reaching the gate electrode 37a and the substrate 20 (silicide layer 31), respectively, can be formed.

As a result, as in the first embodiment, the number of steps for forming a resist pattern serving as a mask at the time of etching can be reduced, and the manufacturing steps of a semiconductor device can be simplified.

Further, since the metal material layer 37 constituting the gate electrode 37a is formed so that a concave portion is formed along the inner wall of the groove pattern 33a, the gate insulating films 35a and 35a are formed as in the first embodiment. Reliability can be secured.

[0074]

As described above, according to the present invention, the stopper layer is provided only on the upper end portions on both sides of the electrode having the concave cross section, and the stopper layer and the sidewall are used as stoppers to form the shoulder portion of the gate electrode. While protecting the electrodes, it is possible to form each connection hole reaching the electrode and the substrate by the same etching process. Therefore, it is possible to reduce the number of mask forming steps for forming the connection holes to one, and to simplify the manufacturing steps of the semiconductor device. In addition, by forming the metal material layer forming the electrode into a shape having a concave portion along the inner wall of the groove pattern, the etching resistance of the metal material layer is improved, and the influence of the etching on the base of the electrode is reduced. Can be prevented. For this reason,
In forming a gate electrode, it is possible to ensure the reliability of a gate insulating film serving as a base. As a result, a semiconductor device having desired characteristics can be formed.

[Brief description of the drawings]

FIG. 1 is a sectional process view illustrating a first embodiment of the present invention.

FIG. 2 is a sectional process view (1) illustrating a second embodiment of the present invention.

FIG. 3 is a sectional process view (part 2) for explaining the second embodiment of the present invention;

FIG. 4 is a sectional process view (3) for explaining the second embodiment of the present invention.

FIG. 5 is a sectional process view (part 4) for explaining the second embodiment of the present invention.

FIG. 6 is a sectional process view (5) for explaining the second embodiment of the present invention.

FIG. 7 is a sectional process view (part 6) explaining the second embodiment of the present invention.

FIG. 8 is a sectional process view (7) for explaining the second embodiment of the present invention.

FIG. 9 is a sectional process view (8) for explaining the second embodiment of the present invention.

FIG. 10 is a sectional process view (No. 9) for explaining the second embodiment of the present invention.

FIG. 11 is a sectional process view illustrating a conventional technique.

FIG. 12 is a sectional process view for explaining a problem of the conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Dummy gate insulating film, 3 ... Dummy gate electrode, 4 ... Side wall, 6 ... First insulating film, 6a ... Groove pattern, 7 ... Gate insulating film, 8 ... Metal material layer, 8a ...
Gate electrode, 9: second insulating film, 10: stopper layer, 12
a, 12b: connection hole, 20: substrate, 24: dummy gate insulating film, 25: dummy gate electrode, 28a: sidewall, 32: first insulating film, 33: groove pattern, 35, 3
5a: gate insulating film, 37: metal material layer, 37a: gate electrode, 38: second insulating film, 40: stopper layer, 54,
55 ... connection hole

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/336 H01L 27/10 681F 29/62 G 29/78 301Y F term (Reference) 4M104 AA01 BB04 BB18 BB20 BB30 BB33 BB36 CC01 CC05 DD02 DD03 DD04 DD08 DD16 DD17 DD72 EE03 EE09 EE16 FF06 FF18 GG09 GG10 GG14 HH14 5F033 HH07 HH09 HH18 HH19 HH33 HH34 HH35 JJ18 JJ19 JJ33 KK25 Q13 Q18 NN13 RR04 RR06 RR09 SS15 SS21 TT08 VV06 VV16 XX15 XX31 5F040 DB03 DB09 DC01 EA08 EC04 EC19 EC26 ED01 ED02 ED03 ED04 ED09 EF02 EH02 EH08 EK05 FA01 FA02 FA07 FB02 FC10 FC19 FC21 FC22 JA27 KA20 MA03 MA06 MA17 MA19 MA20 PR03 PR06 PR10 PR12 PR18 PR23 PR29 PR34 PR38 PR40 PR43 PR44 PR45 PR46 PR53 PR54 P R55 PR56 ZA06 ZA07 ZA12

Claims (4)

[Claims] 1. A step of forming a first insulating film having a groove pattern having a side wall on a substrate, and forming a metal material layer having a concave portion along an inner wall of the groove pattern on the first insulating film. And filling the recesses of the metal material layer with a second insulating film.
Flattening the second insulating film and the metal material layer to expose the first insulating film; and selecting an upper portion of the metal material layer in the groove pattern with respect to the first insulating film and the second insulating film. Forming an electrode made of a metal material layer having a concave cross-section at the bottom of the groove pattern, and embedding a stopper layer in the groove pattern above the electrode, and then removing the stopper layer and Etching the first insulating film and the second insulating film by using the sidewalls as stoppers, thereby forming connection holes respectively reaching the substrate and the electrodes. Device manufacturing method. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the metal material layer, the metal material layer is formed via a gate insulating film, and an electrode made of the metal material layer is formed. Forming a gate electrode made of the metal material layer. 3. An electrode provided on a substrate with a concave cross section having a groove on an upper portion, a stopper layer provided on an upper end portion on both sides of the electrode, and an outside of the stopper layer and the electrode. A sidewall provided on a wall; an insulating film provided on the substrate so as to cover the electrode, the stopper layer and the sidewall; and a stopper layer provided to reach a bottom surface in a concave portion of the electrode and the substrate, respectively. And a connection hole formed in the insulating film using the sidewall as a stopper. 4. The semiconductor device according to claim 3, wherein the electrode is a gate electrode, and a gate insulating film is provided between the substrate and the gate electrode.