CN106298492B - Method for forming tri-gate structure - Google Patents
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- CN106298492B CN106298492B CN201610985906.2A CN201610985906A CN106298492B CN 106298492 B CN106298492 B CN 106298492B CN 201610985906 A CN201610985906 A CN 201610985906A CN 106298492 B CN106298492 B CN 106298492B
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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Abstract
The invention provides a method for forming a tri-gate structure, which comprises the following steps: the first step is as follows: sequentially forming a dielectric layer, a first work function metal layer and a hard mask layer on a substrate; the second step is as follows: forming a pattern of the hard mask layer; the third step: etching the first work function metal layer by using the hard mask layer for forming the pattern so as to form a first work function metal bump; the fourth step: depositing a second work function metal layer, wherein the second work function metal layer and the first work function metal layer are different materials; the fifth step: carrying out chemical mechanical polishing on the second work function metal layer until the first work function metal bump is exposed; a sixth step: and etching the second work function metal layer and the dielectric layer to form a structure in which the side wall of the first work function metal bump surrounds the side wall of the second work function metal.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to optimization of a grid structure; more particularly, the present invention relates to a method of forming a tri-gate structure.
Background
Short channel effects (short channel effects) occur when the length of the gate is reduced to an order of magnitude greater than the depth of the channel. The threshold voltage drifts and the leakage current increases. At present, the mass-produced technical nodes all adopt a gate material with a single work function, but with the further reduction of the gate size, the short channel effect is more and more non-negligible, and a gate structure with a horizontally variable work function is provided. Research shows that the double-gate structure can shield the drain voltage, thereby effectively overcoming the short-channel effect. The double gate structure is a structure in which materials having different work functions are used as a gate electrode, and different threshold voltages are obtained in channels near a source electrode and a drain electrode. There are also patents reporting symmetric or asymmetric structures of the tri-gate, as opposed to such asymmetric structures of the dual gate.
However, how to manufacture such a gate structure from an integration point of view is still a difficult problem. There is a patent that proposes an integration scheme for gate-last scheme, which uses an interlayer dielectric layer as a hard mask and uses an ion implantation with an inclined angle to generate different work functions at different parts of a gate.
Disclosure of Invention
The present invention provides a more convenient manufacturing method for solving the above-mentioned drawbacks in the prior art, which can obtain different work function metal layers on the gate in the horizontal direction along the channel through a hard mask without adding a photomask.
In order to achieve the above technical object, according to the present invention, there is provided a method for forming a tri-gate structure, including: the first step is as follows: sequentially forming a dielectric layer, a first work function metal layer and a hard mask layer on a substrate; the second step is as follows: forming a pattern of the hard mask layer; the third step: etching the first work function metal layer by using the hard mask layer for forming the pattern so as to form a first work function metal bump; the fourth step: depositing a second work function metal layer, wherein the second work function metal layer and the first work function metal layer are different materials; the fifth step: carrying out chemical mechanical polishing on the second work function metal layer until the first work function metal bump is exposed; a sixth step: and etching the second work function metal layer and the dielectric layer to form a structure in which the side wall of the first work function metal bump surrounds the side wall of the second work function metal.
Preferably, the first and second work function metal layers are one of metal nitride, metal silicide, elemental metal, or metal alloy.
Preferably, the first and second work function metal layers have a thickness of 2nm to nm.
In order to achieve the above technical object, according to the present invention, there is also provided a method for forming a tri-gate structure, including: the first step is as follows: sequentially forming a dielectric layer, a first work function metal layer and a hard mask layer on a substrate; the second step is as follows: forming a pattern of the hard mask layer; the third step: etching the first work function metal layer by using the hard mask layer for forming the pattern so as to form a groove; the fourth step: depositing a second work function metal layer to fill the groove, wherein the second work function metal layer and the first work function metal layer are different materials; the fifth step: carrying out chemical mechanical polishing on the second work function metal layer to expose the first work function metal layer; a sixth step: and etching the first work function metal layer and the dielectric layer so as to form a structure which surrounds the first work function metal side wall on the first work function metal bump side wall.
Preferably, the first and second work function metal layers are one of metal nitride, metal silicide, elemental metal, or metal alloy.
Preferably, the first and second work function metal layers have a thickness of 2nm to nm.
In order to achieve the above technical object, according to the present invention, there is also provided a method for forming a tri-gate structure, including: the first step is as follows: sequentially forming a dielectric layer, a first work function metal layer and a hard mask layer on a substrate; the second step is as follows: forming a pattern of the hard mask layer; the third step: etching the first work function metal layer by using the hard mask layer for forming the pattern so as to form a first work function metal bump; the fourth step: depositing a second work function metal layer, wherein the second work function metal layer and the first work function metal layer are different materials; the fifth step: etching the second work function metal layer and the dielectric layer to form a structure in which the side wall of the first work function metal bump surrounds the side wall of the second work function metal; a sixth step: and removing the hard mask on the first work function metal bump.
Preferably, the first and second work function metal layers are one of metal nitride, metal silicide, elemental metal, or metal alloy.
Preferably, the first and second work function metal layers have a thickness of 2nm to nm.
The invention provides a more convenient manufacturing method, which can obtain different work function metal layers on a grid in the horizontal direction along a channel through a hard mask on the basis of not increasing a photomask. By enabling the gate to generate different work functions in the horizontal direction of the channel, different threshold voltages can be obtained, thereby solving a series of problems caused by the reduction of the gate size, such as short channel effect and the like.
Drawings
A more complete understanding of the present invention, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:
fig. 1 schematically shows a first step of a method of forming a tri-gate structure according to a first preferred embodiment of the invention.
Fig. 2 schematically shows a second step of the method of forming a tri-gate structure according to a first preferred embodiment of the invention.
Fig. 3 schematically shows a third step of the method of forming a tri-gate structure according to the first preferred embodiment of the invention.
Fig. 4 schematically shows a fourth step of the method of forming a tri-gate structure according to the first preferred embodiment of the present invention.
Fig. 5 schematically shows a fifth step of the method of forming a tri-gate structure according to the first preferred embodiment of the invention.
Fig. 6 schematically shows a sixth step of the method of forming a tri-gate structure according to the first preferred embodiment of the invention.
Fig. 7 schematically shows a first step of a method of forming a tri-gate structure according to a second preferred embodiment of the invention.
Fig. 8 schematically shows a second step of a method of forming a tri-gate structure according to a second preferred embodiment of the invention.
Fig. 9 schematically shows a third step of a method of forming a tri-gate structure according to a second preferred embodiment of the invention.
Fig. 10 schematically shows a fourth step of the method of forming a tri-gate structure according to the second preferred embodiment of the invention.
Fig. 11 schematically shows a fifth step of the method of forming a tri-gate structure according to the second preferred embodiment of the invention.
Fig. 12 schematically shows a sixth step of the method of forming a tri-gate structure according to the second preferred embodiment of the invention.
Fig. 13 schematically shows a first step of a method of forming a tri-gate structure according to a third preferred embodiment of the invention.
Fig. 14 schematically shows a second step of the method of forming a tri-gate structure according to a third preferred embodiment of the invention.
Fig. 15 schematically shows a third step of a method of forming a tri-gate structure according to a third preferred embodiment of the invention.
Fig. 16 schematically shows a fourth step of the method of forming a tri-gate structure according to a third preferred embodiment of the invention.
Fig. 17 schematically shows a fifth step of the method of forming a tri-gate structure according to a third preferred embodiment of the invention.
Fig. 18 schematically shows a sixth step of a method of forming a tri-gate structure according to a third preferred embodiment of the invention.
It is to be noted, however, that the appended drawings illustrate rather than limit the invention. It is noted that the drawings representing structures may not be drawn to scale. Also, in the drawings, the same or similar elements are denoted by the same or similar reference numerals.
Detailed Description
In order that the present disclosure may be more clearly and readily understood, reference will now be made in detail to the present disclosure as illustrated in the accompanying drawings.
< first preferred embodiment >
Fig. 1 to 6 schematically show steps of a method of forming a tri-gate structure according to a first preferred embodiment of the present invention.
As shown in fig. 1 to 6, a method for forming a tri-gate structure according to a first preferred embodiment of the present invention includes:
the first step is as follows: forming a dielectric layer 10, a first work function metal layer 20 and a hard mask layer 30 on a substrate 100 in sequence;
the second step is as follows: forming a pattern of hard mask layer 30;
the third step: etching the first work function metal layer 20 by using the patterned hard mask layer to form a first work function metal bump 40;
the fourth step: depositing a second work function metal layer 50, wherein the second work function metal layer 50 is a different material than the first work function metal layer 20;
the fifth step: performing chemical mechanical polishing on the second work function metal layer 50 until the first work function metal bump 40 is exposed;
a sixth step: the second work function metal layer 50 and the dielectric layer 10 are etched to form a structure in which the sidewalls of the first work function metal bump 40 surround the sidewalls of the second work function metal 51.
Preferably, the first work function metal layer 20 is one of a metal nitride, a metal silicide, an elemental metal, or a metal alloy. Preferably, the thickness of the first work function metal layer 20 is 2nm to 10 nm.
Preferably, the second work function metal layer 50 is one of a metal nitride, a metal silicide, an elemental metal, or a metal alloy. Preferably, the thickness of the second work function metal layer 50 is 2nm to 10 nm.
< second preferred embodiment >
Fig. 7 to 12 schematically show steps of a method of forming a tri-gate structure according to a second preferred embodiment of the present invention.
As shown in fig. 7 to 12, the method for forming a tri-gate structure according to the second preferred embodiment of the present invention includes:
the first step is as follows: forming a dielectric layer 10, a first work function metal layer 20 and a hard mask layer 30 on a substrate 100 in sequence;
the second step is as follows: forming a pattern of hard mask layer 30;
the third step: etching the first work function metal layer 20 by using the patterned hard mask layer to form a groove 60;
the fourth step: depositing a second work function metal layer 50 to fill the recess 60, wherein the second work function metal layer 50 is a different material than the first work function metal layer 20;
the fifth step: performing chemical mechanical polishing on the second work function metal layer 50 to expose the first work function metal layer 20;
a sixth step: the first work function metal layer 20 and the dielectric layer 10 are etched to form a structure in which the first work function metal sidewall 21 is surrounded at the sidewall of the first work function metal bump 52.
Preferably, the first work function metal layer 20 is one of a metal nitride, a metal silicide, an elemental metal, or a metal alloy. Preferably, the thickness of the first work function metal layer 20 is 2nm to 10 nm.
Preferably, the second work function metal layer 50 is one of a metal nitride, a metal silicide, an elemental metal, or a metal alloy. Preferably, the thickness of the second work function metal layer 50 is 2nm to 10 nm.
< third preferred embodiment >
Fig. 13 to 18 schematically show steps of a method of forming a tri-gate structure according to a third preferred embodiment of the present invention.
As shown in fig. 13 to 18, a method for forming a tri-gate structure according to a third preferred embodiment of the present invention includes:
the first step is as follows: forming a dielectric layer 10, a first work function metal layer 20 and a hard mask layer 30 on a substrate 100 in sequence;
the second step is as follows: forming a pattern of hard mask layer 30;
the third step: etching the first work function metal layer 20 by using the patterned hard mask layer to form a first work function metal bump 40;
the fourth step: depositing a second work function metal layer 50, wherein the second work function metal layer 50 is a different material than the first work function metal layer 20;
the fifth step: etching the second work function metal layer 50 and the dielectric layer 10 to form a structure in which the sidewall of the first work function metal bump 40 surrounds the sidewall 51 of the second work function metal;
a sixth step: the hard mask on the first work function metal bump 40 is removed.
Preferably, the first work function metal layer 20 is one of a metal nitride, a metal silicide, an elemental metal, or a metal alloy. Preferably, the thickness of the first work function metal layer 20 is 2nm to 10 nm.
Preferably, the second work function metal layer 50 is one of a metal nitride, a metal silicide, an elemental metal, or a metal alloy. Preferably, the thickness of the second work function metal layer 50 is 2nm to 10 nm.
The invention provides a more convenient manufacturing method, which can obtain different work function metal layers on a grid in the horizontal direction along a channel through a hard mask on the basis of not increasing a photomask. By enabling the gate to generate different work functions in the horizontal direction of the channel, different threshold voltages can be obtained, thereby solving a series of problems caused by the reduction of the gate size, such as short channel effect and the like.
In addition, it should be noted that the terms "first", "second", "third", and the like in the specification are used for distinguishing various components, elements, steps, and the like in the specification, and are not used for indicating a logical relationship or a sequential relationship between the various components, elements, steps, and the like, unless otherwise specified or indicated.
It is to be understood that while the present invention has been described in conjunction with the preferred embodiments thereof, it is not intended to limit the invention to those embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
It is to be further understood that the present invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "an element" means a reference to one or more elements and includes equivalents thereof known to those skilled in the art. Similarly, as another example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Structures described herein are to be understood as also referring to functional equivalents of such structures. Language that can be construed as approximate should be understood as such unless the context clearly dictates otherwise.
Moreover, implementation of the method and/or system of embodiments of the present invention may include performing the selected task manually, automatically, or in combination. Moreover, the actual instrumentation and equipment according to embodiments of the method and/or system of the present invention may utilize an operating system to accomplish several selected tasks either in hardware, software, or a combination thereof.
Claims (9)
1. A method for forming a tri-gate structure, comprising:
the first step is as follows: sequentially forming a dielectric layer, a first work function metal layer and a hard mask layer on a substrate;
the second step is as follows: forming a pattern of the hard mask layer;
the third step: etching the first work function metal layer by using the hard mask layer for forming the pattern so as to form a first work function metal bump;
the fourth step: depositing a second work function metal layer, wherein the second work function metal layer and the first work function metal layer are different materials;
the fifth step: carrying out chemical mechanical polishing on the second work function metal layer until the first work function metal bump is exposed;
a sixth step: and etching the second work function metal layer and the dielectric layer to form a structure in which the side wall of the first work function metal bump surrounds the side wall of the second work function metal.
2. The method of claim 1, wherein the first and second work-function metal layers are one of a metal nitride, a metal silicide, a simple metal, or a metal alloy.
3. The method of claim 1 or 2, wherein the first and second work function metal layers have a thickness of 2nm to nm.
4. A method for forming a tri-gate structure, comprising:
the first step is as follows: sequentially forming a dielectric layer, a first work function metal layer and a hard mask layer on a substrate;
the second step is as follows: forming a pattern of the hard mask layer;
the third step: etching the first work function metal layer by using the hard mask layer for forming the pattern so as to form a groove;
the fourth step: depositing a second work function metal layer to fill the groove, wherein the second work function metal layer and the first work function metal layer are different materials;
the fifth step: carrying out chemical mechanical polishing on the second work function metal layer to expose the first work function metal layer;
a sixth step: and etching the first work function metal layer and the dielectric layer so as to form a structure which surrounds the first work function metal side wall on the first work function metal bump side wall.
5. The method of claim 4, wherein the first and second work function metal layers are one of metal nitrides, metal silicides, elemental metals, or metal alloys.
6. The method of claim 4 or 5, wherein the first and second work function metal layers have a thickness of 2nm to nm.
7. A method for forming a tri-gate structure, comprising:
the first step is as follows: sequentially forming a dielectric layer, a first work function metal layer and a hard mask layer on a substrate;
the second step is as follows: forming a pattern of the hard mask layer;
the third step: etching the first work function metal layer by using the hard mask layer for forming the pattern so as to form a first work function metal bump;
the fourth step: depositing a second work function metal layer, wherein the second work function metal layer and the first work function metal layer are different materials;
the fifth step: etching the second work function metal layer and the dielectric layer to form a structure in which the side wall of the first work function metal bump surrounds the side wall of the second work function metal;
a sixth step: and removing the hard mask on the first work function metal bump.
8. The method of claim 7, wherein the first and second work-function metal layers are one of metal nitrides, metal silicides, elemental metals, or metal alloys.
9. The method of claim 7 or 8, wherein the first and second work function metal layers have a thickness of 2nm to nm.
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1192053C (en) * | 1998-02-04 | 2005-03-09 | 通用电气公司 | Method for improving adhesion of metal films to polyphenylene ether resins |
JP2009123944A (en) * | 2007-11-15 | 2009-06-04 | Panasonic Corp | Semiconductor device and its manufacturing method |
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JP2007158148A (en) * | 2005-12-07 | 2007-06-21 | Oki Electric Ind Co Ltd | Semiconductor device, and method of manufacturing same |
JP2007243117A (en) * | 2006-03-13 | 2007-09-20 | Oki Electric Ind Co Ltd | Manufacturing method of high breakdown voltage mos transistor |
CN102097376B (en) * | 2009-12-10 | 2013-05-01 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
US8779530B2 (en) * | 2009-12-21 | 2014-07-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal gate structure of a field effect transistor |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1192053C (en) * | 1998-02-04 | 2005-03-09 | 通用电气公司 | Method for improving adhesion of metal films to polyphenylene ether resins |
JP2009123944A (en) * | 2007-11-15 | 2009-06-04 | Panasonic Corp | Semiconductor device and its manufacturing method |
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