TW478050B - Method of fabricating polysilicon resistor on metal gate - Google Patents

Abstract

The present invention discloses a method of fabricating polysilicon resistor on metal gate, which can resolve the problem that the fabricated metal gate is damaged by the high-temperature process in the polysilicon resistor process during the following polysilicon resistor fabrication process after fabricating metal gate. The polysilicon resistor is fabricated together with the dummy resistor, and the high temperature process of polysilicon resistor and dummy gate are integrated together, a passivation layer is formed on the polysilicon resistor in the following processing steps of fabricating metal gate to avoid the damage of polysilicon resistor in the process of metal gate.

Description

478050 V. Description of the invention (1) Technical field: The present invention relates to a logic circuit process, in particular to a method for manufacturing a metal gate and a polysilicon resistor. Background of the invention: The logic circuit is made of CMOS , Resistors, capacitors, etc., and M0S transistor elements use gates as control electrodes. Generally speaking, “Po 1 y — si” containing high concentration n-type or p-type is used for this purpose. Gate material, but in dual poly configuration, when the gate voltage is high enough, there will be part of the voltage drop across the polysilicon gate, which is the phenomenon of depletion. When the width of the empty region is close to the thickness of the gate oxide (for example, after the gate oxide thickness is less than 10 nm), the correlation effect becomes significant. If the activation level of the dopants in the polycrystalline silicon gate is insufficient, the width of the empty region will be larger. In order to improve this phenomenon, Texas Instruments (TI) issued a component technology using metal gates (Al / TiN and W / TiN) as its gate in 1997. The metal gate has low resistance and no carrier. Depletion problems and other advantages. The general method of making a metal gate is as follows: First, please refer to FIG. 1M, a traditional gate structure is used to form a dummy gate structure 100 (dummy gate structure) and a source / drain region 15. On a semiconductor substrate 10 having a shallow trench isolation 20 (STI), a gate dielectric layer, a doped polycrystalline silicon, and a silicide metal layer are successively deposited on the substrate 10, continued to the gate dielectric layer, Silicided metal layer and doped

478050 V. Description of the invention (2) '~-The miscellaneous polycrystalline silicon layer defines the position of the dummy gate, leaving only the gate dielectric layer 90, petrified metal | 80, and doped polycrystalline polysilicon layer 7〇 Composition of interpolar structure 100. Continued [Ion layout to form a lightly doped drain (highiy dped dram; LDD); Then, a spacer wall 60 is formed on both sides of the dummy gate junction // 100 and an ion layout step is performed to The source / inverter region 15 is deposited, and a dielectric layer of emulsified silicon 30 is deposited on the dummy gate structure 100. After the step is performed, the thickness of the deposited dielectric layer and the dummy idler are deposited. The structure 1 0 0 is the same. Please refer to Figure-BB for the continuation. The removal of the dummy gate structure is to etch the reactive gas or the selective wetness with different names. Gate: Electrical layer 90, silicided metal layer 80 and doped , And open the gate opening (gate opening) 100a. In addition to the layer 70, materials such as hafnium oxide (Ta205), which is a high-dielectric constant dielectric screen, are then deposited as the gate dielectric 9, as shown in Shi Xi (Sl3N4) or a C, and titanium nitride (TiN) is deposited successively. ^ Is the layer resistance ^ / continued reference picture ⑺ or Shao M is the metal layer 50, and then the chemical and metal crane ... layer removed, complete with high dielectric constant number in the second electricity), barrier layer 40a and When the metal layer 50a is formed (when the sub-micron device is not manufactured in the figure, the parasitic resistance of the gate ruler dipole structure 2 0 0) also increases, so when the thunder and thunder are low, the gate The delay of the transmission of the logic gate, in terms of the RF circuit, the timeliness, will cause the fmax and noise characteristics, so there are; _ said seriously affecting the component is mainly to improve the component characteristics by improving the gate structure The structure of the gate electrode of the same type is 478050 V. Explanation of the invention (3) It has an extended shape in the upper half of the gate, so the cross section is wide. In this way, the parasitic resistance of the gate can be reduced. It is in the manufacturing process In the process, the dummy gates are also made 'as shown in Figure 1', and then as shown in Figure 1B. The dummy gate structure is removed. Next, a dielectric layer with a high dielectric constant, such as nitride or oxygen, is deposited as the gate dielectric layer. Then, as shown in FIG. 1E, titanium nitride is successively deposited. As the barrier layer 40 and metal tungsten or aluminum as the metal layer 50 / using a photolithography method to form a photoresist 5 1 at the gate electrode position as the etch 20 electrode; as shown in the last figure 1f, using dry = = only left The lower cover protects the barrier layer 40b and the metal layer 50b, and after removing the photoresist 51, the T-gate 200b is completed. After completing the multiple tedious steps, the gold is completed in the trench. After the poly 1 pole is made on the isolation 20, this connection can meet the operation requirements. I Because polycrystalline silicon is deposited, this step is about the resistance value: doped step structure must be added to the polycrystalline stone. The surface temperature is controlled, and the quality of the metal gate layer is formed, which causes the temperature and temperature process of the gate resistor to destroy the ionized ^^^ voltage drift or hysteresis formed before the gate dielectric; and The expansion of its ions forms the source / drain region, which is also difficult in high temperature processes. Control SUMMARY square invention:

The main B resistance of the present invention simultaneously forms an acoustic: After the length of 1 is used to make a polycrystalline gate structure on a metal gate, the gate and polycrystalline silicon resistors are formed, so that the dielectric layer of the gate is damaged when gold is formed. Need to perform the high temperature polycrystalline silicon resistance step to break and quality.

Page 6 of 478050 5. Description of the invention (4) The secondary purpose of the present invention is to provide a polycrystalline silicon resistor on a metal gate, reducing the steps of making metal gate and polycrystalline silicon resistor in the conventional technology. The silicon is made of virtual polycrystalline silicon and substrate poles, and the invention is completed in the electrode opening. After removing the invention, the polysilicon resistors have been fabricated and doped on the two sides of the resistors and resistors. In order, the order of the metal gates is exhausted and the drained polycrystalline silicon is used up. Continue to go back to the same crystal chip to form the structure drawing number description: 10-substrate 20-shallow trench separation 4 0 -barrier layer 4 0 a -barrier layer 5 0 a -metal layer 5 1 -photoresist is to provide a manufacturing metal In the case of polycrystalline gates on the gate, a photoresistor is used to protect the polycrystalline silicon resistor. Steps to achieve the above-mentioned items: the semiconductor substrate of the first / source region 'sequentially deposits a layer and a silicided metal layer on the substrate, continues, sets the silicon resistance, and forms a gap between the dummy gate and the deposited silicon oxide In the dummy gate, polysilicon resistive etching makes the thickness of the deposited dielectric layer and the dummy gate. Then a photoresistive polysilicon resistor is formed, and then the dummy gate is removed to form a gate chromium oxide, titanium nitride, and metal tungsten in the gate opening 15-source / drain region 3 0-dielectric layer 5 0 -Metal layer 4 0 b-barrier layer 5 0 b-metal layer 6 0-high resistance

Page 7 478050

8 0-Shi Xihua gold 1 0 0 -Dummy open 2 0Ob-T-type stern armor, 7 0 0 -Doped 9 0 0 -Dielectric layer belongs to layer structure and extremely polycrystalline hair layer 7 0 -Doped Miscellaneous polycrystalline silicon layer 9 0-gate dielectric layer 2 0 0a-metal gate structure 5 0-photoresistive layer 8 0 0-polymetallic layer 1 0 0 0-polycrystalline silicon resistive structure

Detailed description of the invention: The present invention can be used in the process of forming a metal gate and a polycrystalline silicon resistor in a semiconductor manufacturing process at a high temperature and a layout step to damage the structure. The invention uses two embodiments to illustrate the invention in a polarized manner. First embodiment: In the operation logic circuit, reduce the% step to avoid polysilicon resistance. Only # — w ^ The metal gate junction is made into a mosaic gate and a τ -type gate-formed pole region. Polycrystalline metal with isotropically crushed gold is left before the substrate is lighted, and the gate electrode is set to two = kilograms. According to the tradition, the gate structure is made square, ^, ^, 100, and polycrystalline silicon resistance structure. / 5. A gate dielectric layer, doped polycrystalline silicon and a silicided metal layer are deposited on a semiconductor substrate 10 having a shallow trench isolation 20 (STI), and a photoresist layer is spin-coated on the silicided metal layer. The photoresist is exposed on the gate and the polycrystalline silicon photoresist through lithographic exposure to protect the gate dielectric layer, the doped polycrystalline silicon and the underlying layer during the etching process to form the gate dielectric layer. 〇 、 Poly gate structure 100 composed of metal silicide silicon layer 70 and dielectric layer Qn doped layer 8000 and doped polycrystalline silicon layer 7000 polycrystalline silicon, silicon resistance junction

Page 8 478050 V. Description of Invention (6) Structure 1000. The gate dielectric layer is based on the requirement of the polycrystalline structure of the passivation layers 70 and 7_. First, the polycrystalline silicon resistor junction source of Dou Duo for I 1 Bi is phosphorus (4, V and V are used in the way of ion distribution, and the dose is between 100KeV and 22. The ion energy is between 30 layers and it is cut by chemical vapor deposition .... The metal is all JS + post-purchaser , Flying apart / eight-doped polycrystalline silicon layer and silicidation, the degree of silicide; I is between 1000 angstroms and 300 angstroms. # 杂 3:; τ The value is to form pumice i Α) \ To make N-type elements, it is used to change the impurity ions. Take the cloth value Shishen as an example, and the cloth value energy is between .ν and ί 曰 ΓΪ. Gate structure 丨 〇〇 and ΐ on the two sides of the resistance structure 1000, the thickness of the gap wall 60 is between 300 angstroms j z 1: the material used is silicon nitride or silicon oxide / nitride nitride ψ ^ 二 建 ° # 着 'The ion distribution and high temperature diffusion steps are performed to make the source / drain region i 5. For the ions of the distributed value to make difficult components, phosphorus (P) or arsenic (As) is used. ion, Taking cloth-valued arsenic as an example, the cloth-valued energy is between I KeV and 100 KeV, the cloth-value concentration is between 1 El5 at ⑽ / ㈣ 技 8E15 atom / cm2, and the high-temperature diffusion temperature is between 950.111. Between begging. Finally, a silicon oxide dielectric layer 30 is deposited to cover the dummy gate structure 100, the polycrystalline silicon resistor 1000 and the substrate 10, and a chemical mechanical polishing method is used.

The following page continues to ask the polycrystalline silicon below to make the metal gate structure 1 0 0, or the selective polycrystalline silicon layer is etched as an example, so that the removal of layer 80 and doped CFH3 and so on is continued. 478050 V. Description of the invention (7) Formula A step of back engraving is performed, so that the thickness of the deposited dielectric layer 100 is the same as that of the polycrystalline silicon resistor 100. At this time, the dummy gate structure 100 and the polycrystalline silicon resistor J are completed, and the connection is made of a metal gate. In the production of gold tubes, a replacement gate and a damascene gate are used to form a dummy gate and a field "later" before the metal gate is produced. However, during the manufacturing process, the general process requires After the metal gate is fabricated, it is produced. During the production process of the polycrystalline silicon resistor, due to the high temperature environment of the accumulated time and the polycrystalline silicon doped ionic distribution value, the temperature manufacturing process will affect the completed metal gate. In the examples, a polycrystalline silicon resistor structure 丨 0 〇 is used as a dummy gate to solve the problems encountered in the general process, and the section is shown in Figure 2 β | 4 ″ Silicon resistance structure 1 0 〇〇 Not affected by the subsequent process steps of forming the electrode structure 2000a, using plasma etching and different combinations: Wet gate electrode dielectric layer 90 and silicidation 70 are removed by wet etching, and the gate opening 1 is opened. 〇; Chlorine gas (C12) was used as the reaction gas j polycrystalline silicon layer 70, and a fluorine-containing gate dielectric layer was also used. Initial deposition and fabrication of metal gates &# 1. When the gate junction U 虚 1000 has been fabricated with gates, the gate / source regions are not used as logic circuits. _ Polycrystalline silicon resistors require polycrystalline silicon and ion diffusion. 4. The 100-thousand-manufacturing process r 5 0 0 of the present invention is used to protect the electrode opening 100 a and to dope the reactive gas metal layer 80 at the dummy gate and doping to adopt plasma etching ❹ to desiliconize Metal body such as CF4, V. Description of the invention (8) A dielectric layer such as silicon nitride (Si3N4) or chromium oxide (Ta205) is used as the gate dielectric layer in the opening 10a. In order to avoid the duplication of the pattern, the two are in the resistance map Λ) 4: continued to refer to Figure IIC, and deposited in succession) is the early resistance layer 4 0 and the metal tungsten (W) or aluminum (A 1) as the metal reed 5 0 ° The dielectric layer with a dielectric constant of South uses low pressure chemical vapor deposition (LPCVD) to form a thickness between 15 Angstroms and 200 Angstroms, using chromium oxide as an example. Ta (0C2H5) 5 and 02 were used as reaction gases. Titanium nitride and metal tungsten or aluminum are formed using plasma-enhanced chemical vapor deposition (pECVDM). The thickness of titanium nitride is between 50 angstroms and 500 angstroms. The deposited thickness of metal tungsten or aluminum is between 50 Angstroms and 2000 Angstroms; the important thing is that the combined thickness of titanium nitride and metal tungsten or aluminum needs to fill the gate opening 100a. As shown in FIG. 2D, the barrier layer and the metal layer remaining on the dielectric layer 30 are removed by chemical mechanical polishing (CMP), and the gate dielectric layer (not shown in the figure) and the barrier layer 4 are completed. The metal gate structure 2000 formed by a and the metal layer 50 a. Finally, 'removing the photoresist layer 500 which protects the polycrystalline silicon resistance structure 丨 00' has completed the fabrication of the metal gate and polycrystalline silicon resistance. Among them, the chemical mechanical polishing uses the dielectric layer 30 as the back-engraved stop layer and the photoresist layer 500 uses a dry (plasma method) or wet method to remove the second layer.

Page 11 Description of the invention (9)

The phase of the gate is described in the example of the electroplated structure for protection and removal. Following the ‘Example’, chromium oxide and the like are successively deposited at 50, and the resistance invention can also be applied. At the same time, it is also 100% in the same process, as shown in the figure. And the following polycrystalline I 'deposition process is performed as described above, the material is used as a gate, titanium nitride is used as a barrier layer 40, and the gold gate process, and a polycrystalline silicon resistor can also be fabricated in the fabrication process. The fabrication method of the dummy gate structure 100 is different from that of the polycrystalline silicon A. The manufacturing method is also the same as that of the first implementation. As shown in FIG. 2B, a photoresistive layer 5 0 C silicon resistance structure 10 is formed first. After that, the dummy gate structure is used as the material required for the metal gate. The method is the same as that of a high-k dielectric layer such as silicon nitride or a polar dielectric layer, as shown in Figure 2E. Manufacturing method of barrier layer 40 and metal tungsten or aluminum as metal layer subordinate layer 50 and thickness and former thickness

The embodiment described is the same, but when making a T-type gate, it is necessary to use a photolithography method to form a photoresist 5 at the gate position after depositing the required material of the metal gate. It is used as a mask during etching. Define the T-type gate; finally, as shown in Figure 2F, using anisotropic etching to leave only the barrier layer 4Ob and the metal layer 50b under the protection of the mask, and it is completed after removing the photoresist 51 T-gate 2 0 0bo

Its photoresist 51 can be a material of positive or negative photoresistance, and the anisotropic etching used is plasma etching using a reaction gas containing chlorine to remove the metal layer, and using a reaction gas containing oxygen or nitrogen Plasma etching to remove the barrier layer. The photoresist 51 is removed by conventional methods, such as electro-polymerization or wet etching. The above description illustrates the present invention by way of a preferred embodiment, and is not limiting.

478050

Page 13 478050 Brief description of the diagram Brief description of the diagram: Figure 1A is a cross-sectional view of the process of forming a transistor in a conventional technique. Figure 1B is a cross-sectional view of the process of removing the dummy gate structure in the conventional art. Figure 1C is a cross-sectional view of a process for depositing a barrier layer and a metal layer in a conventional technique. Figure 1D is a cross-sectional view of a process for forming a metal gate electrode after etch-back in the conventional art. Figure 1E is a cross-sectional view of the process of forming a photoresist to define a T-gate in the conventional art. Figure 1F is a cross-sectional view of the process of forming a T-gate in the conventional art. FIG. 2A is a cross-sectional view of a process for forming a dummy gate and a polycrystalline silicon resistor in an embodiment of the present invention. FIG. 2B is a cross-sectional view of a manufacturing process in which a dummy gate structure is removed and a polysilicon resistor is protected by a photoresist according to an embodiment of the present invention. FIG. 2C is a cross-sectional view of a process for depositing a barrier layer and a metal layer in the first embodiment of the present invention. FIG. 2D is a cross-sectional view of a process of forming a metal gate electrode after etch-back in the first embodiment of the present invention. FIG. 2E is a cross-sectional view of a process for forming a photoresist to define a T-type gate in the second embodiment of the present invention. Fig. 2F is a cross-sectional view of a process for forming a T-type gate in the second embodiment of the present invention.

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Claims (1)

478050 VI. Scope of patent application1. A method for making polycrystalline silicon resistor (ρ 〇1 y resistor) on a metal gate (meta gate) includes: (a) simultaneously forming a dummy gate structure and a dummy gate structure; The polycrystalline silicon resistor is on a semiconductor substrate, wherein the drain / source region has been completed on the semiconductor substrate; (b) a dielectric layer is deposited, and a chemical mechanical polishing method is used to perform the engraving step to make the dielectric layer The thickness is the same as that of the dummy gate and polycrystalline silicon resistor; (c) forming a photoresist on the polycrystalline silicon resistor; (d) removing the dummy gate to form a gate opening (gate Φ (e) depositing a high dielectric constant dielectric layer in the gate opening as a gate dielectric layer; (f) depositing a gate metal layer over the semiconductor substrate; (g) will be located The gate metal layer on the dielectric layer is removed to complete the fabrication of the metal gate. 2. The method of making a polycrystalline silicon resistor on a metal gate as described in item 1 of the scope of the patent application, wherein the photoresist is a negative photoresist. • 丨 3 · The method for making a polycrystalline silicon resistor on a metal gate as described in item 1 of the scope of patent application, wherein the photoresist is a positive photoresist. 4 · Fabrication of polycrystalline silicon on metal gate as described in item 1 of the scope of patent application Page 15 478050 6. Method for applying patent range resistance, wherein the interlayer dielectric layer is silicon nitride (Si3N4). 05. Polycrystalline on metal gate as described in the first range of patent application range. The method of Shi Xi resistance, wherein the interlayer dielectric layer is oxidized oxide (Ta205). 6. The method for making a polycrystalline silicon resistor on a metal gate according to item 1 of the scope of the patent application, wherein the intermetallic layer includes a barrier layer and a metal layer. 7. The method for making a polycrystalline silicon resistor on a metal gate as described in item 7 of the scope of patent application, wherein the barrier layer is titanium nitride (T i N). 8. The method for manufacturing a polycrystalline silicon resistor on a metal gate as described in item 7 of the scope of the patent application, wherein the metal layer is metal tungsten (W). The gate is made of gold. The A / (V on the aluminum electrode is gold I is the layer of gold I. It is in the middle of the law, and the application of the law is requested by the law. 10. The method for manufacturing polycrystalline silicon resistors on metal gates as described in item 1 of the scope of the patent application, wherein the removal of the gate metal layer is by chemical mechanical polishing (CMP). Page 16 478050 VI. Application for Patent Scope 11 · The method for making polycrystalline silicon resistors on metal gates as described in the first paragraph of the patent application scope, wherein the simultaneous formation of dummy gates and polycrystalline silicon resistors on a semiconductor substrate includes : (A) sequentially depositing silicon oxide, a doped polycrystalline silicon layer, and a silicided metal layer on the semiconductor substrate; (b) defining the silicon oxide, the doped polycrystalline silicon layer, and the silicided metal layer; A dummy gate and the polycrystalline silicon resistor; (c) forming a gap wall on both sides of the dummy gate and the polycrystalline silicon resistor; 1 2 · —A method for making poly resistors on T-shape gates, including: (a) forming a dummy gate structure and a polycrystalline silicon resistor at the same time On the semiconductor substrate, wherein the drain / source region has been completed on the semiconductor substrate; (b) depositing a dielectric layer and performing an etch-back step using chemical mechanical polishing to make the thickness of the dielectric layer and The dummy gate and the polycrystalline shred resistor are the same; (c) a photoresist is formed on the polycrystalline stone resistor; (d) the dummy gate is removed to form a gate opening (E) depositing a high dielectric constant dielectric layer in the gate opening as a gate dielectric layer; (f) depositing a gate metal layer over the semiconductor substrate; Page 17 478050 6. Scope of patent application (g) Use lithography to define the T-gate position in the gate metal layer; (h) Remove the gate metal layer other than the T-gate position , Complete the production of metal gate (meta 1 gate). 1 3. The method for making a polycrystalline silicon resistor on a T-gate according to item 12 of the scope of the patent application, wherein the photoresist is a positive photoresist. 14. The method for manufacturing a polycrystalline silicon resistor on a T-gate according to item 12 of the scope of the patent application, wherein the photoresist is a negative photoresist. 1 5. The method for manufacturing a polycrystalline silicon resistor on a T-gate according to item 12 of the scope of patent application, wherein the gate dielectric layer is silicon nitride (Si3N4). The method for fabricating a polycrystalline silicon resistor on a T-gate according to item 12 of the scope, wherein the gate dielectric layer is chromium oxide (Ta205). 1 7. The method for manufacturing a polycrystalline silicon resistor on a T-gate according to item 12 of the scope of the patent application, wherein the gate metal layer includes a barrier layer and a metal layer . 1 8. The method for making a polycrystalline silicon resistor on a T-gate according to item 17 of the scope of the patent application, wherein the barrier layer is titanium nitride (T i Ν). Page 18 478050 6. Scope of patent application 1 9. The method for making polycrystalline silicon resistors on T-gates as described in item 17 of the scope of patent application, wherein the metal layer is metal tungsten (W). 20. The method for manufacturing a polycrystalline silicon resistor on a T-gate according to item 17 of the scope of the patent application, wherein the metal layer is metal aluminum (A 1). 2 1. The method for making a polycrystalline silicon resistor on a T-type gate as described in item 12 of the scope of the patent application, wherein the gate metal layer except for removing the position of the T-type gate is anisotropic Sex silver engraving. 22. The method for manufacturing a polycrystalline silicon resistor on a T-gate according to item 12 of the scope of patent application, wherein the simultaneous formation of a dummy gate and a polycrystalline silicon resistor on a semiconductor substrate includes: (a) deposition oxidation Silicon, a doped polycrystalline silicon layer, and a silicided metal layer on the semiconductor substrate; (b) defining the virtual oxide in the oxidized silicon oxide, the doped polycrystalline silicon layer, and the lithiated metal layer; Placing a gate electrode and the polycrystalline silicon resistor; (c) forming a gap between the dummy gate electrode and the polycrystalline silicon resistor; Page 19