JP3259535B2 - Method for manufacturing semiconductor device having NMOS transistor and PMOS transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to manufacturing <br/> manufacturing method of a semiconductor device having an NMOS transistor and a PMOS transistor. In particular, the present invention provides an NMOS transistor capable of obtaining a highly reliable semiconductor device with a reduced number of steps.
Semiconductor device having transistor and PMOS transistor
Is provided. In this specification, “MOS” generally refers to a transistor having a structure including a conductive material, an insulating material, and a semiconductor, and is not limited to a metal-oxide-semiconductor.

[0002]

2. Description of the Related Art In the field of MOS semiconductor devices, further miniaturization and integration are required.
S-device miniaturization according to the scale down rule,
The rate is limited only by the progress of miniaturization technology, and rapid progress is being made. It is also said that there is no limit as a transistor up to a 0.04 μm gate. But MO
The low-voltage operation and the high-speed operation required for the S device are in a so-called trade-off relationship, and are mutually contradictory requests. On the other hand, the threshold voltage is required to be lower than ever before, and therefore, a semiconductor device having a dual gate transistor having good performance, particularly an NMOS transistor and a PMOS transistor, and a method for manufacturing the same are required. I have.

However, in this technique, since gate electrodes of different conductivity types must be formed, the number of gate electrode formation steps is increased, and the cost merit is reduced. In particular, this tendency is remarkable in general use. Furthermore, when a low-concentration boron-doped electrode is used, a roll-off of the threshold voltage occurs, and in many cases, the electrode cannot be formed as theoretically designed. Furthermore, due to the abnormally accelerated diffusion of boron reaching the substrate, there is also a problem in reliability, which is not always practical.

A conventional example of forming a dual polycide gate electrode will be described as follows.

A semiconductor substrate is provided with element isolation, for example, an improved L
It is formed by OCOS (a technique of laying a polysilicon buffer and performing selective oxidation with a SiN mask).

The gate oxidation is performed by pyrogenic oxidation at 850 ° C. to a thickness of 10 nm. This oxide film becomes a gate insulating film.

Subsequently, a gate material is formed in the following steps (1) to (5).

(1) Polysilicon formation For example, a total flow rate of 500 SC is applied to a SiH ₄ / He gas system.
Used in CM, 0.8 Torr, 620 ° C, 100 nm
It is formed with a thickness. (2) after treatment with limp Rede position 850 ° C. with POC1 ₃ in 60min, performs processing etching (for poly reduction, there is a possibility that the gate oxide film attack occurs at Hereafter hydrofluoric acid treatment) (3) p ⁺ Layer window lithography This can be formed with a rough pattern. (4) B ⁺ ion implantation High concentration ion implantation is performed. Therefore, the throughput is low. (5) Immediately before forming the silicide layer, a light etching process is performed, and then LPCVD is performed.
-WSix is formed to a thickness of 100 nm.

Thereafter, a fine pattern is formed by gate cut lithography. Using this as a mask, the subsequent gate dry etching is performed by microwave plasma etching with a selectivity of 40 and overetching of 50%.

As another example, an example in which a gate material is formed in the following steps (1) to (5) has been proposed (IEDM93, 831-834, T. Eguchi,
et. al. , “New Dual Gate Dop”
ing Process using In-situ
Boron Doped-Si for Deep
Sub-μm CMOS Device ”).

(1) Boron-doped amorphous silicon formation (2) CVD-SiO ₂ formation (3) n ⁺ layer window opening lithography (rough pattern formation) (4) Phosphor pre-deposition and diffusion POCl ₃ and mask oxide film After the etching, processing is performed (there may be a gate oxide film attack in the hydrofluoric acid processing thereafter for poly-forming). (5) Immediately before the formation of the silicide layer, a light etching process is performed to reduce WSix to 100 nm.
Form. (Note that pre- and post-processing and inspection processes are omitted from the number of processes.)

[0012] On the other hand, according to recent studies, doping with boron-doped silicon at a higher concentration than before,
By limiting the activation anneal, the enhanced diffusion is conversely suppressed, and thus the possibility of practical use has emerged. However, as compared with the case of only n ⁺ , the process is still longer and the cost merit is low.

Further, there is a strong demand for reducing the thickness of the gate electrode to reduce the resistance in order to increase the speed. For example, the resistance is reduced by reducing the thickness of polysilicon and increasing the thickness of silicide or changing the silicide to titanium silicide. Attempts have been made to achieve this, but the hydrofluoric acid resistance of polysilicon is likely to degrade. On the other hand, when it is acceptable to deviate from the conventional work function, it is known that even if silicon-rich silicide is formed at once, it does not occur if the silicon-rich silicide is peeled off. However, this alone cannot achieve a lower threshold voltage.

[0014]

SUMMARY OF THE INVENTION In view of the above circumstances, the present invention provides a highly reliable gate structure, can reduce manufacturing defects, and can lower the threshold voltage. Can be achieved by a process with a small number of processes.
An object of the present invention is to provide a method for manufacturing a semiconductor device having a MOS transistor and a PMOS transistor.

[0015]

Means for Solving the Problems Each invention according to the present application is:
The above object has been achieved by the following constitutions.

The invention according to claim 1 of the present application is characterized in that NM
In a method for manufacturing a semiconductor device having an OS transistor and a PMOS transistor, an insulating film serving as a gate insulating film is formed over a semiconductor substrate, and then an impurity-containing material layer having one conductivity type is formed. An impurity-containing material layer having a conductivity type of higher than that of the one conductivity type, and forming an NMOS transistor or PM
The other conductive type impurity-containing material layer of the upper layer is removed from any one of the formation regions of the OS transistor, and then activated, so that one conductive type impurity-containing material layer in one transistor becomes a gate electrode material layer. An NMOS transistor characterized in that the other impurity-containing material layer in the other transistor is used as a gate electrode material layer
A method for manufacturing a semiconductor device having a transistor and a PMOS transistor, which achieves the above object.

The invention according to claim 2 of the present application is characterized in that after removing the other conductive type impurity-containing material layer of the upper layer, a conductive material is formed, and thereafter, a gate electrode is formed by patterning. A method of manufacturing a semiconductor device having an NMOS transistor and a PMOS transistor according to claim 1 , which achieves the above object.

According to a third aspect of the present invention, in the NM according to the second aspect , the conductive material is silicide.
A method for manufacturing a semiconductor device having an OS transistor and a PMOS transistor, which achieves the above object.

According to the invention of claim 4 of the present application, after forming an impurity-containing material layer having one conductivity type, an intermediate layer for etching stop is successively formed, and then the upper layer has the other conductivity type. 4. A method for manufacturing a semiconductor device having an NMOS transistor and a PMOS transistor according to claim 1, wherein the impurity-containing material layer is formed. Things.

According to a fifth aspect of the present invention, in the NMO according to any one of the first to fourth aspects , the impurity-containing material layer is made of impurity-containing amorphous silicon.
A method of manufacturing a semiconductor device having an S transistor and a PMOS transistor, which achieves the above object.

According to a sixth aspect of the present invention, in the semiconductor device having the NMOS transistor and the PMOS transistor according to any one of the first to fourth aspects , the impurity-containing material layer is an impurity-containing silicide layer. A method of manufacturing a device, which achieves the above object.

According to a seventh aspect of the present invention, there is provided a method of forming a gate insulating film, forming a boron-doped silicon-rich tungsten silicide, and continuously forming a phosphorus-doped tungsten silicide having a higher concentration than the boron concentration.
7. The method for manufacturing a semiconductor device having an NMOS transistor and a PMOS transistor according to claim 6 , wherein the upper layer of phosphorus-doped tungsten silicide is removed by using a mask in which a transistor formation region is opened, and then activation is performed. Accordingly, the above object is achieved.

Each invention of the present application has
This achieves the stated purpose.

The present invention can be preferably carried out in the following modes. That is, the present invention shortens the formation time of the dual gate electrode by forming amorphous silicon in a form in which P ⁺ and N ⁺ dopants are stacked on a semiconductor device having a gate electrode, and maintains the acid resistance to hydrofluoric acid. Subsequently, it can be carried out in such a manner that a silicide can be formed.

After the formation of a gate insulating film such as a gate oxide film, boron-doped amorphous silicon is
Boron concentration 5E19 to 5E20ato with a thickness of 00 nm
m / cm ³ , and then phosphorus-doped amorphous silicon having a thickness of several nm to 400 nm and a concentration higher than the boron concentration.
cm ³ , a mask in which the PMOS transistor formation area is opened is formed by lithography, and the upper layer of phosphorus-doped amorphous silicon is removed by a silicon etching apparatus by a thickness of several nm to 400 nm plus over-etching, and activated in a subsequent process. Silicide (for example, WSix (x is about 2.4 to
2.8) is changed to a tetragonal crystal growth temperature (450 to 700).
° C) and thermal decomposition of DCS (dichlorosilane) and tungsten hexafluoride (WF ₆ ) to a thickness of several nm to 300 nm), and the dual gate electrode is simultaneously formed in one film formation. Can be.

In this case, the gas system for forming the batch-formed amorphous silicon is formed by a conventional thermal decomposition or plasma excitation using a hologen borane boron halide such as phosphine or phosphorus for the conventionally used silane or polysilane. , Can be directly formed in two layers. Alternatively, by sandwiching between non-doped layers or between a low oxygen concentration SIPOS and the like, an etching stop structure can be realized.

Further, according to the present invention, after a gate insulating film such as a gate oxide film is formed, a boron-doped silicon-rich tungsten silicide is formed to a thickness of several nm to 400 nm at a boron concentration of 5E19 to 5E20 atoms / cm ³ at WSix.
(Composition; x to 2.8) is formed, and then phosphorus-doped tungsten silicide is doped with a thickness of several nm to 400 to a concentration higher than the boron concentration by 6E19 to E21 atom / c.
WSix containing m ³ (composition; x is approximately 2-2.
8) Then, a mask in which the PMOS transistor formation region is opened is formed by lithography, and the upper phosphorus-doped tungsten silicide is removed by a silicide etching apparatus by a thickness of several nm to 400 nm plus over-etching. Activation annealing can be performed, whereby the dual gate electrode can be formed simultaneously by one film formation.

In this case, silicon-rich CVD-WSi
The x formation is performed, for example, by using WSix (x is about 2.4 to 2.x).
8) at the tetragonal crystal growth temperature (450 ° C. to 700
), DCS (dichlorosilane) and tungsten hexafluoride (WF ₆ ) are added with boron or phosphine as a dopant and thermally decomposed, and heated from normal pressure to vacuum (450 ° C to 7 ° C).
(00 ° C.), the residual fluorine extraction reaction is performed in the middle of the formation sequence, and fluorine degassing is performed for several layers in the same chamber (or in a multi-chamber).

The silicon-rich silicide is TiS
ix, NiSix and PtSix are also suitable. Also,
The formation method may be a sputtering method, an ECRCVD method, or the use of a high-density plasma source (such as helicon plasma).

[0030]

The NMOS transistor manufactured according to the present invention
And a PMOS transistor, the impurity-containing material layer of the gate electrode of one transistor is formed to have a smaller thickness than the impurity-containing material layer of the gate electrode of the other transistor.
Low resistance can be realized by thinning the gate electrode.

The NMOS transistor and PMOS of the present invention
The method for manufacturing a semiconductor device having a transistor includes forming an impurity-containing material layer having one conductivity type for forming the gate electrodes, and then forming an impurity-containing material layer having the other conductivity type on the upper layer. The gate electrode is formed at a higher concentration than the impurity of one conductivity type, and the other conductive type impurity-containing material layer of the upper layer is removed from the formation region of either the NMOS transistor or the PMOS transistor to form both gate electrodes. Therefore, the film formation of the impurity-containing material layer for forming each gate electrode was performed in a continuous process, and in particular, one of the upper layers was removed, so that
The troublesome film forming process can be performed only once, and thus the process can be simplified.

In addition, with regard to the effect of thinning the gate electrode of the one transistor, this structure makes it possible to obtain this structure without a problem of etching resistance.

[0033]

Embodiments of the present invention will be described below with reference to the drawings. However, needless to say, the present invention is not limited by the following embodiments.

Embodiment 1 In this embodiment, the present invention is applied to the formation of an VLSI MOS device. FIG. 1 shows a semiconductor device of this embodiment, and FIGS. 2 to 9 show steps of this embodiment in order.

First, the structure of the semiconductor device of this embodiment will be described. In this embodiment, as shown in FIG. 1, in a semiconductor device having an NMOS transistor I and a PMOS transistor II on a semiconductor substrate 1 (here, an Si substrate), the gate of one transistor (here, a PMOS transistor II) is provided. The impurity-containing material layer 4b of the electrode is formed to be thinner than the impurity-containing material layer 4a of the gate electrode of the other transistor (here, the NMOS transistor I).
A structure in which a material layer in which an impurity of the other conductivity type is stacked on a material layer in which an impurity of one conductivity type is stacked is formed by removing the upper material layer; and Impurity-Containing Material Layer 4 of Gate Electrode of Transistor
a activates a structure in which a material layer in which the impurity of the other conductivity type is introduced at a higher concentration than that of the impurity of the one conductivity type is stacked on a layer above the material layer into which the impurity of one conductivity type is introduced. It was formed by the above. In FIG. 1, reference numeral 81 denotes an N-type diffusion layer, reference numeral 82 denotes a P-type diffusion layer, and reference numeral 9 denotes an LDD formation side wall spacer.

Next, a method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS.

In this embodiment, an insulating film serving as the gate insulating film 3 is formed on the semiconductor substrate 1 (FIGS. 2 and 3), and then an impurity-containing material layer 41 having one conductivity type is formed. An impurity-containing material layer 42 having the other conductivity type is formed on the lever at a higher concentration than that of the one conductivity type (FIG. 4), and one of an NMOS transistor and a PMOS transistor (here, a PMOS transistor) is formed. In the formation region, the other conductive type impurity-containing material layer 42 of the upper layer is removed (FIGS. 5 and 6), and then activated to activate one of the transistors as shown in FIG. 1 (here, an NMOS transistor). In the above, one conductive type impurity-containing material layer 4a is used as a gate electrode material,
The other transistor (here, a PMOS transistor)
In the above, the other impurity-containing material layer 42 was used as the gate electrode material layer 4b.

In this embodiment, after the step of removing the other conductive type impurity-containing material layer 42 of the upper layer is further performed, a conductive material 6 (here, silicide) is formed (FIG. 7), and then patterned. (FIGS. 8 and 9) A gate electrode is formed.

In this embodiment, the impurity-containing material layer is an impurity-containing amorphous silicon layer.

In this embodiment, after the gate insulating film 3 is formed, boron-doped amorphous silicon is formed to form the material layer 41.
Subsequently, a phosphorus-doped amorphous silicon having a higher concentration than the boron concentration was continuously formed to form a material layer 42. Thereafter, the upper layer of phosphorus-doped amorphous silicon was removed using a mask (FIG. 5) in which a PMOS transistor formation region was opened (FIG. 6), and thereafter silicide was formed without activation annealing (FIG. 7).

In the present embodiment, for a semiconductor device having a gate electrode, p ⁺ and N ⁺ dopants are formed on amorphous silicon in a laminated manner so as to shorten the formation time of the dual gate electrode and reduce the acidity against hydrofluoric acid. This allows the silicide to be subsequently formed while holding.

Hereinafter, the details of the steps of this embodiment will be described more specifically. First, an element isolation region 2 is formed on a Si substrate which is a semiconductor substrate 1 by, for example, an improved LOCOS (a technique of laying a polysilicon buffer and performing selective oxidation using a SiN mask). Each of the P and N wells 1a and 1b is formed by a photoresist mask pattern and ion implantation to complete element isolation, thereby obtaining the structure shown in FIG.

Next, gate oxidation is performed by pyrogenic oxidation at 850 ° C. to a thickness of 10 nm. This oxide film becomes the gate insulating film 3 (FIG. 3).

Next, after the gate insulating film 3 (gate oxide film) is formed, in this embodiment, boron-doped amorphous silicon is deposited to a thickness of several nm to 400 nm and a boron concentration of E19 to 400 nm.
Continuous formed by E21atom / cm ^2, one not so
A pure substance containing material layer 41 is formed, followed by a phosphorus-doped amorphous layer.
Silicon having the same thickness and an impurity-containing material layer 4
1 so that the impurity concentration is higher than the impurity concentration
Form and, which as the other of the impurity-containing material layer 42, FIG.
Get the structure of 4.

Next, as shown in FIG. 5, a resist mask 5 is formed by lithography.

Next, the upper phosphorus-doped amorphous silicon (material layer 42) is over-etched to a thickness of several nm to 400 nm by a silicon etching apparatus (over 10%).
Below) to obtain the structure of FIG.

In a subsequent process, silicide (here, WSix (x is approximately 2.4 to 2.8)) is used as the conductive material 6 at a tetragoral crystal growth temperature (450 to 700 ° C.) without conducting activation annealing in DCS (dichlorosilane). From several nm by thermal decomposition of tungsten hexafluoride (WF ₆ )
It is formed to a thickness of 00 nm to obtain the structure of FIG. Therefore, here, in the step of forming the dual gate electrode, the dual gate electrode can be formed simultaneously by one film formation.

In this embodiment, as the gas system for forming the amorphous silicon film to be formed at once, a silane or polysilane which has been conventionally used can be a halide such as halogen diborane boron such as phosphine or phosphorus. Was performed by ordinary thermal decomposition or plasma excitation, and in this embodiment, two layers (impurity-containing material layers 41 and 42) were directly formed. Alternatively, by sandwiching between non-doped layers or between low oxygen concentration SIPOS or the like, an etching stop structure can be obtained.

In this embodiment, the following gas system was used for film formation. Gas P-DAS; SiH ₄ / PH ₃ / He = 500 in total
sccm 390/10/100 sccm B-DAS; SiH ₄ / B ₂ H ₆ / He = 50 in total
0sccm390 / 10 / 100sccm

Note that instead of SiH ₄ , Si ₂ H ₆ , S
Polysilane such as i ₃ H ₈ ... or organic silane may be used.

[0051] In addition, PCl ₃ in place of PH _3, PBr
_A halogen-based gas containing phosphorus such as ₃ may be used.

Further, a halogen-based gas such as BCl ₃ or BBr ₃ containing boron may be used instead of B ₂ H ₆ .

The other forming conditions were as follows. Forming temperature 570 ° C. to 300 ° C. Forming pressure 0.1 to 100 Torr Excited species Only heat is required. Alternatively, plasma, microwave plasma, helicon wave plasma or the like can be used in combination. Continuous film formation configuration A multi-chamber may be used even in a single wafer in the same chamber in order to improve process stability and mass productivity. Here, they were performed in the same chamber.

It should be noted that p-aSi / n-aSi may be formed in the opposite manner. However, at this time, the mask is inverted so that the upper layer has a higher density.

In this embodiment, more specifically, the formation of the laminated doped amorphous silicon (material layers 41 and 42) is performed by using a gas system: SiH ₄ / PH ₃ total flow rate 500 sccm pressure: 2 Torr temperature: 550 ° C. : P-aSi / n-aSi was continuously formed.

In this embodiment, the p ⁺ layer window opening lithography may be a rough pattern formation (FIG. 5).

The p ⁺ window opening etch back was performed by just etching with a plasma condition of 30 nm.

For the formation of the silicide layer, light etching was performed immediately before, and WSix was formed to a thickness of 100 nm by LPCVD.

The gate dry etching was performed by microwave plasma etching with a selectivity of 40 and overetching of 50%.

According to the present embodiment, in a semiconductor device in which mutually conductive electrode material layers are used as gate materials, films are continuously formed for gate electrodes requiring two kinds of dopants, and thereafter, unnecessary films are formed. Only the part of the dopant is etched back and the process is returned to the normal process, and the process proceeds to the next process as amorphous silicon.Therefore, there is no attack of the hydrofluoric acid gate oxide film by pretreatment etc. Further, in the annealing step for lowering the resistance after the formation of the pattern, the effect of preventing peeling is also brought about, so that manufacturing defects can be reduced. Therefore, it is possible to manufacture as designed and to obtain a high manufacturing yield.

Further, according to the present embodiment, one to two steps can be reduced as compared with the conventional dual gate forming step.

Further, according to the present embodiment, the thickness of the gate material of the NMOS transistor is made different from that of the PMOS transistor for the complementary element composed of the NMOS transistor and the PMOS transistor.
Because the gate material of the transistor is made thicker than that of the PMOS transistor and the n ⁺ concentration is increased by the increased thickness, mutual diffusion and compensation are achieved by annealing, and the threshold voltage of one transistor is affected. Instead, the threshold voltage of the other transistor can be adjusted.

Example 2 In this example, an intermediate layer was formed between the impurity-containing material layers 41 and 42 by partially modifying Example 1. That is, here, to prevent segregation of the dopant at the oxide film interface,
Non-doped a-Si / p-aSi / non-doped a-Si
And

Alternatively, non-doped a-
It may be Si / p-aSi / non-doped a-Si / n-aSi non-doped a-Si.

Further, a non-doped a-layer sandwiching a layer doped with oxygen or nitrogen to such an extent that interdiffusion of oxygen or nitrogen is not prevented.
It can be Si / p-aSi / oxygen-doped a-Si / n-aSi non-doped a-Si.

In the present embodiment, the formation of the intermediate layer provides an etching stop effect and other effects, and for example, the removal of only the upper material layer 41 by etching can be favorably achieved.

Embodiment 3 In this embodiment, after the gate insulating film 3 (gate oxide film) is formed, in this embodiment, boron-doped silicon-rich tungsten silicide is formed with a thickness of several nm to 400 nm and a boron concentration of E19 to E21 atom / cm. ^Then , WSix (composition: x to 2.8) is formed in step 2, and then phosphorus-doped tungsten silicide is deposited at a thickness of several nm to 400 nm to a concentration of phosphorus higher than the boron concentration by E19 to E21 atom / c.
m ² comprises, WSix (composition; x is about 2 to 2.8) continuously formed in the configuration it is, formed by lithography mask opened the PMOS transistor forming region, a phosphorus-doped tungsten silicide layer of a silicide etching apparatus The thickness is removed by several nm to 400 nm plus over-etching, activation annealing is performed in a subsequent process, and in this step, a dual gate electrode is formed simultaneously by one film formation.

More specifically, the film formation of the gate material in this embodiment was performed as follows.

Gas system In Situ P-Doped WSix; WF ₆ /
SiH ₄ / PH ₃ / He = 1000 sccm total
10/880/10 / 100sccm In Situ B-Doped WSix; WF ₆ /
SiH ₄ / B ₂ H ₆ / He = total 1000 sccm
10/1080/10/100 sccm

Note that WCl ₆ may be used instead of WF ₆ .

Instead of SiH ₄ , halogen-based silane such as SiH ₂ Cl, polysilane such as Si ₂ H ₆ , Si ₃ H ₈ ... Or organic silane may be used.

[0072] In addition, PCl ₃ in place of PH _3, PBr
_A halogen containing phosphorus such as ₃ may be used.

Further, a halogen containing boron instead of B ₂ H ₆ may be used.

The other film forming conditions were as follows. Forming temperature 800 ° C. to 250 ° C. Forming pressure 0.1 to 100 Torr Excited species Only heat may be used, or plasma, microwave plasma, helicon wave plasma or the like may be used in combination. Continuous film formation configuration The same chamber or a multi-chamber may be used. Here, automatic transfer was performed using a multi-chamber.

The p-aWSix / n-aWSix may be formed in the opposite manner. However, at this time, the mask is inverted.

As in the second embodiment, non-doped a-S
i / p-aWSix / n-aWSix non-doped aS
The layer structure may be i.

Further, non-doped a-Si / p is used as an etching stop indicator at the interface between different dopants.
The structure can be a-aWSix / non-doped a-Si / n-aWSix non-doped a-Si.

In this embodiment, silicon-rich CVD
-WSix formation is performed by, for example, WSix (x is approximately 2.4
To 2.8) at the tetragonal crystal growth temperature (450 ° C. to 7
(00 ° C.), DCS (dichlorosilane) and tungsten hexafluoride (WF ₆ ) are doped with boron and phosphine as dopants and thermally decomposed, and heated from normal pressure to vacuum (450 ° C.).
(To 700 ° C.), and a drawing reaction of residual fluorine may be performed in the middle of the formation sequence, and fluorine may be degassed by several layers in the same chamber (or in a multi-chamber).

The silicon-rich silicide is TiS
ix, NiSix and PtSix are also suitable. Also,
The formation method may be a sputtering method, an ECRCVD method, or the use of a high-density plasma source (such as helicon plasma).

In this embodiment, the same effects as those of the first embodiment can be obtained, and in particular, since silicon-rich silicide is used, processing can be performed in the same number of steps as a single gate, and the cost merit is high.

[0081]

As described above, according to the present invention , the reliability is improved.
High gate structure can be obtained, manufacturing defects can be reduced, and
Value voltage can be reduced, and these
NMOS transistor achievable with few processes
Of a semiconductor device having a transistor and a PMOS transistor
The manufacturing method can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view showing the steps of manufacturing the semiconductor device of Example 1 in order (1).

FIG. 3 is a sectional view sequentially showing the manufacturing process of the semiconductor device of Example 1 (2).

FIG. 4 is a sectional view sequentially showing the manufacturing process of the semiconductor device of Example 1 (3).

FIG. 5 is a sectional view showing a step of manufacturing the semiconductor device of the first embodiment in order (4).

FIG. 6 is a sectional view showing a step of manufacturing the semiconductor device of Example 1 in order (5).

FIG. 7 is a cross-sectional view sequentially illustrating the manufacturing process of the semiconductor device of the first embodiment (6).

FIG. 8 is a sectional view sequentially showing the manufacturing process of the semiconductor device of Example 1 (7).

FIG. 9 is a sectional view sequentially showing the manufacturing process of the semiconductor device of Example 1 (8).

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate (Si substrate) 2 element isolation region (LOCOS) 3 gate insulating film (gate oxide film) 41 one impurity-containing material layer 4a one impurity-containing gate material 42 the other impurity-containing material layer 4b the other impurity-containing gate Material 5,7 Resist mask 6 Conductive material (silicide)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 27/092 H01L 21/8238 H01L 21/28 H01L 29/78 H01L 21/336

Claims (7)

(57) [Claims] An NMOS transistor and a PMOS are provided on a substrate.
In a method for manufacturing a semiconductor device having a transistor, an insulating film serving as a gate insulating film is formed over a semiconductor substrate, an impurity-containing material layer having one conductivity type is formed, and then the other conductivity type is formed on this upper layer. Forming an impurity-containing material layer having a higher concentration than the one conductivity-type impurity, and removing the other conductive-type impurity-containing material layer of the upper layer in one of the formation regions of the NMOS transistor and the PMOS transistor; Then, by activation, one impurity-containing material layer of one conductivity type is used as a gate electrode material layer in one transistor, and the other impurity-containing material layer is used as a gate electrode material layer in the other transistor. NMO
A method for manufacturing a semiconductor device having an S transistor and a PMOS transistor. 2. After removing the impurity-containing material layer of the other conductivity type of the upper layer, a conductive material, according to claim 1 and thereafter patterned to and forming a gate electrode
13. A method for manufacturing a semiconductor device having the NMOS transistor and the PMOS transistor according to the above. 3. The NMOS transistor and the PMOS transistor according to claim 2 , wherein the conductive material is a silicide.
A method for manufacturing a semiconductor device having a transistor. 4. A structure in which after forming an impurity-containing material layer having one conductivity type, an intermediate layer for etching stop is continuously formed, and an impurity-containing material layer having the other conductivity type is formed thereon. 2. The method according to claim 1, wherein
Through NMOS transistor according to any one of the 3 and the P
A method for manufacturing a semiconductor device having a MOS transistor. It 5. impurity-containing material layer claims 1, characterized in that an amorphous silicon containing impurities 4
13. A method of manufacturing a semiconductor device having the NMOS transistor and the PMOS transistor according to any one of the above. 6. The method of manufacturing a semiconductor device having an NMOS transistor and a PMOS transistor according to claim 1, wherein the impurity-containing material layer is an impurity-containing silicide layer. 7. A boron-doped silicon-rich tungsten silicide is formed after the gate insulating film is formed, a phosphorus-doped tungsten silicide having a concentration higher than the boron concentration is continuously formed, and an upper layer is formed using a mask in which a PMOS transistor formation region is opened. 請 that the removal of the phosphorus-doped tungsten silicide, and carrying out subsequent activation
A method for manufacturing a semiconductor device comprising the NMOS transistor and the PMOS transistor according to claim 6 .