WO2013185397A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2013185397A1
WO2013185397A1 PCT/CN2012/078317 CN2012078317W WO2013185397A1 WO 2013185397 A1 WO2013185397 A1 WO 2013185397A1 CN 2012078317 W CN2012078317 W CN 2012078317W WO 2013185397 A1 WO2013185397 A1 WO 2013185397A1
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Prior art keywords
layer
stress
stress layer
region
soi
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PCT/CN2012/078317
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English (en)
French (fr)
Inventor
朱慧珑
骆志炯
尹海洲
梁擎擎
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中国科学院微电子研究所
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Priority to US14/407,263 priority Critical patent/US9583622B2/en
Publication of WO2013185397A1 publication Critical patent/WO2013185397A1/zh

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    • H01L29/7849—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
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Definitions

  • the present invention relates to the field of semiconductors, and more particularly to a semiconductor structure and a method of fabricating the same. Background technique
  • a common method of increasing stress is to operate in the source and drain regions to create tensile or compressive stresses on the channel.
  • the transistor channel is oriented along the ⁇ 110 ⁇ of silicon.
  • the mobility of the holes is increased; and when the channel is subjected to the groove
  • the tensile stress in the longitudinal direction of the track and/or the compressive stress in the direction perpendicular to the channel increases, the mobility of electrons increases. Therefore, stress is introduced in the channel region of the semiconductor device, and the performance of the device can be improved.
  • the use of a SOI substrate instead of a silicon substrate can also achieve the effect of reducing short channel effects and improving device performance.
  • the Silicon In On-Sulator (SOI) technology introduces a buried oxide layer between the top silicon layer and the sub-layer silicon layer.
  • SOI Silicon In On-Sulator
  • the S0I material has advantages that are incomparable to bulk silicon: dielectric isolation of components in an integrated circuit can be achieved, eliminating parasitic latch-up effects in bulk silicon CMOS circuits;
  • the integrated circuit also has the advantages of small parasitic capacitance, high integration density, high speed, single process, short channel effect and special suitability for low voltage and low power circuits. Therefore, it can be said that S0I will become a deep submicron low voltage. Mainstream technology for low-power integrated circuits.
  • the heterostructure of the SOI creates an opportunity to build devices with ultra-thin silicon bodies.
  • Ultra-thin soi provides an alternative means of controlling short-channel effects through a natural electrostatic barrier established by a silicon dielectric interface.
  • the present invention provides a method of fabricating a semiconductor structure, the method comprising: a) providing a village bottom, sequentially forming a stress layer, a buried oxide layer, and an SOI layer on the bottom of the village;
  • the present invention also provides a semiconductor structure including a substrate, a stress layer, a buried oxide layer, an SOI layer, a source/drain region, a stress layer polysilicon region, a ground layer, and a gate stack. among them:
  • the gate stack is formed over the SOI layer
  • the source/drain regions are formed in the SOI layer and are located on both sides of the gate stack;
  • the stress layer, the buried oxide layer and the SOI layer are sequentially formed on the bottom of the village;
  • the stress layer polysilicon region is located in the stress layer and is located on either side of the gate stack or below the gate stack depending on the device type of the semiconductor structure.
  • the formation of a ground plane in the layer provides favorable stress to the channel of the semiconductor device by introducing a ground layer, which contributes to improving the performance of the semiconductor device.
  • FIG. 1 is a flow diagram of one embodiment of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIG. 2 to 11(b) are cross-sectional structural views showing respective stages of fabrication of the semiconductor structure in the process of fabricating a semiconductor structure in accordance with the flow shown in Fig. 1.
  • first and second features are formed in direct contact
  • additional features formed between the first and second features.
  • first and second features may not be in direct contact.
  • FIG. 1 is a flow chart of a specific embodiment of a method of fabricating a semiconductor structure in accordance with the present invention, the method comprising:
  • Step S101 providing a substrate, sequentially forming a stress layer, a buried oxide layer, and a S0 I layer on the substrate;
  • Step S102 forming a stress layer doped region disposed at a specific position in the stress layer according to a type of the semiconductor device to be formed;
  • Step S103 sequentially forming an oxide layer and a nitride layer on the SOI layer, forming a through-the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, stopping at the a first trench of an upper surface of the stress layer, the first trench exposing at least a portion of the doped region of the stress layer;
  • Step S104 removing the stress layer doped region by the first trench etching to form a cavity;
  • Step S105 filling the cavity with polysilicon, and performing etch back to form a stress layer polysilicon region and a second trench;
  • Step S106 filling the second trench to form an isolation region.
  • Steps S101 to S106 are described below with reference to FIGS. 2 to 11(b), and FIGS. 2 to 11(b) are processes for fabricating a semiconductor structure according to the flow shown in FIG. 1 according to an embodiment of the present invention.
  • Step S101 is performed. As shown in FIG. 2, a village bottom 100 is provided, a stress layer 120 is formed on the village bottom 100, and a buried oxide layer 130 is formed on the stress layer 120 to form on the buried oxide layer 130. S0I layer 140.
  • the semiconductor substrate 100 includes a silicon substrate (eg, a wafer).
  • the semiconductor substrate 100 can include various doping configurations in accordance with design requirements known in the art (e.g., P-type substrate or N-type substrate).
  • Other examples of semiconductor substrate 100 may also include other basic semiconductors, such as faults.
  • the semiconductor substrate 100 may include a compound semiconductor such as silicon carbide, silicon germanium, indium arsenide or indium phosphide.
  • the stress layer 120 may be formed on the substrate 100 by epitaxial growth, preferably using a silicon germanium material, wherein the germanium content is 15% to 30%, for example, 15%, 20% or 30%.
  • the thickness of the stress layer 120 ranges from 10 to 100 nm, for example: 3 ⁇ 4P10 nm, 50 nm or 100 nm.
  • the buried oxide layer 130 can comprise a method formed by thermal oxidation, deposition, and/or other suitable processes.
  • This layer is usually an oxide material, e.g., Gd 2 0 3, TrHf0 4 , Nd 2 0 3, preferably using Si0 2.
  • the thickness of the buried oxide layer 130 ranges from 5 to 20 nm, for example, 5, 13 or 20 nm.
  • the SOI layer 140 is formed on the buried oxide layer 130 using a smart cut technique.
  • the material of the S0I layer 140 is a single crystal silicon, a Ge or a III-V compound such as SiC, gallium arsenide, indium arsenide or indium phosphide.
  • an ultra-thin S0I layer is formed, and the thickness of the SOI layer ranges from 5 to 20 legs, for example, 5 nm, 15 nm or 20 legs.
  • a stress layer doped region disposed at a specific position is formed in the stress layer according to the type of the semiconductor device to be formed.
  • the photoresist 150 is overlaid on the SOI layer 140, and subjected to exposure patterning. After patterning, a portion can be etched, and ion implantation is performed by patterning. If a NMOS device is to be formed, as shown in FIG. 3(a), the photoresist is overlaid on the region where the gate stack 200 will be formed; if a PMOS device is to be formed, as shown in FIG. 3(b), it will be required. The area where the gate stack 200 is formed is exposed, and portions of both sides of the region are covered with the photoresist 150.
  • the material of the photoresist 150 may be an ethylenic monomer material, a material containing an azide compound or a polyethylene laurate material.
  • the stress layer 120 is ion-implanted through the exposed regions of the photoresist 150 using arsenic or phosphorus to form the stress layer doped region 160 disposed at a specific position.
  • the stress layer doping region 160 is located on both sides of the region where the gate stack 200 will be formed: If a PMOS device is to be formed, the stress layer ⁇ District 16 (M Li Qian will form the area of the gate stack 200 Just below the domain.
  • the photoresist 150 is then removed and annealed to activate impurities in the stressor layer 120.
  • Annealing the previously formed semiconductor structure may be used to activate impurities in the semiconductor structure.
  • the semiconductor structure can be annealed using a transient annealing process, such as laser annealing at a high temperature of about 800-110 (TC).
  • step S103 sequentially forming an oxide layer 170 and a nitride layer 180 on the SOI layer 140, forming through the nitride layer 180, the oxide layer 170, the SOI layer 140, and the The buried oxide layer 130 is stopped at a first trench of the upper surface of the stress layer 120, and the first trench exposes at least a portion of the stress layer doped region 160.
  • an oxide layer 170 and a nitride layer 180 are formed on the SOI layer MO.
  • the oxide layer 170 can comprise a method formed by thermal oxidation, deposition, and/or other suitable processes.
  • This layer is usually an oxide material, e.g., Gd 2 0 3, TrHf0 4 , Nd 2 0 3, preferably using Si0 2.
  • the thickness of the oxide layer 170 ranges from 3 to 10 nm, such as 3 nm, 8 nm or 10 nm.
  • nitride layer 180 can also be formed using methods including deposition and/or other suitable processes. The nitride layer thickness in the range of 180 to 50 _ 150nm, e.g. 50nm, 120nm, or 150nm.
  • a nitride material forming this layer is, for example, Si 3 N 4 .
  • Photoresist patterning is performed to etch nitride layer 180, oxide layer 170, S0I layer 140, and buried oxide layer 130 to form a first trench, after which the photoresist is removed. Since the isolation region is formed at the first trench position in the subsequent process, the position and size of the first trench needs to be determined according to the position and size of the isolation region 300. As shown in FIG. 6), the first trench stops at the upper surface of the stress layer doping region 160. As shown in FIG. 6(b), the etching of the first trench stops at the upper surface of the stressor layer 120. In the case of FIG.
  • the first trench exposes a portion of the stress layer doped region 160 as shown in the top view of FIG. 6(c).
  • Step S104 is performed to remove the stress layer doped region 160 by the first trench etch to form a cavity.
  • the etching may be performed from the first trench formed in the foregoing step, as shown in FIGS. 7(a) and 7(b), wherein FIG. 7(b) shows the front and rear from the device (the front is vertical)
  • the first groove of the opposite direction of the paper surface, and vice versa, not shown in the drawing, is etched to form a cavity in the stress layer 120.
  • the etching is performed by wet etching, and the wet etching may be performed by using a solution which selectively etches the doped silicon and does not substantially etch the silicon and the undoped silicon, such as TMAH, K0H or the like.
  • Suitable etchant solution straight [OO 42]
  • the stress layer 160 is removed after doping region, U0 stress layer is at least partially stress is released, and the tensile stress is generated in the layer 140 S0I.
  • the mobility of electrons in the MN device can be effectively increased by introducing tensile stress.
  • FIG. 7(b) after the stress layer doped region 160 is removed, the stress in the stress layer 120 is at least partially released, and compressive stress is generated in the SOI layer 140.
  • the mobility of holes in the PMOS device can be effectively increased by introducing compressive stress.
  • Step S105 is performed, filling the cavity with polysilicon, and performing etch back to form the stress layer polysilicon region 190 and the second trench.
  • the portion under the first trench is etched, the etching depth is smaller than the height of the cavity, and after the etching, the stress layer polysilicon region 190 and the first layer are formed.
  • Two grooves As shown in FIG. 8(b), the filling cavity forms a stress layer polysilicon region 190, and the stress layer 120 is further etched along the position of the first trench, and the etching depth is smaller than the height of the cavity to form a second trench.
  • the etching can be dry or wet engraved.
  • Step S106 is performed to fill the second trench to form an isolation region.
  • the second trench is filled with an oxide, and a planarization process is performed to make the filled oxide flush with the upper surface of the nitride layer 180 (the term "flush" in the present invention refers to the between The height difference is within the range allowed by the process error).
  • the nitride layer 180 and the oxide layer 170 are further etched away to form the isolation region 300 as shown in Figs. 9(a) and 9(b). After the removal of the above two layers, the tensile stress in the SOI layer 140 is further enhanced to help further reduce the short channel effect to improve device performance.
  • the stressor layer 120 of the device is ion implanted from above the device and annealed to activate the impurity to form the ground plane 400.
  • the ground layer 400 may be adjacent to the buried oxide layer 130 and located in the stress layer 120 under the buried oxide layer 130.
  • the length may be between the inner side spacing and the outer side spacing of the isolation area 300 and intermediate the isolation area 300. Whether to use n-type or p-type injection depends on the type of device and the threshold voltage of the device needs to be adjusted up or down.
  • an n-type implant or a p-type implant can be used; for an nFET (n-type field effect transistor), a p-type implant or an n-type implant can also be used.
  • the process of annealing the activated impurities is described in the foregoing and will not be described herein.
  • a gate stack 200 may be formed on the above semiconductor structure, the gate structure 200 being formed as follows: forming a gate dielectric layer covering the SOI layer 140 and the isolation region 300, and a gate metal covering the gate dielectric layer a layer, a gate electrode layer covering the gate metal layer, an oxide layer covering the gate electrode layer, a nitride layer covering the oxide layer, and a photoresist layer covering the nitride layer and used for drawing to etch the gate stack *, the material of the gate dielectric layer may be a thermal deuteration layer, including silicon germanium, niobium Silicon, which may also be a high-k dielectric such as Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , Zr0 2 , LaAlO, or a combination thereof, having a thickness of 1 nm ⁇ 4; between the materials of the
  • the material of the photoresist layer may be an ethylenic monomer material, a material containing an azide quinone compound, or a polyethylene laurate material.
  • the above multilayer structure may be subjected to chemical vapor deposition (CVD), high density plasma CVD, ALD (atomic layer deposition), plasma enhanced atomic layer deposition (PEALD). , pulsed laser deposition (PLD) or other suitable method is sequentially formed on the SOI layer 100.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • PLD pulsed laser deposition
  • the above multilayer structure may be etched to form a gate structure 200 (gate lines are formed on the SOI substrate).
  • sidewalls 210 are formed on both sides of the gate structure 200 for separating the gate structures 200.
  • the sidewall 210 can be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and/or other suitable materials.
  • the side wall 210 may have a multi-layered structure.
  • the sidewall spacers 210 may be formed by a deposition-etch process having a thickness ranging from about 10 nm to 100 nm.
  • the SOI layer 140 on both sides of the gate stack 200 may be shallowly doped to form a source/drain extension region, and Halo implantation may also be performed to form a Halo implant region.
  • the type of shallow doping impurity is consistent with the device type, and the impurity type of Halo implant is opposite to the device type.
  • Source/drain regions 110 may be formed by implanting P-type or N-type dopants or impurities into the substrate 100.
  • the source/drain regions 110 may be P-type doped.
  • the source/drain regions 110 may be N-type doped.
  • Source/drain regions 110 may be formed by methods including photolithography, ion implantation, diffusion, and/or other suitable processes. In the present embodiment, the source/drain regions 110 are internal to the SOI layer 140.
  • the source/drain regions 110 may be elevated source and drain structures formed by selective epitaxial growth, and the epitaxial portion thereof The top is higher than the bottom of the gate stack 200 (the bottom of the gate stack referred to in this specification means the boundary between the gate stack 200 and the SOI layer 140). As shown in Figure 10 (a) and Figure 10 (b).
  • the method of the present embodiment can further form a contact plug 510 and 520, * Specifically, the method includes: forming a dielectric layer 500 covering the gate structure 200 and the SOI layer 140, and forming a first contact hole exposing at least a portion of the ground layer 400 in the dielectric layer 500, and exposing at least a portion of the source/drain regions 110 Two contact holes.
  • Dielectric layer 500 can be formed by CVD, high density plasma CVD, spin coating, or other suitable method.
  • the material of the dielectric layer 500 may include SiO 2 , carbon doped SiO 2 , BPSG, PSG, UGS, silicon oxynitride, a low k material, or a combination thereof.
  • the thickness of the dielectric layer 500 may range from 40 nm to 150 nm, such as 80 nm, 100 nm or 120 nm, and the first contact penetrating through the dielectric layer 500 and the isolation region 300 stops on the ground layer 400 and exposes at least a portion.
  • the second contact hole of the ground layer 400, another dielectric layer 500 extending through the source/drain region 110 exposes at least a portion of the source/drain regions 110.
  • the upper surface of the ground layer 400 may be used as the etching.
  • the first contact hole and the second contact hole are usually filled with metal to form a first contact plug 510 and a second contact plug 520 as shown in Figs. 11(a) and 11(b).
  • the filler metal is W, of course, according to the manufacturing requirements of the semiconductor, and the material of the metal may also be any one of W, Al, TiAl alloy or a combination thereof.
  • FIG. 10 shows a semiconductor structure corresponding to an NMOS device, the semiconductor structure including: a substrate 100, a stress layer 120, a buried oxide layer 130, an SOI layer 140, and source/drain regions. 110.
  • the gate stack 200 is formed over the SO I layer 140;
  • the source/drain regions 110 are formed in the S 01 layer 140 and on both sides of the gate stack 200; [0054] the substrate 100 is sequentially formed with a stress layer 120, a buried oxide layer 130, and S0I layer 140;
  • the stressor polysilicon regions 190 are located in stress layers 120 on both sides of the gate stack 200.
  • FIG. 10(b) shows a semiconductor structure corresponding to a PMOS device, which is different from the abundance structure shown in FIG. 10(a) in the stress layer polysilicon region 19 (M thousand thousand said grid The stress layer 120 under the pole stack 200.
  • the foregoing two semiconductor structures further include side walls 210 formed on two sides of the gate stack 200.
  • the material of the stress layer 120 is silicon fault.
  • the content of germanium in the stress layer 120 is 15%_30%
  • the thickness of the stressor layer 120 ranges from 10 to 100 nm, for example, 10 nm, 50 nm, and 100 nm.
  • the thickness of the buried oxide layer 130 ranges from 5 to 20, for example, 5 nm to 10 nm to 20 nm.
  • the SOI layer 140 has a thickness in the range of 5-20 nm, such as 5 nm 12 nm 20 nm.
  • the thickness of the oxide layer 170 ranges from 3 to 10 nm, for example, 3 nm, 6 nm, and 10 nm.
  • the thickness of the nitride layer 180 ranges from 50 to 150 nm, for example, 50 nm, 110 nm, 150 nm.
  • the semiconductor structure further includes a ground layer 400 adjacent to the buried oxide layer 130 and located in the stress layer 120 under the buried oxide layer 130, wherein the doping type may be n-type or p-type.
  • the semiconductor structure further includes: a dielectric layer 500 and a first contact plug 510 and a second contact plug 520, wherein: the dielectric layer 500 covers the SOI layer 140, the isolation region 300, and The interlayer dielectric layer 500 of the gate structure 200; the first contact plug 510 penetrates the dielectric layer 500 and the isolation region 300, and is in contact with the ground layer 400; the second contact plug 520 runs through the The dielectric layer 500 is in contact with the source/drain regions 110.
  • the method of introducing stress can effectively reduce the short channel effect of the device and improve the performance of the device.

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Abstract

本发明提供了一种半导体结构及其制造方法，该方法包括提供衬底，在衬底上形成应力层，埋氧层，SOI层；在应力层中形成位于特定位置的应力层掺杂区；在SOI层上形成氧化物层和氮化物层，并刻蚀氮化物层、氧化物层、SOI层和埋氧层，停止于应力层上表面，形成至少暴露所述应力层掺杂区的一部分的第一沟槽；通过第一沟槽采用湿法刻蚀去除应力层掺杂区，形成空腔；向空腔中填充多晶硅并进行回刻蚀，形成应力层多晶硅区和第二沟槽；填充第二沟槽形成隔离区。本发明提供的半导体结构及其制造方法通过引入应力层以及根据器件类型设置在其中的特定位置的应力引发区，为半导体器件的沟道提供了有利应力，有助于提升半导体器件的性能。

Description

半导体结构及其制造方法
[0001 ]本申请要求了 2012年 6月 12日提交的、 申请号为 201210192523. 1、 发 明名称为 "半导体结构及其制造方法" 的中国专利申请的优先权， 其全部内 容通过引用结合在本申请中。 技术领域
[0002]本发明涉及半导体领域， 具体地说涉及一种半导体结构及其制造方 法。 背景技术
[0003]随着半导体器件制造技术的发展，具有更高性能和更强功能的集成电 路要求更大的元件密度， 而且各个部件、 元件之间或各个元件自身的尺寸、 大小和空间也需要进一步缩小， 因此半导体器件制造过程中对工艺控制的要 求较高。
[0004]半导体器件通过按比例缩小来实现更大的集成度。 M0S晶体管的沟道 长度也在不断地按比例缩短， 但当 M0S晶体管的沟道长度变得非常短时， 所 谓的短沟道效应（ SCE ),以及漏极感应势垒降低效应（ Dra in-Induced Barr i er Lower ing , DIBL )给半导体器件微型化设置了严重的障碍。
[0005]由于短沟道效应会使器件性能劣化， 甚至无法正常工作， 因此减小短 沟道效应是半导体器件研究制造中的重要课题。半导体器件内部的机械应力 被广泛地用于调节器件的性能， 通过在沟道施加应力的方法， 可以改善短沟 道效应。
[0006]常用的增加应力的方法是在源漏区进行操作， 以便在沟道上形成拉伸 或压缩应力。 例如， 在通用硅技术中， 晶体管沟道沿着硅的 {110}取向。 在 这种布置中， 当沟道受到沿着沟道长度方向的压缩应力和 /或沿着与沟道垂 直方向的拉伸应力时， 空穴的迁移率提高； 而当沟道受到沿着沟道长度方向 的拉伸应力和 /或沿着与沟道垂直方向的压缩应力时， 电子的迁移率增高。 因此在半导体器件的沟道区引入应力， 可以提高器件的性能。 [0007]使用 SOI村底代替硅村底也可以达到减小短沟道效应和提高器件性能 的效果。 绝缘体上硅 ( S i l icon On Insulator , SOI )技术是在顶部硅层和 村底体硅层之间引入了一层埋氧层。 通过在绝缘体上形成半导体薄膜， S0I 材料具有了体硅所无法比拟的优点： 可以实现集成电路中元器件的介质隔 离， 消除了体硅 CMOS电路中的寄生闩锁效应； 采用这种材料制成的集成电路 还具有寄生电容小、 集成密度高、 速度快、 工艺筒单、 短沟道效应小及特别 适用于低压低功耗电路等优势， 因此可以说 S0I将有可能成为深亚微米的低 压、 低功耗集成电路的主流技术。
[0008]同时， S0I的异质结构为建造具有超薄硅体器件创造了机会。 通过由 硅电介质界面建立的天然静电屏障， 超薄 soi提供一种控制短沟道效应的可 选手段。
[0009]目前， 有技术采用在超薄 SOI M0S晶体管 ( Ul trathin-SOI M0SFET ) 的超薄 BOX层中形成一个接地层来减小短沟道效应， 并控制功耗。 但是很难 在这种器件上施加较大的应力从而改善器件的性能。 发明内容
[0010]本发明的目的在于提供一种半导体结构及其制造方法， 增加应力， 有 效控制短沟道效应， 提高器件的性能。
[0011]—方面， 本发明提供了一种半导体结构的制造方法， 该方法包括： a ) 提供村底， 在所述村底上依次形成应力层， 埋氧层， S0I层；
b ) 根据将要形成的半导体器件的类型，在所述应力层中形成布置在特定 位置的应力层掺杂区；
c ) 在所述 S0I层上依次形成氧化物层和氮化物层， 形成贯穿所述氮化物 层、 所述氧化物层、 所述 S0I层和所述埋氧层， 停止于所述应力层的上表面 的第一沟槽， 所述第一沟槽至少暴露所述应力层掺杂区的一部分；
d ) 通过所述第一沟槽刻蚀去除所述应力层掺杂区， 形成空腔；
e ) 向所述空腔中填充多晶硅， 并进行回刻蚀， 形成应力层多晶硅区和第 二沟槽；
f ) 埴充第二沟槽以形成隔离区 [0012]相应地， 本发明还提供了一种半导体结构， 该半导体结构包括村底、 应力层、 埋氧层、 S0I层、 源 /漏区、 应力层多晶硅区、 接地层、 栅极堆叠， 其中：
[0013]所述栅极堆叠形成在所述 S0I层之上；
[0014]所述源 /漏区形成于所述 S0I层之中且位于所述栅极堆叠两侧；
[0015]所述村底上依次形成有应力层、 埋氧层和 S0I层；
[0016]所述应力层多晶硅区位于所述应力层中，并且根据半导体结构的器件 类型位于所述栅极堆叠两侧或所述栅极堆叠下方。 层中形成接地层， 通过引入接地层为半导体器件的沟道提供了有利应力， 有 助于提高半导体器件的性能。 附图说明
[0018]通过阅读参照以下附图所作的对非限制性实施例所作的详细描述，本 发明的其它特征、 目的和优点将会变得更明显：
[0019]图 1为根据本发明的半导体结构的制造方法的一个具体实施方式的流 程图；
[0020]图 2—图 11 ( b )是根据本发明的按照图 1示出的流程制造半导体结构过 程中该半导体结构各个制造阶段的剖视结构示意图。
[0021]附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0022]为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本 发明的实施例作详细描述。
[0023]下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其 中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功 能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明， 而不能解释为对本发明的限制。
「00241下文的公开拔供了许多不同的实施例或例子用夹实现^^明的不同 结构。 为了筒化本发明的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在 不同例子中重复参考数字和 /或字母。 这种重复是为了筒化和清楚的目的， 其本身不指示所讨论各种实施例和 /或设置之间的关系。 此外， 本发明提供 了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其 他工艺的可应用于性和 /或其他材料的使用。 另外， 以下描述的第一特征在 第二特征之 "上"的结构可以包括第一和第二特征形成为直接接触的实施例， 也可以包括另外的特征形成在第一和第二特征之间的实施例， 这样第一和第 二特征可能不是直接接触。 应当注意， 在附图中所图示的部件不一定按比例 绘制。本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限 制本发明。
[0025]请参考图 1 , 图 1是根据本发明的半导体结构的制造方法的一个具体实 施方式的流程图， 该方法包括：
[0026]步骤 S101 , 提供衬底， 在所述衬底上依次形成应力层， 埋氧层， S0 I 层；
[0027]步骤 S102 , 根据将要形成的半导体器件的类型， 在所述应力层中形成 布置在特定位置的应力层掺杂区；
[0028]步骤 S103 , 在所述 S0I层上依次形成氧化物层和氮化物层， 形成贯穿 所述氮化物层、 所述氧化物层、 所述 S0I层和所述埋氧层， 停止于所述应力 层的上表面的第一沟槽， 所述第一沟槽至少暴露所述应力层掺杂区的一部 分；
[0029]步骤 S104 ,通过所述第一沟槽刻蚀去除所述应力层掺杂区，形成空腔； [0030]步骤 S105 , 向所述空腔中填充多晶硅， 并进行回刻蚀， 形成应力层多 晶硅区和第二沟槽；
[0031 ]步骤 S106 , 填充第二沟槽以形成隔离区。
[0032]下面结合图 2至图 11 ( b )对步骤 S101至步骤 S106进行说明， 图 2至图 11 ( b )是根据本发明的一个具体实施方式按照图 1示出的流程制造半导体结 构过程中该半导体结构各个制造阶段的剖视结构示意图。 需要说明的是， 本 ^明各个实施例的附图仅是为了示意的目的， 因此没有必要按比例绘制 [0033]执行步骤 S101, 如图 2所示， 提供村底 100, 在村底 100上形成应力层 120,在所述应力层 120上形成埋氧层 130,在所述埋氧层 130上形成 S0I层 140。 在本实施例中， 半导体村底 100包括硅村底（例如晶片） 。 根据现有技术公 知的设计要求（例如 P型村底或者 N型村底） ， 半导体村底 100可以包括各种 掺杂配置。 其他例子的半导体村底 100还可以包括其他基本半导体， 例如错。 或者， 半导体村底 100可以包括化合物半导体， 例如碳化硅、 锗化硅、 砷化 铟或者磷化铟。
[0034]应力层 120可以采用外延生长的方式形成于所述村底 100上，其优选采 用硅锗材料， 其中， 锗的含量为 15%_30%, 例如 15%、 20%或 30%。 应力层 120 的厚度范围为 10—lOOnm, 例: ¾Pl0nm、 50nm或 100nm。
[0035]埋氧层 130可以包括由热氧化、 沉积和 /或其他合适工艺的方法形成。 该层通常采用氧化物材料形成， 例如， Gd203, TrHf04, Nd203, 优选地， 采用 Si02。 埋氧层 130的厚度范围为 5_20nm, 例如 5謹、 13謹或 20nm。
[0036]采用智能剥离技术（ Smart cut technique )在埋氧层 130上形成 SOI 层 140。 S0I层 140的材料是单晶硅、 Ge或 III-V族化合物 （如 SiC、 砷化镓、 砷化铟或磷化铟等）。本发明中形成超薄 S0I层， S0I层的厚度范围为 5_20腿， 例如 5nm、 15nm或 20腿。
[0037]执行步骤 S102, 根据将要形成的半导体器件的类型， 在所述应力层中 形成布置在特定位置的应力层掺杂区。 首先， 将光刻胶 150覆盖于 S0I层 140 上， 并进行曝光构图， 构图后可以刻蚀掉一部分， 通过构图图形进行离子注 入。 如果要形成匪 OS器件， 则如图 3 (a)所示， 将光刻胶覆盖于将形成栅极 堆叠 200的区域； 如果要形成 PM0S器件， 则如图 3 (b)所示， 将需要形成栅 极堆叠 200的区域暴露， 用光刻胶 150覆盖该区域两侧部分。 光刻胶 150的材 料可是烯类单体材料、 含有叠氮醌类化合物的材料或聚乙烯月桂酸酯材料 等。
[0038]之后， 采用砷或磷通过光刻胶 150暴露区域对应力层 120进行离子注 入， 形成布置在特定位置的应力层掺杂区 160。 如图 4 (a)和图 4 (b)所示， 如果要形成匪 OS器件， 则应力层掺杂区 160位于将形成栅极堆叠 200的区域两 侧： 如果要形成 PM0S器件， 则应力层揍 区 16(M立千将形成栅极堆鲁 200的区 域正下方。 之后去除光刻胶 150, 并进行退火以激活应力层 120中的杂质。 对 之前形成的半导体结构进行退火处理，例如可以采用激光退火、闪光退火等， 来激活半导体结构中的杂质。 在一个实施例中， 可以采用瞬间退火工艺对半 导体结构进行退火， 例如在大约 800- 110 (TC的高温下进行激光退火。
[0039]执行步骤 S103, 在所述 S0I层 140上依次形成氧化物层 170和氮化物层 180, 形成贯穿所述氮化物层 180、 所述氧化物层 170、 所述 S0I层 140和所述 埋氧层 130, 停止于所述应力层 120的上表面的第一沟槽， 所述第一沟槽至少 暴露所述应力层掺杂区 160的一部分。 参考图 5 )和图 5 (b) , 在 SOI层 MO 上形成氧化物层 170和氮化物层 180。 氧化物层 170可以包括由热氧化、 沉积 和 /或其他合适工艺的方法形成。该层通常采用氧化物材料形成，例如， Gd203, TrHf04, Nd203, 优选地， 采用 Si02。 氧化物层 170的厚度范围为 3_10nm, 例如 3nm、 8nm或 10nm。 相似地， 氮化物层 180也可以采用包括沉积和 /或其他合适 工艺的方法形成。 氮化物层 180的厚度范围为 50_150nm, 例如 50nm、 120nm或 150nm。 形成该层的氮化物材料例如 Si3N4。
[0040]进行光刻胶构图， 刻蚀氮化物层 180、 氧化物层 170、 S0I层 140以及埋 氧层 130, 以形成第一沟槽， 之后去除光刻胶。 由于在后续工艺中， 在该第 一沟槽位置形成隔离区， 因此该第一沟槽的位置和大小需要根据隔离区 300 的位置和大小而定。 如图 6 )所示， 第一沟槽停止于应力层掺杂区 160的 上表面。 如图 6 (b)所示， 刻蚀第一沟槽停止于应力层 120的上表面。 在图 6 (b)的情况中， 尽管只示出了与纸面方向垂直延伸的第一沟槽， 应当理解， 在与纸面方向垂直的方向上， 还可以存在与纸面方向平行延伸的第一沟槽， 其暴露应力层掺杂区 160的一部分， 如图 6 (c) 的俯视图所示。
[0041]执行步骤 S104, 通过所述第一沟槽刻蚀去除所述应力层掺杂区 160, 形成空腔。 可以从前述步骤中形成的第一沟槽处进行刻蚀， 如图 7 (a)和图 7 (b)所示， 其中图 7 (b)示出了从该器件的前后方（前方为垂直纸面正对 的方向， 后方反之， 图中未示出） 的第一沟槽进行刻蚀， 在应力层 120中形 成空腔。 此处刻蚀选用湿刻的方式， 湿刻可以采用包括对掺杂的硅错有选择 性的刻蚀而对硅和未掺杂的硅错基本不刻蚀的溶液， 例如 TMAH、 K0H或其他 合适的刻蚀剂溶液„ [OO42]对于图 7 (a)的情况， 应力层掺杂区 160去掉后， 应力层 U0中的应力 会至少部分得到释放， 并且， 在 S0I层 140中产生拉应力。 通过引入拉应力可 以有效增加丽 OS器件中电子的迁移率。 对于图 7 (b)的情况， 应力层掺杂区 160去掉后， 应力层 120中的应力会至少部分得到释放， 并且， 在 S0I层 140中 产生压应力。 通过引入压应力可以有效增加 PM0S器件中空穴的迁移率。
[0043]执行步骤 S105, 向所述空腔中填充多晶硅， 并进行回刻蚀， 形成应力 层多晶硅区 190和第二沟槽。 如图 8 (a)所示， 多晶硅填充空腔后， 对其位 于第一沟槽下方的部分进行刻蚀， 刻蚀深度小于空腔的高度， 刻蚀后， 形成 应力层多晶硅区 190和第二沟槽。 如图 8 (b)所示， 填充空腔形成应力层多 晶硅区 190, 沿着第一沟槽的位置继续刻蚀应力层 120, 刻蚀深度小于空腔的 高度， 形成第二沟槽。 刻蚀可以采用干刻或者湿刻。
[0044]执行步骤 S106, 填充第二沟槽以形成隔离区。 向第二沟槽中填充氧化 物，并执行平坦化处理，使所填充的氧化物与氮化物层 180的上表面齐平（本 发明中的术语 "齐平"指的是两者之间的高度差在工艺误差允许的范围内）。 进一步刻蚀掉氮化物层 180和氧化物层 170, 形成隔离区 300, 如图 9 (a)和 图 9 (b)所示。 在去除上述两层之后， S0I层 140中的拉应力会进一步增强， 有助于进一步减小短沟道效应， 以提高器件性能。
[0045]可选的， 从器件上方对所述器件的应力层 120进行离子注入， 并退火 激活杂质形成接地层 400。接地层 400可以紧邻埋氧层 130而位于埋氧层 130下 方的应力层 120中， 其长度可以介于隔离区 300的内侧间距与外侧间距之间， 且居于隔离区 300中间。 根据器件的类型以及器件阈值电压需要调高或是调 低来决定使用 n型注入还是 p型注入。 例如对于 pFET (p型场效应晶体管） ， 可以采用 n型注入或 p型注入； 对于 nFET (n型场效应晶体管） ， 也可以采用 p 型注入或 n型注入。 退火激活杂质的工艺在前文中有所描述， 在此不再赘述。
[0046]之后， 可以在上述半导体结构上形成栅极堆叠 200, 该栅极结构 200的 形成过程如下： 形成覆盖 S0I层 140和隔离区 300的栅极介质层、 覆盖栅极介 质层的栅金属层、 覆盖栅金属层的栅电极层、 覆盖栅电极层的氧化物层、 覆 盖氧化物层的氮化物层、 以及覆盖氮化物层并用于绘图以刻蚀出栅极堆叠的 光刻胶层„ *中， 栅极介 f层的材料可以是热氳化层， 包括氳化硅、 氮氳化 硅，也可为高 K介质，例如 Hf02、 HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1203、 La203、 Zr02、 LaAlO中的一种或其组合， 其厚度在 lnm ~ 4謹之间； 栅金属层 的材料可以选用 TaC、 TiN、 TaTbN, TaErN、 TaYbN、 TaSiN、 HfSiN, MoSiN、 RuTax、 NiTa中的一种或其组合， 其厚度在 5nm _ 20腿之间； 栅电极层的材料 可以选用 Poly_Si, 其厚度在 20nm_80nm之间； 氧化物层的材料是 Si02, 其厚 度在 5nm _10nm之间； 氮化物层的材料是 Si 3N4, 其厚度在 10nm _50nm之间； 光刻胶层的材料可是烯类单体材料、含有叠氮醌类化合物的材料或聚乙烯月 桂酸酯材料等。 上述多层结构中除所述光刻胶层以外， 可以通过化学气相沉 积 （Chemical vapor deposition , CVD ) 、 高密度等离子体 CVD、 ALD (原 子层淀积） 、 等离子体增强原子层淀积（PEALD) 、 脉沖激光沉积（PLD)或 其他合适的方法依次形成在 S0I层 100上。 光刻胶层构图后可以刻蚀上述多层 结构形成栅极结构 200 (在所述 S0I衬底上形成栅极线） 。 通常地， 可以考虑 在栅极结构 200形成后， 在该栅极结构 200的两侧形成侧墙 210 , 用于将栅极 结构 200隔开。 侧墙 210可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅和 /或其 他合适的材料形成。 侧墙 210可以具有多层结构。 侧墙 210可以通过沉积-刻 蚀工艺形成， 其厚度范围大约是 10nm- 100nm。
[0047]可选地， 在形成侧墙 210之前， 可以对栅极堆叠 200两侧的 S0I层 140进 行浅掺杂， 以形成源漏延伸区， 还可以进行 Halo注入， 以形成 Halo注入区。 其中浅掺杂的杂质类型与器件类型一致， Halo注入的杂质类型与器件类型相 反。
[0048]进一步形成源 /漏区 110, 可以通过向衬底 100中注入 P型或 N型掺杂物 或杂质而形成， 例如， 对于 PM0S来说， 源 /漏区 110可以是 P型掺杂， 对于丽 OS 来说， 源 /漏区 110可以是 N型掺杂。 源 /漏区 110可以由包括光刻、 离子注入、 扩散和 /或其他合适工艺的方法形成。在本实施例中，源 /漏区 110在 S0I层 140 内部， 在其他一些实施例中， 源 /漏区 110可以是通过选择性外延生长所形成 的提升的源漏极结构， 其外延部分的顶部高于栅极堆叠 200底部 （本说明书 中所指的栅极堆叠底部意指栅极堆叠 200与 S0I层 140的交界线）。如图 10 ( a ) 和图 10 (b)所示。
「00491可选的， 本实施例撻供的方法还可以进一奇形成接触塞 510和 520, * 具体包括： 形成覆盖栅极结构 200和 SOI层 140的介质层 500, 并分别在该介质 层 500中形成暴露至少部分接地层 400的第一接触孔， 以及暴露至少部分源 / 漏区 110的第二接触孔。 介质层 500可以通过 CVD、 高密度等离子体 CVD、 旋涂 或其他合适的方法形成。介质层 500的材料可以包括 Si02、碳掺杂 Si02、 BPSG、 PSG、 UGS、 氮氧化硅、 低 k材料或其组合。 对该介质层 5QQ进行 CMP处理后， 通常介质层 500的厚度范围可以是 40nm_150nm, 如 80nm、 lOOnm或 120nm, 贯 穿介质层 500以及隔离区 300的第一接触停止在接地层 400上并暴露至少部分 接地层 400, 另一贯穿源 /漏区 110之上的介质层 500的第二接触孔暴露至少部 分源 /漏区 110。 在一次使用干法刻蚀、 湿法刻蚀或其他合适的刻蚀方式刻蚀 介质层 500形成第一接触孔和第二接触孔的过程中， 可以将接地层 400的上平 面作为刻蚀第一接触孔的停止层， 同时将源 /漏区 110的上平面作为刻蚀第二 接触孔的停止层， 因此刻蚀第一接触孔和第二接触孔都分别具有对应的停止 层， 这样对刻蚀工艺的控制性要求降低， 即降低了刻蚀的难度。 后续加工中 通常在第一接触孔和第二接触孔内填充金属， 形成第一接触塞 510和第二接 触塞 520, 如图 11 (a)和图 11 (b)所示。 优选地， 填充金属为 W, 当然才艮据 半导体的制造需要， 所述金属的材料还可以选用 W、 Al、 TiAl合金中任一种 或其组合。
[0050]由于本发明提供的半导体结构具有几种优选结构，下面提供一种优选 结构并进行概述。
[0051]参考图 10 ) , 图 10 )示出了一种与 NM0S器件对应的半导体结构， 该半导体结构包括： 衬底 100、 应力层 120、 埋氧层 130、 S0I层 140、 源 /漏区 110、 应力层多晶硅区 190和栅极堆叠 200, 其中：
[0052]所述栅极堆叠 200形成在所述 SO I层 140之上；
[ 0053 ]所述源 /漏区 110形成于所述 S 01层 140之中且位于栅极堆叠 200两侧； [0054]所述衬底 100上依次形成有应力层 120、 埋氧层 130和 S0I层 140;
[0055]对于 NM0S器件，所述应力层多晶硅区 190位于所述栅极堆叠 200两侧的 应力层 120中。
[0056]参考图 10 (b) , 图 10 (b)示出了一种与 PM0S器件对应的半导体结构， 与图 10 ( a )示出的丰异体结构区別在千所述应力层多晶硅区 19 (M立千所述栅 极堆叠 200下方的所述应力层 120中。
[0057]可选的， 上述两种半导体结构还包括形成于所述栅极堆叠 200两侧的 侧墙 210
[0058]优选的， 所述应力层 120的材料为硅错。 其中， 所述应力层 120中锗的 含量为 15%_30%
[0059]所述应力层 120的厚度范围为 10—lOOnm, 例如 10nm 50nm 100nm。 所 述埋氧层 130的厚度范围为 5_20 例如 5nm 10nm 20nm。 所述 SOI层 140的 厚度范围为 5_20nm, 例如 5nm 12nm 20nm。 所述氧化物层 170的厚度范围为 3~10nm, 例如 3nm 6nm 10nm。 所述氮化物层 180的厚度范围为 50_150nm, 例如 50nm 110nm 150nm
[0060]可选的， 所述半导体结构还包括接地层 400, 其紧邻埋氧层 130而位于 埋氧层 130下方的应力层 120中， 其中掺杂类型可以为 n型或 p型。
[0061]可选的， 所述半导体结构还包括： 介质层 500以及第一接触塞 510和第 二接触塞 520, 其中： 所述介质层 500覆盖所述 S0I层 140、 所述隔离区 300和 所述栅极结构 200的层间介质层 500; 所述第一接触塞 510贯穿所述介质层 500 以及隔离区 300, 与所述接地层 400相接触； 所述第二接触塞 520贯穿所述介 质层 500, 与所述源 /漏区 110相接触。
[0062]采用本发明提供的制造方法，通过引入应力的方法可以有效减小器件 的短沟道效应， 提高器件的性能。
[0063]虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发 明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施例进行 各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理 解在保持本发明保护范围内的同时， 工艺步骤的次序可以变化。
[0064]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作 为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发 出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本 发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发 明可以对它们进行应用„ 因此， ^^明所附权利要 ^旨在将这些工艺、机构、 制造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1.一种半导体结构的制造方法， 其特征在于， 包括以下步骤：
a )提供村底（ 100 ) , 在所述村底（ 100 )上依次形成应力层（ 120 ) , 埋氧层（130) , S0I层（140) ；
b)根据将要形成的半导体器件的类型， 在所述应力层（120) 中形成布 置在特定位置的应力层掺杂区 （160) ；
c )在所述 S0I层（ )上依次形成氧化物层（ Π0 )和氮化物层（ 180 ) , 形成贯穿所述氮化物层（180) 、 所述氧化物层（170) 、 所述 S0I层（140) 和所述埋氧层（130) , 停止于所述应力层（120)的上表面的第一沟槽， 所 述第一沟槽至少暴露所述应力层掺杂区 （160) 的一部分；
d)通过所述第一沟槽刻蚀去除所述应力层掺杂区 （160) , 形成空腔； e )向所述空腔中填充多晶硅，并进行回刻蚀，形成应力层多晶硅区（ 190 ) 和第二沟槽；
f )填充第二沟槽以形成隔离区 （ 300 ) 。
2.根据权利要求 1所述的方法，在步骤 f )之后还包括在所述应力层（ 120 ) 和所述应力层多晶硅区 （190) 中形成接地层（ 400 ) 。
3.根据权利要求 1所述的方法， 在步骤 b) 中， 如果要形成的半导体器件 为丽 OS, 则应力层掺杂区 （160)布置在将要在 S0I层（140) 中形成的半导 体器件的沟道区下方两侧的应力层中。
4.根据权利要求 1所述的方法， 在步骤 b) 中， 如果要形成的半导体器件 为 PM0S, 则应力层掺杂区 （160)布置在将要在 S0I层（140) 中形成的半导 体器件的沟道区正下方的应力层中。
5.根据权利要求 1所述的方法， 在步骤 b) 中应力层掺杂区 （160) 的掺 杂为 n型掺杂。
6.根据权利要求 1所述的方法， 其中， 采用智能剥离技术形成所述 S0I层 ( 140) 。
7.根据权利要求 2所述的方法， 其中， 采用离子注入和退火工艺形成所 述接地层（400) 。
8.根据权利要求 1所述的方法， 其中， 所述应力层（120)的材料为硅错。
9.根据权利要求 7所述的方法， 其中， 所述应力层（120) 中锗的含量为 15%—30%。
10.根据权利要求 1所述的方法， 在步骤 f )之后还包括去除氧化物层
( 170)和氮化物层（180) 。
11.根据权利要求 1所述的方法， 在步骤 f )之后还包括形成位于 S0I层之 上的栅极堆叠 （ 200 )和位于栅极堆叠 （ 200 ) 两侧的源 /漏区 （110) 。
U.—种半导体结构包括： 衬底（100)、应力层（U0)、埋氧层（130)、 S0I层（ 140)、 源 /漏区（ 110)、应力层多晶硅区（ 190)和栅极堆叠（200 ) , 其中：
所述栅极堆叠 （200 )形成在所述 S0I层（MO)之上；
所述源 /漏区 （110)形成于所述 S0I层（140)之中且位于所述栅极堆叠 ( 200 ) 两侧；
所述衬底（100)上依次形成有应力层（U0) 、 埋氧层（ O)和 S0I层
( 140) ；
所述应力层多晶硅区 （190)位于所述应力层（120) 中， 并且根据半导 体结构的器件类型位于所述栅极堆叠（ 200 )两侧或所述栅极堆叠（ 200 )下 方。
13.根据权利要求 12所述的结构， 其中如果形成的半导体器件为丽 OS, 则应力层多晶硅区（ 190 )布置在所述栅极堆叠（ 200 )两侧的所述应力层（ 120 ) 中。
14.根据权利要求 12所述的结构， 其中如果形成的半导体器件为 PM0S, 则应力层多晶硅区（ 190 )布置在所述栅极堆叠（ 200 )下方的所述应力层（ 120 ) 中。
15.根据权利要求 12所述的结构， 还包括接地层， 其紧邻埋氧层（130) 而位于埋氧层（130) 下方的应力层（120) 中。
16.根据权利要求 15所述的结构， 其中接地层的掺杂类型为 n型或 p型。
17.根据权利要求 12所述的结构, 其中， 所述应力层（120 )的材料为硅 锗。
18.根据权利要求 17所述的结构, 其中， 所述应力层（120 ) 中锗的含量 为 15%—30%。
PCT/CN2012/078317 2012-06-12 2012-07-06 半导体结构及其制造方法 WO2013185397A1 (zh)

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