WO2013159409A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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Publication number
WO2013159409A1
WO2013159409A1 PCT/CN2012/075605 CN2012075605W WO2013159409A1 WO 2013159409 A1 WO2013159409 A1 WO 2013159409A1 CN 2012075605 W CN2012075605 W CN 2012075605W WO 2013159409 A1 WO2013159409 A1 WO 2013159409A1
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Prior art keywords
heavily doped
layer
buried layer
surface active
doped buried
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PCT/CN2012/075605
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English (en)
French (fr)
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尹海洲
朱慧珑
骆志炯
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中国科学院微电子研究所
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Priority to US14/397,558 priority Critical patent/US20150084130A1/en
Publication of WO2013159409A1 publication Critical patent/WO2013159409A1/zh

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    • H—ELECTRICITY
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
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    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78612—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

Definitions

  • the present invention relates to the field of semiconductor fabrication, and more particularly to a semiconductor structure and a method of fabricating the same. Background technique
  • CMOS devices fabricated using silicon-on-insulator have many advantages such as high speed, low power consumption, high integration, anti-irradiation and no self-locking effects, and have become the preferred structure for deep sub-micron and nano-scale MOS devices.
  • SOI MOS devices are classified into two types, partially depleted and fully depleted SOI MOS, based on the comparison of the thickness of the silicon film and the maximum thickness of the surface depletion layer. The top-end silicon film of the fully depleted SOI MOS is thinner, and the cost of the SOI substrate is higher. Currently, the SOI MOS is partially depleted.
  • the maximum thickness of the surface depletion layer is less than the thickness of the top layer, so that the body region is in a floating state, and the strong electric field at the drain end accelerates the carriers in the channel, causing a collision current and exciting the electrons.
  • - hole pairs The newly generated electron-hole pairs are separated by a strong electric field, and electrons are collected by the drain end, and the holes are collected in the bottom of the village near the drain end and the buried oxygen layer, causing a floating body effect.
  • the floating body effect causes the charge in the body region to accumulate, and the potential increases accordingly, causing the threshold voltage of the MOS device to decrease and the output current to increase, that is, the current warping Kink effect.
  • the floating body effect can also cause device performance and reliability issues such as sub-threshold slope anomaly, source-drain breakdown voltage reduction. Therefore, the floating body effect should be avoided as much as possible in device design and fabrication.
  • a commonly used method for suppressing the effect of the attached body is to use a body contact to connect the body to a fixed potential (source or ground), and to provide a discharge path for accumulating charges in the body region to reduce the body potential.
  • This method increases the complexity of the fabrication process, resulting in other parasitic effects, and increases the circuit area.
  • the short channel effect becomes more and more significant, and even becomes a dominant factor affecting performance.
  • Short channel effects cause deterioration in the electrical performance of the device, such as a drop in gate threshold voltage, increased power consumption, and reduced signal-to-noise ratio.
  • a very steep inverted doped well is introduced into the semiconductor field effect device.
  • the ultra-steeply doped well has a low-level (or low-high) channel doping profile, the channel surface area maintains a low doping concentration, and a high doping is formed in a region below the channel surface by a suitable method such as ion implantation.
  • U.S. Patent No. 7,002,214 describes an ultra-steeply doped well field effect device for ultra-thin silicon-on-insulator. As shown in Fig. 1, a heavily doped region 33L/33R is formed on the silicon film of the bottom of the S0I by ion implantation, and then an ultrathin intrinsic epitaxial region 48L/48R is grown to form a super-steeply doped channel distribution, further forming Field effect device.
  • the source/drain regions are in contact with the inverted doped well region to form a heavily doped pn junction, which has a large junction leakage current, especially a drain terminal, and a large junction leakage current, which affects the semiconductor device. performance.
  • the present invention is directed to at least solving the above technical drawbacks, and provides a method of fabricating a semiconductor device and a structure thereof, which reduce a short channel effect and a floating body effect of a SOI MOS device.
  • the present invention provides a method of fabricating a semiconductor structure, the method comprising the steps of:
  • Another aspect of the invention also provides a semiconductor structure, including a SOI substrate, heavily doped Buried layer, surface active layer, gate stack, sidewall spacer, source region, drain region, where:
  • the bottom of the SOI includes a base layer, an insulating buried layer, and a silicon film in order from bottom to top;
  • the heavily doped buried layer is over the silicon film, under the source region and under the gate stack;
  • the surface active layer is located above the heavily doped buried layer
  • the gate stack is located above the surface active layer
  • the sidewall spacer is located on a sidewall of the gate stack
  • the source region and the drain region are embedded in the surface active layer on both sides of the gate stack, and the source region overlaps the heavily doped buried layer.
  • the present invention has the following advantages:
  • FIG. 1 is a schematic view of a semiconductor device in US Pat. No. 7,002,214; [0019]
  • FIG. 2 is a flow chart showing a specific embodiment of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIG. 3 to FIG. 14 are schematic cross-sectional views of the semiconductor structure at various stages of fabrication in the process of fabricating a semiconductor structure in accordance with the method illustrated in FIG. 2. detailed description
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the structure of the first feature described below "on" the second feature may include embodiments in which the first and second features are formed in direct contact, and may include additional features formed between the first and second features. The embodiment, such that the first and second features may not be in direct contact.
  • FIG. 2 is a flow chart of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIGS. 3 through 14 are schematic cross-sectional views showing stages of fabricating a semiconductor structure in accordance with the flow shown in FIG. 2, in accordance with an embodiment of the present invention.
  • the method of forming the semiconductor structure of Fig. 2 will be specifically described below with reference to Figs. 3 through 14. It is to be understood that the drawings of the embodiments of the present invention are only for the purpose of illustration
  • step S101 is performed to provide a SOI substrate 100, and a heavily doped buried layer 104 and a surface active layer 105 are formed on the substrate 100.
  • the SOI substrate includes a base layer 101, an insulating buried layer 102, and a silicon film 103 in this order from bottom to top.
  • the base layer 101 is single crystal silicon. In other embodiments, the base layer 101 may also include other basic semiconductors such as germanium. Alternatively, the base layer 101 may further include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide. Typically, the thickness of the base layer 101 can be, but is not limited to, a few hundred microns, such as from 0.1 mm to 1.5 mm.
  • the insulating buried layer 102 may be silicon oxide, silicon nitride or any other suitable insulating material. Typically, the insulating buried layer 102 has a thickness ranging from 100 nm to 300 nm.
  • the silicon film 103 may be any one of semiconductor materials included in the base layer 101.
  • the scale 103 is single crystal silicon.
  • the silicon film 103 may also include other basic semiconductors or compound semiconductors.
  • the silicon film 103 has a thickness of 10 nm to 100 nm.
  • the heavily doped buried layer 104 may be formed in the silicon film 103 by ion implantation, or may be formed in the depth of the silicon film 103 by adjusting a dose, a voltage, an energy, or the like of the ion implantation.
  • the surface of the silicon film 103 is used as the surface active layer 105.
  • the heavily doped buried layer 104 may also be formed on the silicon film 103 by epitaxy and form a certain doping profile by in-situ doping.
  • the material of the heavily doped buried layer 104 is Si, Ge, SiGe, and the doping concentration thereof is 10 18 ⁇ 10 2Q cm - 3 , and for the NMOS, the doping type of the heavily doped buried layer 104 is P type; For the PMOS, the doping type of the heavily doped buried layer 104 is N-type.
  • the surface active layer 105 may be formed on the heavily doped buried layer 104 by in-situ doping epitaxy, or by controlling the energy and voltage of ion implantation during ion implantation to form the heavily doped buried layer 104.
  • the power consumption and the like are such that the heavily doped buried layer 104 is formed in a certain depth of the silicon film 103, and the surface layer of the silicon film 103 forms the surface active layer 105.
  • the material of the surface active layer 105 is Si, Ge, SiGe, and the doping concentration thereof is 10 15 ⁇ 10 18 cm - 3 .
  • the doping type of the surface active layer 105 is P type;
  • the doping type of the surface active layer 105 is N-type.
  • step S101 further comprising forming an isolation region, such as a shallow trench isolation (STI) structure 120, in the substrate 100 to electrically isolate the continuous semiconductor device, as shown in FIG.
  • the shallow trench isolation (STI) structure 120 penetrates the surface active layer 105, the heavily doped buried layer 104, and the silicon film 103, and is in contact with the insulating buried layer 102, and may penetrate the insulating buried layer 102.
  • step S102 is performed to form a gate stack and a side wall 230 on the substrate 100.
  • a gate stack is formed on the substrate, the gate stack including a gate dielectric layer 210 and a gate 220.
  • the gate stack may further include a capping layer (not shown) over the gate, such as by depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof. Formed to protect the top region of the gate 220 from damage during subsequent processing.
  • the gate dielectric layer 210 is located on the surface active layer 105 of the substrate 100, and may be a high-k dielectric, for example, Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La 2 0 3 , One of Zr0 2 , LaAlO or a combination thereof. In another embodiment, it may also be a thermal oxide layer, including silicon oxide, silicon oxynitride; The dielectric layer 210 may have a thickness of 1 nm to 10 nm, such as 5 nm or 8 nm.
  • a gate 220 is formed on the gate dielectric layer 210, and the gate 220 may be heavily doped polysilicon formed by deposition, or a shape success function metal layer (for NMOS, such as TaC, TiN, TaTbN, TaErN) , TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa x, etc., for PMOS, such as MoN x , TiSiN TiCN, TaAlC, TiAIN, TaN, PtSi x , Ni 3 Si, Pt, Ru, Ir, Mo, HfRu, RuO x ), which may have a thickness of from 1 nm to 20 nm, such as 3 nm, 5 nm, 8 nm, 10 nm, 12 nm or 15 nm, and further forms heavily doped polysilicon, Ti, Co, Ni, Al, W or on the work function metal layer
  • a gate 220 is formed by an alloy or
  • a gate last process may also be employed.
  • the gate stack includes a gate 220 (in this case, a dummy gate) and a gate dielectric carrying the gate.
  • Layer 210 Forming a gate 220 on the gate dielectric layer 210 by depositing, for example, polysilicon, polycrystalline SiGe, amorphous silicon, doped or undoped silicon oxide and silicon nitride, silicon oxynitride, silicon carbide, or even metal The time is a dummy gate), and the thickness thereof may be 10 nm to 80 nm.
  • the method further includes forming a capping layer on the gate 220 (in this case, a dummy gate), for example, by depositing silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or a combination thereof to protect the dummy gate.
  • the top region of the pole 220 prevents the top region of the gate 220 (which is now a dummy gate) from reacting with the deposited metal layer in a subsequent process of forming the contact layer.
  • the gate stack may also have no gate dielectric layer 210, but in a subsequent process step, after removing the dummy gate, a gate dielectric layer 210 is formed prior to filling the work function metal layer.
  • source extension 310 and drain extension 320 may be P-doped Si; for NMOS, source extension 310 and drain extension 320 may be N-doped Si.
  • the semiconductor structure is then annealed to activate impurities in source extension 310 and drain extension 320, which may be formed by other suitable methods including rapid annealing, spike annealing, and the like.
  • the sidewall spacers 230 are formed on sidewalls of the gate stack for separating the gate stacks.
  • Sidewall 230 can be formed from silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and combinations thereof, and/or other suitable materials.
  • the side wall 230 may have a multi-layered structure.
  • Side wall 230 It may be formed by a deposition-etching process, and may have a thickness ranging from 10 nm to 100 nm, such as 30 nm, 50 nm or 80 nm.
  • step S103 is performed to form an opening 500 on one side of the gate stack, the opening 500 penetrating through the surface active layer 105, heavily doped buried layer 104, and stopped at the The silicon film 103 of the SOI village bottom 100 is described.
  • a mask layer 400 is formed on the substrate 100.
  • the material of the mask layer 400 is silicon oxide, silicon nitride, silicon oxynitride, and is passed through a chemical vapor deposition layer. Forming, sputtering, etc. are formed by suitable methods.
  • a photoresist 410 covering the mask layer 400 is formed first, and the photoresist 410 is exposed and developed to be patterned, and the mask layer 400 is etched to expose the A portion of the surface active layer 105 on one side of the gate stack.
  • the opening 500 through the surface active layer 105, the heavily doped buried layer 104, and stopped in the silicon film 103 is formed by dry RIE etching or wet etching, and the Photoresist 410.
  • step S104 is performed to fill the opening 500 to form a backfill plug 510.
  • the method of filling the opening 500 is epitaxy, and the material of the backfill is Si, Ge, SiGe.
  • the opening 500 may be first filled by the epitaxial portion to be higher than the heavily doped buried layer 104, and then the opening is completely filled by in-situ doping epitaxy. And a leak zone is formed.
  • the backfill plug 510 may have a higher height than the surface active layer 105. In a subsequent process step, it is advantageous to form a lift drain region and reduce the series resistance of the drain region. Finally, the mask layer 400 is removed, as shown in FIG.
  • step S105 is performed to form source region 311 and drain region 321 .
  • P-type or N-type impurity is implanted into the bottom of the village by using the gate stack and the sidewall spacer 239 as a mask, thereby forming a source region 311 and a drain region 321 .
  • the source region 311 and the drain region 321 are P-type doped;
  • the source region 311 and the drain region 321 are N-type doped.
  • the semiconductor structure is then annealed to activate impurities in source region 311 and drain region 321 . Annealing can be formed by other suitable methods including rapid annealing, peak annealing, and the like.
  • the source region 311 overlaps with the heavily doped buried layer 104 to form a heavily doped pn junction to form a larger junction leakage current to facilitate suppression of the floating body effect; a portion of the drain region 321 is located in the backfill plug 510.
  • the fabrication of the semiconductor structure is completed in accordance with the steps of a conventional semiconductor fabrication process, For example, forming a metal silicide on the source/drain regions; depositing an interlayer dielectric layer to cover the source/drain regions and the gate stack; etching the interlayer dielectric layer to expose the source/drain regions to form contact holes, The contact holes are filled with a metal; and subsequent multilayer metal interconnects and the like.
  • the replacement gate process the dummy gate is removed, and a metal gate or the like is formed.
  • the present invention also provides a semiconductor structure, as shown in FIG. 14, including an SOI substrate 100, a heavily doped buried layer 104, a surface active layer 105, a gate stack, a sidewall spacer 230, a source region 311, a drain region 321 , wherein: the SOI substrate 100 includes a base layer 101, an insulating buried layer 102, and a silicon film 103 in order from bottom to top; the heavily doped buried layer 104 is located above the silicon film 103, a source region 311 and a lower surface of the gate stack; the surface active layer 105 is over the heavily doped buried layer 104; the gate stack is over the surface active layer 105; the sidewall spacer 230 Located on the sidewall of the gate stack; the source region 311 and the drain region 321 are embedded in the surface active layer 105 on both sides of the gate stack, the source region 311 and the weight
  • the doped buried layers 104 overlap.
  • the material of the surface active layer 105 is Si, Ge, SiGe, and the doping concentration thereof is 10 15 - 10 18 cm" 3 , and for the NMOS, the doping type of the surface active layer 105 is P type; The doping type of the surface active layer 105 is N.
  • the material of the heavily doped buried layer 104 is Si, Ge, SiGe, and the doping concentration thereof is 10 18 ⁇ 10 20 cm" 3 , for NMOS , The doping type of the heavily doped buried layer 104 is P type; for the PMOS, the doping type of the heavily doped buried layer 104 is N type.
  • the heavily doped buried layer 104 forms an inverted doped well in the substrate, which is advantageous for reducing the width of the source region depletion layer and reducing the short channel effect.
  • the heavily doped buried layer 104 is connected to the source region 311 to form a heavily doped pn junction, which has a large junction leakage current, provides a release path for the body region charge, effectively suppresses the floating body effect of the SOI semiconductor device, and does not have to The body area is taken out, saving device area and cost.

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Abstract

本发明提供了一种半导体结构的制造方法，该方法包括以下步骤：提供SOI衬底，在所述衬底上形成重掺杂埋层以及表面有源层；在所述衬底上形成栅极堆叠和侧墙；在所述栅极堆叠的一侧形成开口，所述开口贯穿所述表面有源层、重掺杂埋层并停止在所述SOI衬底绝缘埋层之上的硅膜中；填充所述开口，形成回填塞；形成源/漏区，所述源区与重掺杂埋层交叠，部分所述漏区位于所述回填塞中。相应地，本发明还提供了一种半导体结构。本发明中，所述重掺杂埋层有利于减小源/漏区耗尽层宽度，抑制短沟道效应，所述重掺杂埋层与源区交叠，形成重掺杂的pn结，有效抑制SOI MOS器件的浮体效应，提高半导体器件性能，而且不必对体区引出，节省器件面积和成本。

Description

一种半导体结构及其制造方法
[0001]本申请要求了 2012年 4月 28日提交的、 申请号为 201210134605.0、 发明名称为 "一种半导体结构及其制造方法" 的中国专利申请的优先权， 其 全部内容通过引用结合在本申请中。 技术领域
[0002]本发明涉及半导体制造领域， 尤其涉及一种半导体结构及其制造方 法。 背景技术
[0003]为了提高集成电路芯片的性能和集成度，器件特征尺寸按照摩尔定 律不断缩小， 目前已经进入纳米尺度。 随着器件体积的缩小， 功耗与漏 电流成为最关注的问题。 采用绝缘体上硅 SOI ( Silicon on Insulator )制备 的 CMOS器件具有高速、 低功耗、 高集成度、 抗辐照和无自锁效应等许 多优点， 已成为深亚微米及纳米级 MOS器件的优选结构。 SOI MOS器件 根据硅膜厚度和表面耗尽层最大厚度的比较分为部分耗尽和全耗尽 SOI MOS两种类型。全耗尽 SOI MOS的顶层硅膜较薄， SOI村底的成本较高， 目前普遍采用的还是部分耗尽 SOI MOS。
[0004] 部分耗尽 SOI MOS器件，表面耗尽层的最大厚度小于顶层规模 的厚度， 使得体区处于悬空状态， 漏端强电场使得沟道中的载流子加速， 引起碰撞电流， 激发出电子-空穴对。 新产生的电子-空穴对在强电场作用 下分离， 电子被漏端收集， 而空穴则聚集在靠近漏端和埋氧层的村底中， 引起了浮体效应。浮体效应导致体区电荷积累， 电势随之增加，使得 MOS 器件的阈值电压降低， 而输出电流增加， 即电流翘曲 Kink效应。 除此之 外， 浮体效应还会导致， 亚阈值斜率反常， 源漏击穿电压减小等器件性 能和可靠性问题。 因此， 在器件设计和制作中， 应尽量避免浮体效应的 发生。 目前， 常用的抑制附体效应的方法为采用体接触将体区接固定电 位（源端或地）， 提供体区积累电荷的泄放通路， 以降低体区电势。 然而， 这种方法增加了制作工艺的复杂度， 导致产生其他的寄生效应， 并且增 力口了电路面积、。
[0005] 随着 M0SFET沟道长度不断缩短， 短沟道效应变得愈发显著， 甚至 成为影响性能的主导因素。 短沟道效应导致器件的电学性能恶化， 如造成栅 极阈值电压下降、 功耗增加以及信噪比下降等问题。 为了改善短沟道效应， 超陡倒掺杂阱（SSRW )被引入到半导体场效应器件中。 超陡倒掺杂阱具有低 高低（或低高）的沟道掺杂分布， 沟道表面区域维持低掺杂浓度， 通过离子 注入等合适的方法在沟道表面以下的区域内形成高掺杂区， 减小源 /漏区耗 尽层宽度， 避免源漏穿通、 阈值电压增加导致漏电流增大等短沟道效应。 美 国专利 US7002214 中介绍了一种超薄绝缘体上硅的超陡倒掺杂阱场效应器 件。 如图 1 所示， 通过离子注入在 S0 I 村底的硅膜上形成重掺杂区域 33L/ 33R,然后生长超薄本征外延区域 48L/ 48R ,形成超陡倒掺杂的沟道分 布， 进一步形成场效应器件。 然而如图中所示， 源 /漏区与倒掺杂阱区接 触， 形成重掺杂 pn节， 有较大的结漏电流， 尤其是漏端， 较大的结漏电 流， 影响半导体器件的性能。 发明内容
[0006]本发明旨在至少解决上述技术缺陷，提供一种半导体器件的制造方 法及其结构， 减小短沟道效应以及 SOI MOS器件的浮体效应。
[0007]为达上述目的， 本发明提供了一种半导体结构的制造方法， 该方法 包括以下步骤：
( a ) 提供 SOI村底， 在所述村底上形成重掺杂埋层以及表面有源层；
( b ) 在所述村底上形成栅极堆叠和侧墙；
( c ) 在所述栅极堆叠的一侧形成开口， 所述开口贯穿所述表面有源层、 重掺杂埋层并停止在所述 SOI村底绝缘埋层之上的硅膜中；
( d ) 填充所述开口， 形成回填塞；
( e ) 形成源 /漏区， 所述源区与重掺杂埋层交叠， 部分所述漏区位于所 述回填塞中。
[0008]本发明另一方面还提出一种半导体结构， 包括 SOI村底、 重掺杂 埋层、 表面有源层、 栅极堆叠、 侧墙、 源区、 漏区， 其中：
[0009]所述 SOI村底从下至上依次包括基底层、 绝缘埋层、 硅膜；
[0010]所述重掺杂埋层位于所述硅膜之上，位于所述源区和栅极堆叠的下 面；
[0011]所述表面有源层位于所述重掺杂埋层之上；
[0012]所述栅极堆叠位于所述表面有源层之上；
[0013]所述侧墙位于所述栅极堆叠的侧壁上；
[0014]所述源区、漏区嵌于所述表面有源层中，位于所述栅极堆叠的两侧， 所述源区与所述重掺杂埋层交叠。
[0015]与现有技术相比， 本发明具有如下优点：
[0016]通过在村底中形成重掺杂埋层， 引入倒掺杂阱， 减小源 /漏区耗尽 层宽度， 减小了短沟道效应； 另一方面， 源区和重掺杂埋层相连， 提供 体电荷的释放通路， 有效抑制了 SOI半导体器件的浮体效应， 而且不必 做体区引出， 节省了器件面积和成本。 附图说明
[0017]本发明上述的和 /或附加的方面和优点从下面结合附图对实施例的 描述中将变得明显和容易理解， 其中：
[0018] 图 1是现有技术中美国专利 US7002214中半导体器件的示意图； [0019]图 2 是根据本发明的半导体结构的制造方法的一个具体实施方式 的流程图；
[0020]图 3至图 14为根据图 2示出的方法制造半导体结构过程中该半导体 结构在各个制造阶段的剖面结构示意图。 具体实施方式
[0021]下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类 似功能的元件。 下面通过参考附图描述的实施例是示例性的， 仅用于解 释本发明， 而不能解释为对本发明的限制。 下文的公开提供了许多不同 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并 且目的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数 字和 /或字母。 这种重复是为了筒化和清楚的目的， 其本身不指示所讨论 各种实施例和 /或设置之间的关系。 此外， 本发明提供了的各种特定的工 艺和材料的例子， 但是本领域普通技术人员可以意识到其他工艺的可应 用于性和 /或其他材料的使用。 另外， 以下描述的第一特征在第二特征之 "上" 的结构可以包括第一和第二特征形成为直接接触的实施例， 也可 以包括另外的特征形成在第一和第二特征之间的实施例， 这样第一和第 二特征可能不是直接接触。
[0022]图 2为根据本发明的半导体结构制造方法的流程图， 图 3至图 14为 根据本发明的一个实施例按照图 2所示流程制造半导体结构的各个阶段的剖 面示意图。 下面将结合图 3至图 14对图 2中形成半导体结构的方法进行具 体地描述。 需要说明的是， 本发明实施例的附图仅是为了示意的目的， 因 此没有必要按比例绘制。
[0023]参考图 2、 图 3和图 4, 执行步骤 S101 , 提供 SOI村底 100, 在所 述村底 100上形成重掺杂埋层 104以及表面有源层 105。所述 SOI村底从 下至上依次包括基底层 101、 绝缘埋层 102和硅膜 103。
[0024]在本实施例中， 所述基底层 101为单晶硅。 在其他实施例中， 所述 基底层 101还可以包括其他基本半导体， 例如锗。 或者， 所述基底层 101 还可以包括化合物半导体， 例如， 碳化硅、 砷化镓、 砷化铟或者磷化铟。 典型地， 所述基底层 101 的厚度可以约为但不限于几百微米， 例如从 0.1mm-1.5mm的厚度范围。
[0025]所述绝缘埋层 102可以为氧化硅、氮化硅或者其他任何适当的绝缘 材料， 典型地， 所述绝缘埋层 102的厚度范围为 100nm-300nm。
[0026]所述硅膜 103可以为所述基底层 101包括的半导体材料中的任何一 种。 在本实施例中， 所述规模 103 为单晶硅。 在其他实施例中， 所述硅 膜 103 还可以包括其他基本半导体或者化合物半导体。 典型地， 所述硅 膜 103的厚度为 10nm~100nm。 [0027]所述重掺杂埋层 104可以通过离子注入形成在所述硅膜 103中，或 通过调整离子注入的剂量、 电压、 能量等， 形成在所述硅膜 103 —定深 度中， 所述硅膜 103的表面作为表面有源层 105 , 另外， 所述重掺杂埋层 104还可以通过外延形成在所述硅膜 103上面，并通过原位掺杂形成一定 的掺杂分布。 所述重掺杂埋层 104的材料为 Si、 Ge、 SiGe, 其掺杂浓度 为 1018 ~ 102Qcm-3,对于 NMOS,所述重掺杂埋层 104的掺杂类型为 P型； 对于 PMOS, 所述重掺杂埋层 104的掺杂类型为 N型。
[0028]所述表面有源层 105可以通过原位掺杂外延形成在重掺杂埋层 104 之上， 或在离子注入形成重掺杂埋层 104 过程中， 通过控制离子注入的 能量、 电压、 功耗等参数， 使得重掺杂埋层 104形成在硅膜 103的一定 深度中， 硅膜 103的表面层形成表面有源层 105。 所述表面有源层 105的 材料为 Si、 Ge、 SiGe, 其掺杂浓度为 1015 ~ 1018cm-3 , 对于 NMOS , 所述 表面有源层 105 的掺杂类型为 P型； 对于 PMOS, 所述表面有源层 105 的掺杂类型为 N型。
[0029]特别地， 在步骤 S101中， 还包括在所述村底 100中形成隔离区， 例如浅沟槽隔离（STI)结构 120, 以便电隔离连续的半导体器件， 如图 5 所示， 所述浅沟槽隔离（STI)结构 120贯穿所述表面有源层 105、重掺杂埋 层 104、 硅膜 103 , 与所述绝缘埋层 102相接， 也可以贯穿所述绝缘埋层 102。
[0030]参考图 2、 图 6~图 8, 执行步骤 S102, 在所述村底 100上形成栅 极堆叠和侧墙 230。
[0031]首先， 如图 6所示， 在所述村底上形成栅极堆叠， 所述栅极堆叠包 括栅介质层 210和栅极 220。 可选地， 所述栅极堆叠还可以包括覆盖在所 述栅极上的覆盖层 （未在图中示出） ， 例如通过沉积氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其组合形成， 用以保护栅极 220 的顶部区域， 防止 其在后续的工艺中受到破坏。 所述栅介质层 210位于村底 100的表面有 源层 105之上， 可以为高 K介质， 例如， Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO、 HfZrO, A1203、 La203、 Zr02、 LaAlO 中的一种或其组合。 在另 一个实施例中， 还可以是热氧化层， 包括氧化硅、 氮氧化硅； 所述栅极 介质层 210的厚度可以为 lnm~10nm, 如 5nm或 8nm。 而后在所述栅介 质层 210上形成栅极 220,所述栅极 220可以是通过沉积形成的重掺杂多 晶硅，或是先形成功函数金属层（对于 NMOS,例如 TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax等，对于 PMOS,例如 MoNx, TiSiN TiCN, TaAlC, TiAIN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, HfRu, RuOx ), 其厚度可 以为 lnm-20nm, 如 3nm、 5nm、 8nm、 10nm、 12nm或 15nm, 再在所述功 函数金属层上形成重掺杂多晶硅、 Ti、 Co、 Ni、 Al、 W或其合金等而形成栅 极 220。
[0032]在本发明的另外一些实施例中， 也可采用后栅工艺 （gate last ), 此 时， 栅极堆叠包括栅极 220 (此时为伪栅） 和承载所述栅极的栅介质层 210。 在所述栅介质层 210上通过沉积例如多晶硅、 多晶 SiGe、 非晶硅， 掺杂或未掺杂的氧化硅及氮化硅、 氮氧化硅、 碳化硅， 甚至金属形成栅 极 220 (此时为伪栅）， 其厚度可以为 10nm -80nm。 可选地， 还包括在所 述栅极 220 (此时为伪栅）上形成覆盖层， 例如通过沉积氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其组合形成， 用以保护伪栅极 220 的顶部区域， 防 止栅极 220 (此时为伪栅）的顶部区域在后续形成接触层的工艺中与沉积 的金属层发生反应。 在另一个采用后栅工艺实施例中， 栅极堆叠也可以 没有栅介质层 210, 而是后续工艺步骤中， 除去所述伪栅后， 在填充功函 数金属层之前形成栅介质层 210。
[0033]可选地， 如图 7所示， 形成所述栅极堆叠之后， 还包括以所述栅极 堆叠为掩膜， 向表面有源层 105中注入 P型或 N型掺杂物或杂质， 进而 在所述栅极堆叠两侧形成源 /漏延伸区 310和 320。 对于 PMOS来说， 源 延伸区 310和漏延伸区 320可以是 P型掺杂的 Si; 对于 NMOS来说， 源 延伸区 310和漏延伸区 320可以是 N型掺杂的 Si。 然后对所述半导体结 构进行退火， 以激活源延伸区 310和漏延伸区 320 中的杂质， 退火可以 采用包括快速退火、 尖峰退火等其他合适的方法形成。
[0034]如图 8所示， 所述侧墙 230形成于栅极堆叠的侧壁上， 用于将栅极 堆叠隔开。 侧墙 230 可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅及其组 合， 和 /或其他合适的材料形成。 侧墙 230可以具有多层结构。 侧墙 230 可以通过包括沉积-刻蚀工艺形成， 其厚度范围可以是 10nm ~100nm, 如 30nm、 50nm或 80nm。
[0035]参考图 9~图 11 , 执行步骤 S103 , 在所述栅极堆叠的一侧形成开口 500, 所述开口 500贯穿所述表面有源层 105、 重掺杂埋层 104并停止在 所述 SOI村底 100的硅膜 103中。
[0036]首先， 如图 9所示， 在所述村底 100上形成一层掩膜层 400, 所述 掩膜层 400 的材料为氧化硅、 氮化硅、 氮氧化硅， 通过化学气相淀积、 溅射等合适的方法形成。 然后， 如图 10所示， 先形成一层覆盖所述掩膜 层 400的光刻胶 410, 对光刻胶 410进行曝光显影图形化， 刻蚀所述掩膜 层 400, 以暴露出所述栅极堆叠一侧的部分表面有源层 105。 随后， 如图 11所示， 通过干法 RIE刻蚀或湿法腐蚀形成贯穿所述表面有源层 105、 重掺杂埋层 104并停止在所述硅膜 103 中的开口 500, 去除所述光刻胶 410。
[0037]参考图 12和图 13 , 执行步骤 S104, 填充所述开口 500, 形成回填 塞 510。填充所述开口 500的方法为外延， 回填塞的材料为 Si、 Ge、 SiGe。 可选地，在填充所述开口过程中，可以先通过外延部分填充所述开口 500, 使之高于所述重掺杂埋层 104, 然后通过原位掺杂外延， 完全填充所述开 口， 并形成漏区。 所述回填塞 510的高度可以高于所述表面有源层 105 , 在后续工艺步骤中， 利于形成提升漏区， 减小漏区的串联电阻。 最后去 掉掩膜层 400, 如图 13所示。
[0038]参考图 14, 执行步骤 S105 , 形成源区 311和漏区 321。 以栅极堆 叠和侧墙 239为掩膜，向村底中注入 P型或 N型杂质，从而形成源区 311 和漏区 321 ,对于 PMOS ,源区 311和漏区 321为 P型掺杂；对于 NMOS , 源区 311和漏区 321为 N型掺杂。 然后对所述半导体结构进行退火， 以 激活源区 311和漏区 321 中的杂质。 退火可以采用包括快速退火、 尖峰 退火等其他合适的方法形成。 所述源区 311与重掺杂埋层 104交叠， 形 成重掺杂 pn结， 形成较大的结漏电流， 利于抑制浮体效应； 部分所述漏 区 321位于所述回填塞 510中。
[0039]随后按照常规半导体制造工艺的步骤完成该半导体结构的制造，例 如， 在源 /漏区上形成金属硅化物； 沉积层间介质层以覆盖所述源 /漏区和 栅极堆叠； 刻蚀所述层间介质层暴露源 /漏区以形成接触孔， 在所述接触 孔中填充金属； 以及后续的多层金属互连等工艺步骤。 或者， 在替代栅 工艺中， 去除伪栅极， 形成金属栅等工艺步骤。
[0040]本发明还提供了一种半导体结构，如图 14所示，包括 SOI村底 100、 重掺杂埋层 104、 表面有源层 105、 栅极堆叠、 侧墙 230、 源区 311、 漏 区 321 , 其中： 所述 SOI村底 100从下至上依次包括基底层 101、 绝缘埋 层 102、 硅膜 103; 所述重掺杂埋层 104位于所述硅膜 103之上， 位于所 述源区 311和栅极堆叠的下面； 所述表面有源层 105位于所述重掺杂埋 层 104之上； 所述栅极堆叠位于所述表面有源层 105之上； 所述侧墙 230 位于所述栅极堆叠的侧壁上； 所述源区 311、 漏区 321嵌于所述表面有源 层 105 中， 位于所述栅极堆叠的两侧， 所述源区 311 与所述重掺杂埋层 104交叠。 所述表面有源层 105 的材料为 Si、 Ge、 SiGe, 其掺杂浓度为 1015 - 1018cm"3 , 对于 NMOS , 所述表面有源层 105的掺杂类型为 P型； 对于 PMOS , 所述表面有源层 105的掺杂类型为 N型。 所述重掺杂埋层 104的材料为 Si、 Ge、 SiGe, 其掺杂浓度为 1018 ~ 1020cm"3, 对于 NMOS , 所述重掺杂埋层 104的掺杂类型为 P型； 对于 PMOS , 所述重掺杂埋层 104的掺杂类型为 N型。 所述重掺杂埋层 104在村底中形成了倒掺杂阱， 利于减小源区耗尽层宽度， 减小短沟道效应。 所述重掺杂埋层 104 和源 区 311相连， 形成重掺杂 pn结， 具有较大的结漏电流， 提供了体区电荷 的释放通路， 有效抑制了 SOI半导体器件的浮体效应， 而且不必做体区 引出， 节省了器件面积和成本。
[0041]虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发 明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施例进行 各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理 解在保持本发明保护范围内的同时， 工艺步骤的次序可以变化。
[0042]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作 为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发 出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本 发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发 明可以对它们进行应用。 因此，本发明所附权利要求旨在将这些工艺、机构、 制造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1、 一种半导体结构的制造方法， 该方法包括以下步骤：
( a)提供 SOI村底，在所述村底上形成重掺杂埋层以及表面有源层； (b) 在所述村底上形成栅极堆叠和侧墙；
(C)在所述栅极堆叠的一侧形成开口， 所述开口贯穿所述表面有源 层、 重掺杂埋层并停止在所述 SOI村底绝缘埋层之上的硅膜中；
(d) 填充所述开口， 形成回填塞；
(e)形成源 /漏区， 所述源区与重掺杂埋层交叠， 部分所述漏区位于 所述回填塞中。
2、 根据权利要求 1 所述的方法， 其中步骤 （a) 中， 形成重掺杂埋 层的方法为离子注入或在 SOI村底的硅膜上原位掺杂外延。
3、 根据权利要求 1 所述的方法， 其中步骤 （a) 中， 形成表面有源 层的方法为在所述重掺杂埋层上原位掺杂外延。
4、 根据权利要求 1或 2所述的方法， 其中步骤 （a) 中， 所述重掺 杂埋层的材料为 Si、Ge、SiGe,其掺杂浓度为 1018 ~ 102Qcm-3,对于 NMOS, 所述重掺杂埋层的掺杂类型为 P型； 对于 PMOS, 所述重掺杂埋层的掺 杂类型为 N型。
5、 根据权利要求 1或 3所述的方法， 其中步骤 （a) 中， 所述表面 有源层的材料为 Si、Ge、SiGe,其掺杂浓度为 1015 ~ 1018cm-3,对于 NMOS, 所述表面有源层的掺杂类型为 P型； 对于 PMOS, 所述表面有源层的掺 杂类型为 N型。
6、 根据权利要求 1 所述的方法， 其中步骤 （c) 中， 形成开口的步 骤包括：
(i) 形成覆盖所述栅极堆叠和村底的掩膜层；
(ii)刻蚀所述掩膜层， 以暴露出所述栅极堆叠一侧的部分表面有源 层；
(iii)通过刻蚀形成贯穿所述表面有源层、重掺杂埋层并停止在所述
SOI村底绝缘埋层之上的硅膜中的开口。
7、 根据权利要求 1 所述的方法， 其中步骤（d ) 中， 填充所述开口 的方法为外延。
8、 根据权利要求 1 所述的方法， 其中步骤（d ) 中， 还包括通过外 延部分填充所述开口， 使之高于所述重掺杂埋层， 然后通过原位掺杂外 延， 形成漏区。
9、 根据权利要求 1 所述的方法， 其中步骤（d ) 中， 所述回填塞的 材料为 Si、 Ge、 SiGe。
10、 一种半导体结构， 该结构包括 SOI村底、 重掺杂埋层、 表面有 源层、 栅极堆叠、 侧墙、 源区、 漏区， 其中：
所述 SOI村底从下至上依次包括基底层、 绝缘埋层、 硅膜； 所述重掺杂埋层位于所述硅膜之上， 位于所述源区和栅极堆叠的下 面；
所述表面有源层位于所述重掺杂埋层之上；
所述栅极堆叠位于所述表面有源层之上；
所述侧墙位于所述栅极堆叠的侧壁上；
所述源区、 漏区嵌于所述表面有源层中， 位于所述栅极堆叠的两侧， 所述源区与所述重掺杂埋层交叠。
11、 根据权利要求 10所述的半导体结构， 其中所述重掺杂埋层的材 料为 Si、 Ge、 SiGe, 其掺杂浓度为 1018 ~ 102Qcm-3, 对于 NMOS , 所述重 掺杂埋层的掺杂类型为 P型； 对于 PMOS , 所述重掺杂埋层的掺杂类型 为 N型。
12、 根据权利要求 10所述的半导体结构， 其中所述表面有源层的材 料为 Si、 Ge、 SiGe, 其掺杂浓度为 1015 ~ 1018cm-3, 对于 NMOS , 所述表 面有源层的掺杂类型为 P型； 对于 PMOS , 所述表面有源层的掺杂类型 为 N型。
13、 根据权利要求 10所述的半导体结构， 其中所述漏区与所述绝缘 埋层之间具有硅膜， 所述硅膜的掺杂浓度小于所述重掺杂埋层的掺杂浓 度。
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