CN103377947B - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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CN103377947B
CN103377947B CN201210134605.0A CN201210134605A CN103377947B CN 103377947 B CN103377947 B CN 103377947B CN 201210134605 A CN201210134605 A CN 201210134605A CN 103377947 B CN103377947 B CN 103377947B
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buried regions
heavy doping
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CN103377947A (zh
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尹海洲
朱慧珑
骆志炯
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Institute of Microelectronics of CAS
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Abstract

本发明提供了一种半导体结构的制造方法，该方法包括以下步骤：提供SOI衬底，在所述衬底上形成重掺杂埋层以及表面有源层；在所述衬底上形成栅极堆叠和侧墙；在所述栅极堆叠的一侧形成开口，所述开口贯穿所述表面有源层、重掺杂埋层并停止在所述SOI衬底绝缘埋层之上的硅膜中；填充所述开口，形成回填塞；形成源/漏区，所述源区与重掺杂埋层交叠，部分所述漏区位于所述回填塞中。相应地，本发明还提供了一种半导体结构。本发明中，所述重掺杂埋层有利于减小源/漏区耗尽层宽度，抑制短沟道效应，所述重掺杂埋层与源区交叠，形成重掺杂的pn结，有效抑制SOI？MOS器件的浮体效应，提高半导体器件性能，而且不必对体区引出，节省器件面积和成本。

Description

一种半导体结构及其制造方法
技术领域
本发明涉及半导体制造领域，尤其涉及一种半导体结构及其制造方法。
背景技术
为了提高集成电路芯片的性能和集成度，器件特征尺寸按照摩尔定律不断缩小，目前已经进入纳米尺度。随着器件体积的缩小，功耗与漏电流成为最关注的问题。采用绝缘体上硅SOI(SilicononInsulator)制备的CMOS器件具有高速、低功耗、高集成度、抗辐照和无自锁效应等许多优点，已成为深亚微米及纳米级MOS器件的优选结构。SOIMOS器件根据硅膜厚度和表面耗尽层最大厚度的比较分为部分耗尽和全耗尽SOIMOS两种类型。全耗尽SOIMOS的顶层硅膜较薄，SOI衬底的成本较高，目前普遍采用的还是部分耗尽SOIMOS。
部分耗尽SOIMOS器件，表面耗尽层的最大厚度小于顶层规模的厚度，使得体区处于悬空状态，漏端强电场使得沟道中的载流子加速，引起碰撞电流，激发出电子-空穴对。新产生的电子-空穴对在强电场作用下分离，电子被漏端收集，而空穴则聚集在靠近漏端和埋氧层的衬底中，引起了浮体效应。浮体效应导致体区电荷积累，电势随之增加，使得MOS器件的阈值电压降低，而输出电流增加，即电流翘曲Kink效应。除此之外，浮体效应还会导致，亚阈值斜率反常，源漏击穿电压减小等器件性能和可靠性问题。因此，在器件设计和制作中，应尽量避免浮体效应的发生。目前，常用的抑制附体效应的方法为采用体接触将体区接固定电位(源端或地)，提供体区积累电荷的泄放通路，以降低体区电势。然而，这种方法增加了制作工艺的复杂度，导致产生其他的寄生效应，并且增加了电路面积。
随着MOSFET沟道长度不断缩短，短沟道效应变得愈发显著，甚至成为影响性能的主导因素。短沟道效应导致器件的电学性能恶化，如造成栅极阈值电压下降、功耗增加以及信噪比下降等问题。为了改善短沟道效应，超陡倒掺杂阱(SSRW)被引入到半导体场效应器件中。超陡倒掺杂阱具有低高低(或低高)的沟道掺杂分布，沟道表面区域维持低掺杂浓度，通过离子注入等合适的方法在沟道表面以下的区域内形成高掺杂区，减小源/漏区耗尽层宽度，避免源漏穿通、阈值电压增加导致漏电流增大等短沟道效应。美国专利US7002214中介绍了一种超薄绝缘体上硅的超陡倒掺杂阱场效应器件。如图1所示，通过离子注入在SOI衬底的硅膜上形成重掺杂区域33L/33R，然后生长超薄本征外延区域48L/48R，形成超陡倒掺杂的沟道分布，进一步形成场效应器件。然而如图中所示，源/漏区与倒掺杂阱区接触，形成重掺杂pn节，有较大的结漏电流，尤其是漏端，较大的结漏电流，影响半导体器件的性能。
发明内容
本发明旨在至少解决上述技术缺陷，提供一种半导体器件的制造方法及其结构，减小短沟道效应以及SOIMOS器件的浮体效应。
为达上述目的，本发明提供了一种半导体结构的制造方法，该方法包括以下步骤：
(a)提供SOI衬底，在所述衬底上形成重掺杂埋层以及表面有源层；
(b)在所述衬底上形成栅极堆叠和侧墙；
(c)在所述栅极堆叠的一侧形成开口，所述开口贯穿所述表面有源层、重掺杂埋层并停止在所述SOI衬底绝缘埋层之上的硅膜中；
(d)填充所述开口，形成回填塞；
(e)形成源/漏区，所述源区与重掺杂埋层交叠，部分所述漏区位于所述回填塞中。
本发明另一方面还提出一种半导体结构，包括SOI衬底、重掺杂埋层、表面有源层、栅极堆叠、侧墙、源区、漏区，其中：
所述SOI衬底从下至上依次包括基底层、绝缘埋层、硅膜；
所述重掺杂埋层位于所述硅膜之上，位于所述源区和栅极堆叠的下面；
所述表面有源层位于所述重掺杂埋层之上；
所述栅极堆叠位于所述表面有源层之上；
所述侧墙位于所述栅极堆叠的侧壁上；
所述源区、漏区嵌于所述表面有源层中，位于所述栅极堆叠的两侧，所述源区与所述重掺杂埋层交叠。
与现有技术相比，本发明具有如下优点：
通过在衬底中形成重掺杂埋层，引入倒掺杂阱，减小源/漏区耗尽层宽度，减小了短沟道效应；另一方面，源区和重掺杂埋层相连，提供体电荷的释放通路，有效抑制了SOI半导体器件的浮体效应，而且不必做体区引出，节省了器件面积和成本。
附图说明
本发明上述的和/或附加的方面和优点从下面结合附图对实施例的描述中将变得明显和容易理解，其中：
图1是现有技术中美国专利US7002214中半导体器件的示意图；
图2是根据本发明的半导体结构的制造方法的一个具体实施方式的流程图；
图3至图14为根据图2示出的方法制造半导体结构过程中该半导体结构在各个制造阶段的剖面结构示意图。
具体实施方式
下面详细描述本发明的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明，而不能解释为对本发明的限制。下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外，以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例，也可以包括另外的特征形成在第一和第二特征之间的实施例，这样第一和第二特征可能不是直接接触。
图2为根据本发明的半导体结构制造方法的流程图，图3至图14为根据本发明的一个实施例按照图2所示流程制造半导体结构的各个阶段的剖面示意图。下面将结合图3至图14对图2中形成半导体结构的方法进行具体地描述。需要说明的是，本发明实施例的附图仅是为了示意的目的，因此没有必要按比例绘制。
参考图2、图3和图4，执行步骤S101，提供SOI衬底100，在所述衬底100上形成重掺杂埋层104以及表面有源层105。所述SOI衬底从下至上依次包括基底层101、绝缘埋层102和硅膜103。
在本实施例中，所述基底层101为单晶硅。在其他实施例中，所述基底层101还可以包括其他基本半导体，例如锗。或者，所述基底层101还可以包括化合物半导体，例如，碳化硅、砷化镓、砷化铟或者磷化铟。典型地，所述基底层101的厚度可以约为但不限于几百微米，例如从0.1mm-1.5mm的厚度范围。
所述绝缘埋层102可以为氧化硅、氮化硅或者其他任何适当的绝缘材料，典型地，所述绝缘埋层102的厚度范围为100nm-300nm。
所述硅膜103可以为所述基底层101包括的半导体材料中的任何一种。在本实施例中，所述规模103为单晶硅。在其他实施例中，所述硅膜103还可以包括其他基本半导体或者化合物半导体。典型地，所述硅膜103的厚度为10nm～100nm。
所述重掺杂埋层104可以通过离子注入形成在所述硅膜103中，或通过调整离子注入的剂量、电压、能量等，形成在所述硅膜103一定深度中，所述硅膜103的表面作为表面有源层105，另外，所述重掺杂埋层104还可以通过外延形成在所述硅膜103上面，并通过原位掺杂形成一定的掺杂分布。所述重掺杂埋层104的材料为Si、Ge、SiGe，其掺杂浓度为1018～1020cm-3对于NMOS，所述重掺杂埋层104的掺杂类型为P型；对于PMOS，所述重掺杂埋层104的掺杂类型为N型。
所述表面有源层105可以通过原位掺杂外延形成在重掺杂埋层104之上，或在离子注入形成重掺杂埋层104过程中，通过控制离子注入的能量、电压、功耗等参数，使得重掺杂埋层104形成在硅膜103的一定深度中，硅膜103的表面层形成表面有源层105。所述表面有源层105的材料为Si、Ge、SiGe，其掺杂浓度为1015～1018cm-3，对于NMOS，所述表面有源层105的掺杂类型为P型；对于PMOS，所述表面有源层105的掺杂类型为N型。
特别地，在步骤S101中，还包括在所述衬底100中形成隔离区，例如浅沟槽隔离(STI)结构120，以便电隔离连续的半导体器件，如图5所示，所述浅沟槽隔离(STI)结构120贯穿所述表面有源层105、重掺杂埋层104、硅膜103，与所述绝缘埋层102相接，也可以贯穿所述绝缘埋层102。
参考图2、图6～图8，执行步骤S102，在所述衬底100上形成栅极堆叠和侧墙230。
首先，如图6所示，在所述衬底上形成栅极堆叠，所述栅极堆叠包括栅介质层210和栅极220。可选地，所述栅极堆叠还可以包括覆盖在所述栅极上的覆盖层(未在图中示出)，例如通过沉积氮化硅、氧化硅、氮氧化硅、碳化硅及其组合形成，用以保护栅极220的顶部区域，防止其在后续的工艺中受到破坏。所述栅介质层210位于衬底100的表面有源层105之上，可以为高K介质，例如，HfO2、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al2O3、La2O3、ZrO2、LaAlO中的一种或其组合。在另一个实施例中，还可以是热氧化层，包括氧化硅、氮氧化硅；所述栅极介质层210的厚度可以为1nm～10nm，如5nm或8nm。而后在所述栅介质层210上形成栅极220，所述栅极220可以是通过沉积形成的重掺杂多晶硅，或是先形成功函数金属层(对于NMOS，例如TaC，TiN，TaTbN，TaErN，TaYbN，TaSiN，HfSiN，MoSiN，RuTax，NiTax等，对于PMOS，例如MoNx，TiSiN，TiCN，TaAlC，TiAlN，TaN，PtSix，Ni3Si，Pt，Ru，Ir，Mo，HfRu，RuOx)，其厚度可以为1nm-20nm，如3nm、5nm、8nm、10nm、12nm或15nm，再在所述功函数金属层上形成重掺杂多晶硅、Ti、Co、Ni、Al、W或其合金等而形成栅极220。
在本发明的另外一些实施例中，也可采用后栅工艺(gatelast)，此时，栅极堆叠包括栅极220(此时为伪栅)和承载所述栅极的栅介质层210。在所述栅介质层210上通过沉积例如多晶硅、多晶SiGe、非晶硅，掺杂或未掺杂的氧化硅及氮化硅、氮氧化硅、碳化硅，甚至金属形成栅极220(此时为伪栅)，其厚度可以为10nm-80nm。可选地，还包括在所述栅极220(此时为伪栅)上形成覆盖层，例如通过沉积氮化硅、氧化硅、氮氧化硅、碳化硅及其组合形成，用以保护伪栅极220的顶部区域，防止栅极220(此时为伪栅)的顶部区域在后续形成接触层的工艺中与沉积的金属层发生反应。在另一个采用后栅工艺实施例中，栅极堆叠也可以没有栅介质层210，而是后续工艺步骤中，除去所述伪栅后，在填充功函数金属层之前形成栅介质层210。
可选地，如图7所示，形成所述栅极堆叠之后，还包括以所述栅极堆叠为掩膜，向表面有源层105中注入P型或N型掺杂物或杂质，进而在所述栅极堆叠两侧形成源/漏延伸区310和320。对于PMOS来说，源延伸区310和漏延伸区320可以是P型掺杂的Si；对于NMOS来说，源延伸区310和漏延伸区320可以是N型掺杂的Si。然后对所述半导体结构进行退火，以激活源延伸区310和漏延伸区320中的杂质，退火可以采用包括快速退火、尖峰退火等其他合适的方法形成。
如图8所示，所述侧墙230形成于栅极堆叠的侧壁上，用于将栅极堆叠隔开。侧墙230可以由氮化硅、氧化硅、氮氧化硅、碳化硅及其组合，和/或其他合适的材料形成。侧墙230可以具有多层结构。侧墙230可以通过包括沉积-刻蚀工艺形成，其厚度范围可以是10nm～100nm，如30nm、50nm或80nm。
参考图9～图11，执行步骤S103，在所述栅极堆叠的一侧形成开口500，所述开口500贯穿所述表面有源层105、重掺杂埋层104并停止在所述SOI衬底100的硅膜103中。
首先，如图9所示，在所述衬底100上形成一层掩膜层400，所述掩膜层400的材料为氧化硅、氮化硅、氮氧化硅，通过化学气相淀积、溅射等合适的方法形成。然后，如图10所示，先形成一层覆盖所述掩膜层400的光刻胶410，对光刻胶410进行曝光显影图形化，刻蚀所述掩膜层400，以暴露出所述栅极堆叠一侧的部分表面有源层105。随后，如图11所示，通过干法RIE刻蚀或湿法腐蚀形成贯穿所述表面有源层105、重掺杂埋层104并停止在所述硅膜103中的开口500，去除所述光刻胶410。
参考图12和图13，执行步骤S104，填充所述开口500，形成回填塞510。填充所述开口500的方法为外延，回填塞的材料为Si、Ge、SiGe。可选地，在填充所述开口过程中，可以先通过外延部分填充所述开口500，使之高于所述重掺杂埋层104，然后通过原位掺杂外延，完全填充所述开口，并形成漏区。所述回填塞510的高度可以高于所述表面有源层105，在后续工艺步骤中，利于形成提升漏区，减小漏区的串联电阻。最后去掉掩膜层400，如图13所示。
参考图14，执行步骤S105，形成源区311和漏区321。以栅极堆叠和侧墙239为掩膜，向衬底中注入P型或N型杂质，从而形成源区311和漏区321，对于PMOS，源区311和漏区321为P型掺杂；对于NMOS，源区311和漏区321为N型掺杂。然后对所述半导体结构进行退火，以激活源区311和漏区321中的杂质。退火可以采用包括快速退火、尖峰退火等其他合适的方法形成。所述源区311与重掺杂埋层104交叠，形成重掺杂pn结，形成较大的结漏电流，利于抑制浮体效应；部分所述漏区321位于所述回填塞510中。
随后按照常规半导体制造工艺的步骤完成该半导体结构的制造，例如，在源/漏区上形成金属硅化物；沉积层间介质层以覆盖所述源/漏区和栅极堆叠；刻蚀所述层间介质层暴露源/漏区以形成接触孔，在所述接触孔中填充金属；以及后续的多层金属互连等工艺步骤。或者，在替代栅工艺中，去除伪栅极，形成金属栅等工艺步骤。
本发明还提供了一种半导体结构，如图14所示，包括SOI衬底100、重掺杂埋层104、表面有源层105、栅极堆叠、侧墙230、源区311、漏区321，其中：所述SOI衬底100从下至上依次包括基底层101、绝缘埋层102、硅膜103；所述重掺杂埋层104位于所述硅膜103之上，位于所述源区311和栅极堆叠的下面；所述表面有源层105位于所述重掺杂埋层104之上；所述栅极堆叠位于所述表面有源层105之上；所述侧墙230位于所述栅极堆叠的侧壁上；所述源区311、漏区321嵌于所述表面有源层105中，位于所述栅极堆叠的两侧，所述源区311与所述重掺杂埋层104交叠。所述表面有源层105的材料为Si、Ge、SiGe，其掺杂浓度为1015～1018cm-3，对于NMOS，所述表面有源层105的掺杂类型为P型；对于PMOS，所述表面有源层105的掺杂类型为N型。所述重掺杂埋层104的材料为Si、Ge、SiGe，其掺杂浓度为1018～1020cm-3，对于NMOS，所述重掺杂埋层104的掺杂类型为P型；对于PMOS，所述重掺杂埋层104的掺杂类型为N型。所述重掺杂埋层104在衬底中形成了倒掺杂阱，利于减小源区耗尽层宽度，减小短沟道效应。所述重掺杂埋层104和源区311相连，形成重掺杂pn结，具有较大的结漏电流，提供了体区电荷的释放通路，有效抑制了SOI半导体器件的浮体效应，而且不必做体区引出，节省了器件面积和成本。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下，可以对这些实施例进行各种变化、替换和修改。对于其他例子，本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时，工艺步骤的次序可以变化。
此外，本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容，作为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤，其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进行应用。因此，本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。

Claims (13)

1.一种半导体结构的制造方法，该方法包括以下步骤：
(a)提供SOI衬底，在所述衬底上形成重掺杂埋层以及表面有源层；
(b)在所述衬底上形成栅极堆叠和侧墙；
(c)在所述栅极堆叠的一侧形成开口，所述开口贯穿所述表面有源层、重掺杂埋层并停止在所述SOI衬底绝缘埋层之上的硅膜中；
(d)填充所述开口，形成回填塞；
(e)形成源/漏区，所述源区与重掺杂埋层交叠，部分所述漏区位于所述回填塞中。
2.根据权利要求1所述的方法，其中步骤(a)中，形成重掺杂埋层的方法为离子注入或在SOI衬底的硅膜上原位掺杂外延。
3.根据权利要求1所述的方法，其中步骤(a)中，形成表面有源层的方法为在所述重掺杂埋层上原位掺杂外延。
4.根据权利要求1或2所述的方法，其中步骤(a)中，所述重掺杂埋层的材料为Si、Ge、SiGe，其掺杂浓度为1018～1020cm-3，对于NMOS，所述重掺杂埋层的掺杂类型为P型；对于PMOS，所述重掺杂埋层的掺杂类型为N型。
5.根据权利要求1或3所述的方法，其中步骤(a)中，所述表面有源层的材料为Si、Ge、SiGe，其掺杂浓度为1015～1018cm-3，对于NMOS，所述表面有源层的掺杂类型为P型；对于PMOS，所述表面有源层的掺杂类型为N型。
6.根据权利要求1所述的方法，其中步骤(c)中，形成开口的步骤包括：
(i)形成覆盖所述栅极堆叠和衬底的掩膜层；
(ii)刻蚀所述掩膜层，以暴露出所述栅极堆叠一侧的部分表面有源层；
(iii)通过刻蚀形成贯穿所述表面有源层、重掺杂埋层并停止在所述SOI衬底绝缘埋层之上的硅膜中的开口。
7.根据权利要求1所述的方法，其中步骤(d)中，填充所述开口的方法为外延。
8.根据权利要求1所述的方法，其中步骤(d)中，还包括通过外延部分填充所述开口，使之高于所述重掺杂埋层，然后通过原位掺杂外延，形成漏区。
9.根据权利要求1所述的方法，其中步骤(d)中，所述回填塞的材料为Si、Ge、SiGe。
10.一种半导体结构，该结构包括SOI衬底、重掺杂埋层、表面有源层、栅极堆叠、侧墙、源区、漏区、回填塞，其中：
所述SOI衬底从下至上依次包括基底层、绝缘埋层、硅膜；
所述重掺杂埋层位于所述硅膜之上，位于所述源区和栅极堆叠的下面；
所述表面有源层位于所述重掺杂埋层之上；
所述栅极堆叠位于所述表面有源层之上；
所述侧墙位于所述栅极堆叠的侧壁上；
所述源区、漏区嵌于所述表面有源层中，位于所述栅极堆叠的两侧，所述源区与所述重掺杂埋层交叠；
所述回填塞位于漏区和重掺杂埋层之间。
11.根据权利要求10所述的半导体结构，其中所述重掺杂埋层的材料为Si、Ge、SiGe，其掺杂浓度为1018～1020cm-3，对于NMOS，所述重掺杂埋层的掺杂类型为P型；对于PMOS，所述重掺杂埋层的掺杂类型为N型。
12.根据权利要求10所述的半导体结构，其中所述表面有源层的材料为Si、Ge、SiGe，其掺杂浓度为1015～1018cm-3，对于NMOS，所述表面有源层的掺杂类型为P型；对于PMOS，所述表面有源层的掺杂类型为N型。
13.根据权利要求10所述的半导体结构，其中所述漏区与所述绝缘埋层之间具有硅膜，所述硅膜的掺杂浓度小于所述重掺杂埋层的掺杂浓度。
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