WO2014071754A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

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Publication number
WO2014071754A1
WO2014071754A1 PCT/CN2013/080537 CN2013080537W WO2014071754A1 WO 2014071754 A1 WO2014071754 A1 WO 2014071754A1 CN 2013080537 W CN2013080537 W CN 2013080537W WO 2014071754 A1 WO2014071754 A1 WO 2014071754A1
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Prior art keywords
layer
semiconductor structure
gate
soi
stress
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PCT/CN2013/080537
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English (en)
French (fr)
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朱慧珑
尹海洲
骆志炯
梁擎擎
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中国科学院微电子研究所
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Priority to US14/439,165 priority Critical patent/US20150270399A1/en
Publication of WO2014071754A1 publication Critical patent/WO2014071754A1/zh

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
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    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support

Definitions

  • the present invention relates to the field of semiconductors, and more particularly to a semiconductor structure and a method of fabricating the same. Background technique
  • a common method of increasing stress is to operate in the source and drain regions to create tensile or compressive stresses on the channel.
  • the transistor channel is oriented along the ⁇ 110 ⁇ of silicon.
  • the mobility of the holes is increased; and when the channel is subjected to the channel along the channel.
  • the tensile mobility of the direction and/or the compressive stress in the direction perpendicular to the channel increases the mobility of electrons. Therefore, stress is introduced in the channel region of the semiconductor device, and the performance of the device can be improved.
  • SOI Silicon On Insulator
  • SOI materials have advantages that are incomparable to bulk silicon: dielectric isolation of components in integrated circuits can be achieved, and parasitic latch-up effects in bulk silicon CMOS circuits are completely eliminated;
  • the integrated circuit also has the advantages of small parasitic capacitance, high integration density, high speed, single process, short channel effect and especially suitable for low voltage and low power circuits. Therefore, it can be said that SOI will become deep submicron.
  • Ultra-thin soi provides an alternative means of controlling short-channel effects through a natural electrostatic barrier established by a silicon dielectric interface.
  • the channel region of the device introduces favorable stresses that improve the performance of the semiconductor device.
  • the present invention provides a method of fabricating a semiconductor structure, the method comprising: a) providing an SOI substrate comprising a substrate layer (130), an 80 layer (110) and a top to bottom SOI layer (100);
  • the present invention also provides a semiconductor structure including the semiconductor structure [0013] the SOI substrate includes an SOI layer, a BOX layer, and a bulk silicon layer from top to bottom;
  • a gate stack formed over the SOI layer, including a gate and gate dielectric layer;
  • a stress inducing region is formed in the bulk silicon layer directly under the gate.
  • the semiconductor structure and the method of fabricating the same provided by the present invention form a stress inducing region in a bulk silicon layer under the BOX layer of the SOI substrate directly under the gate by ion implantation and annealing operation, the stress contributing to improvement Performance of semiconductor devices ( description of the drawings
  • FIG. 1 is a flow diagram of one embodiment of a method of fabricating a semiconductor structure in accordance with the present invention
  • FIG. 2 to FIG. 11 are cross-sectional structural views showing respective stages of fabrication of the semiconductor structure in the process of fabricating a semiconductor structure in accordance with the flow shown in FIG. 1 in accordance with an embodiment of the present invention.
  • first and second features are formed in direct contact
  • additional features formed between the first and second features.
  • first and second features may not be in direct contact.
  • the semiconductor structure provided by the present invention has several preferred structures, a preferred structure is provided below and outlined.
  • FIG. 10 illustrates a semiconductor structure including an SOI substrate, a ground layer 140, a gate stack, source/drain regions 160, source/drain extension regions 170, and stress inducing regions 150. And an interlayer dielectric layer 250, wherein:
  • the SOI substrate includes an SOI layer 100, a BOX layer 110, and a bulk silicon layer 130 from top to bottom;
  • the gate stack includes a gate electrode 200 and a gate dielectric layer 280, and the gate dielectric layer 280 and the gate electrode 200 are sequentially formed on the SOI substrate;
  • the source/drain region 160 and the source/drain extension region 170 are formed in the SOI layer 100, the interlayer dielectric layer 250 covers the source/drain region 160;
  • the ground layer 140 is located in the bulk silicon layer 130, below the BOX layer 110;
  • the stress inducing region 150 is formed in the bulk silicon layer 130 directly under the gate electrode 200.
  • sidewall spacers 210 are also formed on both sides of the gate stack.
  • the SOI substrate has at least three layers of structures: a bulk silicon layer 130, a BOX layer 110 over the bulk silicon layer 130, and an SOI layer 100 overlying the BOX layer 110.
  • the material of the BOX layer 110 may be selected from a crystalline or amorphous oxide, a nitride or any combination thereof. Preferably, Si0 2 is usually used.
  • the material of the SOI layer 100 is a single crystal silicon, a Ge or a III-V compound such as SiC, gallium arsenide, indium arsenide or indium phosphide.
  • the SOI substrate selected in the present invention is an SOI substrate having an ultrathin SOI layer 100 and an ultrathin BOX layer 110, wherein the ultrathin SOI layer 100 has a thickness ranging from 5 to 20 nm, such as 5 nm, 15 nm or 20 nm;
  • the thickness of layer 110 ranges from 5 to 30 nm, such as 5 nm, 20 nm or 30 nm.
  • an isolation region 120 may also be formed in the SOI substrate for using the SOI layer 100. Divided into separate regions for subsequent processing to form a transistor structure.
  • the material of the isolation region 120 is an insulating material, and for example, SiO 2 , Si 3 N 4 or a combination thereof may be selected.
  • the width of the isolation region 120 can be determined by the design requirements of the semiconductor structure.
  • the gate stack includes a gate 200 and a gate dielectric layer 280.
  • the material of the gate dielectric layer 280 may be a thermal oxide layer including silicon oxide, silicon oxynitride or a high K dielectric.
  • the gate electrode 200 may include a gate metal layer, a gate electrode layer, a polysilicon layer, or the like.
  • the sidewall spacer 210 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and/or other suitable materials.
  • the side wall 210 may have a multi-layered structure.
  • the spacer 210 may be formed by a deposition-etching process having a thickness ranging from about 10 nm to about 100 nm.
  • Source/drain regions 160 and source/drain extension regions 170 are formed by ion implantation in the SOI layer 100.
  • source/drain regions 160 and source/drain extensions 170 may be P-type doped
  • source/drain regions 160 and source/drain extension regions 170 may be N-type doped.
  • the ground layer 140 is formed in the bulk silicon layer 130 at a position close to the BOX layer 110.
  • n-type or p-type doping may be arbitrarily used for the PFET or the NFET.
  • the stress inducing region 150 is formed in the ground layer 140 using carbon doping. The location of the stress inducing region 150 is within the bulk silicon layer directly under the gate stack (via the BOX layer), which facilitates the introduction of compressive stress into the channel region and significantly improves the performance of the P-type FET. Further elaboration.
  • FIG. 1 is a flow chart of a specific embodiment of a method of fabricating a semiconductor structure in accordance with the present invention, the method comprising:
  • Step S101 providing an SOI substrate, the SOI substrate including a base layer, a BOX layer and an SOI layer from top to bottom;
  • Step S102 forming a dummy gate stack on the SOI substrate and an implanted spreading layer on both sides of the dummy gate stack;
  • Step S103 removing the dummy gate stack to form a gate recess
  • Step S104 stress-inducing ions are implanted into the semiconductor structure by the gate recess and annealed, and a stress inducing region under the BOX layer of the SOI substrate is formed directly under the gate recess.
  • Steps S101 to S104 are described below with reference to FIGS. 2 through 10, which are various fabrications of the semiconductor structure in the process of fabricating a semiconductor structure in accordance with the flow shown in FIG. 1 in accordance with an embodiment of the present invention. Schematic diagram of the cross-sectional structure of the stage. It is to be understood that the appended claims
  • step S101 is performed to provide an SOI substrate including a base layer, a BOX layer and an SOI layer.
  • the SOI substrate has at least three layers of structures: a bulk silicon layer 130, a BOX layer 110 over the bulk silicon layer 130, and an SOI overlying the BOX layer 110.
  • Layer 100 The material of the BOX layer 110 is generally selected from Si0 2 .
  • the material of the SOI layer 100 is a single crystal silicon, a Ge or a III-V compound such as SiC, gallium arsenide, indium arsenide or indium phosphide.
  • the SOI substrate selected in the present invention is an SOI substrate having an ultrathin SOI layer 100 and an ultrathin BOX layer 110, wherein the thickness of the SOI layer 100 ranges from 5 to 20 nm, for example, 5 nm, 15 nm, and 20 nm; and the thickness of the BOX layer 110 The range is 5-3 Onm, such as 5 nm, 20 nm, 30 nm.
  • An isolation region 120 is further formed in the SOI substrate for dividing the SOI layer 100 into separate regions for subsequent processing to form a transistor structure, as shown in FIG.
  • the material of the isolation region 120 is an insulating material. For example, Si0 2 , Si 3 N 4 or a combination thereof may be selected, and the width of the isolation region 120 may be determined according to the design requirements of the semiconductor structure.
  • the ground layer 140 is formed by ion implantation, with reference to FIG.
  • the implantation energy is controlled such that the ground layer is formed under the BOX layer 110.
  • n-type and p-type doping can be arbitrarily used for the PFET and the NFET.
  • the type of ions implanted in the step of forming the ground layer 140 depends on the type of the MOSFET and the target value of the threshold voltage. If it is desired to increase the threshold voltage of the device, for NFETs, p-type ions such as boron (8 or 8?
  • n-type ions such as arsenic (As) may be used, Phosphorus (P) or a combination thereof.
  • n-type ions such as arsenic (As), phosphorus (P) or a combination thereof may be used;
  • p-type ions such as boron (B or BF 2 ) or Indium (In ) or a combination thereof.
  • step S102 is performed to form a dummy gate stack and an implant shielding layer on both sides of the dummy gate stack on the SOI substrate.
  • a dummy gate stack is formed on the SOI substrate (specifically, on the SOI layer 100), the dummy gate stack including a gate dielectric layer 260 and a dummy gate 270, which may be A replacement gate process is performed in the subsequent steps to remove the dummy gate 270 to form the desired gate stack structure.
  • the material of the gate dielectric layer 260 may be a thermal oxide layer, including silicon oxide, silicon oxynitride, or a high-k dielectric such as Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La.
  • a thermal oxide layer including silicon oxide, silicon oxynitride, or a high-k dielectric such as Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, A1 2 0 3 , La.
  • One or a combination of 2 0 3 , Zr0 2 , and LaAlO having a thickness between 1 nm and 1 Onm, which can be subjected to chemical vapor deposition (CVD), high-density plasma CVD, or ALD (atomic layer).
  • CVD chemical vapor deposition
  • ALD atomic layer
  • PEALD plasma enhanced atomic layer deposition
  • PLD pulsed laser deposition
  • the material of the dummy gate 270 may include polysilicon, amorphous silicon, or other suitable material.
  • an anneal may be performed to control the doping profile of the ground layer 140 to adjust the turn-on voltage of the device.
  • source/drain extension regions 170 are formed in the SOI layer 100 by low energy implantation, with reference to FIG. P-type or N-type dopants or impurities may be implanted into the SOI layer 100. That is, if the semiconductor device to be fabricated is an NMOS, the SOI layer 100 is doped with N-type impurities such as arsenic and phosphorus. If the semiconductor device is a PMOS, the SOI layer 100 is doped with P-type impurities such as boron and indium. The semiconductor structure is then annealed to activate doping in the source/drain extension 170. In one embodiment, source/drain extension regions 170 may also not be formed.
  • sidewall spacers 210 are formed on both sides of the dummy gate stack for separating the dummy gate stacks.
  • the spacer 210 may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, and/or other suitable materials.
  • the side wall 210 may have a multi-layered structure.
  • the spacer 210 may be formed by a deposition-etching process having a thickness ranging from about 10 nm to about 100 nm, such as 30 nm, 50 nm or 80 nm.
  • the source/drain regions 160 may be formed after the sidewall spacers 210 are formed.
  • the source/drain regions 160 may be formed by implanting P-type or N-type dopants or impurities into the SOI layer 100.
  • the source/drain regions 160 may be P-type doped
  • Source/drain regions 160 may be N-type doped.
  • Source/drain regions 160 may be formed by methods including photolithography, ion implantation, diffusion, and/or other suitable processes.
  • the source/drain regions 160 are formed inside the SOI layer 100.
  • the source/drain regions are higher than the bottom of the gate stack (the bottom of the gate stack referred to in this specification means the gate).
  • the high temperature treatment is then used to activate the impurities, such as an annealing process.
  • the material of the interlayer dielectric layer 250 may include SiO 2 , carbon doped SiO 2 , BPSG, PSG, UGS, silicon oxynitride, a low k material, or a combination thereof.
  • the thickness of the interlayer dielectric layer 250 may range from 40 ⁇ to 150 ⁇ , such as 80 ⁇ , 100 ⁇ or 120 ⁇ .
  • the interlayer dielectric layer 250 and the dummy gate stack on the semiconductor device are subjected to a planarization process of a chemical-mechanical polish (CMP), as shown in FIG. 7, such that the upper surface of the dummy gate stack is The upper surface of the interlayer dielectric layer 250 is flush and exposes the top of the dummy gate 270 and the sidewall spacers 210.
  • CMP chemical-mechanical polish
  • the interlayer dielectric layer 250 will function as an implantation shield during subsequent implantation of stress-inducing ions.
  • step S103 is performed to remove the dummy gate stack to form a gate recess.
  • the dummy gate 270 is removed to form a gate recess 220 as shown in FIG.
  • the dummy gate 270 can be removed by etching.
  • the semiconductor structure is subjected to stress-initiated ion implantation and annealing through the gate recess, and a stress inducing region under the BOX layer of the SOI substrate is formed directly under the gate recess.
  • the semiconductor structure is subjected to stress-induced ion implantation by the gate recess 220 and annealed, and a stress inducing region under the BOX layer of the SOI substrate is formed directly under the gate recess.
  • carbon injection is performed by a conventional ion implantation process to control its energy. In the gate recessed position, carbon ions will pass through the gate dielectric layer, the SOI layer, and the BOX layer into the bulk silicon layer below the BOX layer.
  • the carbon ions will be absorbed by the interlayer dielectric layer 250, so the interlayer dielectric layer 250 acts as an implantation shield during this implantation.
  • High temperature annealing is then performed to activate the carbon to form the stress inducing region 150.
  • laser annealing, flash annealing, or the like can be used to activate the dopant in the semiconductor structure.
  • the semiconductor structure can be annealed using a transient annealing process, such as laser annealing at a high temperature of about 800 to 1100 °C. Annealing also repairs damage to the SOI layer, BOX layer, and ground plane by carbon injection.
  • the stress inducing region 150 is formed in the SOI substrate directly under the gate dielectric layer 260, penetrates the ground layer 140, and extends into the bulk silicon layer 130.
  • the upper plane of the stress inducing region 150 is not higher than the SOI substrate.
  • the formation of the stress inducing region 150 can introduce a compressive stress into the channel region, significantly improving the performance of the p-type semiconductor device. [0059]
  • the gate is to be formed at the position where the gate is recessed in the subsequent step, the position of the stress inducing region 150 is directly under the gate to be formed later. Therefore, the injection of the above stress-inducing ions can be considered to be self-aligned.
  • a gate is then formed at the gate recess.
  • the original gate dielectric layer 260 is removed from the gate recess; then a new gate dielectric layer 280 is formed on the SOI layer 100; forming a new gate over the gate dielectric layer 280
  • the gate metal layer 200 of the dielectric layer 280 may be one of TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTa x , NiTa or a combination thereof, and the thickness thereof is between 5 nm and 20 nm.
  • the gate structure may be by chemical vapor deposition (CVD), high density plasma CVD, ALD (atomic layer deposition), plasma enhanced atomic layer deposition (PEALD), pulsed laser deposition (PLD) or other suitable
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • PLD pulsed laser deposition
  • a first contact plug 230 and a second contact plug 240 may be further formed in the above-described formed semiconductor structure for forming an electrical connection.
  • the specific forming step includes: forming a first contact hole exposing at least a portion of the source/drain region 160 in the dielectric layer 250, and exposing at least a portion of the second contact hole of the ground layer 140.
  • the second contact through the dielectric layer 250 and the isolation region 120 stops on the ground layer 140 and exposes at least a portion of the ground layer 140, and the other first contact hole through the dielectric layer 250 over the source/drain region 160 exposes at least a portion of the source/ Drain area 160.
  • the upper surface of the ground layer 140 may be used as the etching.
  • a stop layer of the contact hole, and the upper plane of the source/drain region 160 is used as a stop layer for etching the first contact hole, so that the first contact hole and the second contact hole are respectively etched to have corresponding stop layers, so that The control requirements of the etching process are reduced, that is, the difficulty of etching is reduced.
  • the first contact hole and the second contact hole are usually filled with metal to form a first contact plug 230 and a second contact plug 240, as shown in Fig. 11.
  • the filler metal is W.
  • the material of the metal may also be any one of W, Al, TiAl alloy or a combination thereof.
  • the semiconductor structure and the method of fabricating the same provided in the present invention form a stress inducing region in a ground layer on an ultrathin SOI substrate, which provides favorable stress for the channel of the semiconductor device, while reducing the short channel effect. Significantly improved the performance of semiconductor devices.

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Abstract

本发明提供了一种半导体结构的制造方法，该方法包括：提供SOI衬底，该SOI衬底从上至下包括基底层（130），BOX层（110）和SOI层（100）；在所述SOI衬底上形成伪栅堆叠以及伪栅堆叠两侧的注入屏蔽层；去除伪栅堆叠形成栅极凹陷（220）；d）通过所述栅极凹陷（220）对半导体结构进行应力引发离子的注入并进行退火，在栅极凹陷（220）正下方形成位于所述SOI衬底的BOX（110）层之下的应力引发区（150）。相应地，本发明还提供了一种根据上述方法形成的半导体结构。

Description

半导体结构及其制造方法
[0001】本申请要求了 2012年 11月 6日提交的、 申请号为 201210591064.4、 发 明名称为"半导体结构及其制造方法"的中国专利申请的优先权，其全部内容 通过引用结合在本申请中。 技术领域
[0002]本发明涉及半导体领域， 具体地说涉及一种半导体结构及其制造方 法。 背景技术
[0003]随着半导体器件制造技术的发展， 具有更高性能和更强功能的集成电 路要求更大的元件密度， 而且各个部件、 元件之间或各个元件自身的尺寸、 大小和空间也需要进一步缩小， 因此半导体器件制造过程中对工艺控制的要 求较高。
[0004]半导体器件通过按比例缩小来实现工作速度的提升。 MOS晶体管的沟 道长度也在不断地按比例缩短， 但当 MOS晶体管的沟道长度变得非常短时， 所谓的短沟道效应（ SCE ),以及漏极感应势垒降低效应（ Drain-Induced Barrier Lowering , DIBL )给半导体器件微型化设置了严重的障碍。
[0005] 由于短沟道效应会使器件性能劣化， 甚至无法正常工作， 因此减小短 沟道效应是半导体器件研究制造中的重要课题。半导体器件内部的机械应力 被广泛地用于调节器件的性能， 通过在沟道施加应力的方法， 可以有效减小 短沟道效应。
[0006]常用的增加应力的方法是在源漏区进行操作， 以便在沟道上形成拉伸 或压缩应力。 例如， 在通用硅技术中， 晶体管沟道沿着硅的 {110}取向。 在 这种布置中，当沟道受到沿着沟道方向的压缩应力和 /或沿着与沟道垂直方向 的拉伸应力时， 空穴的迁移率提高； 而当沟道受到沿着沟道方向的拉伸应力 和 /或沿着与沟道垂直方向的压缩应力时， 电子的迁移率增高。 因此在半导体 器件的沟道区引入应力， 可以提高器件的性能。 [0007]使用 SOI衬底代替硅衬底也可以达到减小短沟道效应和提高器件性能 的效果。 绝缘体上硅（ Silicon On Insulator, SOI )技术是在顶部硅层和衬底 体硅层之间引入了一层埋氧层。 通过在绝缘体上形成半导体薄膜， SOI材料 具有了体硅所无法比拟的优点： 可以实现集成电路中元器件的介质隔离， 彻 底消除了体硅 CMOS电路中的寄生闩锁效应； 采用这种材料制成的集成电路 还具有寄生电容小、 集成密度高、 速度快、 工艺筒单、 短沟道效应小及特别 适用于低压低功耗电路等优势， 因此可以说 SOI将有可能成为深亚微米的低 压、 低功耗集成电路的主流技术。
[0008] 同时， SOI的异质结构为建造具有超薄硅体器件创造了机会。 通过由 硅电介质界面建立的天然静电屏障， 超薄 soi提供一种控制短沟道效应的可 选手段。
[0009] 目前， 有技术采用在超薄 SOI MOS晶体管 （ Ultrathin-SOI MOSFET ) 的超薄 BOX ( Buried Oxide, 埋氧）层之下形成接地层来减小短沟道效应， 并控制功耗。但是如果能在此种结构的半导体器件中引入应力则可以进一步 减小短沟道效应并提高半导体器件的性能。 发明内容
[0010]本发明的目的在于提供一种半导体结构及其制造方法， 通过在 SOI衬 底的 BOX层之下的体硅层中形成应力引发区， 对在 SOI衬底的 SOI层中制造 的半导体器件的沟道区引入有利应力， 提高所述半导体器件的性能。
[0011】一方面， 本发明提供了一种半导体结构的制造方法， 该方法包括： a ) 提供 SOI衬底，该 SOI衬底从上至下包括基底层（ 130 ) , 80 层（ 110 ) 和 SOI层（ 100 ) ；
b ) 在所述 SOI衬底上形成伪栅堆叠以及伪栅堆叠两侧的注入屏蔽层； c ) 去除伪栅堆叠形成栅极凹陷 （220 ) ；
d ) 通过所述栅极凹陷（ 220 )对半导体结构进行应力引发离子的注入并 进行退火， 在栅极凹陷 （220 )正下方形成位于所述 SOI衬底的 BOX ( 110 ) 层之下的应力引发区 （150 ) 。
[0012】相应地， 本发明还提供了一种半导体结构， 该半导体结构包括 [0013] SOI衬底， 从上至下包括 SOI层、 BOX层和体硅层；
[0014]形成于 SOI层之上的栅极堆叠， 包括栅极和栅极介质层；
[0015]应力引发区， 形成在所述栅极正下方的体硅层内。
[0016]本发明提供的半导体结构及其制造方法通过离子注入和退火操作在 栅极正下方的 SOI衬底的 BOX层之下的体硅层中形成应力引发区， 所述应力 有助于提升半导体器件的性能( 附图说明
[0017]通过阅读参照以下附图所作的对非限制性实施例所作的详细描述， 本 发明的其它特征、 目的和优点将会变得更明显：
[0018] 图 1为根据本发明的半导体结构的制造方法的一个具体实施方式的流 程图；
[0019] 图 2〜图 11是根据本发明的一个具体实施方式按照图 1示出的流程制造 半导体结构过程中该半导体结构各个制造阶段的剖视结构示意图。
[0020]附图中相同或相似的附图标记代表相同或相似的部件。 具体实施方式
[0021]为使本发明的目的、 技术方案和优点更加清楚， 下面将结合附图对本 发明的实施例作详细描述。
[0022】下面详细描述本发明的实施例， 所述实施例的示例在附图中示出， 其 中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功 能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本发明， 而不能解释为对本发明的限制。
[0023]下文的公开提供了许多不同的实施例或例子用来实现本发明的不同 结构。 为了筒化本发明的公开， 下文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并且目的不在于限制本发明。 此外， 本发明可以在 不同例子中重复参考数字和 /或字母。这种重复是为了筒化和清楚的目的，其 本身不指示所讨论各种实施例和 /或设置之间的关系。此外，本发明提供了的 各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工 艺的可应用于性和 /或其他材料的使用。另外， 以下描述的第一特征在第二特 征之 "上" 的结构可以包括第一和第二特征形成为直接接触的实施例， 也可 以包括另外的特征形成在第一和第二特征之间的实施例， 这样第一和第二特 征可能不是直接接触。应当注意，在附图中所图示的部件不一定按比例绘制。 本发明省略了对公知组件和处理技术及工艺的描述以避免不必要地限制本 发明。
[0024] 由于本发明提供的半导体结构具有几种优选结构， 下面提供一种优选 结构并进行概述。
[0025]参考图 10, 图 10示出了一种半导体结构，该半导体结构包括 SOI衬底、 接地层 140、 栅极堆叠、 源 /漏区 160、 源 /漏延伸区 170、 应力引发区 150和层 间介质层 250, 其中：
[0026]所述 SOI衬底从上至下包括 SOI层 100、 BOX层 110和体硅层 130;
[0027]所述栅极堆叠包括栅极 200和栅极介质层 280, 所述栅极介质层 280、 栅极 200依次形成在所述 SOI衬底之上；
[0028]所述源 /漏区 160和源 /漏延伸区 170形成于所述 SOI层 100之中， 所述层 间介质层 250覆盖所述源 /漏区 160;
[0029]所述接地层 140位于所述体硅层 130中， 所述 BOX层 110的下方；
[0030]所述应力引发区 150形成在栅极 200正下方的体硅层 130内。
[0031]此外， 在栅极堆叠的两侧还形成侧墙 210。
[0032】所述 SOI衬底至少具有三层结构， 分别是： 体硅层 130、 体硅层 130之 上的 BOX层 110, 以及覆盖在 BOX层 110之上的 SOI层 100。 其中， 所述 BOX 层 110的材料可以选用晶体或者非晶体氧化物、 氮化物或其任意组合， 优选 地， 通常选用 Si02。 SOI层 100的材料是单晶硅、 Ge或 III-V族化合物（如 SiC、 砷化镓、砷化铟或磷化铟等）。本发明中选用的 SOI衬底是具有超薄 SOI层 100 和超薄 BOX层 110的 SOI衬底， 其中超薄 SOI层 100的厚度范围为 5~20nm, 例 如 5nm、 15nm或 20nm;超薄 BOX层 110的厚度范围为 5~30nm,例如 5nm、 20nm 或 30nm。
[0033]可选的，还可以在 SOI衬底中还形成隔离区 120,用于将所述 SOI层 100 分割为独立的区域， 用于后续加工形成晶体管结构所用。 隔离区 120的材料 是绝缘材料， 例如可以选用 Si02、 Si3N4或其组合。 隔离区 120的宽度可以视 半导体结构的设计需求决定。
[0034]栅极堆叠包括栅极 200和栅极介质层 280。 栅极介质层 280的材料可以 是热氧化层， 包括氧化硅、 氮氧化硅， 也可为高 K介质。 栅极 200可以包括栅 金属层、 栅电极层、 多晶硅层等结构。
[0035】侧墙 210可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅和 /或其他合适的 材料形成。 侧墙 210可以具有多层结构。 侧墙 210可以通过沉积 -刻蚀工艺形 成， 其厚度范围大约是 10nm-100nm。
[0036]在 SOI层 100内通过离子注入的方式形成源 /漏区 160和源 /漏延伸区 170。 例如， 对于 PMOS来说， 源 /漏区 160和源 /漏延伸区 170可以是 P型掺杂， 对于 NMOS来说， 源 /漏区 160和源 /漏延伸区 170可以是 N型掺杂。
[0037】接地层 140形成于体硅层 130内靠近 BOX层 110的位置， 例如， 对于 PFET或 NFET可以任意采用 n型或 p型掺杂。 在本发明的一个实施例中， 应力 引发区 150采用碳掺杂形成于接地层 140内。 应力引发区 150的位置在栅堆叠 正下方的体硅层内 （隔着 BOX层）， 有利于为沟道区引入压应力， 显著提高 P型 FET的性能。 行进一步的阐述。
[0039】请参考图 1 , 图 1是根据本发明的半导体结构的制造方法的一个具体实 施方式的流程图， 该方法包括：
[0040]步骤 S101 , 提供 SOI衬底， 该 SOI衬底从上至下包括基底层， BOX层 和 SOI层；
[0041]步骤 S102, 在所述 SOI衬底上形成伪栅堆叠以及伪栅堆叠两侧的注入 展蔽层；
[0042]步骤 S103 , 去除伪栅堆叠形成栅极凹陷；
[0043]步骤 S104,通过所述栅极凹陷对半导体结构进行应力引发离子的注入 并进行退火， 在栅极凹陷正下方形成位于所述 SOI衬底的 BOX层之下的应力 引发区。 [0044]下面结合图 2至图 10对步骤 S101至步骤 S104进行说明，图 2至图 10是根 据本发明的一个具体实施方式按照图 1示出的流程制造半导体结构过程中该 半导体结构各个制造阶段的剖视结构示意图。 需要说明的是， 本发明各个实 施例的附图仅是为了示意的目的， 因此没有必要按比例绘制。
[0045】参考图 2〜图 10, 执行步骤 S101 , 提供 SOI衬底， 该 SOI衬底包括基底 层， BOX层和 SOI层。
[0046]首先参考图 2, 其中， 所述 SOI衬底至少具有三层结构， 分别是： 体硅 层 130、 体硅层 130之上的 BOX层 110 , 以及覆盖在 BOX层 110之上的 SOI层 100。其中，所述 BOX层 110的材料通常选用 Si02。 SOI层 100的材料是单晶硅、 Ge或 III- V族化合物（如 SiC、 砷化镓、 砷化铟或磷化铟等） 。 本发明中选用 的 SOI衬底是具有超薄 SOI层 100和超薄 BOX层 110的 SOI衬底，其中 SOI层 100 的厚度范围为 5~20nm, 例如 5nm、 15nm、 20nm; BOX层 110的厚度范围为 5-3 Onm, 例如 5nm、 20nm、 30nm。
[0047]之后在该 SOI衬底中还形成隔离区 120,用于将所述 SOI层 100分割为独 立的区域， 用于后续加工形成晶体管结构所用， 如图 3所示。 隔离区 120的材 料是绝缘材料， 例如可以选用 Si02、 Si3N4或其组合， 隔离区 120的宽度可以 视半导体结构的设计需求决定。
[0048】形成隔离区 120之后， 通过离子注入的方式形成接地层 140, 参考图 4。 控制注入能量使得所述接地层形成于 BOX层 110之下。 例如， 对于 PFET和 NFET可以任意采用 n型和 p型掺杂。 具体地， 在形成接地层 140的步骤中注入 的离子类型取决于 MOSFET的类型以及阈值电压的目标值。 如果希望提高器 件的阈值电压， 对于 NFET, 可以采用 p型离子， 例如硼（8或8?2 )或铟（In ) 或其组合； 对于 PFET, 可以采用 n型离子， 例如砷（As ) 、 磷（P )或其组 合。 如果希望减小器件的阈值电压， 对于 NFET, 可以采用 n型离子， 例如砷 ( As ) 、 磷（P ) 或其组合； 对于 PFET, 可以采用 p型离子， 例如硼 （B或 BF2 )或铟 （In )或其组合。
[0049]接下来执行步骤 S102 , 在所述 SOI衬底上形成伪栅堆叠以及伪栅堆叠 两侧的注入屏蔽层。 参考图 5 , 在所述 SOI衬底上 （具体而言是在 SOI层 100 上）形成伪栅堆叠， 所述伪栅堆叠包括栅极介质层 260和伪栅 270, 可以在随 后的步骤中进行替代栅工艺， 移除伪栅 270以形成所需的栅极堆叠结构。 其 中， 栅极介质层 260的材料可以是热氧化层， 包括氧化硅、 氮氧化硅， 也可 为高 K介质， 例如 Hf02、 HfSiO、 HfSiON、 HfTaO、 HfTiO、 HfZrO, A1203、 La203、 Zr02、 LaAlO中的一种或其组合， 其厚度在 1 nm〜 1 Onm之间, 可以通 过化学气相沉积（ Chemical vapor deposition , CVD )、高密度等离子体 CVD、 ALD (原子层淀积）、 等离子体增强原子层淀积（PEALD )、 脉沖激光沉积 ( PLD )或其他合适的方法形成在 SOI层 100上。 伪栅 270的材料可以包括多 晶硅、 非晶硅或其他合适的材料。
[0050]在伪栅堆叠形成之后， 可以进行退火以控制接地层 140的掺杂分布， 以便调节器件的开启电压。
[0051]在进行退火之后， 通过低能注入的方式在所述 SOI层 100中形成源 /漏 延伸区 170,参考图 6。可以向所述 SOI层 100中注入 P型或 N型掺杂物或杂质。 即，如果要制作的半导体器件为 NMOS ,则向所述 SOI层 100中掺杂 N型杂质， 例如砷和磷。 如果所述半导体器件为 PMOS , 则向所述 SOI层 100中掺杂 P型 杂质，例如硼和铟。然后对所述半导体结构进行退火，以激活源 /漏延伸区 170 中的掺杂。 在一个实施例中， 也可以不形成源 /漏延伸区 170。
[0052】通常地， 可以考虑在源 /漏延伸区 170形成后， 在伪栅堆叠的两侧形成 侧墙 210, 用于将伪栅堆叠隔开。侧墙 210可以由氮化硅、 氧化硅、 氮氧化硅、 碳化硅和 /或其他合适的材料形成。侧墙 210可以具有多层结构。侧墙 210可以 通过沉积-刻蚀工艺形成， 其厚度范围大约是 lOnm-lOOnm, 如 30nm、 50nm 或 80nm。
[0053]形成侧墙 210之后可以形成源 /漏区 160。 源 /漏区 160可以通过向 SOI层 100中注入 P型或 N型掺杂物或杂质而形成， 例如， 对于 PMOS来说， 源 /漏区 160可以是 P型掺杂， 对于 NMOS来说， 源 /漏区 160可以是 N型掺杂。 源 /漏区 160可以由包括光刻、 离子注入、 扩散和 /或其他合适工艺的方法形成。 在本 实施例中， 源 /漏区 160形成于 SOI层 100内部， 在其他一些实施例中， 源 /漏区 顶部高于栅极堆叠底部 （本说明书中所指的栅极堆叠底部意指栅极堆叠与 SOI层 100的交界线） 。 之后采用高温处理激活杂质， 例如退火工艺。 [0054]在 SOI衬底上形成覆盖所述源 /漏区 160、伪栅堆叠、侧墙 210和隔离 vapor deposition, CVD )、 高密度等离子体 CVD、 旋涂或其他合适的方法形 成在 SOI衬底上。层间介质层 250的材料可以包括 Si02、碳掺杂 Si02、BPSG、 PSG、 UGS、 氮氧化硅、 低 k材料或其组合。 层间介质层 250的厚度范围可 以是 40匪~150匪， 如 80匪、 100匪或 120匪。
[0055]对该半导体器件上的层间介质层 250和伪栅堆叠进行化学机械抛光 ( Chemical-mechanical polish, CMP )的平坦化处理， 如图 7所示， 使得该伪 栅堆叠的上表面与层间介质层 250的上表面齐平， 并露出所述伪栅 270的顶部 和侧墙 210。 如后面将描述的， 层间介质层 250在后续的应力引发离子的注入 过程中将起到注入屏蔽层的作用。
[0056】之后， 执行步骤 S103 , 去除伪栅堆叠形成栅极凹陷。 去除伪栅 270, 形成栅极凹陷 220, 如图 8所示。 可以用刻蚀的方法去除伪栅 270。
[0057]之后， 执行步骤 S104, 通过所述栅极凹陷对半导体结构进行应力引发 离子的注入并进行退火， 在栅极凹陷正下方形成位于所述 SOI衬底的 BOX层 之下的应力引发区。 参考图 9, 通过所述栅极凹陷 220对半导体结构进行应力 引发离子的注入并进行退火， 在栅极凹陷正下方形成位于所述 SOI衬底的 BOX层之下的应力引发区。 例如， 通过传统的离子注入工艺进行碳注入， 控 制其能量。 在所述栅极凹陷位置， 碳离子将穿过栅介质层、 SOI层和 BOX层， 进入 BOX层下方的体硅层中。 而在其他位置， 碳离子将被层间介质层 250吸 收， 因此层间介质层 250在此注入过程中作为注入屏蔽层。 之后进行高温退 火， 以激活碳， 形成应力引发区 150, 例如可以采用激光退火、 闪光退火等， 来激活半导体结构中的掺杂物。 在一个实施例中， 可以采用瞬间退火工艺对 半导体结构进行退火， 例如在大约 800~1100°C的高温下进行激光退火。 退火 还可以修复碳注入对 SOI层、 BOX层和接地层的损伤。
[0058]应力引发区 150形成在栅极介质层 260正下方的 SOI衬底内， 贯穿接地 层 140, 并延伸至体硅层 130内， 应力引发区 150的上平面不高于 SOI衬底的 BOX层 110的下平面。应力引发区 150的形成可以为沟道区引入压应力， 显著 提高 p型半导体器件的性能。 [0059】如下文所述， 由于在后续步骤中将在栅极凹陷的位置处形成栅极， 因 此应力引发区 150的位置处于之后将形成的栅极的正下方。 因此， 上述应力 引发离子的注入可以认为是自对准的。
[0060]参考图 10, 之后在所述栅极凹陷处形成栅极。 首先， 去除所述栅极凹 陷处原有的栅极介质层 260; 之后在 SOI层 100上形成新的栅极介质层 280; 在 所述栅极介质层 280上形成覆盖所述新的栅极介质层 280的栅极金属层 200。 其中，栅极金属层的材料可以选用 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN、 RuTax、 NiTa中的一种或其组合， 其厚度在 5nm~20nm之间。 栅极结构可以通过化学气相沉积（ Chemical vapor deposition , CVD ) 、 高密 度等离子体 CVD、 ALD (原子层淀积）、等离子体增强原子层淀积（ PEALD )、 脉沖激光沉积 （PLD )或其他合适的方法依次沉积栅极介质层 280和栅极金 属层 200之后进行平坦化而形成。
[0061]可选的， 还可以在上述形成的半导体结构中进一步形成第一接触塞 230和第二接触塞 240, 用于形成电连接。 具体形成步骤包括： 分别在介质层 250中形成暴露至少部分源 /漏区 160的第一接触孔，以及暴露至少部分接地层 140的第二接触孔。 贯穿介质层 250以及隔离区 120的第二接触停止在接地层 140上并暴露至少部分接地层 140,另一贯穿源 /漏区 160之上的介质层 250的第 一接触孔暴露至少部分源 /漏区 160。 在一次使用干法刻蚀、 湿法刻蚀或其他 合适的刻蚀方式刻蚀介质层 250形成第一接触孔和第二接触孔的过程中， 可 以将接地层 140的上平面作为刻蚀第二接触孔的停止层， 同时将源 /漏区 160 的上平面作为刻蚀第一接触孔的停止层， 因此刻蚀第一接触孔和第二接触孔 都分别具有对应的停止层， 这样对刻蚀工艺的控制性要求降低， 即降低了刻 蚀的难度。 后续加工中通常在第一接触孔和第二接触孔内填充金属， 形成第 一接触塞 230和第二接触塞 240, 如图 11所示。 优选地， 填充金属为 W, 当然 根据半导体的制造需要， 所述金属的材料还可以选用 W、 Al、 TiAl合金中任 一种或其组合。
[0062]本发明提供的半导体结构及其制造方法在超薄 SOI衬底上的接地层中 形成应力引发区， 为半导体器件的沟道提供了有利应力， 在减小短沟道效应 的同时， 显著提高了半导体器件的性能。 [0063] 虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发 明的精神和所附权利要求限定的保护范围的情况下， 可以对这些实施例进行 各种变化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理 解在保持本发明保护范围内的同时， 工艺步骤的次序可以变化。
[0064]此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工 艺、 机构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作 为本领域的普通技术人员将容易地理解，对于目前已存在或者以后即将开发 出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本 发明描述的对应实施例大体相同的功能或者获得大体相同的结果，依照本发 明可以对它们进行应用。 因此，本发明所附权利要求旨在将这些工艺、机构、 制造、 物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1. 一种半导体结构的制造方法， 包括：
a )提供 SOI衬底，该 SOI衬底从上至下包括基底层（ 130 ) , BOX层（110) 和 SOI层（ 100 ) ；
b )在所述 SOI衬底上形成伪栅堆叠以及伪栅堆叠两侧的注入屏蔽层； c)去除伪栅堆叠形成栅极 陷 （220) ；
d)通过所述栅极凹陷（220)对半导体结构进行应力引发离子的注入并 进行退火， 在栅极凹陷 （220)正下方形成位于所述 SOI衬底的 BOX ( 110) 层之下的应力引发区 （150) 。
2. 根据权利要求 1所述的方法， 在步骤 a) 中还包括： 通过离子注入和 退火工艺形成接地层。
3. 根据权利要求 1所述的方法， 在步骤 b) 中所述伪栅堆叠至少包括伪 栅（ 270 ) 。
4. 根据权利要求 3所述的方法， 在形成伪栅堆叠之后还包括在所述伪栅 堆叠的两侧形成侧墙（210) 。
5. 根据权利要求 3所述的方法，在形成伪栅堆叠之后还包括形成源 /漏区 ( 160) 。
6. 根据权利要求 1所述的方法， 在步骤 b)中注入屏蔽层为层间介质层。
7. 根据权利要求 1所述方法， 在步骤 d)之后还包括在栅极凹陷中形成 栅极介质层和栅极金属层。
8. 根据权利要求 1所述的方法， 其中应力引发离子为碳离子。
9. 根据权利要求 1或 8所述方法， 其中通过自对准的方式对半导体结构 进行应力引发离子的注入。
10. 一种半导体结构， 包括：
SOI衬底，从上至下包括 SOI层（ 100 )、 BOX层（110)和体硅层（ 130 )； 形成于 SOI层（100)之上的栅极堆叠， 包括栅极 (200)和栅极介质层 (260) ；
应力引发区 （150) , 形成在所述栅极（200)正下方的体硅层（130) 内。
11. 根据权利要求 10所述的半导体结构，其特征在于，应力引发区（ 150) 中包含碳离子。
12. 根据权利要求 10所述的半导体结构，其特征在于，所述体硅层（ 130) 中包括接地层， 所述接地层靠近所述 BOX层（110) 。
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