JP2004241755A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2004241755A JP2004241755A JP2003295234A JP2003295234A JP2004241755A JP 2004241755 A JP2004241755 A JP 2004241755A JP 2003295234 A JP2003295234 A JP 2003295234A JP 2003295234 A JP2003295234 A JP 2003295234A JP 2004241755 A JP2004241755 A JP 2004241755A
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Abstract
【解決手段】 凹部14を形成することによってシリコン層3が予め薄膜化された後に、不純物導入領域11が形成される。従って、素子分離絶縁膜5の底面とBOX層2の上面との間に位置している部分のp型のシリコン層3内に、n型の不純物が注入されないため、分離耐圧が低下することを回避できる。しかも、不純物導入領域11はBOX層2の上面に到達して形成されるため、ソース・ドレイン領域12の接合容量が増加することもない。
【選択図】 図1
Description
図1は、本発明の実施の形態1に係る半導体装置の構造を示す断面図である。SOI基板4は、シリコン基板1、BOX(buried oxide)層2、及びp型のシリコン層3がこの順に積層された構造を有している。シリコン層3の上面内には、いわゆる部分分離型の素子分離絶縁膜5が部分的に形成されている。素子分離絶縁膜5の材質は、例えばシリコン酸化膜である。素子分離絶縁膜5の底面とBOX層2の上面とによって、シリコン層3の一部が挟まれている。
図9は、本発明の実施の形態2に係る半導体装置の構造を示す断面図である。サイドウォール9の底面は、ゲート絶縁膜6の底面よりも下方に位置している。即ち、サイドウォール9が形成されている部分のシリコン層3の膜厚は、ゲート絶縁膜6が形成されている部分のシリコン層3の膜厚よりも薄い。
図17,18は、図7に示した構造のうち、凹部14が形成されている付近の構造を拡大して示す断面図である。図17を参照して、ゲート絶縁膜6が形成されている部分のシリコン層3の上面と、凹部14の側面とが成す角度αは、90°よりも大きい。角度αは、Cl2やHBr等のエッチングガスに添加するO2ガスの量によって調整することができる。
凹部14の深さは、エッチング時間によって調整することができる。
図19は、本発明の実施の形態4に係る半導体装置の構造を示す断面図である。SOI基板4内には、NMOSトランジスタとPMOSトランジスタとが形成されている。NMOSトランジスタは、p型のシリコン層31、ゲート絶縁膜61、ゲート電極71、コバルトシリサイド層81,131、サイドウォール91、及びn型のソース・ドレイン領域121を備えている。ソース・ドレイン領域121は、不純物導入領域101,111を有している。NMOSトランジスタに関しては、上記実施の形態1と同様に、凹部141の底面内にソース・ドレイン領域121が形成された構造(以下、本明細書において「リセスソース・ドレイン構造」と称する)が採用されている。
図29は、本発明の実施の形態5に係る半導体装置の構造を示す断面図である。SOI基板4内には、比較的低い電源電圧(例えば1.0V)で動作するMOSトランジスタ(以下「低電圧動作トランジスタ」と称する)と、比較的高い電源電圧(例えば3.3V)で動作するMOSトランジスタ(以下「高電圧動作トランジスタ)とが形成されている。低電圧動作トランジスタは、例えばCPUコアを構成するトランジスタである。高電圧動作トランジスタは、例えば入出力回路を構成するトランジスタである。
図31は、本発明の実施の形態6に係る半導体装置の製造方法の一工程を示す断面図である。上記実施の形態1等では、ポリシリコン膜19上に形成されたシリコン酸化膜20が除去された後に、凹部14を形成するためのエッチングが行われた。そのため、図7に示したように、エッチングによってポリシリコン膜19が薄膜化された結果として、ゲート電極7が形成された。
図32,33は、本発明の実施の形態7に係る半導体装置の製造方法を工程順に示す断面図である。図32を参照して、図31に示す構造を得た後、CVD法によって、シリコン窒化膜又はシリコン酸化膜を全面に形成する。次に、そのシリコン窒化膜又はシリコン酸化膜をエッチバックすることにより、サイドウォール41,42を形成する。サイドウォール41は、サイドウォール9の側面に接して、凹部14の底面上に形成されている。サイドウォール42は、素子分離絶縁膜5の側面に接して、凹部14の底面上に形成されている。
図34,35は、本発明の実施の形態8に係る半導体装置の製造方法を工程順に示す断面図である。図34を参照して、図8に示す構造を得た後、選択的エピタキシャル成長法によって、ゲート電極7上及びソース・ドレイン領域12上に、シリコン層50,51をそれぞれ形成する。次に、イオン注入法によって、シリコン層50,51内にn型の不純物を高濃度で注入する。
図36〜38は、本発明の実施の形態9に係る半導体装置の製造方法を工程順に示す断面図である。図36を参照して、図4に示す構造を得た後、CVD法によって、シリコン窒化膜60を全面的に形成する。次に、写真製版法によって、素子分離絶縁膜5の上方に位置する部分のシリコン窒化膜60上に、フォトレジスト61を形成する。
図39は、本発明の実施の形態10に係る半導体装置の構造を示す断面図である。図1に示した上記実施の形態1に係る半導体装置を基礎として、n型の不純物導入領域70が、シリコン層3の上面内にさらに形成されている。すなわち、ソース・ドレイン領域12は、いずれもn型の不純物導入領域10,11,70を有している。
上記実施の形態10では、NMOSトランジスタのみを形成する例について述べたが、本実施の形態11では、上記実施の形態10に係る発明をCMOSトランジスタの形成に適用する場合の製造方法について説明する。
図57は、本発明の実施の形態12に係る半導体装置の製造方法の一工程を示す断面図である。まず、上記実施の形態1と同様の方法により、図6に示した構造を得る。
Claims (11)
- 半導体基板、絶縁層、及び第1導電型の半導体層がこの順に積層された構造を有するSOI基板と、
前記半導体層の主面内に部分的に形成され、前記絶縁層とによって前記半導体層の一部を挟む底面を有する素子分離絶縁膜と、
前記素子分離絶縁膜によって規定される素子形成領域内において、前記半導体層の前記主面上に部分的に形成されたゲート構造と、
前記素子形成領域内において、前記ゲート構造から露出している部分の前記半導体層の前記主面内に形成され、前記ゲート構造の下方のチャネル形成領域を挟んで対を成す凹部と、
前記凹部の底面内に形成され、前記チャネル形成領域を挟んで対を成し、その底面又はその空乏層が前記絶縁層に到達し、前記第1導電型とは異なる第2導電型のソース・ドレイン領域と
を備える、半導体装置。 - 前記ゲート構造が形成されている部分の前記半導体層の前記主面と、前記凹部の側面とが成す角度は、90°よりも大きい、請求項1に記載の半導体装置。
- 前記凹部の端部は、前記ゲート構造の端部の下方に潜り込んでいる、請求項1又は2に記載の半導体装置。
- 前記ソース・ドレイン領域は、
前記半導体層の前記主面内に形成された、比較的低濃度の第1の不純物導入領域と、
前記第1の不純物導入領域よりも深く形成された、比較的高濃度の第2の不純物導入領域と
を有し、
前記半導体層の前記主面から前記凹部の前記底面までの深さは、前記半導体層の前記主面から前記第1の不純物導入領域の底面までの深さよりも浅い、請求項1〜3のいずれか一つに記載の半導体装置。 - 前記ソース・ドレイン領域は、前記第2の不純物導入領域よりも浅く前記半導体層の前記主面内に形成された第3の不純物導入領域をさらに有する、請求項4に記載の半導体装置。
- 前記ソース・ドレイン領域は、
前記半導体層の前記主面内に形成された、比較的低濃度の第1の不純物導入領域と、
前記第1の不純物導入領域よりも深く形成された、比較的高濃度の第2の不純物導入領域と、
前記半導体層の前記主面内に形成された第3の不純物導入領域と
を有し、
前記半導体層の前記主面から前記第3の不純物導入領域の底面までの深さは、前記半導体層の前記主面から前記第1の不純物導入領域の底面までの深さよりも深く、
前記半導体層の前記主面から前記凹部の前記底面までの深さは、前記半導体層の前記主面から前記第3の不純物導入領域の前記底面までの深さよりも浅い、請求項1〜3のいずれか一つに記載の半導体装置。 - 前記ゲート構造は、
前記半導体層の前記主面上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成されたゲート電極と、
前記ゲート電極の側面に形成された第1のサイドウォールと
を有し、
前記半導体装置は、
前記第1のサイドウォールに接して前記凹部の前記底面上に形成された第2のサイドウォールと、
前記第2のサイドウォールから露出している部分の前記ソース・ドレイン領域上に形成された、金属−半導体化合物層と
をさらに備える、請求項1〜6のいずれか一つに記載の半導体装置。 - 前記素子分離絶縁膜に接して前記凹部の前記底面上に形成された第3のサイドウォールをさらに備え、
前記金属−半導体化合物層は、前記第2及び第3のサイドウォールから露出している部分の前記ソース・ドレイン領域上に形成されている、請求項7に記載の半導体装置。 - 前記凹部の底面上に形成された半導体領域と、
前記半導体領域上に形成された金属−半導体化合物層と
をさらに備える、請求項1〜6のいずれか一つに記載の半導体装置。 - 前記SOI基板内にはNMOSトランジスタ及びPMOSトランジスタが形成されており、
前記半導体装置は、前記NMOSトランジスタ及び前記PMOSトランジスタのうちのいずれか一方である、請求項1〜9のいずれか一つに記載の半導体装置。 - 前記SOI基板内には、比較的低い電源電圧で動作する第1のトランジスタと、比較的高い電源電圧で動作する第2のトランジスタとが形成されており、
前記半導体装置は、前記第1及び第2のトランジスタのうちのいずれか一方である、請求項1〜9のいずれか一つに記載の半導体装置。
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JP2007173356A (ja) * | 2005-12-20 | 2007-07-05 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP2007201240A (ja) * | 2006-01-27 | 2007-08-09 | Renesas Technology Corp | 半導体装置及びその製造方法 |
US8350331B2 (en) | 2006-01-27 | 2013-01-08 | Renesas Electronics Corporation | Semiconductor device and manufacturing method for the same |
JP2015073138A (ja) * | 2006-12-05 | 2015-04-16 | 株式会社半導体エネルギー研究所 | 半導体装置及び半導体装置の作製方法 |
JP2015073137A (ja) * | 2006-12-05 | 2015-04-16 | 株式会社半導体エネルギー研究所 | 半導体装置及び半導体装置の作製方法 |
CN102208448A (zh) * | 2011-05-24 | 2011-10-05 | 西安电子科技大学 | 多晶Si1-xGex/金属并列覆盖双栅SSGOI nMOSFET器件结构 |
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US20050275021A1 (en) | 2005-12-15 |
CN1519946A (zh) | 2004-08-11 |
KR20040065998A (ko) | 2004-07-23 |
KR100523310B1 (ko) | 2005-10-24 |
TWI231044B (en) | 2005-04-11 |
US7067881B2 (en) | 2006-06-27 |
US20040227185A1 (en) | 2004-11-18 |
CN100336228C (zh) | 2007-09-05 |
TW200414547A (en) | 2004-08-01 |
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