WO2010049086A2 - Recessed drain and source areas in combination with advanced silicide formation in transistors - Google Patents
Recessed drain and source areas in combination with advanced silicide formation in transistors Download PDFInfo
- Publication number
- WO2010049086A2 WO2010049086A2 PCT/EP2009/007548 EP2009007548W WO2010049086A2 WO 2010049086 A2 WO2010049086 A2 WO 2010049086A2 EP 2009007548 W EP2009007548 W EP 2009007548W WO 2010049086 A2 WO2010049086 A2 WO 2010049086A2
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- Prior art keywords
- transistor
- drain
- source regions
- gate electrode
- etch
- Prior art date
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- 230000015572 biosynthetic process Effects 0.000 title description 6
- 229910021332 silicide Inorganic materials 0.000 title description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title description 2
- 238000000034 method Methods 0.000 claims abstract description 107
- 230000008569 process Effects 0.000 claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
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- 206010010144 Completed suicide Diseases 0.000 claims abstract description 37
- 125000006850 spacer group Chemical group 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims description 59
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- 229910045601 alloy Inorganic materials 0.000 claims description 15
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 14
- 239000002210 silicon-based material Substances 0.000 claims description 12
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- 239000010410 layer Substances 0.000 description 42
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- 229910052581 Si3N4 Inorganic materials 0.000 description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
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- 238000000151 deposition Methods 0.000 description 11
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- 229910052710 silicon Inorganic materials 0.000 description 9
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- 230000002708 enhancing effect Effects 0.000 description 8
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- 239000002019 doping agent Substances 0.000 description 6
- 238000002513 implantation Methods 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
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- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H01L29/66409—Unipolar field-effect transistors
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- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
- H01L29/66507—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide providing different silicide thicknesses on the gate and on source or drain
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
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Definitions
- the subject matter disclosed herein relates to integrated circuits and more particularly to transistors having strained channel regions by using stress sources, such as stressed overlayers, a strained semiconductor alloy in drain and source areas so as to enhance charge carrier mobility in the channel region of a MOS transistor.
- stress sources such as stressed overlayers, a strained semiconductor alloy in drain and source areas so as to enhance charge carrier mobility in the channel region of a MOS transistor.
- CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency.
- millions of transistors i.e., n-channel transistors and p-channel transistors, are formed on a substrate including a crystalline semiconductor layer.
- a MOS transistor irrespective of whether an n-channel transistor or a p-channel transistor is considered, comprises so-called pn-junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
- the conductivity of the channel region i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer.
- the conductivity of the channel region upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode depends on the dopant concentration, the mobility of the majority charge carriers, and - for a given extension of the channel region in the transistor width direction - on the distance between the source and drain regions, which is also referred to as channel length.
- the overall conductivity of the channel region substantially determines the performance of the MOS transistors.
- the reduction of the channel length is a dominant design criterion for accomplishing an increase in the operating speed and packing density of the integrated circuits.
- the continuing shrinkage of the transistor dimensions involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors.
- One major problem in this respect is to provide for low sheet and contact resistivity in drain and source regions and any contacts connected thereto and to maintain channel controllability.
- reducing the channel length may necessitate an increase of the capacitive coupling between the gate electrode and the channel region, which may call for reduced thickness of the gate insulation layer.
- the thickness of silicon dioxide based gate insulation layers is in the range of 1 to 2 nanometers, wherein a further reduction may be less desirable in view of leakage currents which typically exponentially increase when reducing the gate dielectric thickness.
- One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively.
- creating tensile strain in the channel region increases the mobility of electrons, which, in turn, may directly translate into a corresponding increase in the conductivity and thus drive current and operating speed.
- compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of p-type transistors.
- strained silicon may be considered as a "new" type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
- the dielectric material that is formed above the basic transistor structure may be provided in a highly stressed state so as to induce a desired type of strain at the transistor and in particular in the channel region thereof.
- the transistor structures are typically enclosed by an interlayer dielectric material, which may provide for the desired mechanical and electrical integrity of the individual transistor structures and which may provide a platform for the formation of additional wiring layers, which are typically required for providing the electrical interconnections between the individual circuit elements. That is, a plurality of wiring levels or metallization layers may typically be provided which may include horizontal metal lines and vertical vias including appropriate conductive materials for establishing the electrical connections.
- an appropriate contact structure has to be provided which connects the actual circuit elements, such as transistors, capacitors, and the like, or respective portions thereof with the very first metallization layer.
- the interlayer dielectric material has to be appropriately patterned in order to provide respective openings connecting to the desired contact areas of the circuit elements, which may typically be accomplished by using an etch stop material in combination with the actual interlayer dielectric material.
- silicon dioxide is a well-established interlayer dielectric material in combination with silicon nitride, which may act as an efficient etch stop material during the formation of the contact openings. Consequently the etch stop material, ie. the silicon nitride material, is in close contact with the basic transistor structure and thus may efficiently be used for inducing strain in the transistors, in particular as silicon nitride may be deposited on the basis of well- established plasma enhanced CVD (chemical vapour deposition) techniques with high internal stress. For instance, silicon nitride may be deposited with high internal compressive stress of up to 2 GPa and even higher by selecting appropriate deposition parameters.
- CVD chemical vapour deposition
- a moderately high internal tensile stress level may be created to 1 GPa and higher by appropriately adjusting the process parameters, for instance in particular the degree of ion bombardment during the deposition of the silicon nitride material. Consequently, the magnitude of the strain created in the channel region of a transistor element may depend on the internal stress level of the dielectric etch stop material and the thickness of stressed dielectric material in combination with the effective offset of the highly stressed dielectric material with respect to the channel region. Consequently, in view of enhancing transistor performance it may be desirable to increase the internal stress level and also provide enhanced amounts of highly stressed dielectric material in the vicinity of the transistor element, while also positioning the stressed dielectric material as closely as possible to the channel region.
- the internal stress levels of silicon nitride material may be restricted by the overall deposition capabilities of presently available plasma enhanced CVD techniques, while also the effective layer thickness may substantially be determined by the basic transistor topography and the distance between neighbouring circuit elements. Consequently, although providing significant advantages, the efficiency of the stress transfer mechanism may significantly depend on process and device specifics and may result in reduced performance gain for well-established standard transistor designs having gate lengths of 50 nanometers and less, since the given device topography and the gap fill capabilities of the respective deposition process in combination with a moderately high offset of the highly stressed material from the channel region caused by sophisticated spacer structures may reduce the finally obtained strain in the channel region.
- transistors such as p-channel transistors
- semiconductor materials at least in portions of the drain and source areas, in such a manner that a desired type of strain may be generated in the adjacent channel region.
- a silicon/germanium mixture or alloy may be used, which may be grown by selective epitaxial growth techniques on a silicon template material, thereby creating a strained state of the silicon/germanium alloy, which may exert a certain stress on the adjacent channel region, thereby creating the desired type of strain therein. Consequently, in combination with an overlying stressed dielectric material, a highly efficient strain inducing mechanism may be accomplished for p-channel transistors.
- the conductivity of doped silicon-based semiconductor regions may be increased by providing a metal suicide therein in order to reduce overall sheet resistance and contact resistivity.
- the drain and source regions may receive a metal suicide, such as nickel suicide, nickel platinum suicide and the like, thereby reducing the overall series resistance of the conductive path between the drain and source terminals and the intermediate channel region.
- a metal suicide may typically be formed in the gate electrode, which may comprise polysilicon material, thereby enhancing conductivity and thus reducing signal propagation delay.
- a substantially complete silicidation of the polycrystalline silicon material down to the gate dielectric material may not be desirable in view of threshold voltage adjustment of the corresponding transistor element. It may therefore be desirable to maintain a certain portion of the doped polysilicon material in direct contact with the gate dielectric material so as to provide well-defined electronic characteristics in the channel region, so as to avoid significant threshold variations, which may be caused by a substantially full silicidation within portions of the gate electrode. Consequently, it may be difficult to provide a significant amount of metal suicide, while nevertheless reliably avoiding a complete silicidation of the polysilicon material. Other characteristics of the gate electrode may also have an influence on the overall transistor performance.
- the height of the gate electrode which, however, may typically be limited due to required ion blocking capabilities during the generation of the drain and source dopant profiles by sophisticated implantation techniques.
- This required gate height may result in an increased fringing capacitance with respect to contact elements, which may be formed so as to connect the drain and source regions. Consequently, the overall performance of complex transistor elements may be less pronounced than expected, even though corresponding performance increasing mechanisms, such as strained silicon/germanium material and the like may be used, as will be described in more detail with reference to Figs 1a and 1 b.
- Fig 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 , above which is formed a semiconductor layer 103, in which a plurality of isolation structures 104 may define active regions 103a, 103b of an n-channel 150a and a p-channel transistor 150b, respectively.
- An active region is to be understood as a portion of the semiconductor layer 103 in which appropriate dopant profiles are to be established in order to obtain the desired transistor function.
- the transistors 150a, 150b comprise a gate electrode 151 that is formed on a gate insulation layer 152, which separates the gate electrode 151 from a channel region 153.
- a spacer structure 155 is formed on a portion of the sidewalls of the gate electrode 151 , wherein it should be appreciated that the spacer structure 155 may have any appropriate configuration as is required for defining the dopant profile of corresponding drain and source regions 154.
- the spacer structure 155 may comprise a plurality of individual spacer elements, possibly in combination with corresponding etch stop liners (not shown).
- the p-channel transistor 150b comprises a silicon/germanium alloy 105, which may have a strained state so as to create a corresponding compressive strain component in the channel region 153 of the transistor 150b.
- the semiconductor device 100 as shown in Fig 1 a may be formed on the basis of the following process sequence.
- the active regions 103a, 103b may be defined by established implantation techniques in combination with a corresponding masking regime.
- the gate electrodes 151 in combination with the gate insulation layers 152 may be formed, for instance providing an appropriate dielectric material and depositing a polysilicon material, which may then be patterned on the basis of sophisticated lithography and etch techniques.
- a height 151 h of the gate electrode 151 may typically be selected so as to provide for a sufficient ion blocking effect during the subsequent processing of the device 100.
- the transistor 150a may be masked, for instance by a hard mask in combination with a resist mask, while also the gate electrode 151 of the transistor 150b may be encapsulated, for instance on the basis of appropriate cap layers and sidewalls spacers (not shown) in order to form corresponding cavities in the active region 103b and subsequently depositing the silicon/germanium alloy 105 on the basis of selective epitaxial growth techniques.
- the mask layer may be removed and the gate electrodes 151 may be exposed and the further processing may be continued, for instance by forming offset spacer elements, if required, which may be used for a first implantation sequence for defining a first part of the drain and source regions 154.
- the spacer structure 155 is formed by depositing an appropriate layer stack, such as an etch stop liner such as silicon dioxide followed by a silicon nitride material, which may be accomplished by well-established CVD (chemical vapour deposition) techniques. Thereafter, the layer stack is patterned by an anisotropic etch process, during which silicon nitride material is preferably removed from horizontal portions, while typically reliably exposing the horizontal device areas and also a portion 151 s of the sidewalls of the gate electrodes 151 are exposed during the corresponding etch process and during subsequent etch and cleaning processes. Next, further implantation sequences may be performed so as to obtain the desired dopant profile for the drain and source regions 154.
- an appropriate layer stack such as an etch stop liner such as silicon dioxide followed by a silicon nitride material, which may be accomplished by well-established CVD (chemical vapour deposition) techniques.
- the layer stack is patterned by an anisotropic etch process, during which silicon nitride material is preferably removed from
- the device 100 is prepared for performing a silicidation process which may typically include corresponding cleaning processes, thereby even further exposing the sidewall portion 151 s.
- Fig 1 b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which metal suicide regions 155 are formed in a portion of the drain and source regions 154, while also metal suicide 157 is formed in the gate electrode 151.
- nickel and platinum may be used for obtaining the metal suicide 156, 157 wherein, due to the different diffusion behaviour of the polycrystalline material in the gate electrode 151 and the crystalline material in the drain and source regions 154, a significantly different "conversion rate" may be obtained wherein, in particular, at the sidewall portion 151s metal may increasingly diffuse into the gate electrode 151 , thereby resulting in an increased silicidation rate.
- the metal suicide 157 may extend down to the gate insulation layer 152, at least locally within the gate electrode 151 , thereby resulting in a corresponding threshold voltage variation since the work function of the metal suicide may differ from the corresponding work function of the correspondingly doped polysilicon material.
- the further processing may be continued, for instance by depositing strain inducing material layers, for instance in the form of silicon nitride, which may be deposited with high compressive and tensile stress, depending on the deposition parameters used.
- a tensile stressed silicon nitride material may be formed above the n-channel transistor 150a, while a compressively stressed silicon nitride material may be formed above the transistor 150b, thereby appropriately enhancing overall performance of these transistors due to the corresponding additional strain created in the channel regions 153.
- an interlayer dielectric material such as silicon dioxide and the like, is deposited and patterned so as to obtain corresponding contact openings, which are subsequently filled with a conductive material, such as tungsten, thereby providing contact elements connecting to the gate electrodes 151 and the drain and source regions 154.
- the contact elements extending to the drain and source regions 154 may define, together with the gate electrode 151 and the intermediate dielectric material, a corresponding parasitic capacitor, which may have an influence on the overall channel controllability, which is typically referred to as fringing capacitance. Consequently, although reduced device dimensions may be applied in combination with sophisticated strain inducing mechanisms, the transistors 150a, 150b may suffer from a less pronounced performance gain due to a moderately high fringing capacitance, while also a certain degree of threshold variability may be observed.
- the present disclosure relates to semiconductor devices and techniques for forming transistor elements, while avoiding or at least reducing one or more of the problems identified above.
- the subject matter disclosed herein relates to semiconductor devices and techniques for fabricating the same, wherein enhanced transistor performance may be obtained for n-channel transistors and p-channel transistors on the basis of a recessed transistor configuration, at least for one type of transistor, while additionally a height of a gate electrode may be removed in order to reduce the fringing capacitance between contact elements and the gate electrode.
- the reduced height of the gate electrode may nevertheless result in enhanced controllability of a corresponding silicidation process, thereby significantly reducing the probability of completely suiciding the polysilicon gate electrode material, which may therefore result in reduced threshold variability.
- the reduction of the gate height and the recessing of drain and source regions of at least one transistor may be accomplished on the basis of a non-masked etch regime, thereby not unduly contributing to overall process complexity.
- a semiconductor alloy may be provided in one type of transistor with an appropriate amount of excess height so as to allow a substantially planar transistor configuration even after recessing the drain and source areas of the other type of transistors. Due to the recessed drain and source configuration, the overall strain inducing effect of a corresponding highly stressed dielectric material may be enhanced, since a stressed dielectric material may be positioned at a height level that corresponds to the channel region 153. Furthermore, an increased surface area for the silicidation process may be provided in the drain and source regions, thereby reducing the overall series resistance between the drain and source terminals.
- On illustrative semiconductor device disclosed herein comprises drain and source regions of a first transistor formed in a semiconductor material, wherein the drain and source regions have a recessed surface portion that is positioned at a lower height level compared to a height level defined by a surface of a gate insulation layer of the first transistor.
- the semiconductor device further comprises a gate electrode formed on the gate insulation layer, which comprises a doped silicon material that is formed on the gate insulation layer and which comprises a metal suicide formed on the doped silicon material.
- a spacer structure is provided so as to have a height that is greater than a height of the gate electrode and metal suicide regions are formed in the drain and source regions.
- One illustrative method disclosed herein comprises forming a spacer structure on sidewalls of a gate electrode of a transistor and exposing drain and source regions of the transistor and the gate electrode to an etch ambient so as to remove material at least from the gate electrode selectively to the spacer structure.
- the method further comprises forming a metal suicide material in the drain and source regions and the gate electrode after removing the material.
- the method comprises forming a strain inducing layer above the gate electrode and the drain and source regions.
- a still further illustrative method disclosed herein comprises forming an etch process so as to remove material from a first gate electrode of a first transistor and a second gate electrode of a second transistor and from drain and source regions from the first and/or the second transistor while protecting sidewalls of the first and second gate electrodes by a spacer structure. Moreover, the method comprises forming a metal suicide in the first and second gate electrodes and the drain and source regions in the presence of the spacer structure, wherein the metal suicide terminates in a doped silicon material of the first and second gate electrodes.
- Figs 1 a and 1 b schematically illustrate cross-sectional views of a sophisticated semiconductor device including an n-channel transistor and a p-channel transistor during various manufacturing stages in forming a metal suicide and strain inducing mechanisms according to conventional strategies;
- Figs 2a - 2c schematically illustrate cross-sectional views of a semiconductor device including different types of transistors during various manufacturing stages, wherein a recessed drain and source configuration may be formed in combination with reducing a height of a gate electrode structure according to illustrative embodiments;
- Figs 2d and 2e schematically illustrate cross-sectional views of the semiconductor device according to still further illustrative embodiments, in which recessing of drain and source regions and reducing the gate height may be coupled to a certain degree;
- Fig 2f schematically illustrates a cross-sectional view of the semiconductor device in a further advanced manufacturing stage according to still further illustrative embodiments.
- the present disclosure relates to semiconductor devices and process techniques for providing a recessed transistor configuration, for instance in a selective manner, while at the same time enabling a reduction of the height of gate electrodes while nevertheless providing for reduced threshold variability due to using the probability of creating fully suicided gate electrode structures.
- a recessed drain and source configuration of, for instance, one type of device, such as an n-channel transistor, an enhanced surface topography may be provided for the subsequent deposition of a highly stressed dielectric material, such as a dielectric etch stop layer, an interlayer dielectric material and the like.
- the recessed drain and source configuration may enable the positioning of the highly stressed dielectric material more closely to the channel region, even if a reduced layer thickness in other device regions may be required due to the restricted conformal deposition capabilities of the deposition process under consideration.
- the amount of dielectric material positioned closely to the channel region at a height level that substantially corresponds to the height level of the channel region may be increased which, in combination with the generally enhanced lateral stress transfer, may provide for a higher strain in the adjacent channel region, thereby contributing to enhanced charge carrier mobility and thus drive current capability of the transistor under consideration.
- the recessed drain and source configuration may also provide an increased surface area that is available in a silicidation process, which may therefore result in a reduced sheet resistance of the contact areas of the transistor.
- a substantially complete silicidation of the gate electrode may be suppressed, although a reduced height thereof may be created prior to the silicidation process so that in total any threshold variabilities may be reduced, while also the resulting fringing capacitance may be maintained at a reduced level compared to conventional strategies.
- the degree of recess, if any, in p-channel transistors may be adjusted on the basis of the amount of any excess material that may be formed in the drain and source areas in the form of a strain inducing semiconductor alloy, thereby enabling an efficient reduction of gate height, wherein the finally obtained level of the drain and source areas may be adjusted on the basis of the previously provided excess material. Consequently, the strain inducing effect of the semiconductor alloy may substantially be maintained while at the same time the reduced gate height with the enhanced controllability of the metal suicide formation may also provide for reduced transistor variability and a reduced fringing capacitance.
- FIGs 2a - 2f further illustrative embodiments will now be described in more detail, wherein also reference may be made to Figs 1 a and 1 b, if appropriate.
- Fig 2a schematically illustrates a cross-sectional view of a semiconductor device 200, which may comprise a substrate 201 above which may be formed a semiconductor layer 203.
- the semiconductor layer 203 in combination with the substrate 201 may form, at least in some device areas of the device 200, an SOI configuration when a buried insulating layer 202 is provided.
- the layer 202 as illustrated in Fig 2a may represent a substantially crystalline material, such as an upper portion of the substrate 201.
- isolation structures 204 such as shallow trench isolations and the like, may define corresponding active regions 203a, 203b for transistors 250a, 250b, respectively.
- the transistor 250a may represent an n-channel transistor while the transistor 250b may represent a p-channel transistor.
- the transistor 250a, 250b may comprise a gate electrode 251 , a gate insulation layer 252 and a spacer structure 255 that is formed on a portion of the sidewalls of the gate electrode 251 , thereby exposing an upper sidewall portion 251 s.
- drain and source regions 254 may be formed in the active regions 203a, 203b, which may laterally enclose respective channel regions 253.
- the transistor 250b may comprise a strain inducing semiconductor alloy 205, such as a silicon/germanium alloy, a silicon/germanium/tin alloy, a silicon/tin alloy and the like, if a corresponding compressive strain is desired in the channel region 253.
- a strain inducing semiconductor alloy 205 such as a silicon/germanium alloy, a silicon/germanium/tin alloy, a silicon/tin alloy and the like, if a corresponding compressive strain is desired in the channel region 253.
- the semiconductor device 200 may be formed on the basis of corresponding manufacturing techniques, as are also described with reference to the device 100.
- the sidewall portion 251 s may have been exposed, which conventionally may result in a certain degree of metal "wraparound" during the silicidation process, which may thus result in a moderately high diffusion rate and thus silicidation rate. Consequently, the increased silicidation rate may contribute to a corresponding variability of transistor characteristics, as previously explained.
- Fig 2b schematically illustrates the semiconductor device 200 in an advanced manufacturing stage.
- the device 200 is exposed to an etch ambient 206, which in one illustrative embodiment may be established as a plasma ambient on the basis of an appropriate etch chemistry so as to obtain a high degree of etch selectivity for silicon material with respect to silicon dioxide, silicon nitride and the like.
- the spacer structure 255 may be comprised of a silicon nitride material according to well-established techniques, possibly in combination with a silicon dioxide-based etch liner 255a.
- well-established highly selective etch recipes may be used for establishing the process 206.
- similar process recipes may be used, as are typically applied when patterning the gate electrode 251 .
- material of the gate electrode 251 may be removed selectively to the spacer structure 255, while at the same time material of the drain and source regions 254 may be removed selectively with respect to the isolation structures 204 and the spacer structure 255. Consequently, corresponding recesses 206r are formed in the drain and source regions 254, at least at the transistor 250a, while in the transistor 250b, depending on the initial thickness of the semiconductor alloy 205, a substantially planar configuration may be obtained, as illustrated, while in other cases a certain degree of excess height may still be maintained or a recessing may be produced, however with a less pronounced depth compared to the recesses 206r.
- the recesses 206r may be defined as device regions in which a surface 206s may have a portion, such as the centre portion, the height level of which is positioned lower compared to a height level of the interface between the gate insulation layer 252 and the channel region 253.
- the initial height of the gate electrode 251 is reduced so as to obtain a reduced gate height 251 r, which may be selected such that the spacer structure 255 may extend above the gate electrode 251.
- the reduced gate height 251 r allows for a reduced fringing capacitance with respect to contact elements still to be formed, while at the same time the surface area of the gate electrode 251 that may be available during a silicidation process may be restricted by the spacer structure 255, thereby also reducing the overall silicidation rate. Consequently, the etch process 206 may provide for an enhanced surface topography implementing an efficient strain inducing mechanism, at least in the transistor 250a on the basis of a stressed dielectric material to be deposited in a later manufacturing stage, while also providing for enhanced controllability of a silicidation process, wherein additionally the reduced height 251 r provides enhanced transistor performance due to a reduced fringing capacitance.
- the process 206 may be performed as a non-masked process, thereby not unduly contributing to overall process complexity, for instance in terms of additional lithography steps and the like.
- the etch process 206 may comprise additional cleaning recipes, for instance on the basis of wet chemical etch processes, in order to prepare the exposed portions of the drain and source regions 254 and of the gate electrode 251 for the subsequent silicidation process.
- Fig 2c schematically illustrates the semiconductor device 200 in an advanced manufacturing stage.
- metal suicide regions 256 such as nickel/platinum suicide regions are formed in the drain and source regions of the transistors 250a, 250b. Due to the recessing of the drain and source regions 254 of at least the transistor 250a, an increased surface area of the region 256 may be obtained compared to conventional configurations as for instance shown in Fig 1 b, thereby enhancing overall conductivity of the transistor 250a.
- the metal suicide 256 may define a recessed configuration, that is, at least a surface portion 256s may be positioned at a height level that is lower compared to a height level of the interface between the gate insulation layer 252 and the channel region 253.
- any positional information is to be considered as relative position statements, wherein the substrate 201 is to be used as a reference.
- the channel region 253 and the metal suicide regions 256 are formed "above” the substrate 201 , wherein however the surface portion 256s is positioned “lower” compared to the interface between the channel region 253 and the gate insulation layer 252.
- the gate electrode 251 comprises a metal suicide region 257, which may be separated from the gate insulation layer 252 by a doped polysilicon material 251 b. It should be appreciated that the degree of doping of the polysilicon materials 251 d may be different in the transistors 250a, 250b, due to the preceding implantation processes for defining the corresponding drain and source regions 254. Consequently, the threshold characteristics of the respective transistors 250a, 250b may be determined by the correspondingly doped silicon regions 251 b.
- a well-defined metal suicide portion such as the region 257, may be formed while also maintaining a silicon- based material, such as the material 251 b, so as to reduce the probability of substantially completely silicidizing the initial silicon-based gate electrode material, which may conventionally result in significant threshold variability.
- the metal suicide regions 256 and 257 may be formed on the basis of well-established process techniques in which an appropriate refractory metal, such as nickel, platinum and the like, may be deposited and may be converted into a metal suicide by performing an appropriate heat treatment. Thereafter, any non- reacted metal material may be removed on the basis of well-established selective etch techniques, wherein additional heat treatments for stabilizing the overall characteristics may follow, if required.
- the spacer structure 255 may reliably cover the sidewalls of the gate electrode 251 , thereby avoiding significant metal "wraparound" so that enhanced controllability and uniformity of the silicidation process may be accomplished. Consequently, a desired thickness of the metal suicide regions 257 may be obtained in a highly controllable manner.
- Fig 2d schematically illustrates the semiconductor device 200 according to further illustrative embodiments, in which the degree of recessing of the drain and source regions 254 may be decoupled to a certain degree of reducing the height of the gate electrode 251.
- an etch process 206a such as a plasma-based etch process, may be performed so as to obtain a substantially anisotropic etch behaviour in order to substantially define a desired degree of recessing 206r in the drain and source regions 254 of the transistor 250a, while efficient excess material may be provided for the semiconductor alloy 205 in the transistor 250b when a significant degree of recessing is not desired for this transistor.
- the etch process 206a may be performed on the basis of well-established highly selective etch recipes, as is also previously described. It should be appreciated that, depending on the desired degree of recessing 206r, also a corresponding degree of recessing 206g may be obtained in the gate electrode 251.
- Fig 2e schematically illustrates the semiconductor device 200 when exposed to a further etch ambient 206b, which may be designed as a selective wet chemical etch ambient in order to preferably remove material in the gate electrode 251 , while substantially maintaining the desired degree of recessing 206r in the transistor 250a.
- the etch ambient 206b may be established by using tetramethyl ammonium hydroxide (TMAH), which is a well-established material for etching exposed photoresist material.
- TMAH tetramethyl ammonium hydroxide
- TMAH tetramethyl ammonium hydroxide
- the etch rate of TMAH in crystalline silicon material having a high degree of n-doping may significantly be slowed down compared to polycrystalline silicon material. Consequently, the height of the gate electrode 251 may efficiently be reduced, while a significant increase of the recess 206r in the drain and source regions 254 of the transistor 250a may be avoided.
- the p-doped semiconductor alloy 205 may also be removed during the process 206b, wherein a previously provided excess height may selected such that a desired degree of recessing or a substantially planar configuration or a reduced degree of excess height may be achieved in the transistor 250b.
- a corresponding excess amount of semiconductor alloy material may be provided so as to take into consideration the etch sequence comprising the process steps 206a and 206b in order to obtain the desired topography for the drain and source regions 254 of the transistor 250b. Consequently, on the basis of the etch process 206b, the final gate height 251 r and the depth of the recess 206r may substantially be decoupled from each other so as to provide for a further reduced fringing capacitance while not contributing to reduced reliability of a corresponding silicidation process for forming metal suicide regions in the drain and source areas 254 in view of shorting the corresponding pn junctions and the like.
- Fig 2f schematically illustrates the semiconductor device 200 in a further advanced manufacturing stage.
- an interlayer dielectric material 211 is formed above the transistors 250a, 250b, for instance in the form of a silicon dioxide material, wherein also a strain inducing portion 210a for the transistor 250a and a strain inducing portion 210b for the transistor 250b may be provided.
- the layers 210a, 210b may be provided as a silicon nitride material having a desired internal stress level so as to individually enhance performance of the transistors 250a, 250b, respectively.
- the transistor 250a may represent an n-channel transistor and thus the layer 210a may be provided in the form of a tensile stressed material, possibly in combination with an etch stop material and the like, as may be required in accordance with corresponding process strategies.
- the layer 210b may be provided in the form of a compressively stressed silicon nitride material, or any other appropriate material, thereby enhancing performance of the transistor 250b.
- the corresponding stress component may more efficiently act on the channel region 253, as previously explained, thereby providing higher strain levels in the channel region 253, even if in general a reduced thickness for the layer 210a may have to be used, for instance with respect to the overall packing density of the device 200 and the like.
- the transistor 250b may have the combined strain effect of the material 205 and the layer 210b. It should be appreciated, however, that any other configuration for the layers 210a, 210b may be used, depending on the overall device strategy.
- the layers 210a, 210b may be provided with the same internal stress level, thereby significantly reducing overall process complexity.
- a high stress level such as tensile stress
- tensile stress may be used in order to enhance performance of the transistor 250a, while a corresponding stress effect in the transistor 250b may be compensated for or overcompensated by the material 205.
- an excess height of the material 205 may be maintained during the preceding manufacturing processes, thereby further reducing the effect of the layer 210b.
- a tensile stressed material may be deposited and may subsequently be selectively relaxed above the transistor 250b, for instance by ion implantation and the like.
- the interlayer dielectric material 21 1 may be deposited and may be planarized in accordance with well-established process techniques.
- corresponding lithography and etch processes may be performed so as to obtain corresponding contact openings, in which are to be formed contact elements 212, indicated as dashed lines.
- well-established process techniques may be applied. Consequently, the corresponding contact elements 212 may produce a reduced fringing capacitance with a gate electrode 251 due to the reduced height thereof, while nevertheless the portion 251 b may provide for a well-defined threshold behaviour of the transistors 250a, 250b.
- the present disclosure provides semiconductor devices and techniques for forming the same in which a plurality of performance enhancing mechanisms may be implemented, while avoiding or at least significantly reducing any combined negative defects. That is, a recessed drain and source configuration may be accomplished without unduly adding to process complexity, while also a reduction of gate height may be accomplished during the same etch sequence. On the other hand, the reduction in gate height during recessing of the drain and source regions results in enhanced process uniformity and reliability of the subsequent silicidation process. Consequently, reduced fringing capacitance in combination with reduced threshold variability and enhanced transistor performance due to the recessed drain and source configuration may be accomplished. Further modifications and variations of the present disclosure will be apparent to those skilled in the art in view of this description.
Abstract
Description
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JP2011533583A JP5544367B2 (en) | 2008-10-31 | 2009-10-21 | Recessed drain and source areas combined with advanced silicide formation in transistors |
CN200980143153.9A CN102203915B (en) | 2008-10-31 | 2009-10-21 | The recessed drain be combined with advanced Formation of silicide in transistor and source area |
KR1020117012510A KR101482200B1 (en) | 2008-10-31 | 2009-10-21 | Recessed drain and source areas in combination with advanced silicide formation in transistor |
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DE102008054075.7 | 2008-10-31 | ||
US12/549,769 | 2009-08-28 | ||
US12/549,769 US8026134B2 (en) | 2008-10-31 | 2009-08-28 | Recessed drain and source areas in combination with advanced silicide formation in transistors |
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US20020053711A1 (en) * | 1997-06-30 | 2002-05-09 | Chau Robert S. | Device structure and method for reducing silicide encroachment |
US6887762B1 (en) * | 1998-11-12 | 2005-05-03 | Intel Corporation | Method of fabricating a field effect transistor structure with abrupt source/drain junctions |
US20040227185A1 (en) * | 2003-01-15 | 2004-11-18 | Renesas Technology Corp. | Semiconductor device |
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