TWI626678B - 用於類比應用之高增益電晶體 - Google Patents

用於類比應用之高增益電晶體 Download PDF

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TWI626678B
TWI626678B TW106119447A TW106119447A TWI626678B TW I626678 B TWI626678 B TW I626678B TW 106119447 A TW106119447 A TW 106119447A TW 106119447 A TW106119447 A TW 106119447A TW I626678 B TWI626678 B TW I626678B
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transistor
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dopant concentration
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孫遠
學深 陳
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格羅方德半導體私人有限公司
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Abstract

本發明所揭示的是一種類比高增益電晶體。類比高增益電晶體的形成與現有CMOS製程高度相容。類比高增益電晶體包括雙重井，其包括低電壓(LV)與中間電壓(IV)電晶體的井植入物。另外，類比高增益電晶體包括IV電晶體的輕摻雜延展區、及LV電晶體的薄閘極介電質。

Description

用於類比應用之高增益電晶體
本發明是關於提供具有高增益且改良型Rout的CMOS電晶體，其適用於低功率類比與IoT應用。
互補式金屬氧化物半導體(CMOS)電晶體已受到廣泛運用。舉例而言，CMOS電晶體已用於類比應用。類比應用需要具有高增益的CMOS電晶體。然而，已發現目前用於類比應用的CMOS電晶體會遇到高漏電流的問題，使其在低功率與物聯網(IoT)應用受到限制。再者，這些CMOS電晶體的輸出電阻(Rout)就類比應用而言，並不適用於短通道裝置。
具體實施例大體上是關於半導體裝置或積體電路(IC)。在一項具體實施例中，所揭示的是一種用於形成裝置的類比高增益電晶體的方法。本方法包括形成位在基板上的類比裝置，並且形成位在裝置區中的類比裝置井。該裝置井包括類比井體摻質濃度，其就LV電晶體高於低電壓(LV)裝置井的摻質濃度，並且就IV電晶體高於中 間電壓(IV)裝置井的摻質濃度。本方法更包括形成位在裝置區中基板上的類比閘極。該閘極包括位在類比閘極介電質上方的類比閘極電極。該類比閘極介電質是用於該LV電晶體的薄閘極介電質。該基板中該裝置井中諸類比源極汲極(S/D)區相鄰於該類比閘極。一S/D區包含重度摻雜主區及類比輕度摻雜延展區。該類比輕度摻雜延展區就IV電晶體包括IV輕度摻雜延展區的摻質濃度。該類比裝置井的該更高摻雜濃度、該類比閘極的該薄閘極介電質、及該類比S/D區的該IV輕度摻雜延展區提升該類比高增益電晶體的效能。
在另一具體實施例中，所揭示的是一種屬於一裝置的類比高增益電晶體。該類比高增益電晶體包括位在基板上的類比裝置區、及位在該裝置區中的類比裝置井。該裝置井包括井體摻質濃度，其高於用於LV電晶體的LV裝置井的低電壓(LV)摻質濃度、或用於IV電晶體的IV裝置井的中間電壓(IV)摻質濃度。該電晶體更包括位在裝置區中基板上的類比閘極。該閘極包括位在類比閘極介電質上方的類比閘極電極。該類比閘極介電質是用於該LV電晶體的薄閘極介電質。該電晶體更包括相鄰於該類比閘極的諸類比源極汲極(S/D)區，其中一S/D區包括重度摻雜主區及類比輕度摻雜延展區。該類比輕度摻雜延展區就IV電晶體包括IV輕度摻雜延展區的摻質濃度。該類比裝置井的該更高摻雜濃度、該類比閘極的該薄閘極介電質、及該類比S/D區的該IV輕度摻雜延展區提升該類比高增益電晶 體的效能。
在又一個具體實施例中，揭示用於形成裝置的方法。本方法包括在具有用於LV電晶體的LV裝置井的基板上形成低電壓(LV)裝置區。該LV裝置井包括LW井體摻質濃度。亦在具有用於IV電晶體的IV裝置井的基板上形成中間(IV)裝置。該IV裝置井包括IV井體摻質濃度。本方法更包括在就類比電晶體具有類比裝置井的基板上形成類比裝置區。該類比裝置井包括類比井體摻質濃度，其高於該LV裝置井摻質濃度或該IV井體摻質濃度。本方法更包括形成位在LV裝置區中的LV電晶體。該LV電晶體包括在屬於薄閘極介電質的LV閘極介電質上方具有LV閘極電極的LV閘極、以及相鄰於該LV閘極的諸LV S/D區。一LV S/D區包括LV重度摻雜主S/D區、及具有LV延展摻質濃度的LV延展區。在該IV裝置區中形成該IV電晶體。該IV電晶體包括在屬於中間閘極介電質的IV閘極介電質上方具有IV閘極電極的IV閘極，該中間閘極介電質比該薄閘極介電質具有更大的厚度。該IV電晶體更包括相鄰於該IV閘極的IV S/D區。IV S/D區包括IV重度摻雜主S/D區、及具有比LV延展摻質濃度更低的IV延展摻質濃度的IV延展區。本方法更包括形成位在類比裝置區中的類比高增益電晶體。該類比高增益電晶體包括在與該薄閘極介電質具有相同厚度的類比閘極介電質上方具有類比閘極電極的類比閘極、及相鄰於該類比閘極的類比S/D區。該類比S/D區包括類比重度摻雜主S/D區、及具有比LV延 展摻質濃度更低的類比延展摻質濃度的類比延展區。
本文中所揭示的具體實施例的這些及其它優點及特徵，透過參考以下說明及附圖會變為顯而易見。再者，要瞭解的是，本文中所述的各項具體實施例的特徵並不互斥，並且可用各種組合及排列呈現。
100‧‧‧裝置
102‧‧‧第一裝置區
104‧‧‧第二裝置區
105‧‧‧基板
105a‧‧‧第一主表面
105b‧‧‧第二主表面
106‧‧‧第三裝置區
114‧‧‧裝置井、電晶體井
120‧‧‧第一電晶體、類比高增益(AHG)電晶體
124‧‧‧第二電晶體、核心電晶體
126‧‧‧第三電晶體、輸入/輸出(I/O)電晶體
150‧‧‧第一與第二源極/汲極(S/D)區
155‧‧‧延展S/D區、第一極性類型延展區、第二極性類型延展區
157‧‧‧主S/D區、第一極性類型主S/D區、第二極性類 型主S/D區
160‧‧‧閘極
162‧‧‧閘極介電質
164‧‧‧閘極電極
168‧‧‧介電性側壁間隔物
180‧‧‧隔離區
200‧‧‧程序
202a‧‧‧第一裝置區
202b‧‧‧第二裝置區
230‧‧‧第一布植
231‧‧‧第一布植遮罩
232‧‧‧第二布植
233‧‧‧第二布植遮罩
234‧‧‧布植
235‧‧‧圖型化布植遮罩
236‧‧‧布植
237‧‧‧布植遮罩
262‧‧‧閘極介電層
264‧‧‧閘極電極層
268‧‧‧介電質間隔物層
在圖式中，不同視圖中相同的附圖標記大體上是指相同的零件。此外，圖式不必然有依照比例繪示，而是在繪示本發明的原理時，大體上可能會出現重點描述的情況。在以下說明中，本發明的各項具體實施例參考以下圖式說明，其中：第1圖展示裝置的一具體實施例其中一部分的截面圖；以及第2a至2n圖展示用於形成裝置的程序的一具體實施例的截面圖。
具體實施例大體上是關於半導體裝置或積體電路(IC)。更具體地說，一些具體實施例是關於高增益裝置。舉例而言，高增益裝置包括電晶體，諸如金屬氧化物電晶體(MOS)。高增益裝置可運用在類比應用中，諸如高直流增益放大器、音頻放大器或音訊Codex。可輕易地將高增益電晶體整合到具有核心及輸入/輸出(I/O)電晶體的裝置或IC內。該裝置或IC舉例而言，可併入各類消費性電子產品或與其配合使用。
第1圖展示裝置100的一具體實施例其中一部分的截面圖。該裝置舉例而言，為IC。其它類型的裝置也可有作用。如圖所示，該裝置包括基板105。此基板舉例而言，為矽基板。諸如矽鍺、鍺、砷化鎵、或例如矽絕緣體(SOI)的絕緣體上晶體(COI)等其它類基板也有作用。該基板可以是摻雜基板。舉例而言，該基板可輕度摻有p型摻質。提供具有其它類摻質或摻質濃度的基板、及未摻雜基板也可有作用。
該裝置可包括具有不同摻質濃度的摻雜區。舉例而言，該裝置可包括重度摻雜(x+)、中度摻雜(x)及輕度摻雜(x-)區，其中x為極性類型，其可以是p或n。輕度摻雜區可具有約1E15至1E17/cm3的摻質濃度，中度摻雜區可具有約1E17至1E19/cm3的摻質濃度，並且重度摻雜區可具有約1E19至1E21/cm3的摻質濃度。就不同類型的摻雜區提供其它摻質濃度也可有作用。舉例而言，該範圍可隨技術節點而變。另外，該範圍可基於電晶體或裝置的類型而改變，諸如高電壓、中間電壓或低電壓電晶體。P型摻質可包括硼(B)、鋁(Al)、銦(In)或以上的組合，而n型摻質可包括磷(P)、砷(As)、銻(Sb)或以上的組合。
該基板包括各種裝置區。舉例而言，如圖所示，該基板就第一、第二及第三電晶體120、124及126包括第一、第二及第三裝置區102、104及106。在一項具體實施例中，第一裝置區102作用為用於類比高增益(AHG)電晶體120的裝置區，第二裝置區104作用為用於諸如低 電壓(LV)電晶體的核心電晶體124的裝置區，並且第三裝置區106作用為用於諸如輸入/輸出(I/O)電晶體126的中間電壓(IV)電晶體的裝置區。此裝置可包括其它裝置區。其它裝置區組態也可有作用。舉例而言，該裝置可包括用於HV電晶體的高電壓(HV)區域、或用於存儲胞的存儲器陣列區。
可提供隔離區用於使基板的不同區域隔離或分開。在一項具體實施例中，該裝置區通過隔離區180與其它區域隔離。舉例而言，隔離區圍繞裝置區。該隔離區舉例而言，為淺溝槽隔離(STI)區。亦可運用其它類隔離區。舉例而言，該隔離區可以是深溝槽隔離(DTI)區。該STI區舉例而言，延展至約2000Å至5000Å的深度。提供延展至其它深度的隔離區也可有作用。
裝置區中可佈置裝置井114。舉例而言，第一、第二及第三裝置區包括第一、第二及第三裝置井。在一項具體實施例中，第一裝置區102包括AHG電晶體或裝置井114，第二裝置區104包括LV電晶體井114，並且第三裝置區106包括IV電晶體井114。裝置井舉例而言，含括裝置區。該裝置井可具有約0.5μm至5μm的深度。其它深度對於裝置井也可有作用。
一裝置井是第二極性類型摻雜井體，其作用為第一極性類型裝置的本體。舉例而言，就n型電晶體提供p型裝置井，或就p型電晶體提供n型裝置井。在一些情況下，裝置井可通過起始基板來提供。舉例而言，起 始基板若包括適當摻雜類型與濃度，則可作用為裝置井。裝置井的摻質濃度可為輕至中度。在一項具體實施例中，不同類型的裝置井具有不同的摻質濃度。舉例而言，AHG、LV與IV電晶體井具有不同的摻質濃度。
在一項具體實施例中，即使LV與IV井體可稱為輕度或中度摻雜井體，LV電晶體井仍比IV電晶體井具有更高摻質濃度。舉例而言，輕度或中度摻雜LV電晶體井相對於輕度或中度IV摻雜電晶體井具有更高摻質濃度。舉例而言，LV電晶體井的摻質濃度為約1E16/cm3，而IV電晶體井的摻質濃度為約5E15/cm3。其它摻質濃度對於井體也可有作用。LV與IV井體可具有類似的摻質分佈，差別在於LV井體的摻質濃度比IV井體更高。
正如AHG井體，其是以這三類井體的最高摻質濃度來提供。舉例而言，輕度或中度摻雜AHG比LV或IV井體具有更高摻質濃度。AHG井體的摻質濃度可約為1.5E16/cm3。提供其它摻質濃度也可有作用。在一項具體實施例中，AHG井體具有LV與IV井體的組合摻質濃度。舉例而言，AHG井體是雙重井，其具有來自形成LV及IV井體的摻質。AHG井體可通過形成LV井體的LV布植、及形成IV井體的IV布植來形成。替代地，AHG井可使用AHG布植遮罩，通過AHG布植來形成。
電晶體的閘極160佈置於裝置區中的基板表面上。舉例而言，閘極佈置於裝置井上方。在一項具體實施例中，AHG閘極佈置於第一裝置區中的基板上方，LV 閘極佈置於第二裝置區中的基板上方，以及IV閘極佈置於第三裝置區中的基板上方。閘極包括位在閘極介電質162上方的閘極電極164。舉例而言，AHG閘極包括位在AHG閘極介電質上方的AHG閘極電極，LV閘極包括位在LV閘極介電質上方的LV閘極電極，並且IV閘極包括位在IV閘極介電質上方的IV閘極電極。閘極電極舉例而言，可以是多晶矽，而閘極介電質可以是氧化矽。其它類型的閘極電極或閘極介電質也可有作用。舉例而言，閘極電極可以是金屬閘極電極，並且閘極介電質可以是高k閘極介電質。高電壓電晶體可包括比中間閘極介電質更厚的厚閘極介電質。
在一項具體實施例中，AHG閘極介電質及LV閘極介電質為薄閘極介電質。舉例而言，AHG與LV閘極介電質是用於LV電晶體的介電層。正如IV閘極介電質，其為更厚或中間閘極介電質。舉例而言，更厚閘極介電質是用於IV電晶體的介電層。中間閘極介電質由於需要高崩潰電壓(BV)而相對於薄閘極介電質更厚。舉例而言，薄閘極介電質可約為20Å厚，而中間閘極介電質可約為60Å厚。其它相對厚度對於閘極介電質也可有作用。
介電性側壁間隔物168佈置於閘極的側壁上。側壁間隔物舉例而言，可以是氧化矽。其它類介電材料或材料組合可用於間隔物。據瞭解，LV、AHG及IV閘極不需要為相同類型的閘極。舉例而言，LV、AHG及IV閘極的各種組件可由不同材料所構成或具有不同組態。
電晶體包括佈置於裝置井中與閘極的第一和第二側邊相鄰的第一與第二源極/汲極(S/D)區150。在一項具體實施例中，S/D區包括主S/D區157及延展S/D區155。主區及延展區是第一極性類型摻雜區。主區是重度摻雜區，而延展區是輕度摻雜區。延展S/D區可稱為輕度摻雜汲極(LDD)延展區。如圖所示，主S/D區相鄰於介電性側壁間隔物的外緣附近而置，並且閘極與延展區重疊。閘極舉例而言，與延展區重疊大約10Å。與延展區重疊其它距離也可有作用。
在一項具體實施例中，AHG電晶體包括具有AHG主區與AHG延展區的AHG S/D區、LV電晶體包括具有LV主區與LV延展區的LV S/D區，並且IV電晶體包括具有IV主區與IV延展區的IV S/D區。重度摻雜主區的摻質濃度可約為1E20/cm3。其它摻質濃度對於主區也可有作用。
至於延展區，不同類型的電晶體可具有不同的摻質濃度。在一項具體實施例中，LV延展區相對於IV延展區具有更高摻質濃度。舉例而言，LV延展區具有約1E18/cm3的摻質濃度，而IV延展區則具有約1E17/cm3的摻質濃度。其它摻質濃度對於延展區也可有作用。LV S/D區包括光暈區。舉例而言，第二極性類型光暈區相鄰於LV延展區。光暈區抑制LV延展區的橫向擴散。IV S/D區不設有光暈區。
在一項具體實施例中，AHG延展區與IV延 展區相同。舉例而言，AHG電晶體若為LV電晶體則具有經過修改(tailored)的閘極介電質，但若為IV電晶體則具有經過修改的延展區。AHG延展區可具有約1E17/cm3的摻質濃度。提供具有其它摻質濃度的AHG延展區也可有作用。AHG S/D區類似於IV S/D區，不包括光暈區。
電晶體的通道佈置於閘極下面及S/D區之間。通道長度是介於S/D區之間的距離，並且通道寬度方向是介於垂直於長度方向的主動區的諸側邊之間。在一項具體實施例中，LV電晶體包括相對於IV或AHG電晶體更小的通道長度及通道寬度。舉例而言，IV或AHG電晶體相對於LV電晶體具有更大的長度與寬度。在一項具體實施例中，IV與AHG電晶體具有相同或類似的通道寬度與長度。其它組態對於電晶體的通道長度與寬度也可有作用。IV、LV及AHG電晶體的閘極的總高可約為相同。舉例而言，IV閘極的高度因閘極介電質更厚而可稍微更高。提供具有相同高度的閘極也可有作用。舉例而言，可進行平坦化程序以建立相同的閘極高度。
在一些具體實施例中，在電晶體上方形成介電質蝕刻終止層(圖未示)。蝕刻終止層舉例而言，為氮化矽蝕刻終止層。其它類蝕刻終止層也可有作用。蝕刻終止層應具有可選擇性地從其上方的介電層移離的材料。蝕刻終止層有助於對電晶體的諸如閘極電極及摻雜區等接觸區形成接觸插塞。在一些具體實施例中，蝕刻終止層亦可作用為應力層，用於在電晶體的通道上施加應力以改善效 能。
可在S/D區上及閘極電極上形成金屬矽化物接觸部(圖未示)。金屬矽化物接觸部舉例而言，可以是鎳基接觸部。其它類型的金屬矽化物接觸部也可有作用。舉例而言，金屬矽化物接觸部可以是矽化鈷(CoSi)。矽化物接觸部可約為50Å至300Å厚。其它厚度也可有作用。金屬矽化物接觸部可用於降低接觸電阻，並且有助於接觸至後段金屬互連件。舉例而言，電晶體上方可提供介電層(圖未示)。諸如鎢接觸部的貫孔接點可形成於介電層中，其將電晶體的接觸區耦合至佈置於裝置的金屬層中的金屬線。
裝置的增益是由以下方程式所定義：增益=Gm x Rout
其中Gm=跨導，以及Rout=輸出電阻。
通過將用於形成LV與IV井體兩者的布植組合，AHG井體具有更均勻的通道摻質分佈。此抑制短通道效應與通道夾止，其促使AHG電晶體的Rout更佳。另外，AHG井體就AHG電晶體降低通道漏電。
第2a至2n圖展示用於形成裝置的程序200的一具體實施例的截面圖。請參閱第2a圖，所提供的是基板105。基板包括第一與第二主表面105a與105b。在一項具體實施例中，此基板為矽基板。基板可以是摻雜基板， 諸如輕度摻雜p型(p-)基板。諸如鍺基、例如SOI的COI、或藍寶石等其它類基板也可有作用。基板可摻有其它類摻質或摻質濃度。
請參閱第2b圖，處理基板以界定第一與第二裝置區202a至202b。界定裝置區包括形成隔離區180。隔離區可以是STI區。STI區舉例而言，圍繞裝置區。其它類隔離區也可有作用。可運用各種程序以形成STI區。例如，可採用蝕刻與遮罩技巧蝕刻基板以形成溝槽，接著用矽氧化物之類的介電材料填充溝槽。可進行化學機械研磨(CMP)以移除過剩氧化物並且提供平面型基板頂部表面。其它程序或材料也可用於形成STI。STI區的深度舉例而言，可約為2000Å至5000Å。其它深度對於STI區也可有作用。
第一裝置區202a可就第一類型AHG電晶體作用為裝置區，並且第二裝置區202b可就CMOS裝置的第二類型AHG電晶體作用為裝置區。舉例而言，第一裝置區用於n型AHG電晶體，並且第二裝置區用於p型AHG電晶體。基板可包括其它類裝置區，諸如LV與IV電晶體區。
在第2c圖中，於第一裝置區中形成裝置井114。裝置井就第一極性類型AHG電晶體是第二極性類型裝置井。舉例而言，裝置井就n型AHG電晶體是p型井。就p型AHG電晶體形成n型井也可有作用。在一項具體實施例中，裝置井是輕度或中度摻雜第二極性類型裝置井。舉例而言，將第二極性類型摻質植入基板以在第一裝置區 中形成裝置井。
在一項具體實施例中，裝置井是由多個離子布植程序所形成。如圖所示，第一布植遮罩231設於基板上。該布植遮罩舉例而言，是通過透過分劃板(reticle)利用曝照源將其曝照來圖型化的光阻層。若要改善光刻解析度，可在光阻層下面使用抗反射塗料(ARC)。分劃板上的圖型是在顯影之後轉移至阻劑。舉例而言，移除第一裝置上方的布植遮罩，留下其包覆第二裝置區。第一布植230將第二極性類型摻質植入基板。在一項具體實施例中，第一布植為用於形成第二極性類型LV電晶體井的相同布植。舉例而言，第一布植遮罩亦就第一極性類型LV電晶體使裝置區曝露。布植之後，將遮罩移除。舉例而言，布植遮罩是通過灰化來移除。其它技巧對於移除布植遮罩也可有作用。
如第2d圖所示，進行第二布植232。第二布植運用第二布植遮罩233，諸如圖型化光阻遮罩。第二布植將第二極性類型摻質植入基板。在一項具體實施例中，第二布植為用於形成第二極性類型IV電晶體井的相同布植。舉例而言，第二布植遮罩亦就第一極性類型IV電晶體使裝置區曝露。布植之後，舉例而言，通過灰化將遮罩移除。第二布植完成就第一極性類型AHG電晶體形成第二極性類型AHG電晶體井。
請參閱第2e圖，在第二裝置區中形成裝置井114。裝置井就第二極性類型AHG電晶體是第一極性類 型裝置井。舉例而言，裝置井就p型AHG電晶體是n型井。就n型AHG電晶體形成p型井也可有作用。在一項具體實施例中，裝置井是輕度或中度摻雜第一極性類型裝置井。舉例而言，將第一極性類型摻質植入基板以在第二裝置區中形成裝置井。
類似於第一裝置區中的裝置井，第二裝置井中的裝置井是通過多個離子布植程序所形成。圖型化布植遮罩235設於基板上，不僅包覆第一裝置區，還使第二裝置區曝露。布植234(用於第二裝置區的第一布植)將第一極性類型摻質植入基板。在一項具體實施例中，該布植為用於形成第一極性類型LV電晶體井的相同布植。舉例而言，該布植遮罩亦就第二極性類型LV電晶體使裝置區曝露。布植之後，舉例而言，通過灰化將遮罩移除。
進行另一布植236(用於第二裝置區的第二布植)，如第2f圖所示。該布植運用布植遮罩237，諸如圖型化光阻遮罩。該布植將第一極性類型摻質植入基板。在一項具體實施例中，該布植為用於形成第一極性類型IV電晶體井的相同布植。舉例而言，該布植遮罩亦就第二極性類型IV電晶體使裝置區曝露。布植之後，舉例而言，通過灰化將遮罩移除。用於第二裝置區的兩個布植完成就第二極性類型AHG電晶體形成第一極性類型AHG電晶體井。形成井體之後，可進行退火程序以活化井體摻質。退火程序可緊接形成井體之後進行，或在其它處理階段進行，諸如形成S/D區之後進行。
雖然AHG井體如所述是按照特定布植順序所形成，但據瞭解，仍可使用其它布植順序。再者，據瞭解，可在基板上形成其它井體，端視裝置類型而定。如所述，可將AHG井體整合到目前的製程而免成本。舉例而言，可將AHG井體整合到目前的製程，不需要另外的遮罩。
在一些具體實施例中，裝置井可通過就AHG電晶體修改的特定布植所形成。舉例而言，可就第一極性與第二極性AHG電晶體井來具體修改單獨布植。其它用於形成AHG的技巧或程序也可有作用。然而，這可能需要另外的遮罩。
請參閱第2g圖，在基板上形成閘極的閘極層。在一項具體實施例中，閘極層包括位在基板上的閘極介電層262、及形成於其上的閘極電極層264。在一項具體實施例中，閘極介電層是氧化矽。在一項具體實施例中，閘極介電層是薄閘極介電層。舉例而言，閘極介電層與用於LV電晶體者相同。閘極介電層的厚度舉例而言，可約為20Å。其它厚度也可有作用。閘極介電層可通過熱氧化作用來形成。舉例而言，介電層通過濕式氧化作用再於氧化環境中退火基板所形成。濕式氧化作用的溫度舉例而言，可約為600℃至900℃。退火程序舉例而言，可在約600℃至1000℃的溫度下進行。使用其它程序來形成其它類閘極介電層也可有作用。
基板可就諸如IV裝置的其它類裝置包括介電質。舉例而言，基板可在IV裝置區中包括更厚或中間閘 極介電質。形成更厚閘極介電質可包括另外的程序。
至於閘極電極層，其可以是矽層。矽層舉例而言，可以是多晶矽層。閘極電極層的厚度可約為700Å至1000Å。其它厚度也可有作用。閘極電極層舉例而言，可通過化學氣相沉積(CVD)來形成。用於形成閘極電極層的其它技巧也可有作用。可將閘極電極層形成為非晶或非非晶層。在非晶層的情況下，可進行退火程序以形成多結晶矽層。
其它類閘極介電質及閘極電極材料或厚度也可有作用。舉例而言，閘極介電材料可以是高k介電材料，而閘極電極可以是金屬閘極電極材料。其它閘極層組態也可有作用。舉例而言，閘極介電質及/或閘極電極層可具有多層。該層可通過各種技巧來形成，諸如熱氧化作用、CVD及濺鍍。
在第2h圖中，閘極層進行圖型化以在第一與第二裝置區中形成閘極160。可運用蝕刻遮罩進行閘極層圖型化以形成閘極。舉例如可使用軟遮罩，諸如光阻層。曝照源可透過含有所欲圖型的分劃板來選擇性地曝照光阻層。選擇性地曝照光阻層之後，將其顯影以形成與要移除閘極層處的位置對應的開口。若要改善光刻解析度，可在光阻層下面使用抗反射塗料(ARC)。
使用蝕刻遮罩來進行諸如反應性離子蝕刻(RIE)的非等向性蝕刻以將閘極層圖型化而形成閘極。其它類蝕刻程序也可有作用。在一項具體實施例中，運用RIE 進行閘極層圖型化以形成諸閘極160，各閘極具有位在閘極介電質162上方的閘極電極164。
請參閱第2i圖，該程序接著形成位在第一裝置區中的第一極性類型延展區155。形成延展區可包括遮罩與布植技巧。舉例而言，圖型化布植遮罩(圖未示)設於基板上。布植遮罩使第一裝置區曝露。進行布植以形成延展區。該布植形成與第一裝置區中閘極相鄰的AHG LDD延展區。該布植深度形成具有約1E17/cm3摻質濃度及約50nm深度的延展區。其它摻質濃度及深度也可有作用。在一項具體實施例中，該布植區形成與IV延展區相同的LDD延展區。舉例而言，該布植遮罩是就第一極性類型IV電晶體用於形成第一極性類型IV延展區的相同布植遮罩。該布植遮罩在形成延展區之後遭受移除。
在第2j圖中，該程序接著在第二裝置區中形成第二極性類型延展區155。形成延展區可包括遮罩與布植技巧。該布植形成與第二裝置區中閘極相鄰的AHG LDD延展區。該布植形成具有約1E17/cm3摻質濃度及約50nm深度的延展區。其它摻質濃度及深度也可有作用。在一項具體實施例中，該布植區形成與該IV延展區相同的LDD延展區。舉例而言，該布植遮罩是就第二極性類型IV電晶體用於形成第二極性類型IV延展區的相同布植遮罩。該布植遮罩在形成延展區之後遭受移除。
如第2k圖所示，於基板上形成介電質間隔物層268。介電層舉例而言，可以是氧化矽層。也可使用 其它類介電材料，諸如氮化矽。此介電層可通過CVD來形成。介電層亦可使用其它技巧來形成。介電層的厚度舉例而言，可為100Å至1000Å。介電層的其它厚度也可有作用。該厚度舉例而言，可取決於間隔物的所欲寬度。可進行諸如RIE的非等向性蝕刻以移除介電層的水平部分，在閘極的側壁上留下間隔物，如第21圖所示。在一些應用中，間隔物可由多個介電層所形成。
請參閱第2m圖，在第一裝置區中形成第一極性類型主S/D區157。可運用遮罩與布植技巧以在第一裝置區中形成主S/D區。舉例而言，使第一裝置區曝露的遮罩用於布植。該布植在裝置區中形成重度摻雜主S/D區。主S/D區的摻質濃度可約為1E20/cm3。主S/D區可具有約200nm的深度。其它摻質濃度與深度對於主S/D區也可有作用。在一項具體實施例中，該遮罩亦使第二裝置區的內有形成第一極性類型井接觸部272的一部分曝露。該遮罩可以是用於形成第一極性類型主S/D區及第一極性類型井接觸部的相同遮罩。形成主S/D區及井接觸部之後，移除布植遮罩。該布植遮罩舉例而言，可通過灰化來移除。其它技巧對於移除布植遮罩也可有作用。
在第2n圖中，在第二裝置區中形成第二極性類型主S/D區157。可運用遮罩與布植技巧以在第二裝置區中形成主S/D區。舉例而言，使第二裝置區曝露的遮罩用於布植。該布植在裝置區中形成重度摻雜主S/D區。主S/D區的摻質濃度可約為1E20/cm3。主S/D區可具有約 200nm的深度。其它摻質濃度與深度對於主S/D區也可有作用。在一項具體實施例中，該遮罩亦使第二裝置區之內有形成第二極性類型井接觸部272的一部分曝露。該遮罩可以是用於形成第二極性類型主S/D區及第一極性類型井接觸部的相同遮罩。形成主S/D區及井接觸部之後，移除布植遮罩。雖然延展區與主S/D區如所述是按照特定布植順序所形成，據瞭解，仍可使用其它布植順序。舉例而言，第二極性類型區域可在第一極性類型區域前先形成。
形成S/D區之後可進行諸如快速熱退火(RTA)的退火程序以活化S/D區中的摻質。摻雜區的內緣舉例而言，可因摻質自摻雜區擴散而在介電質間隔物底下延展。
該程序接著形成該裝置。該處理可包括對胞元的接端、及一或多個互連階形成金屬矽化物接觸部、預金屬介電(PMD)層與接觸部、最終鈍化、分切、裝配及封裝。亦可包括其它程序。舉例如形成互連前，可先形成諸如低電壓、中電壓及高電壓I/O裝置等其它組件。
如所述，閘極使用閘極先製程序(gate first process)所形成。替代地，閘極可使用閘極後製程序(gate last process)所形成。在閘極後製程序中，先形成的是虛設閘極，如所述。形成S/D區之後，可形成並且平坦化介電層以使閘極曝露。選擇性地移除閘極，並且在溝槽中形成“真實”閘極，導致虛設閘極遭受移除。閘極後製程序可用於金屬閘極或其它類閘極。使用閘極先製程序來形成金 屬閘極或其它類閘極也可有作用。
本發明可體現成其它特定形式而不會脫離其精神或主要特性。因此，前述具體實施例在所有層面都要視為說明性，而不是限制本文中所述的發明。因此，本發明的範疇由隨附申請專利範圍指出，而不是由前述說明指出，而且均等於申請專利範圍的意義及範圍內的所有變更全都意欲囊括於其中。

Claims (20)

  1. 一種用於形成裝置的類比高增益電晶體的方法，包含：在基板上形成類比裝置區；在該裝置區中形成類比裝置井，其中，該裝置井包含類比井體摻質濃度，其就LV電晶體高於低電壓(LV)裝置井的摻質濃度，並且就IV電晶體高於中間電壓(IV)裝置井的摻質濃度；在該裝置區中該基板上形成類比閘極，其中，該閘極包含位在類比閘極介電質上方的類比閘極電極，其中，該類比閘極介電質是用於該LV電晶體的薄閘極介電質；在該基板中該裝置井中相鄰於該類比閘極處形成諸類比源極汲極(S/D)區，其中，一S/D區包含重度摻雜主區，以及類比輕度摻雜延展區，其中，該類比輕度摻雜延展區就IV電晶體包含IV輕度摻雜延展區的摻質濃度；以及其中，該類比裝置井的該更高摻雜濃度、該類比閘極的該薄閘極介電質、及該類比S/D區的該IV輕度摻雜延展區提升該類比高增益電晶體的效能。
  2. 如申請專利範圍第1項所述的方法，其中，形成該類比裝置井就形成裝置與互補式金屬氧化物半導體(CMOS)程序相容。
  3. 如申請專利範圍第1項所述的方法，其中，該類比裝 置井的該摻質濃度約等於用於該LV電晶體的該LV裝置井與用於該IV電晶體的該IV裝置井的組合摻質濃度。
  4. 如申請專利範圍第1項所述的方法，其中，該類比裝置井的該摻質濃度為約1.5E16/cm3。
  5. 如申請專利範圍第1項所述的方法，其中，相比於約60Å厚的中間閘極介電質，該類比閘極介電質包含約20Å厚的厚度。
  6. 如申請專利範圍第1項所述的方法，其中，相比於LV延展區的約1E18/cm3的摻質濃度，該類比輕度摻雜延展區包含約1E17/cm3的摻質濃度。
  7. 如申請專利範圍第1項所述的方法，其中，該重度摻雜主區為約1E20/cm3。
  8. 如申請專利範圍第1項所述的方法，其中，形成該類比裝置井包含形成雙重井，其包含：進行LV布植，該LV布植用於形成該LV電晶體的該LV井體；以及進行IV布植，該IV布植用於形成該IV電晶體的該IV井體。
  9. 如申請專利範圍第8項所述的方法，其中，該類比裝置井的該摻質濃度為約1.5E16/cm3。
  10. 如申請專利範圍第8項所述的方法，其中：該LV延展區包含約1E18/cm3的摻質濃度；以及該IV延展區包含約1E17/cm3的摻質濃度。
  11. 如申請專利範圍第1項所述的方法，其中，該類比S/D區的該重度摻雜主區為約1E20/cm3，並且與該LV與IV電晶體的該重度摻雜主區相同。
  12. 如申請專利範圍第1項所述的方法，其中，形成該類比裝置井包含進行布植以形成該類比裝置井，其比用於該LV電晶體的該LV裝置井、及用於該IV電晶體的該IV裝置井包含該更高摻質濃度。
  13. 如申請專利範圍第12項所述的方法，其中，該類比裝置井的該摻質濃度為約1.5E16/cm3。
  14. 一種屬於一裝置的類比高增益電晶體，包含：位在基板上的類比裝置區；位在該裝置區中的類比裝置井，其中，該裝置井包含類比井體摻質濃度，其高於用於LV電晶體的LV裝置井的低電壓(LV)摻質濃度、或用於IV電晶體的IV裝置井的中間電壓(IV)摻質濃度；位在該裝置區中該基板上的類比閘極，其中，該閘極包含位在類比閘極介電質上方的類比閘極電極，該類比閘極介電質是用於該LV電晶體的薄閘極介電質；相鄰於該類比閘極的諸類比源極汲極(S/D)區，其中，一S/D區包含重度摻雜主區，以及類比輕度摻雜延展區，其中，該類比輕度摻雜延展區就IV電晶體包含IV輕度摻雜延展區的 摻質濃度；以及其中，該類比裝置井的該更高摻雜濃度、該類比閘極的該薄閘極介電質、及該類比S/D區的該IV輕度摻雜延展區提升該類比高增益電晶體的效能。
  15. 如申請專利範圍第14項所述的裝置，其中，該類比裝置井的該摻質濃度約等於用於該LV電晶體的該LV裝置井與用於該IV電晶體的該IV裝置井的組合摻質濃度。
  16. 如申請專利範圍第14項所述的裝置，其中，該類比裝置井的該摻質濃度為約1.5E16/cm3。
  17. 如申請專利範圍第14項所述的裝置，其中，相比於約60Å厚的中間閘極介電質，該類比閘極介電質包含約20Å厚的厚度。
  18. 如申請專利範圍第14項所述的裝置，其中，相比於LV延展區的約1E18/cm3的摻質濃度，該類比輕度摻雜延展區包含約1E17/cm3的摻質濃度。
  19. 如申請專利範圍第14項所述的裝置，其中，該類比S/D區的該重度摻雜主區為約1E20/cm3。
  20. 一種用於形成裝置的方法，包含：在具有用於LV電晶體的LV裝置井的基板上形成低電壓(LV)裝置區，其中，該LV裝置井包含LV井體摻質濃度；在具有用於IV電晶體的IV裝置井的基板上形成中間電壓(IV)裝置，其中，該IV裝置井包含IV井體摻 質濃度；在具有用於類比高增益電晶體的類比裝置井的基板上形成類比裝置區，其中，該類比裝置井包含類比井體摻質濃度，其高於該LV裝置井摻質濃度或該IV井體摻質濃度；在該LV裝置區中形成該LV電晶體，其中，該LV電晶體包含在屬於薄閘極介電質的LV閘極介電質上方具有LV閘極電極的LV閘極，以及相鄰於該LV閘極的諸LV S/D區，其中，一LV S/D區包含LV重度摻雜主S/D區，以及具有LV延展摻質濃度的LV延展區；在該IV裝置區中形成該IV電晶體，其中，該IV電晶體包含在屬於中間閘極介電質的IV閘極介電質上方具有IV閘極電極的IV閘極，該中間閘極介電質比該薄閘極介電質具有更大的厚度，以及相鄰於該IV閘極的諸IV S/D區，其中，一IV S/D區包含IV重度摻雜主S/D區，以及具有比該LV延展摻質濃度更低的IV延展摻質濃度的IV延展區；以及在該類比裝置區中形成該類比高增益電晶體，其 中，該類比高增益電晶體包含在與該薄閘極介電質具有相同厚度的類比閘極介電質上方具有類比閘極電極的類比閘極，以及相鄰於該類比閘極的諸類比S/D區，其中，一類比S/D區包含類比重度摻雜主S/D區，以及具有比該LV延展摻質濃度更低的類比延展摻質濃度的類比延展區。
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