JP5332781B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5332781B2 JP5332781B2 JP2009068233A JP2009068233A JP5332781B2 JP 5332781 B2 JP5332781 B2 JP 5332781B2 JP 2009068233 A JP2009068233 A JP 2009068233A JP 2009068233 A JP2009068233 A JP 2009068233A JP 5332781 B2 JP5332781 B2 JP 5332781B2
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Description
を提供することである。
半導体基板に、第1のMOSトランジスタ領域、前記第1のMOSトランジスタよりも高い耐圧を有する第2のMOSトランジスタ領域を画定する素子分離領域を形成する工程と、
前記第1のMOSトランジスタ領域、および前記第2のMOSトランジスタ領域に第1導電型の第1不純物をイオン注入することにより、前記第1のMOSトランジスタ領域に第1ウェルを、前記第2のトランジスタ領域に第2ウェルを形成する工程と、
前記第1ウェル中および前記第2ウェル中に、前記第1導電型の第2不純物をイオン注入する工程と、
前記第2のMOSトランジスタ領域の一部を露出し、前記第1のMOSトランジスタ領域を覆う第1マスク層を形成する工程と、
前記第1マスク層をマスクとして、前記半導体基板に前記第1導電型と逆の第2導電型の第3不純物をイオン注入する工程と、
前記第1マスク層を除去した後、前記第1のMOSトランジスタ領域上に第1ゲート絶縁膜および第1ゲート電極を、前記第2のMOSトランジスタ領域上に前記第3不純物が注入された領域に一部重なるように第2ゲート絶縁膜および第2ゲート電極を形成する工程と、
前記第2のMOSトランジスタのドレイン領域を覆い、前記第2のMOSトランジスタのソース領域、前記第1のMOSトランジスタのドレイン領域および前記第1のMOSトランジスタのソース領域を露出する第2マスク層を形成する工程と、
前記第2マスク層、前記第1ゲート電極および前記第2ゲート電極をマスクとして、前記半導体基板に前記第2導電型の第4不純物をイオン注入する工程と、
前記第1ゲート電極の両側壁上、および前記第2ゲート電極の両側壁上に絶縁性サイドウォールスペーサを形成する工程と、
前記第1ゲート電極、前記第2ゲート電極、および前記絶縁性サイドウォールスペーサ、をマスクとして、前記第2導電型の第5不純物をイオン注入する工程と、
を有する半導体装置の製造方法
が提供される。
12 素子分離領域(STI)、
PW p型ウェル、
NW n型ウェル、
13 n型LDD領域、
14 n型チャネルドーズ領域、
15 ゲート絶縁膜、
16 ゲート電極、
18,19 p型チャネルドーズ領域、
21 n型チャネルドーズ領域、
20 n型エクステンション領域、
22 p型エクステンション領域、
26 n型低抵抗ソース/ドレイン領域、
27 p型低抵抗ソース/ドレイン領域、
29 シリサイド膜。
Claims (4)
- 半導体基板に、第1のMOSトランジスタ領域、前記第1のMOSトランジスタよりも高い耐圧を有する第2のMOSトランジスタ領域を画定する素子分離領域を形成する工程と、
前記第1のMOSトランジスタ領域、および前記第2のMOSトランジスタ領域に第1導電型の第1不純物をイオン注入することにより、前記第1のMOSトランジスタ領域に第1ウェルを、前記第2のトランジスタ領域に第2ウェルを形成する工程と、
前記第1ウェル中および前記第2ウェル中に、前記第1導電型の第2不純物をイオン注入する工程と、
前記第2のMOSトランジスタ領域の一部を露出し、前記第1のMOSトランジスタ領域を覆う第1マスク層を形成する工程と、
前記第1マスク層をマスクとして、前記半導体基板に前記第1導電型と逆の第2導電型の第3不純物をイオン注入する工程と、
前記第1マスク層を除去した後、前記第1のMOSトランジスタ領域上に第1ゲート絶縁膜および第1ゲート電極を、前記第2のMOSトランジスタ領域上に前記第3不純物が注入された領域に一部重なるように第2ゲート絶縁膜および第2ゲート電極を形成する工程と、
前記第2のMOSトランジスタのドレイン領域を覆い、前記第2のMOSトランジスタのソース領域、前記第1のMOSトランジスタのドレイン領域および前記第1のMOSトランジスタのソース領域を露出する第2マスク層を形成する工程と、
前記第2マスク層、前記第1ゲート電極および前記第2ゲート電極をマスクとして、前記半導体基板に前記第2導電型の第4不純物をイオン注入する工程と、
前記第1ゲート電極の両側壁上、および前記第2ゲート電極のソース側側壁に絶縁性サイドウォールスペーサを形成すると共に、前記第2ゲート電極のドレイン側側壁から前記第2不純物が注入された領域上に延在する絶縁膜を形成する工程と、
前記第1ゲート電極、前記第2ゲート電極、前記絶縁性サイドウォールスペーサ、および前記絶縁膜をマスクとして、前記第2導電型の第5不純物をイオン注入する工程と、
を有する半導体装置の製造方法。 - 半導体基板に、第1のMOSトランジスタ領域、前記第1のMOSトランジスタよりも高い耐圧を有する第2のMOSトランジスタ領域を画定する素子分離領域を形成する工程と、
前記第1のMOSトランジスタ領域、および前記第2のMOSトランジスタ領域に第1導電型の第1不純物をイオン注入することにより、前記第1のMOSトランジスタ領域に第1ウェルを、前記第2のトランジスタ領域に第2ウェルを形成する工程と、
前記第1ウェル中および前記第2ウェル中に、前記第1導電型の第2不純物をイオン注入する工程と、
前記第2のMOSトランジスタ領域の一部を露出し、前記第1のMOSトランジスタ領域を覆う第1マスク層を形成する工程と、
前記第1マスク層をマスクとして、前記半導体基板に前記第1導電型と逆の第2導電型の第3不純物をイオン注入する工程と、
前記第1マスク層を除去した後、前記第1のMOSトランジスタ領域上に第1ゲート絶縁膜および第1ゲート電極を、前記第2のMOSトランジスタ領域上に前記第3不純物が注入された領域に一部重なるように第2ゲート絶縁膜および第2ゲート電極を形成する工程と、
前記第2のMOSトランジスタのドレイン領域を覆い、前記第2のMOSトランジスタのソース領域、前記第1のMOSトランジスタのドレイン領域および前記第1のMOSトランジスタのソース領域を露出する第2マスク層を形成する工程と、
前記第2マスク層、前記第1ゲート電極および前記第2ゲート電極をマスクとして、前記半導体基板に前記第2導電型の第4不純物をイオン注入する工程と、
前記第1ゲート電極の両側壁上、および前記第2ゲート電極の両側壁上に絶縁性サイドウォールスペーサを形成する工程と、
前記第1ゲート電極、前記第2ゲート電極、および前記絶縁性サイドウォールスペーサ、をマスクとして、前記第2導電型の第5不純物をイオン注入する工程と、
を有する半導体装置の製造方法。 - 前記第2導電型の第3不純物のイオン注入は、前記半導体基板の法線方向から傾いた方向から行なう請求項1または2記載の、
半導体装置の製造方法。 - 前記第2ゲート電極のゲート長の20%〜50%が、前記第3不純物が注入された領域とオーバラップする請求項1または2記載の
半導体装置の製造方法。
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