JP5153121B2 - 電界効果トランジスタ・デバイスとその形成方法 - Google Patents
電界効果トランジスタ・デバイスとその形成方法 Download PDFInfo
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- JP5153121B2 JP5153121B2 JP2006303408A JP2006303408A JP5153121B2 JP 5153121 B2 JP5153121 B2 JP 5153121B2 JP 2006303408 A JP2006303408 A JP 2006303408A JP 2006303408 A JP2006303408 A JP 2006303408A JP 5153121 B2 JP5153121 B2 JP 5153121B2
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- 238000000034 method Methods 0.000 title claims description 55
- 230000005669 field effect Effects 0.000 title claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 42
- 239000010703 silicon Substances 0.000 claims description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 41
- 125000006850 spacer group Chemical group 0.000 claims description 31
- 239000012212 insulator Substances 0.000 claims description 30
- 239000004020 conductor Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 15
- 229910021332 silicide Inorganic materials 0.000 claims description 14
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 14
- 239000004065 semiconductor Substances 0.000 claims description 12
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 4
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 claims 2
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 20
- 230000000694 effects Effects 0.000 description 12
- 239000000463 material Substances 0.000 description 11
- 239000002019 doping agent Substances 0.000 description 8
- 230000003071 parasitic effect Effects 0.000 description 8
- 230000007423 decrease Effects 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 125000001475 halogen functional group Chemical group 0.000 description 5
- 239000007943 implant Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 230000006911 nucleation Effects 0.000 description 3
- 238000010899 nucleation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910001423 beryllium ion Inorganic materials 0.000 description 1
- 239000013590 bulk material Substances 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78639—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a drain or source connected to a bulk conducting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
Description
304 ドレイン・エクステンション
306 BOX層
308 バルク・シリコン
316 ゲート電極
324 側壁スペーサ
330 結晶境界
332 ソース領域
334 ドレイン領域
336 コンタクト
Claims (5)
- バルク基板上に形成された埋込み絶縁体層および前記埋込み絶縁体層上に形成された半導体−オン−インシュレータ層を含む半導体ウェハの能動デバイス領域上にゲート導体およびゲート誘電体を形成するステップと、
前記ゲート導体の両側に隣接して、前記半導体−オン−インシュレータ層内にソースおよびドレインのエクステンションを形成するステップと、
前記ゲート導体に隣接してソースおよびドレインの側壁スペーサを形成するステップと、
前記半導体−オン−インシュレータ層の前記側壁スペーサで保護されていない部分を除去して、前記埋込み絶縁体層の一部が露出するようにするステップと、
前記埋込み絶縁体層の前記露出部分を垂直方向のエッチングと、それに続く水平方向のエッチングとにより除去して、前記バルク基板の一部を露出させると共に、前記ゲート導体および前記側壁スペーサの下の前記ソースおよびドレインのエクステンションの底面の一部を露出させるステップと、
前記バルク基板と前記ソースおよびドレインのエクステンションとの前記露出部分上に、半導体層をエピタキシャル成長させるステップと、
前記エピタキシャル成長させた半導体層内に、ソースおよびドレインの注入領域を形成するステップと
を含む、電界効果トランジスタ(FET)デバイスを形成するための方法。 - 前記バルク基板がシリコンを含み、
前記埋込み絶縁体層が、埋込み酸化物(BOX)層をさらに含み、
前記半導体−オン−インシュレータ層が、シリコン−オン−インシュレータ(SOI)層からなる、請求項1に記載の方法。 - 前記エピタキシャル成長した半導体層が、シリコン(Si)、シリコン・ゲルマニウム(SiGe)、シリコン・カーボン(SiC)、シリコン・ゲルマニウム・カーボン(SiGeC)、ゲルマニウム(Ge)、およびこれらの組合せの、1つまたは複数をさらに含む、請求項2に記載の方法。
- 前記ゲート導体およびゲート誘電体を形成するステップは、前記ゲート導体上に保護窒化物キャップを形成するステップを含み、
前記ソースおよびドレインの注入領域を形成する前記ステップの後、前記ゲート導体上の前記保護窒化物キャップを除去するステップと、
前記ソース領域、前記ドレイン領域、および前記ゲート導体内にシリサイド・コンタクトを形成するステップと、をさらに含む、請求項2に記載の方法。 - 半導体−オン−インシュレータ層上に形成された、ゲート導体およびゲート誘電体と、
前記ゲート導体に隣接して形成された、ソースおよびドレインの側壁スペーサと、
半導体−オン−インシュレータ層内と前記ソースおよびドレインの側壁スペーサの下に形成された、ソースおよびドレインのエクステンションと、
前記半導体−オン−インシュレータ層が表面に形成されている、埋込み絶縁体構造と、
前記埋込み絶縁体構造の両側の側壁に隣接して形成された、ドープされたソースおよびドレイン領域であって、前記ドープされたソースおよびドレインの少なくとも一部は、前記ソースおよびドレインのエクステンションの下に配置されているドープされたソースおよびドレイン領域とを含み、
前記ソースおよびドレイン領域内に形成されたシリサイド・コンタクトが、前記ソースおよびドレインの側壁スペーサの底面で、前記ソースおよびドレインの側壁スペーサに接触している、電界効果トランジスタ(FET)デバイス。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/164343 | 2005-11-18 | ||
US11/164,343 US7659172B2 (en) | 2005-11-18 | 2005-11-18 | Structure and method for reducing miller capacitance in field effect transistors |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007142402A JP2007142402A (ja) | 2007-06-07 |
JP5153121B2 true JP5153121B2 (ja) | 2013-02-27 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006303408A Expired - Fee Related JP5153121B2 (ja) | 2005-11-18 | 2006-11-08 | 電界効果トランジスタ・デバイスとその形成方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7659172B2 (ja) |
JP (1) | JP5153121B2 (ja) |
CN (1) | CN100464397C (ja) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2881273B1 (fr) * | 2005-01-21 | 2007-05-04 | St Microelectronics Sa | Procede de formation d'un substrat semi-conducteur de circuit integre |
US20080164523A1 (en) * | 2007-01-04 | 2008-07-10 | Macronix International Co., Ltd. | Dynamic random access memory cell and manufacturing method thereof |
US8106456B2 (en) * | 2009-07-29 | 2012-01-31 | International Business Machines Corporation | SOI transistors having an embedded extension region to improve extension resistance and channel strain characteristics |
US8492838B2 (en) | 2009-11-16 | 2013-07-23 | International Business Machines Corporation | Isolation structures for SOI devices with ultrathin SOI and ultrathin box |
US20130050166A1 (en) * | 2011-08-24 | 2013-02-28 | Qualcomm Mems Technologies, Inc. | Silicide gap thin film transistor |
FR2985089B1 (fr) * | 2011-12-27 | 2015-12-04 | Commissariat Energie Atomique | Transistor et procede de fabrication d'un transistor |
US9093564B2 (en) | 2013-03-20 | 2015-07-28 | International Business Machines Corporation | Integrated passive devices for FinFET technologies |
FR3025941A1 (fr) * | 2014-09-17 | 2016-03-18 | Commissariat Energie Atomique | Transistor mos a resistance et capacites parasites reduites |
US9502505B2 (en) * | 2014-12-31 | 2016-11-22 | Stmicroelectronics, Inc. | Method and structure of making enhanced UTBB FDSOI devices |
US9685535B1 (en) | 2016-09-09 | 2017-06-20 | International Business Machines Corporation | Conductive contacts in semiconductor on insulator substrate |
FR3079616B1 (fr) * | 2018-03-30 | 2021-02-12 | Soitec Silicon On Insulator | Micro-capteur pour detecter des especes chimiques et procede de fabrication associe |
CN113316486B (zh) * | 2018-11-16 | 2022-10-18 | 维蒙股份公司 | 电容式微机械超声换能器及其制造方法 |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4797718A (en) * | 1986-12-08 | 1989-01-10 | Delco Electronics Corporation | Self-aligned silicon MOS device |
JPH05121744A (ja) * | 1991-10-28 | 1993-05-18 | Fujitsu Ltd | Soi型半導体装置とその製造方法 |
JPH05206455A (ja) | 1992-01-27 | 1993-08-13 | Nec Corp | 半導体装置およびその製造方法 |
JP4348757B2 (ja) * | 1998-11-12 | 2009-10-21 | ソニー株式会社 | 半導体装置 |
KR100350575B1 (ko) | 1999-11-05 | 2002-08-28 | 주식회사 하이닉스반도체 | 소오스-바디-기판이 접촉된 이중막 실리콘 소자 및 제조방법 |
JP2001284598A (ja) * | 2000-03-31 | 2001-10-12 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US6566198B2 (en) * | 2001-03-29 | 2003-05-20 | International Business Machines Corporation | CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture |
US6521949B2 (en) | 2001-05-03 | 2003-02-18 | International Business Machines Corporation | SOI transistor with polysilicon seed |
US20020171107A1 (en) * | 2001-05-21 | 2002-11-21 | Baohong Cheng | Method for forming a semiconductor device having elevated source and drain regions |
US6902980B2 (en) | 2003-06-05 | 2005-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating a high performance MOSFET device featuring formation of an elevated source/drain region |
US6946696B2 (en) * | 2002-12-23 | 2005-09-20 | International Business Machines Corporation | Self-aligned isolation double-gate FET |
JP2004241755A (ja) * | 2003-01-15 | 2004-08-26 | Renesas Technology Corp | 半導体装置 |
JP2004228365A (ja) * | 2003-01-23 | 2004-08-12 | Fujitsu Ltd | Soi型電界効果トランジスタ、soi型半導体装置及びその製造方法 |
US7081655B2 (en) | 2003-12-03 | 2006-07-25 | Advanced Micro Devices, Inc. | Formation of abrupt junctions in devices by using silicide growth dopant snowplow effect |
US7045407B2 (en) * | 2003-12-30 | 2006-05-16 | Intel Corporation | Amorphous etch stop for the anisotropic etching of substrates |
US6958516B2 (en) | 2004-01-08 | 2005-10-25 | International Business Machines Corporation | Discriminative SOI with oxide holes underneath DC source/drain |
US20060115949A1 (en) * | 2004-12-01 | 2006-06-01 | Freescale Semiconductor, Inc. | Semiconductor fabrication process including source/drain recessing and filling |
US7091071B2 (en) * | 2005-01-03 | 2006-08-15 | Freescale Semiconductor, Inc. | Semiconductor fabrication process including recessed source/drain regions in an SOI wafer |
US7226820B2 (en) * | 2005-04-07 | 2007-06-05 | Freescale Semiconductor, Inc. | Transistor fabrication using double etch/refill process |
JPWO2007034553A1 (ja) * | 2005-09-22 | 2009-03-19 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
-
2005
- 2005-11-18 US US11/164,343 patent/US7659172B2/en not_active Expired - Fee Related
-
2006
- 2006-11-02 CN CNB2006101437092A patent/CN100464397C/zh not_active Expired - Fee Related
- 2006-11-08 JP JP2006303408A patent/JP5153121B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20070117334A1 (en) | 2007-05-24 |
JP2007142402A (ja) | 2007-06-07 |
US7659172B2 (en) | 2010-02-09 |
CN1967793A (zh) | 2007-05-23 |
CN100464397C (zh) | 2009-02-25 |
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