WO2012152762A1

WO2012152762A1 - Tunnel field effect transistor device

Info

Publication number: WO2012152762A1
Application number: PCT/EP2012/058387
Authority: WO
Inventors: Daniele Leonelli; Anne Vandooren; Marc Heyns; Cedric Huyghebaert
Original assignee: Imec
Priority date: 2011-05-06
Filing date: 2012-05-07
Publication date: 2012-11-15

Abstract

A Tunnel Field Effect Transistor device (TFET) wherein at least part of the channel region (3, 13, 23) is situated in between at least part of the source region (2, 12, 22) and the gate structure (5, 6, 15, 16, 25, 26).

Description

Tunnel Field Effect Transistor device

FIELD OF THE DISCLOSURE

The present disclosure relates to the field of semiconductor devices and nanotechnology.

More specifically, the disclosure relates to a nanostructure semiconductor device, more specifically to a tunnel field effect transistor (TFET) wherein the tunneling effect is band-to-band tunneling.

The disclosure further relates to a method of fabricating tunnel Field Effect Transistors (TFETs). More specifically the fabrication method relates to but is not limited to standard planar technology, double gate technology, finFET technology and nanotechnology, wherein the latter includes implementations with integrated nanowires. BACKGROUND OF THE DISCLOSURE

Microelectronic devices are generally fabricated on semiconductor substrates as integrated circuits. A complementary metal-oxide- semiconductor (CMOS) field effect transistor is one of the core elements of the integrated circuits. Dimensions and operating voltages of CMOS transistors are continuously reduced, or scaled down, to obtain ever-higher performance and packaging density of the integrated circuits.

One of the problems due to the scaling down of CMOS transistors, is that the power consumption keeps increasing. This is partly because leakage currents are increasing (e.g. due to short channel effects) and because it becomes difficult to decrease the supply voltage. The latter is mainly due to the fact that the subthreshold slope is limited tominimally about 60 mV/decade at room temperature (or 300K). This means that the off current is increasing while reducing the supply voltage. The increase of the off current will affect the static power and degrades the ON/OFF ratio performance of the transistor. Tunnel field-effect transistors (TFETs) are typically advertised as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), because of their potential sub 60 mV/dec subthreshold swing and, consequently, lower supply voltages compared to conventional MOSFETs. However, Silicon TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunneling barrier determined by the large Silicon bandgap.

To increase the on-current of a silicon TFET, suggestions have been made in literature e.g. by Bhuwalka et al. (IEEE transactions on electron devices Vol. 52, No 7, July 2005) to add a small (about 3 nm wide) section of highly-doped Si₍i-_X)Ge_x at the tunnel barrier. Verhulst et al [A.S. Verhulst et al, J. Appl. Phys., 104(6):064514, 2008] have shown that the ON current of a tunnel field-effect transistor can be boosted by using a p-doped Ge (or p-doped SiGe) source in combination with a Si channel and n doped drain. However, in most designs the ON-current is not sufficiently high to provide the speed performance needed in advanced technologies. In these state of the art TFET devices the ON-current is determined by the band- to-band tunneling from the highly doped source into the inversion layer created under the gate electrode.

As a conclusion, there is still a need for an improved

TFET design because the state of the art TFET devices suffer from a too high subthreshold swing and too low on-currents.

AIM OF THE DISCLOSURE

It is an object of particular embodiments of the present disclosure to provide a tunnel Field Effect transistor (TFET) with significant improved tunneling thereby making the Band-To-Band (BTB) tunneling at the source more effective such that a TFET device can achieve the similar currents as a regular MOSFET device but within a smaller voltage swing.

It is an object of particular embodiments of the present disclosure to provide a TFET with an improved architecture in order to improve the performance of a TFET device. DEFECTIONS

When reference is made in the present disclosure to a TFET device having a planar architecture, this refers to TFET devices in which the current is flowing in a direction parallel to the wafer surface in contrast to a TFET having a vertical architecture in which the current is flowing in a direction perpendicular to the wafer surface. The planar TFET devices may comprise planar TFET devices having source, channel and drain regions embedded in the wafer substrate as well as 3 dimensional TFET devices such as FinFET- like TFET devices in which the channel and/or source region are formed in a 3D "fin"-like shaped structure built on a SOI substrate.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not correspond to actual reductions to practice of the disclosure.

Moreover, the term top and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the particular embodiments described herein are capable of operation in other orientations than described or illustrated herein.

It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present disclosure, the only relevant components of the device are A and B.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.

Similarly it should be appreciated that in the description of exemplary particular embodiments, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.

Embodiments of the present disclosure disclose a tunnel field effect transistor (TFET) with an improved architecture in order to increase the tunneling thereby making the Band-To-Band (BTB) tunneling at the source more effective.

According to embodiments of the present disclosure the improved tunneling may be achieved by placing at least a part of the source region and the gate structure parallel to each other but not in the same longitudinal direction, i.e. parallel to each other along a direction different from the longitudinal direction extending along the dielectric covering at least part if the channel region, and separated by at least a part of the channel area. In this way a larger tunneling area may be achieved, and the larger tunneling area will increase the tunneling current. Since at least part of the channel is sandwiched between the gate structure and the at least a part of the source, all the tunneling field is concentrated in the channel which leads towards a significant higher current compared to the state of the art. In addition there is a suppression of point tunneling (or traverse tunneling), i.e. the tunneling direction parallel to the gate which has a poor swing compared to the tunneling perpendicular to the gate.

According to embodiments, the implementation of the architecture of the TFET of the present disclosure may be done by providing at least part of the source region parallel to the gate structure and having at least part of the channel region in between the gate structure (more specific the gate dielectric) and the source region and provided that the source region is not in contact with the gate structure. In the architecture the drain region may be provided on the opposite side of the channel region, i.e. the channel region opposing the source, provided that the drain region is not in contact with the source region (or preferably does not overlap with the source region). The drain region may be provided on the side of the channel region opposing the source region along the longitudinal direction. The drain region can also be situated on top of the channel region adjacent to the channel region along the longitudinal direction and thus not in the same longitudinal direction of the channel region.

The present disclosure solves the problem of state of the art TFET devices by implementing an integration scheme in which at least part of the channel region is situated in between at least part of the source region and the gate structure and thus the channel is deposited at least partly on top of the source region in order to improve the junction control and maximize the ON current.

According to embodiments of the present disclosure the source region is preferably being in direct contact with the at least part of the channel region which is situated underneath the gate structure and thus in between at least part of the source region and the gate structure.

According to embodiments of the present disclosure, the implementation of a short gate structure, or in other words a gate structure that overlaps only that part of the channels region which has the source region underneath may further reduce the ambipolar behavior and avoid a short between the drain region and the source. The principle and implementation of this short gate structure in a TFET device is described by Vandenberghe et al in US 2008 0224224 and incorporated herein by reference.

The TFET structure of the present disclosure has the advantage that it can be fabricated using state of the art semiconductor processing e.g. epitaxial growth which may allow more easily the introduction of heterojunctions as described and disclosed by Verhulst et al. (US2008067607). Using the architecture of the TFET according to the present disclosure makes the integration of a heterostructure easier to implement since the tunneling junction is parallel to the gate.

The TFET of the present disclosure is made of at least following regions (also called segments):

A highly doped drain region made of a drain semiconductor material, e.g. with a doping level of 10¹⁸ cm^"3 or higher,

A highly doped source region made of a source semiconductor material e.g. with a doping level of 10¹⁸ cm^"3 or higher, and making contact to the channel region, and

A channel region made of a lowly doped, e.g. doped at a doping level below 10¹⁷ cm^"3, or undoped channel semiconductor material situated in between and making contact to the source and drain region, and

A gate structure comprising a gate dielectric and a gate electrode, the gate dielectric covering along the longitudinal direction at least part of the channel region and the gate electrode situated on top of the gate dielectric and not extending beyond the gate dielectric.

The TFET of the present disclosure is further characterized in that the channel region is at least partly situated in between at least part of the source region and the gate structure.

According to embodiments the TFET of the present disclosure may be further characterized in that the channel region is at least partly situated in between at least part of the source region and the gate structure and wherein the at least part of the channel region (situated in between the source region and the gate structure) is in direct contact with the source region.

According to embodiments the drain region is provided on the side of the channel region opposing the source region along the longitudinal direction, the drain region of the TFET of the present disclosure thus being placed in the same longitudinal direction of the channel region, provided that it is avoided that source and drain regions can make contact to each other.

According to embodiments the complete channel region of the TFET of the present disclosure may be placed in between the source region and the gate structure or in other words the complete channel region may be placed parallel to the source region which means that the channel region is placed completely above the source region (or alternatively underneath) or in other words there is no part of the channel region situated in the same longitudinal direction of the source region. It is herewith provided that the source region is not making contact to the drain region of the TFET device.

According to embodiments, a significant, i.e. substantial, part of the channel region of the TFET of the present disclosure may be placed in between the source region and the gate structure or in other words a significant , i.e. substantial, part of the channel region may be placed parallel to the source region and a remaining part of the channel region may be situated in the same longitudinal direction of the source and drain region in such a way that it is avoided that source and drain regions can make contact to each other.

According to embodiments the TFET of the present disclosure comprises a gate structure which is parallel to (or in other words situated on top of) at least part of the channel region and parallel to at least part of the source region and such that at least part of the channel region is situated in between the gate structure and the source region and provided that the gate structure does not make direct contact to the source region. The gate structure comprises a gate dielectric (e.g. an oxide) and a gate electrode. The gate dielectric covers along the longitudinal direction at least part of the channel region and the gate electrode is situated onto the gate dielectric and not extending beyond the gate dielectric.

According to embodiments the TFET of the present disclosure may furthermore comprise at least one source contact on the source region.

According to embodiments the TFET of the present disclosure may furthermore comprise at least one drain contact on the drain region.

Figure 2A illustrates simulations for the TFET architectures having at least part of the channel region situated in between the source and gate structure compared to state of the art TFET architectures. The graphs illustrate the effect of the overlap, measured along the longitudinal direction, of the gate structure with the source or in other words the gate- source overlap. Furthermore, equivalent oxide thickness (EOT), workfunction of the gate (O_gate) and gate length (L_G) are indicated in the figure. The measurements were done at a single indicated V_DS (electrical potential difference between drain and source) in V. The Y axis denotes the current l_DS between drain and source in Α/μηη, whereas the X axis denotes the voltage VQS (electrical potential difference between gate and source) in V. Figure 2A moreover shows in an inset a general overview of a cross section of the TFET used for the simulations. In the inset the X and Y axis indicate the dimensions of the TFET and its general composition in μηη (indicated as urn).

Figure 2B illustrates simulations for TFET architectures according to the present disclosure having at least part of the channel region situated in between the source and gate structure compared to shown state of the art TFET architectures. The graphs illustrate the effect of the channel thickness t_ch of the at least part of the channel region situated in between the source and gate structure for TFET architectures according to the present disclosure. The thickness of the channel region which is situated in between the gate structure and the source region is preferably 5nm or less in order to get a significant advantage over a prior art p-i-n TFET device. In case of higher channel doping, an onset shift may be observed because of a different flat band voltage. Furthermore, equivalent oxide thickness (EOT), workfunction of the gate (O_gate) and gate length (L_G) are indicated in the figure. The measurements were done at a single indicated V_DS (electrical potential difference between drain and source) in V. The Y axis denotes the current l_DS between drain and source in Α/μηΊ, whereas the X axis denotes the voltage VQS (electrical potential difference between gate and source) in V. Figure 2B moreover shows in insets a general overview of a cross section of the respective TFETs used for the simulations. In the inset the X and Y axis indicate the dimensions of the TFETs and its general composition in μηη (indicated as urn).

The TFET structure of the present disclosure has a further advantage that it may be implemented in a planar or vertical architecture thereby using state of the art semiconductor processing. The planar architecture may be a horizontal TFET or alternatively a 3 dimensional (3D) Fin-Shaped TFET (indicated as Fin-TFET). The vertical architecture may be a TFET comprising vertical nanostructures such as nanowires (indicated as NW-TFET).

According to embodiments the TFET of the present disclosure has a planar architecture.

Figure 1A illustrates a state of the art planar TFET device wherein the source 2, channel 3 and drain 4 region are situated in a same longitudinal direction, preferably substantially in a same plane or layer. In addition a legend is shown indicating possible examples of materials used in the configuration shown. Although not all the figures show the legend, the legend is usable for all the figures.

The preferred layer comprising the source 2, channel 3 and drain 4 region is provided on top of a substrate 1 , 41. The substrate 1 , 41 shown in figure 1A, although not necessarily, preferably comprises an intermediate insulating layer 1 a, for example substantially made of Si0₂, separating two semi-conductive layers 1 b and 41 , for example substantially made of substantially undoped Si. Further figure 1 further also shows preferred source and drain contacts 7, 8 provided onto the respectively source and drain regions 2, 4. The source and drain contacts 7, 8 are made from a conductive material.

Figure 1A further shows a gate structure 5, 6 is provided. The gate structure 5, 6 comprises a gate dielectric 5 and a gate electrode 6. The gate dielectric 5 preferably although not necessarily comprises, as shown in figure 1A, a first layer comprising Si0₂ and a second layer comprising Hf0₂.

Figure 1A further shows that a spacer 42, in particular but not necessarily a SiN spacer, is provided in between the gate structure 5, 6 and the source region 2 and/or the drain region 4 such as to avoid direct electrical contact between the gate structure 5, 6 and the source region 2 and/or the drain region 4 and thus current in between the gate structure 5, 6 and the source region 2 and/or the drain region 4.

Figures 1 B-1 G illustrate similar implementations of planar architectures of a TFET device but according to the present disclosure wherein the channel region 3 is placed at least partly in between the gate structure 5, 6 and the source region 2 and such that at least part of the channel region 3 and part of the source region 2 are parallel to the gate structure 5, 6 of the TFET but not situated in the same longitudinal direction. The channel region 3 situated in between the source 2 and the drain 4 structure may be replaced by a buffer material 40 (insulating or semiconductor) in order to improve the separation between source and drain region 2, 4 (avoiding pin diode leakage) as illustrated in Figure 1 C and 1 D. The drain region 4 may be situated in the same longitudinal direction as the source region 2 as illustrated in Figures 1 B and 1 C or alternatively the drain region 4 may be raised and situated on top of the channel region 3 as illustrated in Figures 1 D, 1 E, 1 F and 1 G. It has been found that the position of the drain region 4 on top of the channel region 3 but moreover not on top of the source region 2, reduces leakage of current through the channel region 3 in between the source region 2 and the drain region 4 along a part of the channel region 3 which is not situated in between at least part of the source region 2 and the gate structure 5, 6. Without wanting to be bound to any theory, it is believed that this is at least partly caused by an increased length of travel for such leakage current due to, in such configuration, the lack of parallel surfaces of the source region 2 and the drain region 4 along opposing sides of the channel region 3.

Figure 1 E in particular shows an embodiment of the present disclosure wherein the drain region 4 is on top of the channel region 3 but wherein no buffer material 40 is present in between the source 2 and the drain 4 structure.

Figure 1 F shows an embodiment of the current disclosure wherein the source region 2 extends to below the drain region 4.

Figure 1 G shows an enmbodiment of the current disclosure wherein the intermediate layer 1 a is not present.

According to embodiments the TFET of the present disclosure has a 3 dimensional Fin-FET like architecture, referred to in this application as a Fin-TFET. In the Fin-TFET the fin-like structure may form the source region or alternatively the channel region.

The Fin-TFET according to the present disclosure may be implemented as a device in which the fin preferably defines the channel region and a larger tunneling area for the band-to-band tunneling is achieved by placing the gate structure on one side and the source region on the other, preferably opposing, side of the (thin) fin such that a large area is available for band-to-band tunneling which strongly increases the ON-current of the device. The basic Fin-TFET structure of the present disclosure resembles that of a state of the art double-gate Fin-FET structure (with two independent gates) wherein one of the gate structures is replaced by the source. The source can be formed by providing a dedicated doping to one side of the fin but can also be formed by a heterojunction or can be epitaxially grown to provide junctions that are very effective in generating band-to-band tunneling.

Preferably, in the TFET according to the disclosure the source region is formed to one side of the fin-like structure and the drain region is to the other side, taken along the longitudinal direction, of the fin-like structure as for example shown in figure 4A.

Figure 4A illustrates a schematic top view of the Fin- TFET device according to the present disclosure having the fin 23 acting as a channel and a gate structure 25, 26 on one side of the fin and a source 22 on the other side of the fin, taken along cross direction of the fin, preferably perpendicular to the longitudinal direction. The Fin-TFET device illustrated in Figure 4A may be an n-type TFET design whereby the source region 22 is preferably highly doped (e.g. p-type doped), the fin area 23 itself is preferably lowly doped (undoped or intrinsic) and the drain region 24 is preferably highly doped again (e.g. n-type doped). Also, the preferred source and drain contacts 27, 28 are shown.

Figure 4B illustrates a 3D view of a cross-section of the Fin-TFET device according to the present disclosure having the fin acting as a source region 22 and wherein the channel region is a channel shell layer 23 of several nm (preferably less than 5 nm) and which is at least partly surrounding the fin (source region 22). The gate structure 25, 26 is provided on top of the channel shell layer 23 and covers at least part of the channel shell layer 23. Further, the drain region 24 and the substrate 21 , here comprising a top insulating layer, are shown. Similar to figure 1 C, a buffer material 40 is present in between the source region 22 and the drain region 24 to avoid electrical contact between the source region 22 and the drain region 24. Figure 4C illustrates a 3D view of the of the Fin-TFET device of figure 4B.

Figure 4D illustrates a 3D view of a cross-section of the Fin-TFET device according to Figure 4B and 4C in which the drain region 24 is provided on top of the channel shell layer 23 similar to figure 1 D. The drain region may be provided at a finite distance from the gate structure 25, 26 thereby taking care that the drain region 24 does not make contact to the source region 22.

The height of the fin in the Fin-TFET of the present disclosure may be increased such that the tunneling current can be further enhanced as in regular Fin-FET devices. Ideally the electrostatics of the device have to be optimized in such a way that the area over which band-to-band tunneling occurs is made as large as possible. To this purpose it may be beneficial to include a dopant profile across the drain region (or alternatively across the source region) in order to create a uniform potential across the fin while current is flowing (which will cause a potential drop across the fin.

The doping level and/or thickness of the fin in the Fin- TFET of the present disclosure may be further optimized to enhance the overall current of the device.

According to embodiments the TFET of the present disclosure has a vertical architecture. The vertical architecture may be comprising nanostructures such as Nanowires.

Figure 3A illustrates a state of the art vertical TFET device wherein the source 12, channel 13 and drain region 14 are situated in the same longitudinal direction and wherein the regions may be fabricated as a nanostructure (nanowire). Figure 3a further shows the gate structure 15, 16, comprising the gate electrode 16 and the gate dielectric 15, with the preferred at least one gate contact 19 and the preferred source 17 and/or drain 18 contacts.

Figure 3A further shows that a spacer 42, in particular but not necessarily a SiN spacer, is provided in between the gate structure 15, 16 and the source region 12 such as to avoid direct electrical contact between the gate structure 15, 16 and the source region 12 and thus current in between the gate structure 15, 16 and the source region 12.

Figure 3A further shows that a spacer 20, in particular but not necessarily a SiN spacer, is provided in between the gate structure 15, 16 and the drain region 14 such as to avoid direct electrical contact between the gate structure 15, 16 and the drain region 14 and thus current in between the gate structure 15, 16 and the drain region 14.

Figures 3B-3E illustrate implementations of a vertical architecture of the TFET in accordance with embodiments of the present disclosure thereby making use of vertically grown nanostructures (nanowires).

Figure 3B illustrates a vertical TFET (NW-TFET) in which a capping channel layer 13a of several nanometers is deposited by for example selective epitaxial growth (SEG) onto the vertical sidewalls of the nanostructure (nanowire), more preferably at least onto the sidewalls of the source region 12 and channel region 13 of the vertical nanostructure

(nanowire). The position of the source-channel interface thereby modulates the area of tunneling. The capping channel layer 13a is preferably 5nm or less in order to get a significant advantage over a prior art p-i-n TFET device. The drain region 14 may be implanted or grown by selective epitaxial process before the nanowire patterning.

The materials used to provide the vertical TFET (NW- TFET) in accordance with embodiments of the present disclosure may be all Si (or alternatively heterojunctions can be used for the source region). The material for channel capping layer should be chosen to minimize the effective band gap at the tunnel junction improving the band-to-band tunneling.

The disclosure described above proposes several TFET architectures and implementations in order to improve the tunneling in the TFET devices thereby making the Band-To-Band (BTB) tunneling at the source more effective and increasing the ON-current. In all TFET devices of the present disclosure the source and drain regions in the TFET's of the present disclosure may be selectively doped to a desired doping level with a desired dopant type, for example the source and drain regions may be selectively doped to a dopant concentration of 10¹⁸/cc to 10²¹/cc to form a highly doped source and drain region. The source in the TFET devices of the present disclosure may be for example highly doped with a p-type dopant selected from B, ... or n-type dopant selected from As, P, ...

The semiconductor material in all TFET devices of the present disclosure may be selected from at least one of group IV materials such as Si, Ge, C and binary compounds thereof, or group lll/V materials such as In, Ga, As, Sb, Al, P, B, N and binary, tertiary and quaternary compounds thereof or group IIA I materials such as Cd, Zn, S, Se, Te, O and binary, tertiary and quaternary compounds thereof. As an example the source semiconductor material in the TFET devices of the present disclosure may be made of germanium or SiGe (e.g. Si₍i-_X)Ge_x with x > 0.15) and the channel semiconductor material may be made of silicon.

In all TFET devices of the present disclosure a transition layer may be inserted in between the source and the channel to avoid direct contact between the doped source and the intrinsic channel and allows preserving all of the dopants (e.g. B atoms) entirely within the source and transition layer. The insertion of a transition layer has therein the purpose of achieving an abrupt source-channel interface and to engineer the doping profile to coincide with the interface. The transition layer may be made of the source semiconductor material or a combination of the source and the channel semiconductor material and wherein the dopants of the source have higher diffusivity in the channel semiconductor material (e.g. Si) compared to its diffusivity in the source semiconductor material (e.g. Ge or SiGe). The effect of obtaining a steep doping profile is most pronounced if both a Ge source and Ge transition layer are used, such that the difference in dopant diffusivity with the Si channel is the largest.

In all TFET devices of the present disclosure a gate structure is provided, the gate structure comprises a gate dielectric and a gate electrode. The gate dielectric may be selected from at least one of silicon based oxide (e.g. silicon dioxide, silicon oxy nitride) aluminium oxide, high-k oxides (oxides, nitrided oxides), silicates and nitrided silicates of transition metals such as Hf, Ta, Ti, Nb, V, Y, Zr. More particular the gate dielectric (oxide) may be a high-k oxide such as hafnium oxide. The gate electrode (contact) may be made of a conductive material and may be selected from at least one of poly silicon, poly germanium, metals such as Al, W, Ta, Ti, Ru, Pd, Rh, Re, Pt, and alloys thereof, metal-nitrides such as TaN and TiN, metal- silicon nitrides such as TaSiN, conductive oxides such as Ru0₂ and Re0₃, fully silicided metals (FUSI) such as CoSi₂, NiSi and TiSi₂, fully germanided metals (FUGE), workfunction tunable metals, engineered materials to obtain a particular gate workfunction. More particular the gate electrode may be made of a metal of which the workfunction has been engineered specifically for the chosen TFET semiconductor material.

In all TFET devices of the present disclosure the thickness of the gate dielectric in the gate structure may be varied, which means that (optionally) a gradient may be provided in the thickness of the gate dielectric (gate oxide) in order to achieve a variation in the threshold voltage (or anything else within the gate structure that has a similar effect).

In all TFET devices of the present disclosure a gate structure is provided, the gate structure may be a short gate structure meaning that the gate structure does not align with or cover the drain, and only overlaps with the source and optionally with part of the channel. A shorter gate structure has the advantage to suppress the ambipolar behavior, typical of gated p-i-n devices. A shorter gate structure may be especially attractive in the fabrication of a Nanostructure (nanowire) TFET because it is leading to a more realistic processing.

In all TFET devices of the present disclosure a source and drain contact may be provided onto the respectively source and drain regions. The and drain contacts may be made from a conductive material which is selected from at least one of a silicide containing structure (NiSi, CoSi₂, TiSi₂, ...), a germanide containing structure, a metal containing structure, poly silicon or a combination thereof. More particularly the source and drain may be a combination of a metal with a silicide.

It is to be understood that although particular embodiments, specific constructions and configurations, as well as materials, have been discussed herein for all TFET devices according to the present disclosure, various changes or modifications in form and detail may be made without departing from the scope of this disclosure as defined by the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

All figures are intended to illustrate some aspects and particular embodiments of the present disclosure. The figures are depicted in a simplified way for reason of clarity. Not all alternatives and options are shown and therefore the disclosure is not limited to the content of the given drawings. Like numerals are employed to reference like parts in the different figures.

Figure 1A illustrates the implementation of a state of the art TFET device.

Figures 1 B-1 E illustrates planar implementations of the TFET architectures in accordance with embodiments of the present disclosure wherein at least part of the channel region is situated in between the gate structure and the source region of the TFET and wherein at least part of the channel region is parallel to the source region and the gate structure or wherein the complete channel region is placed parallel to source region and the gate structure. Figure 2A illustrates simulations for the TFET architectures having at least part of the channel region situated in between the source and gate structure compared to state of the art TFET architectures. The graphs illustrate the effect of the overlap of the gate structure with the source or in other words the gate-source overlap.

Figure 2B illustrates simulations for TFET architectures according to the present disclosure having at least part of the channel region situated in between the source and gate structure compared to state of the art TFET architectures. The graphs illustrates the effect of the channel thickness of the at least part of the channel region situated in between the source and gate structure for TFET architectures according to the present disclosure.

Figures 3A-3D illustrate vertical TFET architectures which may comprise vertical nanostructures such as nanowires (NW-TFET) in accordance with embodiments of the present disclosure.

Figures 4A-4D illustrate vertical Fin-TFET like architectures in accordance with embodiments of the present disclosure.

Figure 4A illustrates a schematic top view of the Fin- TFET device according to the present disclosure having the fin 23 acting as a channel and a gate structure 25, 26 on one side of the fin a source 22 on the other side of the fin.

Figure 4B illustrates a 3D view of a cross-section of figure 4C showing the Fin-TFET device according to the present disclosure having the fin acting as a source region 22 and wherein the channel region 23 is a channel shell layer of several nm and which is at least partly surrounding the source region 22. The gate structure 25, 26 is provided on top of the channel shell layer 23 and covering at least part of the channel shell layer.

Figure 4D illustrates a 3D view of a cross-section of the Fin-TFET device according the present disclosure having the fin acting as a source region 22 and wherein the channel region 23 is a channel shell layer of several nm and which is at least partly surrounding the source region and in which a drain region is provided on top of the channel shell layer 23. The drain region may be provided at a finite distance from the gate structure thereby taking care that the drain region does not make contact to the source region.

Claims

1 . A Tunnel Field Effect Transistor device (TFET) made of at least following regions:

- a highly doped drain region (4, 14, 24) made of a drain semiconductor material, e.g. with a doping level of 10¹⁸ cm^"3 or higher,

- a highly doped source region (2, 12, 22) made of a source semiconductor material e.g. with a doping level of 10¹⁸ cm^"3 or higher, and making contact to a channel region (3, 13, 23), and

- the channel region (3, 13, 23) made of a lowly doped, e.g. doped at a doping level below 10¹⁷ cm^"3, or undoped channel semiconductor material situated in between and making contact to the source (2, 12, 22) and drain region (3, 13, 23), and

- a gate structure (5, 6, 15, 16, 25, 26) comprising a gate dielectric (5, 15, 25) and a gate electrode (6, 16, 26), the gate dielectric

(5, 15, 25) covering along a longitudinal direction at least part of the channel region (3, 13, 23) and the gate electrode (6, 16, 26) situated on top of the gate dielectric (5, 15, 25) and not extending beyond the gate dielectric (5, 15, 25) characterized in that at least part of the channel region (3, 13, 23) is situated in between at least part of the source region (2, 12, 22) and the gate structure (5, 6, 15, 16, 25, 26).

2. The TFET according to claim 1 wherein at least a part of the source region (2, 12, 22) and the gate structure (5, 15, 25, 6, 16, 26) are placed parallel to each other along a direction different from the longitudinal direction and separated by the at least a part of the channel area (3, 13, 23) situated in between at least part of the source region (2, 12, 22) and the gate structure (4, 14, 24).

3. The TFET according to any one of claims 1 - 2 wherein the drain region (4, 14, 24) is provided on the side of the channel region (3, 13, 23) opposing the source (2, 12, 22) and wherein the drain region (4, 14, 24) is not in contact with the source region (2, 12, 22).

4. The TFET according to any one of claims 1 - 3 wherein the source region (2, 12, 22) is in direct contact with the at least part of the channel region (3, 13, 23) which is situated underneath the gate structure (5, 15, 25, 6, 16, 26) in between at least part of the source region (2, 12, 22) and the gate structure (5, 15, 25, 6, 16, 26).

5. The TFET according to any one of claims 1 - 4 wherein the wherein the drain region (4, 14, 24) is provided on the side of the channel region (3, 13, 23) opposing the source region (2, 12, 22) along the longitudinal direction.

6. The TFET according to any one of claims 1 - 4 wherein the drain region (4, 14, 24) is situated on top of the channel region (3, 13, 23) adjacent to the channel region (3, 13, 23) along the longitudinal direction.

7. The TFET according to any one of claims 1 - 6 wherein a significant part of the channel region (3, 13, 23) is placed in between the source region (2, 12, 22) and the gate structure (5, 15, 25, 6, 16, 26).

8. The TFET according to claim 7 wherein the significant part of the channel region (3, 13, 23) is the complete channel region (3, 13, 23).

9. The TFET according to any one of claims 1 - 8 wherein the gate structure (5, 15, 25, 6, 16, 26) does not make direct contact to the source region (2, 12, 22).

10. The TFET according to any one of claims 1 - 9 wherein the thickness of the channel region (3, 13, 23) which is situated in between the gate structure (5, 15, 25, 6, 16, 26) and the source region (2, 12, 22) is 5nm or less.

1 1 . The TFET according to any one of claims 1 - 10 wherein the TFET has a planar architecture.

12. The TFET according to any one of claims 1 - 10 wherein the TFET has a 3 dimensional Fin-FET like architecture (Fin-TFET) and wherein the fin-like structure forms the source region (22) or alternatively the channel region (23).

13. The TFET according to claim 12 wherein the Fin-TFET has a gate structure (25, 26) which is placed on one side and the source region (22) on the other side of the fin-like structure along cross direction of the fin-like structure.

14. The TFET according to claim 12 or 13 wherein the source region (22) is formed to one side of the fin-like structure, the drain region (24) is to the other side of the fin-like structure along the longitudinal direction.

15. The TFET according to claim 12 wherein the fin-like structure is acting as source region (22) and wherein the channel region (23) is a shell layer having a thickness of preferably less than 5 nm and which is at least partly surrounding the fin-like structure (source region) and the gate structure (25, 26) is provided on top of the channel shell layer (23) and covering at least part of the channel shell layer (23).

16. The TFET according to any of foregoing claims 1 to 10 wherein the TFET has a vertical architecture comprising nanostructures and further comprising a capping channel layer (13a) of preferably 5nm or less at least onto the sidewalls of the source region (12) and channel region (13) of the vertical nanostructure (nanowire).