CN104347692A - Tunneling field effect transistor inhibiting output non-linear opening and preparing method of tunneling field effect transistor - Google Patents
Tunneling field effect transistor inhibiting output non-linear opening and preparing method of tunneling field effect transistor Download PDFInfo
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- CN104347692A CN104347692A CN201410448766.6A CN201410448766A CN104347692A CN 104347692 A CN104347692 A CN 104347692A CN 201410448766 A CN201410448766 A CN 201410448766A CN 104347692 A CN104347692 A CN 104347692A
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- 230000005669 field effect Effects 0.000 title claims abstract description 25
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- 230000002401 inhibitory effect Effects 0.000 title abstract 2
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- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
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- 229910004298 SiO 2 Inorganic materials 0.000 claims description 2
- 239000012190 activator Substances 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- 239000010941 cobalt Substances 0.000 claims description 2
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- 230000001629 suppression Effects 0.000 description 5
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention provides a tunneling field effect transistor inhibiting output non-linear opening. The tunneling field effect transistor comprises a tunneling source region, a channel region, a drain region, a semiconductor substrate region, a gate dielectric layer and a control gate, wherein the gate dielectric layer is positioned above the channel region, the control gate is positioned above the gate dielectric layer, the channel region is positioned above the channel source region, in addition, the position of the channel region is partially overlapped with the tunneling source region, a tunneling junction is formed at the interface part of the channel region and the tunneling source region, the drain region is parallel to the channel region and is positioned at the other side of the channel region, the control gate is positioned above the overlapping part of the channel region and the tunneling source region, a control-gate-free region is arranged in the channel region near the drain region, and in addition, the channel region adopts semiconductor materials with the energy state density being lower than 1E18cm<-3>. The tunneling field effect transistor has the advantages that the nonlinear opening phenomenon in the device output characteristics can be effectively inhabited, and in addition, the steeper and straighter sub-threshold slope is maintained.
Description
Technical field
The invention belongs to field-effect transistor logical device field in cmos vlsi (ULSI), be specifically related to a kind of tunneling field-effect transistor suppressing output nonlinear to be opened and preparation method thereof.
Background technology
Since integrated circuit is born, microelectronics integrated technology is always according to " Moore's Law " development, and dimensions of semiconductor devices constantly reduces.Along with semiconductor device enters deep sub-micron range, conventional MOSFET device limit owing to being subject to self spreading the conduction mechanism drifted about, and sub-threshold slope is subject to the restriction of thermoelectric potential kT/q and synchronously cannot reduces along with reducing of device size.This just causes MOSFET element leakage current to reduce the requirement that cannot reach device dimensions shrink, and the energy consumption of whole chip constantly rises, and chip power-consumption density sharply increases, and seriously hinders the development that chip system is integrated.In order to adapt to the development trend of integrated circuit, the R and D work of Novel super-low power consuming devices just seems particular importance.Tunneling field-effect transistor (TFET, Tunneling Field-Effect Transistor) adopt the new conduction mechanism of band-to-band-tunneling (BTBT), be a kind of Novel low power consumption device being suitable for system integration application development having very much development potentiality.TFET controls the tunnelling width of source and raceway groove interface place tunnel junctions by gate electrode, makes source valence-band electrons be tunneling to channel conduction band (or raceway groove valence-band electrons is tunneling to source conduction band) and forms tunnelling current.This novel conduction mechanism breaks through the restriction of thermoelectric potential kT/q in conventional MOS FET sub-threshold slope theoretical limit, can realize the super steep sub-threshold slope lower than 60mV/dec, reduces device static leakage current and then reduces device quiescent dissipation.
But because semiconductor tape band tunneling efficiency is on the low side, the ON state current of TFET is lower compared with conventional MOS FET, the requirement in system integration application can not be met.Therefore, while keeping more steep sub-threshold slope, improving TFET ON state current is the very important problem needing in TFET device application to solve.
In addition, TFET output characteristic and conventional MOS FET are completely different, and output current increases with drain terminal voltage and increases, and is by drain terminal voltage drop at source tunnel junctions place, effectively change tunnel junctions tunnelling width thus the increase of output tunnelling current is realized.Become e index relation owing to exporting tunnelling current value with tunnelling width of lambda, drain terminal voltage presents a kind of super e index relation with output tunnelling current.Thus TFET output characteristic curve leading portion is a kind of nonlinear curve of super e index, i.e. the non-linear unlatching phenomenon of output characteristic, and cause device channel conductance very little, the output resistance in circuit application is quite large.This output characteristic of TFET is unfavorable for the circuit application of device very much, and therefore improving TFET output characteristic is also a very important problem in TFET circuit application.
Summary of the invention
The object of the present invention is to provide a kind of suppress output nonlinear to be opened tunneling field-effect transistor and preparation method.This tunneling field-effect transistor can non-linear unlatching phenomenon effectively in suppression device output characteristic, and maintains more steep sub-threshold slope.
Technical scheme provided by the invention is as follows:
A kind of tunneling field-effect transistor suppressing output nonlinear to be opened, as shown in Figure 1, comprise tunnelling source region 5, channel region 6, drain region 9, semiconductor substrate region 1, be positioned at the gate dielectric layer 7 above channel region, and be positioned at the control gate 8 on gate dielectric layer, it is characterized in that, described channel region 6 is positioned at above tunnelling source region 5 and position and tunnelling source region 5 partly overlaps, and forms tunnel junctions in channel region 6 and interface, tunnelling source region 5; Described drain region 9 is parallel with channel region 6, is positioned at the opposite side (side, non-tunnelling source region) of channel region 6; Described control gate 8 is positioned at the top of channel region 6 and tunnelling source region 5 lap, and there is a region not having control gate to cover in the channel region 6 near drain region 9; Further, described channel region 6 selects energy state density lower than 1E18cm
-3semi-conducting material.
For N-type device, tunnelling source region is the heavy doping of P type, and its doping content is about 1E20cm
-3-1E21cm
-3, drain region is N-type heavy doping, and its doping content is about 1E18cm
-3-1E19cm
-3, channel region is P type light dope, and its doping content is about 1E13cm
-3-1E15cm
-3; And for P type device, tunnelling source region is N-type heavy doping, its doping content is about 1E20cm
-3-1E21cm
-3, drain region is the heavy doping of P type, and its doping content is about 1E18cm
-3-1E19cm
-3, channel region is N-type light dope, and its doping content is about 1E13cm
-3-1E15cm
-3.
Described tunneling field-effect transistor can be applied to Si, or Ge, also the germanium (GOI) on the binary of other II-VI, III-V and IV-IV races or ternary semiconductor material or isolate supports (SOI) or insulator can be applied to.
The preparation method of the tunneling field-effect transistor that the present invention provides described suppression output nonlinear to open simultaneously, comprises the following steps:
1) substrate prepares: light dope or unadulterated Semiconductor substrate;
2) initial thermal oxidation deposit one deck nitride on substrate;
3) carry out shallow trench isolation after photoetching from (Shallow Trench Isolation, STI), and deposit isolated material carries out chemical-mechanical planarization (Chemical Mechanical Polishing, CMP) after filling deep hole;
4) photoetching exposes tunnelling source region, take photoresist as mask, and carry out ion implantation and form tunnelling source region, concentration is about 1E20cm
-3-1E21cm
-3;
5) deposit has lower state density (energy state density is lower than 1E18cm
-3) heterogeneous semiconductor layer;
6) deposit gate dielectric material and grid material, carries out photoetching and etching, forms gate figure;
7) again photoetching is carried out, etching channel region figure;
8) photoetching exposes drain region, take photoresist as mask, and carry out ion implantation and form drain region, concentration is about 1E18cm
-3-1E19cm
-3;
9) quick high-temp annealing activator impurity;
10) finally enter the consistent later process of same CMOS, comprise deposit passivation layer, opening contact hole and metallization etc., the tunneling field-effect transistor suppressing output nonlinear to be opened can be obtained.
Described preparation method, is characterized in that, step 1) described in light dope, its doping content is about 1E13cm
-3-1E15cm
-3.
Described preparation method, it is characterized in that, step 1) described in semiconductor substrate materials be selected from Si or Ge, or the germanium (GOI) on the binary of other II-VI, III-V and IV-IV races or ternary semiconductor, isolate supports (SOI) or insulator.
Described preparation method, is characterized in that, step 5) described in heterogeneous semiconductor layer material be selected from the II-VI with lower state density, the binary of III-V and IV-IV race or ternary semiconductor.
Described preparation method, is characterized in that, step 6) described in gate dielectric material be selected from SiO
2, Si
3n
4or high K grid (dielectric constant K>3.9) dielectric material.
Described preparation method, is characterized in that, step 6) described in the method for deposit gate dielectric material be selected from one of following method: chemical vapor deposition or physical vapor deposition.
Described preparation method, is characterized in that, step 6) described in grid material be selected from doped polycrystalline silicon, metallic cobalt, nickel and other metals or metal silicide.
Technique effect of the present invention (for N-type device):
1, control gate is positioned at above channel region and source region, gate electrode adds positive voltage, channel region can be with drop-down, tunneling window is formed when channel region conduction band is pulled down to below the valence band of tunnelling source region, the band-to-band-tunneling perpendicular to control gate is there is at tunnel junctions place, device is opened, thus obtains more steep sub-threshold slope.
2, under the ON state condition that gate voltage is enough large, due to channel region employing is the semi-conducting material with lower state density, when channel surface band curvature reaches capacity, channel region conduction band can be made to be bent to below the Fermi level of channel region.
3, further, when the larger drain voltage of gate voltage is zero, because channel region conduction band is positioned at below the Fermi level of channel region, namely channel region conduction band is positioned at (tunnelling source region heavy doping below the valence band of tunnelling source region, source region valence band is positioned at above Fermi level), when making drain voltage be zero, in tunnel junctions, namely place forms tunneling window, significantly increase drain voltage less time channel conduction, thus effectively inhibit the non-linear unlatching phenomenon in device output characteristic.
Compared with existing TFET, the tunneling field-effect transistor suppressing output nonlinear to be opened, by device structure design, significantly improves device output characteristic, maintains steep sub-threshold slope simultaneously.
The tunneling field-effect transistor preparation technology that suppression output nonlinear of the present invention is opened is simple, the CMOS IC process compatible of preparation method and standard, can integrated TFET device in CMOS integrated circuit effectively, standard technology can also be utilized to prepare the low power consumption integrated circuit be made up of TFET, significantly reduce production cost, simplify technological process.
Accompanying drawing explanation
Fig. 1 is the structural representation of the tunneling field-effect transistor that the present invention suppresses output nonlinear to be opened.
Fig. 2 is the device profile map after removing nitride after forming STI isolation on a semiconductor substrate;
Fig. 3 is that photoetching exposes the tunnelling source region of TFET device and the device profile map behind ion implantation formation tunnelling source region;
Fig. 4 is the device profile map after deposit one deck has the heterogeneous semiconductor layer of low-energy zone density;
Fig. 5 is photoetching and device profile map after etching formation control grid;
Fig. 6 is photoetching and device profile map after etching channel region figure;
Fig. 7 is that photoetching exposes the drain region of TFET device and the device profile map behind ion implantation formation drain region.
In figure,
1-Semiconductor substrate; 2-STI isolates; 3-oxide layer; 4-photoresist; 5-tunnelling source region; 6-channel region;
7-high-k dielectric layer; 8-control gate; 9-drain region; The passivation layer of 10-later process; The metal of 11-later process.
Embodiment
Below in conjunction with accompanying drawing, be described further by the implementation method of specific embodiment to the tunneling field-effect transistor that suppression output nonlinear of the present invention is opened.
Concrete implementation step is as shown in Fig. 1-Fig. 7: (this example for N-type device, P type device can by that analogy)
1, be light dope (about 1E13cm in substrate doping
-3-1E15cm
-3), crystal orientation be <001> Si substrate 1 on initial thermal oxidation layer of silicon dioxide 3, thickness is about 10nm, and deposit one deck silicon nitride (Si
3n
4), thickness is about 100nm, adopts shallow-trench isolation fabrication techniques active area STI to isolate 2 afterwards, then carries out CMP, as shown in Figure 2;
2, photoetching exposes tunnelling source region 5, with photoresist 4 for mask, carries out tunnelling source region 8 ion implantation (BF
2, 1E16/cm
-2, 20keV), as shown in Figure 3;
3, the silicon dioxide of surperficial initial growth is removed in drift, and the heterogeneous semiconductor layer 6 adopting LPCVD deposit one deck to have lower state density is InAs, and thickness is 6-15nm, as shown in Figure 4;
4, then deposit one deck high-k gate dielectric layer 7, gate dielectric layer is Al
2o
3, thickness is 1 ~ 5nm; Adopt LPCVD deposit control gate 8, grid material is doped polysilicon layer, and thickness is 50 ~ 200nm.Make gate figure by lithography, etching control gate figure, as shown in Figure 5;
5, photoetching etch channel region 6 figure, as shown in Figure 6;
6, photoetching exposes drain region 9, with photoresist 4 for mask, carries out drain region 9 ion implantation (As, 1E14/cm
-2, 30keV), as shown in Figure 7.Carry out a quick high-temp annealing, implanted dopant is activated (1050 DEG C, 10s)
7, conventional later process is finally entered, comprise deposit passivation layer 10, opening contact hole and metallization 11 etc., Figure 1 shows that the tunneling field-effect transistor structural representation that the suppression output nonlinear of the obtained described N-type prepared based on standard CMOS IC technique is opened.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (11)
1. the tunneling field-effect transistor suppressing output nonlinear to be opened, comprise tunnelling source region (5), channel region (6), drain region (9), semiconductor substrate region (1), be positioned at the gate dielectric layer (7) above channel region, and be positioned at the control gate (8) on gate dielectric layer; It is characterized in that, described channel region (6) is positioned at top, tunnelling source region (5) and position and tunnelling source region (5) partly overlap, and forms tunnel junctions in channel region (6) and tunnelling source region (5) interface; Described drain region (9) is parallel with channel region (6), is positioned at the opposite side of channel region (6); Described control gate (8) is positioned at the top of channel region (6) and tunnelling source region (5) lap, and there is a region not having control gate to cover in the channel region (6) near drain region (9); Further, described channel region (6) select energy state density lower than 1E18cm
-3semi-conducting material.
2. tunneling field-effect transistor as claimed in claim 1, it is characterized in that, for N-type device, tunnelling source region is the heavy doping of P type, and its doping content is about 1E20cm
-3-1E21cm
-3, drain region is N-type heavy doping, and its doping content is about 1E18cm
-3-1E19cm
-3, channel region is P type light dope, and its doping content is about 1E13cm
-3-1E15cm
-3; And for P type device, tunnelling source region is N-type heavy doping, its doping content is about 1E20cm
-3-1E21cm
-3, drain region is the heavy doping of P type, and its doping content is about 1E18cm
-3-1E19cm
-3, channel region is N-type light dope, and its doping content is about 1E13cm
-3-1E15cm
-3.
3. the tunneling field-effect transistor described in claim 1 or 2 is applied to Si, or Ge, or the germanium on the binary of other II-VI, III-V and IV-IV races or ternary semiconductor material or isolate supports or insulator.
4. a preparation method for the tunneling field-effect transistor suppressing output nonlinear to be opened, comprises the following steps:
1) substrate prepares: light dope or unadulterated Semiconductor substrate;
2) initial thermal oxidation deposit one deck nitride on substrate;
3) carry out after photoetching shallow trench isolation from, and deposit isolated material is filled after deep hole and is carried out chemical-mechanical planarization;
4) photoetching exposes tunnelling source region, take photoresist as mask, and carry out ion implantation and form tunnelling source region, concentration is about 1E20cm
-3-1E21cm
-3;
5) deposit has the heterogeneous semiconductor layer of lower state density;
6) deposit gate dielectric material and grid material, carries out photoetching and etching, forms gate figure;
7) again photoetching is carried out, etching channel region figure;
8) photoetching exposes drain region, take photoresist as mask, and carry out ion implantation and form drain region, concentration is about 1E18cm
-3-1E19cm
-3;
9) quick high-temp annealing activator impurity;
10) finally enter the consistent later process of same CMOS, comprise deposit passivation layer, opening contact hole and metallization, the tunneling field-effect transistor suppressing output nonlinear to be opened can be obtained.
5. preparation method as claimed in claim 4, is characterized in that, step 1) described in light dope, its doping content is about 1E13cm
-3-1E15cm
-3.
6. preparation method as claimed in claim 4, it is characterized in that, step 1) described in semiconductor substrate materials be selected from Si or Ge, or the germanium on the binary of other II-VI, III-V and IV-IV races or ternary semiconductor, isolate supports or insulator.
7. preparation method as claimed in claim 4, is characterized in that, step 5) described in heterogeneous semiconductor layer energy state density lower than 1E18cm
-3.
8. preparation method as claimed in claim 4, is characterized in that, step 5) described in heterogeneous semiconductor layer material be selected from the II-VI with lower state density, the binary of III-V and IV-IV race or ternary semiconductor.
9. preparation method as claimed in claim 4, is characterized in that, step 6) described in gate dielectric material be selected from SiO
2, Si
3n
4or high-K gate dielectric material.
10. preparation method as claimed in claim 4, is characterized in that, step 6) described in the method for deposit gate dielectric material be selected from one of following method: chemical vapor deposition or physical vapor deposition.
11. preparation methods as claimed in claim 4, is characterized in that, step 6) described in grid material be selected from doped polycrystalline silicon, metallic cobalt, nickel and other metals or metal silicide.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104810405A (en) * | 2015-04-13 | 2015-07-29 | 北京大学 | Tunneling field effect transistor and preparation method |
| KR20160149419A (en) * | 2015-06-18 | 2016-12-28 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
| WO2018090301A1 (en) * | 2016-11-17 | 2018-05-24 | 华为技术有限公司 | Tunnel field effect transistor, and manufacturing method thereof |
| CN109065615A (en) * | 2018-06-12 | 2018-12-21 | 西安电子科技大学 | A kind of heterogeneous tunneling field-effect transistor of novel planar InAs/Si and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110729355B (en) * | 2019-10-23 | 2021-04-27 | 电子科技大学 | Longitudinal tunneling field effect transistor for improving sub-threshold swing amplitude |
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