WO2021227311A1

WO2021227311A1 - Transistor and method for fabricating the same

Info

Publication number: WO2021227311A1
Application number: PCT/CN2020/113547
Authority: WO
Inventors: Haitao Xu; Ningfei GAO; Xiaodong Du
Original assignee: Beijing Hua Tan Yuan Xin Electronics Technology Co., Ltd.
Priority date: 2020-05-11
Filing date: 2020-09-04
Publication date: 2021-11-18
Also published as: CN113644113B; CN113644113A

Abstract

Disclosed are a transistor and a method for fabricating a transistor. The transistor includes a base; a narrow-bandgap material layer, a gate dielectric layer and a gate provided on the base in sequence, in which the narrow-bandgap material layer has a channel region, and a boss is provided in a layer on a surface of the narrow-bandgap material layer away from the base and at the channel region; a source and a drain provided on and in contact with the surface of the narrow-bandgap material layer away from the base, in which atleast the drain covers the boss and the source and the drain are each made of a metal material.

Description

TRANSISTOR AND METHOD FOR FABRICATING THE SAME

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and benefits of Chinese Patent Application Serial No. 202010393423. X, filed with the National Intellectual Property Administration of P.R. China on May 11, 2010, the entire content of which is incorporated herein by reference.

FIELD

The present disclosure relates to a field of semiconductor technology, in particularly to a transistor and a method for fabricating a transistor.

BACKGROUND

Carbon nanotubes are ideal channel materials for transistors, with excellent physical and chemical characteristics such as one-dimensional nanostructure, ultra-thin thickness, high mobility, perfect lattice, high physical and chemical stability, and high thermal conductivity. Transistors with channels made of carbon nanotubes have significant advantages in extreme performance and energy utilization efficiency over traditional transistors. In a transistor, a gate controls distribution of carriers in a channel between a source and a drain, and thus controls, in combination with the applied source-drain voltage, the channel to be switched on or switched off.

However, a transistor with a channel made of carbon nanotubes and a method for fabricating the transistor still need to be improved.

SUMMARY

The present disclosure is based on discoveries and recognitions of the following facts and issues.

Existing transistors using carbon nanotubes as channel materials have problems such as large off-state leakage current, short lifetime, and low reliability. It is found by the inventors of the present disclosure that these problems of the existing transistors are caused due to a relatively drastic energy band bending near the drain (refer to a schematic diagram showing an energy band of a CNT-PMOS device in an off state as shown in Fig. 2) under an operating voltage between the source and the drain and a gate voltage. Specifically, for the existing transistors, high-k dielectric materials are usually used for a gate dielectric layer to improve gate control. However, it also brings about the problem that the energy band near the drain changes drastically, that is, when the transistor is turned on, the energy band near the drain side is bended, in favor of carriers in the channel to have higher energy when they approach the drain. High-speed carriers collide with the gate dielectric layer and the base near the drain side, resulting in charge injection, or the carriers collide with the drain to generate a large amount of heat. With accumulation of running time, the gate dielectric layer and the base near the drain side are damaged, and migration happens to metal materials of the drain, thus deteriorating drain structure and reducing the lifetime of the device. Since carbon nanotubes are used as narrow-bandgap materials, dramatic bending in the energy band makes Schottky barrier at the drain side thinner when the transistor is in the off state. At a high bias voltage, reverse tunneling may easily happen to the carriers at the drain side, resulting in a larger off-state leakage current and increasing power consumption of the transistor.

Embodiments of the present disclosure seek to solve at least one of the problems existing in the related art to at least some extent.

In an aspect, the present disclosure provides in embodiments a transistor. The transistor includes a base; a narrow-bandgap material layer, a gate dielectric layer and a gate provided on the base in sequence, wherein the narrow-bandgap material layer has a channel region, and a boss is provided in a layer on a surface of the narrow-bandgap material layer away from the base and at the channel region; a source and a drain provided on and in contact with the surface of the narrow-bandgap material layer away from the base, wherein at least the drain covers the boss and the source and the drain are each made of a metal material. When the transistor is in an on state, the energy band at the drain side changes gently, which avoids significant acceleration of the carriers caused by excessive band bending, thus reducing impact of the carriers on the gate dielectric layer, the base at the drain side and on the drain, and reducing thermal migration of the drain and damage to the gate dielectric layer and the base. In this way, the transistor is more reliable and the lifetime is increased. When the transistor is in the off state, the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor.

In some embodiments, a ratio of a length of the boss at an end of the layer to a length of the gate is in a range of 0.01 to 2. Therefore, the energy band at the drain side may be well-adjusted without significant increase in contact resistance at source and drain sides.

In some embodiments, a material for the narrow-bandgap material layer includes at least one of carbon nanotubes, nanowires, and two-dimensional materials. Therefore, the above-mentioned material is suitable for the channel material of the transistor, and thus provides the transistor with excellent performance.

In some embodiments, the transistor further includes a spacer covering a sidewall of the gate, wherein orthographic projections of the spacer and the gate on the base are within an orthographic projection of the gate dielectric layer on the base, and a part of the gate dielectric layer that is uncovered by the spacer and the gate forms the boss. Therefore, when the transistor is in the on state or the off state, the channel region below the boss can be electrostatically controlled by a part where the drain cover the boss, thus realizing the adjustment of the energy band and alleviating the excessive band bending at the drain side. The spacer may be provided to achieve the insulation between the source/drain and the gate.

In some embodiments, an orthographic projection of the gate on the base is within an orthographic projection of the gate dielectric layer on the base, and the transistor includes a spacer covering a surface of the gate away from the base and a sidewall of the gate and extending along the gate dielectric layer to form the boss. Therefore, when the transistor is in the on state or the off state, the channel region below the boss can be electrostatically controlled by a part where the drain cover the boss, thus realizing the adjustment of the energy band and alleviating the excessive band bending at the drain side. The spacer may be provided to achieve the insulation between the source/drain and the gate. Moreover, the spacer may be provided to isolate the gate from air, to realize passivation protection for the gate.

In some embodiments, an extension part of the spacer has a fixed charge or a dipole, or an interface between the extension part of the spacer and the gate dielectric layer has a dipole. Therefore, the channel region below the boss can be electrostatically controlled by the fixed charge or the dipole of the extension part of the spacer, or by the dipole at the interface between the extension part of the spacer and the gate dielectric layer, thus realizing the adjustment of the energy band and alleviating the excessive band bending at the drain side.

In some embodiments, an orthographic projection of the gate on the base coincides with an orthographic projection of the gate dielectric layer on the base, and the transistor includes a spacer covering a sidewall of the gate and a sidewall of the gate dielectric layer and extending away from the gate dielectric layer to form the boss. Therefore, when the transistor is in the on state or the off state, the channel region below the boss can be electrostatically controlled by a part where the drain cover the boss, thus realizing the adjustment of the energy band and alleviating the excessive band bending at the drain side. The spacer may be provided to achieve the insulation between the source/drain and the gate.

In some embodiment, an extension part of the spacer has a fixed charge or a dipole. Therefore, the channel region below the boss can be electrostatically controlled by the fixed charge or the dipole of the extension part of the spacer, thus realizing the adjustment of the energy band and alleviating the excessive band bending at the drain side.

In some embodiment, the gate dielectric layer has a U-shaped structure, the gate is disposed in a receiving space formed by the U-shaped structure, and the transistor includes a protective structure in contact with the narrow-bandgap material layer and the gate dielectric layer to form the boss. Therefore, when the transistor is in the on state or the off state, the channel region below the boss can be electrostatically controlled by a part where the drain cover the boss, thus realizing the adjustment of the energy band and alleviating the excessive band bending at the drain side. The spacer may be provided to achieve the insulation between the source/drain and the gate.

In some embodiment, the protective structure has a fixed charge or a dipole. Therefore, the channel region below the boss can be electrostatically controlled by the fixed charge or the dipole of the protective structure, thus realizing the adjustment of the energy band and alleviating the excessive band bending at the drain side.

In some embodiment, a material for the protective structure is chemically etched to form a pattern. Therefore, during the fabrication of the transistor, when the material is chemically etched to form the protective structure, the narrow-bandgap material layer will not be damaged or polluted, and impurities and molecules adsorbed on the surface of the narrow-bandgap material layer can be removed to improve the performance of the narrow-bandgap material layer.

In some embodiments, a material for the protective structure includes at least one of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide and aluminum oxide. Therefore, during the fabrication of the transistor, the above material is chemically etched to form the protective structure, which not only can prevent the narrow-bandgap material layer from being damaged and polluted, but also can remove impurities and molecules adsorbed on the surface of the narrow-bandgap material layer, so as to improve the performance of the narrow-bandgap material layer. Silicon oxide has a low dielectric constant, and thus the protective structure made of silicon oxide can avoid dramatic bending in the energy band at the drain side and further alleviate excessive bending of the energy band.

In some embodiments, a dielectric layer is provided between a sidewall of the gate dielectric layer and a sidewall of the gate, the dielectric layer is made of a low-K dielectric material including at least one of silicon oxide, silicon nitride and silicon oxynitride, thus reducing parasitic capacitance between the gate and the source/drain.

In some embodiments, the gate dielectric layer is made of a high-K dielectric material including at least one of Al ₂O ₃, HfO ₂, ZrO ₂, TiO ₂, HfO _xN _y, LaO _xN _y, Y ₂O ₃ and La ₂O ₃, where 1 ≤ x/y ≤ 5, preferably 1.5 ≤ x/y ≤ 2, more preferably 1.6 ≤ x/y ≤ 1.8. Therefore, the transistor can have improved gate control, and based on the improved gate control, the energy band can be adjusted by using the structure described above to alleviate excessive bending of the energy band at the drain side.

In some embodiments, the spacer is made of an insulating dielectric material. In this way, insulation between the source/drain and the gate can be achieved.

In some embodiments, the spacer is made of a high-K dielectric material including at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide. In a case that the spacer extends to form the boss made of the high-K dielectric material, it is in favor of the electrostatically control of the channel region below the boss by the drain metal, thus realizing the adjustment of the energy band and alleviating the excessive band bending at the drain side.

In some embodiments, the spacer is made of a low-K dielectric material including at least one of silicon oxide, silicon nitride and silicon oxynitride. Therefore, the spacer has a low dielectric constant, which can reduce the parasitic capacitance between the source/drain and the gate. In a case that the spacer extends to form the boss made of the low-K dielectric material, the gate control of the channel region below the boss can be reduced, thus further alleviating excessive bending of the energy band at the drain side.

In another aspect, the present disclosure provides in embodiments a method for fabricating a transistor, including: providing a narrow-bandgap material layer, a gate dielectric layer and a gate in sequence on a base, wherein the narrow-bandgap material layer has a channel region, and a boss is provided in a layer on a surface of the narrow-bandgap material layer away from the base and at the channel region, and providing a source and a drain on and in contact with the surface of the narrow-bandgap material layer away from the base, wherein at least the drain covers the boss, and the source and the drain are made of a metal material, respectively. When the transistor fabricated by the above method is in an on state, the energy band at the drain side changes gently, which avoids significant acceleration of the carriers caused by excessive band bending, thus reducing impact of the carriers on the drain, the gate dielectric layer and the base at the drain, and reducing thermal migration of the drain and damage such as charge injection to the gate dielectric layer and the base. In this way, the transistor is more reliable and the lifetime is increased. When the transistor fabricated by the above method is in the off state, the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor.

In some embodiments, the boss is formed by: depositing a gate dielectric material layer on the surface of the narrow-bandgap material layer away from the base, and providing the gate and a spacer covering a sidewall of the gate on a surface of the gate dielectric material layer away from the base, chemically etching the gate dielectric material layer to form the gate dielectric layer in such a way that orthographic projections of the spacer and the gate on the base are within an orthographic projection of the gate dielectric layer on the base, and forming the boss by a part of the gate dielectric layer that is uncovered by the spacer and the gate. Therefore, the part of the gate dielectric layer may be formed as the boss through a simple method, and the channel region under the boss can be electrostatically controlled by a part where the drain covers the boss, so as to realize the adjustment of the energy band and reduce the excessive band bending. Moreover, the spacer may be provided to realize the insulation between the source/drain and the gate.

In some embodiments, before depositing the gate dielectric material layer on the surface of the narrow-bandgap material layer away from the base, the method further includes: depositing a protective material layer on the surface of the narrow-bandgap material layer away from the base, and chemically etching the protective material layer to expose the channel region. After the gate dielectric layer is formed, the method further includes: removing the protective material layer. Therefore, by arranging the protective material layer, the material for the gate dielectric layer may be selected from a wider range.

In some embodiments, after the spacer is provided, the method further includes: depositing a dielectric material layer on the gate dielectric material layer, the spacer and the gate, and patterning the dielectric material layer to expose a sidewall of the spacer and a part of the gate dielectric material layer, and chemically etching the exposed part of the gate dielectric material layer to expose a part of the narrow-bandgap material layer and to form the gate dielectric layer, and forming the boss by a part of the gate dielectric layer that is uncovered by the spacer and the gate. Therefore, the dielectric material layer is provided to facilitate the formation of the source and the drain.

In some embodiments, the boss is formed by: depositing a gate dielectric material layer on the surface of the narrow-bandgap material layer away from the base, and depositing a first photoresist layer and a second photoresist layer on a surface of the gate dielectric material layer away from the base in sequence, exposing and developing the second photoresist layer and the first photoresist layer to expose a part of the gate dielectric material layer in such a way that a length of an opening of the first photoresist layer is greater than a length of an opening of the second photoresist layer in an extension direction of the first photoresist layer, providing the gate on the exposed part of the gate dielectric material layer in such a way that an orthographic projection of the gate on the base is within an orthographic projection of the opening of the second photoresist layer on the base, a length of the gate is the same as the length of the opening of the second photoresist layer in an extension direction of the second photoresist layer, and a height of the first photoresist layer is greater than a height of the gate, depositing a spacer material layer on a surface and a sidewall of the second photoresist layer, a sidewall of the first photoresist layer, the surface of the gate dielectric material layer, and a surface and a sidewall of the gate, wherein a first part of the spacer material layer covering the sidewall of the first photoresist layer is spaced apart by a clearance from a second part of the spacer material layer covering the sidewall of the gate, and peeling off the first photoresist layer and the second photoresist layer to form the spacer in such a way that an extension part of the spacer below the clearance remains and forms the boss. Therefore, the spacer covering the gate and extending along the gate dielectric material layer to both sides can be synchronously formed by the self-alignment process, thus simplifying the operations and reducing the cost. The boss is formed by the extension part of the spacer, the channel region under the boss can be electrostatically controlled by a part where the drain covers the boss, so as to realize the adjustment of the energy band and reduce the excessive band bending at the drain side. Moreover, the spacer may be provided to realize the insulation between the source/drain and the gate.

In some embodiments, the extension part of the spacer has a fixed charge or a dipole, or an interface between the extension part of the spacer and the gate dielectric layer has a dipole. Therefore, the channel region below the boss can be electrostatically controlled by the fixed charge or the dipole of the extension part of the spacer, or by the dipole of the interface between the extension part of the spacer and the gate dielectric layer, thus realizing the adjustment of the energy band and further alleviating the excessive band bending at the drain side.

In some embodiments, the boss is formed by: depositing a gate dielectric material layer on the surface of the narrow-bandgap material layer away from the base, providing the gate on a surface of the gate dielectric material layer away from the base, and chemically etching the gate dielectric material layer to form the gate dielectric layer in such a way that an orthographic projection of the gate dielectric layer on the base coincides with an orthographic projection of the gate on the base, and depositing a spacer material layer on the gate and the narrow-bandgap material layer, chemically etching the spacer material layer to form the spacer in such a way that the spacer covers sidewalls of the gate and the gate dielectric layer and extends away from the sidewall of the gate dielectric layer, and forming the boss by an extension part of the spacer. Therefore, the part of the spacer may be formed as the boss through a simple method, and the channel region under the boss can be electrostatically controlled by a part where the drain covers the boss, so as to realize the adjustment of the energy band and reduce the excessive band bending. Moreover, the spacer may be provided to realize the insulation between the source/drain and the gate.

In some embodiments, the extension part of the spacer has a fixed charge or a dipole. Therefore, the channel region below the boss can be electrostatically controlled by the fixed charge or the dipole of the extension part of the spacer, thus realizing the adjustment of the energy band and further alleviating the excessive band bending at the drain side.

In some embodiments, the boss is formed by: depositing a protective material layer and a dielectric material layer in sequence on the surface of the narrow-bandgap material layer away from the base, patterning the dielectric material layer and chemically etching the protective material layer, to form a notch through the dielectric material layer and the protective material layer, depositing a gate dielectric material layer and a gate material layer in the notch and on a surface of the dielectric material layer away from the base, patterning the gate dielectric material layer and the gate material layer in sequence to form the gate dielectric layer and the gate, wherein the gate dielectric layer has a U-shaped structure, and the gate is disposed in a receiving space formed by the U-shaped structure, and patterning the dielectric material layer to expose the sidewall of the gate dielectric layer and a part of the protective material layer, chemically etching the exposed part of the protective material layer to form a protective structure in contact with the narrow-bandgap material layer and the gate dielectric layer, respectively, and forming the boss by the protective structure. Therefore, the protective structure may be provided by a simple method. The protective structure is used to form the boss, and the channel region below the boss is electrostatically controlled by a part where the drain covers the boss, thus adjusting the energy band and alleviating excessive band bending at the drain side.

In some embodiments, the protective structure has a fixed charge or a dipole. Therefore, the channel region below the boss can be electrostatically controlled by the fixed charge or the dipole of the protective structure, thus realizing the adjustment of the energy band and further alleviating the excessive band bending at the drain side.

In some embodiments, the protective material layer is chemically etched with a reactive solution or a reactive gas. Therefore, when the protective material layer is etched, the lattice structure of the narrow-bandgap material will not be destroyed and the narrow-bandgap material layer will not be damaged or polluted.

In some embodiments, the reactive solution includes an acidic solution or an alkaline solution. Therefore, the protective material layer can be patterned by the reaction of the protective material with the acidic solution or the alkaline solution. Moreover, the lattice structure of the narrow-bandgap material will not be destroyed and the narrow-bandgap material layer will not be damaged or polluted in the reaction.

In some embodiments, the acidic solution includes at least one selected from hydrochloric acid, acetic acid, nitric acid, phosphoric acid and sulphuric acid. Therefore, a portion of the protective material layer may be removed by the reaction of the protective material with the above acidic solution. Moreover, the lattice structure of the narrow-bandgap material will not be destroyed and the narrow-bandgap material layer will not be damaged or polluted.

In some embodiments, the alkaline solution includes at least one selected from potassium hydroxide, sodium hydroxide and tetramethylammonium hydroxide. Therefore, a portion of the protective material layer may be removed by the reaction of the protective material with the above alkaline solution. Moreover, the lattice structure of the narrow-bandgap material will not be destroyed and the narrow-bandgap material layer will not be damaged or polluted.

In some embodiments, the reactive gas includes at least one selected from hydrogen chloride and hydrogen fluoride. Therefore, a portion of the protective material layer may be removed by the reaction of the protective material with the above reactive gas, and the lattice structure of the narrow-bandgap material will not be destroyed.

In some embodiments, a material for the protective material layer includes at least one selected from yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide, and aluminum oxide. Therefore, the protective material layer can prevent the narrow-bandgap material layer from being damaged and polluted when the first and second photoresist layers are exposed and developed. When the protective material layer is etched, the lattice structure of the narrow-bandgap material will not be damaged, the narrow-bandgap material layer will not be damaged or polluted, and impurities and molecules adsorbed on the surface of the narrow-bandgap material layer can be removed to improve the performance of the narrow-bandgap material layer.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects and advantages of embodiments of the present disclosure will become apparent and more readily appreciated from the following descriptions made with reference to the drawings, in which:

Fig. 1 is a schematic cross-sectional view of a transistor according to an embodiment of the present disclosure;

Fig. 2 is a schematic diagram showing an energy band of a traditional transistor in an off state;

Fig. 3 is a schematic diagram showing an energy band of a transistor in an off state according to an embodiment of the present disclosure;

Fig. 4 is a schematic cross-sectional view of a transistor according to another embodiment of the present disclosure;

Fig. 5 is a schematic cross-sectional view of a transistor according to still another embodiment of the present disclosure;

Fig. 6 is a schematic cross-sectional view of a transistor according to a further another embodiment of the present disclosure;

Fig. 7 is a flow chart of operations of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 8 is a process diagram of a part of operations of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 9 is a process diagram of a part of operations of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 10 is a process diagram of a part of operations of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 11 is a process diagram of a part of operations of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 12 is a process diagram of a part of operations of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 13 is a process diagram of a part of operations of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 14 is a process diagram of a part of operations of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 15 is a process diagram of a part of operations of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 16 is a process diagram of a part of operations of a method for fabricating a transistor according to an embodiment of the present disclosure;

Fig. 17 is a schematic cross-sectional view of a transistor of Comparative Example 1;

Fig. 18 is a graph showing a transfer characteristic curve of a transistor of Example 1; and

Fig. 19 is a graph showing a transfer characteristic curve of a transistor of Comparative Example 1.

Reference numerals:

base 100, narrow-bandgap material layer 200, gate dielectric layer 300, gate 400, source 500, drain 600, spacer 700, protective structure 800, gate dielectric material layer 310, gate material layer 410, spacer material layer 710, protective material layer 810, dielectric material layer 910, boss 10, source/drain metal material layer 20, first photoresist layer 30, second photoresist layer 40.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be described in detail in the following descriptions, examples of which are shown in the accompanying drawings, in which the same or similar elements and elements having same or similar functions are denoted by like reference numerals throughout the descriptions. The embodiments described herein with reference to the accompanying drawings are explanatory and illustrative, which are used to generally understand the present disclosure. The embodiments shall not be construed to limit the present disclosure.

In an aspect, the present disclosure provides in embodiments a transistor. As shown in Figs. 1, 4, 5 and 6, the transistor includes a base 100, a narrow-bandgap material layer 200, a gate dielectric layer 300, a gate 400, a source 500 and a drain 600. Specifically, the narrow-bandgap material layer 200, the gate dielectric layer 300 and the gate 400 are provided on the base 100 in sequence, i.e., from bottom to top. The narrow-bandgap material layer 200 has a channel region, and a boss 10 is provided in a layer on a surface of the narrow-bandgap material layer 200 away from the base 100 and the boss 10 is provided at the channel region. The source 500 and the drain 600 are provided on and in contact with the surface of the narrow-bandgap material layer 200 away from the base 100. The source 500 is provided at a first side of the gate 400 and the drain 600 is provided at a second side of the gate 400. At least the drain 600 of the source 500 and the drain 600 covers the boss 10. The source 500 and the drain 600 are each made of a metal material. When the transistor is in the on state, the energy band at the drain side changes gently, which avoids significant acceleration of carriers caused by excessive band bending, thus reducing impact of the carriers on the gate dielectric layer 300, the base 100 at the drain side and on the drain 600, and reducing thermal migration of the drain 600 and damage to the gate dielectric layer 300 and the base 100. In this way, the transistor is more reliable and the lifetime is increased. When the transistor is in the off state, the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor.

With the transistor according to the embodiments of the present disclosure, the boss 10 is provided in the layer on a surface of the narrow-bandgap material layer 200 away from the base 100 and is covered by the drain 600. Therefore, the channel region below the boss 10 can be electrostatically controlled with the drain 600, thus realizing the adjustment of the energy band at the drain side. When the transistor is in the on state, significant acceleration of the carriers caused by excessive band bending can be alleviated, thus reducing impact of the carriers on the drain 600, the gate dielectric layer 300 and the base 100 at the drain side, and reducing thermal migration of the drain 600 and damage to the gate dielectric layer 300 and the base 100. In this way, the transistor is more reliable and the lifetime is increased. When the transistor is in the off state, the energy band at the drain side changes gently (indicated by a dotted line in Fig. 3) , such that the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor.

The source 500 and the drain 600 may be made of any suitable metal material. For example, palladium (Pd) or scandium (Sc) may be used, to allow the source 500 and the drain 600 to be in a P-type or N-type ohmic contact with the narrow-bandgap material layer 200.

In an embodiment of the present disclosure, in the present transistor, only the drain 600 covers the boss 10, that is, the boss 10 is formed at the second side of the gate 400. Alternatively, the boss 10 is formed at the first and second sides of the gate 400, respectively, that is, the drain 600 and the source 500 cover the boss 10, respectively. In this way, the transistor may have a symmetric structure, and maintain the high performance in the on state, thus facilitating subsequent circuit design.

As described above, it should be noted that the source 500 and drain 600 are respectively located on opposite sides of the gate 400. When the boss 10 is covered by both the source 500 and the drain 600, it means that the layer on the surface of the narrow-bandgap material layer 200 away from the base 100 provides one boss at the source side and the drain side respectively. The source 500 covers the boss 10 that is formed at the source side and the drain 600 covers the boss 10 that is formed at the drain side.

Each structure of the transistor according to embodiments of the present disclosure will be described in details below.

In some embodiments of the present disclosure, as shown in Fig. 1, the transistor further includes a spacer 700. The spacer 700 covers a sidewall of the gate 400. Orthographic projections of the spacer 700 and the gate 400 on the base 100 are within an orthographic projection of the gate dielectric layer 300 on the base 100, and a part of the gate dielectric layer 300 that is uncovered by the spacer 700 and the gate 400 forms the boss 100. In this way, the channel region below the boss 10 can be electrostatically controlled by the drain 600 covering the boss 10, thus realizing the adjustment of the energy band at the drain side. When the transistor is in the on state, excessive band bending can be alleviated. The transistor is more reliable and the lifetime is increased. When the transistor is in the off state, the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor. Moreover, the spacer 700 may be used to insulate the source 500 and the drain 600 from the gate 400. In an embodiment of the present disclosure, the spacer 700 further covers a surface of the gate 400 away from the base 100. Therefore, the gate 400 is isolated from air to realize passivation protection for the gate 400.

In some other embodiments of the present disclosure, as shown in Fig. 4, an orthographic projection of the gate 400 on the base 100 is within an orthographic projection of the gate dielectric layer 300 on the base 100. In this case, the transistor includes a spacer 700 covering a surface of the gate 400 away from the base 100 and a sidewall of the gate 400 and extending along the gate dielectric layer, i.e., to a periphery of the gate dielectric layer 300 to form the boss 10. In this way, the channel region below the boss 10 can be electrostatically controlled by the drain 600 covering the boss 10, thus realizing the adjustment of the energy band at the drain side. When the transistor is in the on state, excessive band bending can be alleviated. The transistor is more reliable and the lifetime is increased. When the transistor is in the off state, the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor. Moreover, the spacer 700 may be used to insulate the source 500 and the drain 600 from the gate 400, and the gate 400 is isolated from air to realize passivation protection for the gate 400. It should be noted that the spacer 700 extends to the periphery of the gate dielectric layer 300, and the extension part of the spacer and a part of the gate dielectric layer 300 that is below the extension part of the spacer 700 form the boss 10 together.

As shown in Fig. 4, in a further embodiment of the present disclosure, the extension part of the spacer 700 has a fixed charge or a dipole, or an interface between an extension part of the spacer 700 and the gate dielectric layer 300 has a dipole. Therefore, the channel region below the boss 10 can be electrostatically controlled by the fixed charge or the dipole of the extension part of the spacer 700, or by the dipole of the interface between the extension part of the spacer 700 and the gate dielectric layer 300, thus realizing the adjustment of the energy band and further alleviating the excessive band bending at the drain side. The extension part of the spacer 700 has the fixed charge. The extension part of the spacer 700 may be made of a material having a fixed charge. Alternatively, the spacer 700 is made of a material having a fixed charge, and thus is easy for preparation. The extension part of the spacer 700 has the dipole. The extension part of the spacer 700 is made of two materials and the dipole is provided at an interface between the two materials. Alternatively, the spacer 700 is made of two materials, which is easy for preparation, and the dipole is provided at an interface between the two materials. For example, first spacer material and second spacer material are sequentially deposited (e.g., by atomic layer deposition) , and the dipole is formed at the interface of the first spacer material and the second spacer material. Specific materials of the first and second spacer materials may be adjusted so that the extension part has the dipole. Alternatively, the dipole may be formed at the interface between the extension part of the spacer and the gate dielectric layer by adjusting materials of the extension part of the spacer and the gate dielectric layer.

In some other embodiments of the present disclosure, as shown in Fig. 5, an orthographic projection of the gate 400 on the base 100 coincides with an orthographic projection of the gate dielectric layer 300 on the base 100. In this case, the transistor includes a spacer 700 covering a sidewall of the gate 400 and a sidewall of the gate dielectric layer 300 and extending away from the gate dielectric layer 300, i.e., extending in a direction away from the gate dielectric layer 300 to form the boss 10. The extension part of the spacer 700 forms the boss 10. In this way, the channel region below the boss 10 can be electrostatically controlled by the drain 600 covering the boss 10, thus realizing the adjustment of the energy band at the drain side. When the transistor is in the on state, excessive band bending can be alleviated. The transistor is more reliable and the lifetime is increased. When the transistor is in the off state, the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor. Moreover, the spacer 700 may be used to insulate the source 500 and the drain 600 from the gate 400. In an embodiment of the present disclosure, the spacer 700 further covers a surface of the gate 400 away from the base 100. Therefore, the gate 400 is isolated from air to realize passivation protection for the gate 400.

As shown in Fig. 5, in a further embodiment of the present disclosure, the extension part of the spacer 700 has a fixed charge or a dipole. Therefore, the channel region below the boss 10 can be electrostatically controlled by the fixed charge or the dipole of the extension part of the spacer 700, thus realizing the adjustment of the energy band and further alleviating the excessive band bending at the drain side. The extension part of the spacer 700 has the fixed charge. The extension part of the spacer 700 may be made of a material having a fixed charge. Alternatively, the spacer 700 is made of a material having a fixed charge, and thus is easy for preparation. For example, the material for the spacer 700 may have the fixed charge by adjustment of process parameters. The extension part of the spacer 700 has the dipole. The extension part of the spacer 700 is made of two materials and the dipole is provided at an interface between the two materials. Alternatively, the spacer 700 is made of two materials, which is easy for preparation, and the dipole is provided at an interface between the two materials. For example, first spacer material and second spacer material are sequentially deposited (e.g., by atomic layer deposition) , and the dipole is formed at the interface of the first spacer material and the second spacer material. Specific materials of the first and second spacer materials may be adjusted so that the extension part has the dipole. The transistor may be a P-type transistor or an N-type transistor. The channel region of the P-type transistor below the boss 10 can be doped with holes by the fixed charge or the dipole, and the channel region of the N-type transistor below the boss 10 can be doped with electrons by the fixed charge or the dipole.

In some embodiments of the present disclosure, the spacer 700 is made of an insulating dielectric material, thus realizing the insulation between the source/drain and the gate. The spacer 700 may be made of any suitable high-K dielectric material or low-K dielectric material. For example, the high-K dielectric material includes at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide. For another example, the low-K dielectric material includes at least one of silicon oxide, silicon nitride and silicon oxynitride. As shown in Figs. 4 and 5, the boss 10 is formed by the extension part. When the boss is made of the high-K dielectric material, the channel region below the boss can be electrostatically controlled by the drain, thus realizing the adjustment of the energy band and further alleviating excessive band bending at the drain side. When the boss is made of the low-K dielectric material, the gate control of the channel region below the boss 10 can be reduced, and the excessive bending of the energy band at the drain side may be further alleviated. Moreover, the spacer made of the low-K dielectric material can reduce parasitic capacitance between the gate and the source/drain.

It should be noted that specific component (such as aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide) , structure and morphology of the spacer are not particularly limited herein as long as it has the fixed charge or the dipole, or the interface between the boss of the spacer and the gate dielectric layer has the dipole.

In some other embodiments of the present disclosure, as shown in Fig. 6, the gate dielectric layer 300 has a U-shaped structure, the gate 400 is disposed in a receiving space formed by the U-shaped structure. In this case, the transistor includes a protective structure 800 in contact with the narrow-bandgap material layer 200 and the gate dielectric layer 300 to form the boss 10. In this way, the channel region below the boss 10 can be electrostatically controlled by the drain 600 covering the boss 10, thus realizing the adjustment of the energy band at the drain side. When the transistor is in the on state, excessive band bending can be alleviated. The transistor is more reliable and the lifetime is increased. When the transistor is in the off state, the Schottky barrier at the drain side of the transistor becomes thicker, thus alleviating the reverse tunneling of the carriers, effectively reducing the off-state leakage current and reducing the power consumption of the transistor. In an embodiment, a dielectric layer (not shown in figures) is provided between a sidewall of the gate dielectric layer 300 and a sidewall of the gate 400, the dielectric layer is made of any suitable low-K dielectric material. The low-K dielectric material includes, but not limited to, silicon oxide, silicon nitride and silicon oxynitride. The dielectric layer can reduce parasitic capacitance between the gate and the source/drain.

Material for the protective structure is not particularly limited as long as it can be chemically etched to form a pattern. For example, the material for the protective structure includes at least one of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide and aluminum oxide. Therefore, during the fabrication of the transistor, the above material is chemically etched to form the protective structure, which not only can prevent the narrow-bandgap material layer from being damaged and polluted, but also can remove impurities and molecules adsorbed on the surface of the narrow-bandgap material layer, so as to improve the performance of the narrow-bandgap material layer. Silicon oxide has a low dielectric constant, and thus the protective structure made of silicon oxide can avoid dramatic bending in the energy band at the drain side and further alleviate excessive bending of the energy band. It should be noted that when the protective structure is made of silicon oxide, the silicon oxide may be formed on the narrow-bandgap material layer by the spin coating, which is easy to operate. Alternatively, the silicon oxide can be formed on the narrow-bandgap material layer by the thermal deposition without negatively affecting the performance of the narrow-bandgap material layer.

In an embodiment of the present disclosure, the protective structure has a fixed charge or a dipole. In this way, the channel region below the protective structure can be electrostatically controlled by the fixed charge or the dipole, to adjust the energy band and further alleviate the excessive bending of the energy band. The fixed charge or the dipole of the protective structure is formed in same or similar way to the formation of the fixed charge or the dipole of the extension part of the spacer, and thus is not described in detail again.

In some embodiments of the present disclosure, the gate dielectric layer 300 is made of a high-K dielectric material. The high-K dielectric material includes metal oxides which may be incorporated with Si or N. The high-K dielectric material may include at least one of Al ₂O ₃, HfO ₂, ZrO ₂, TiO ₂, HfO _xN _y, LaO _xN _y, Y ₂O ₃ and La ₂O ₃, where 1 ≤ x/y ≤ 5, preferably 1.5 ≤ x/y ≤ 2, more preferably 1.6 ≤ x/y ≤ 1.8. Therefore, the transistor can have improved gate control, and based on the improved gate control, the energy band can be adjusted by using the structure described above to alleviate excessive bending of the energy band at the drain side.

The base of the transistor may be made of any suitable composition or material, which can be selected by those skilled in the art. For example, the base 100 may include a silicon substrate and a silicon oxide layer, a glass layer, a polymer layer or other electrically-insulating layer disposed on the silicon substrate.

In some embodiments of the present disclosure, a ratio of a length (L ₁ as shown in Fig. 1) of the boss at an end of the layer to a length (L ₂ as shown in Fig. 1) of the gate is in a range of 0.01 to 2, e.g., 0.01, 0.05, 0.1, 0.3, 0.5, 0.8, 1, 1.2, 1.5, 1.8 and 2. It has been found that when the length of the boss meets the above requirement, a good control of the energy band at the drain side may be realized, the excessive bending of the energy band can be effectively alleviated, and the length of the boss will not be too long which results in significant increase in contact resistance at source and drain sides. It should be noted that the above ratio refers to a ratio of the length of the boss at one end to the length of the gate. When the layer forms another boss at the source side, a ratio of a length of the boss at the source side to the length of the gate may also be in a range of 0.01 to 2.

In an embodiment of the present disclosure, a material for the narrow-bandgap material layer includes at least one of carbon nanotubes, nanowires, and two-dimensional materials. Specifically, the carbon nanotube may be a single carbon nanotube, a network carbon nanotube array or an oriented carbon nanotube array, and the two-dimensional materials may include layered narrow-bandgap materials, e.g., black phosphorus or molybdenum disulfide. Therefore, the transistor with the channel made of the above materials has excellent performances.

In another aspect, the present application provides in embodiments a method for fabricating a transistor. In some embodiments, the transistor prepared the present method may be the transistor described above. Therefore, features and advantages of the transistor described in the above embodiments may also applicable to the transistor prepared by the present method, which are not described in detail again here.

As shown in Fig. 7, the method of the present disclosure includes the following operations.

In S100, a narrow-bandgap material layer, a gate dielectric layer and a gate are provided in sequence on a base. The narrow-bandgap material layer has a channel region, and a boss is provided in a layer on a surface of the narrow-bandgap material layer away from the base and at the channel region.

In this operation, the narrow-bandgap material layer, the gate dielectric layer and the gate are formed on the base from bottom to top, and the layer on the surface of the narrow-bandgap material layer away from the base forms the boss at the channel region. Details of the base, the narrow-bandgap material layer, the gate dielectric layer may refer to the embodiments of the transistor described above.

In some embodiments of the present disclosure, as shown in Figs. 8 and 9, the boss may be provided by the following operations.

A gate dielectric material layer 310 is deposited on the surface of the narrow-bandgap material layer 200 away from the base 100, and the gate 400 and a spacer 700 covering a sidewall of the gate 400 are provided on a surface of the gate dielectric material layer 310 away from the base 100. The gate 400 may be formed by photolithography and etching processes. Alternatively, the gate 400 may be formed by photolithography and peeling processes. The gate 400 may be formed by any suitable method known in the art. After forming the gate 400 (as shown in Fig. 8 (a) ) , a spacer material layer 710 is deposited on the sidewall of the gate 400 and the gate dielectric material layer 310 away from the base 100 (as shown in Fig. 8 (b) ) . The spacer material layer 710 is patterned to form the spacer 700 (as shown in Fig. 8 (c) ) . The spacer material layer 710 may deposited, e.g., by atomic layer deposition or chemical vapor deposition, preferably by the atomic layer deposition, such that spacer material may be deposited on the surface and the sidewall of the gate 400 and on the surface of the gate dielectric material layer 310. If material of channel region layer is exposed, it should be avoided to apply plasma process, for example, oxygen plasma process should to generate the spacer material layer. Method for patterning the spacer material layer may be a reactive ion etching (RIE) method.

The gate dielectric material layer 310 is chemically etched to form the gate dielectric layer 300, such that orthographic projections of the gate 400 and the spacer 700 on the base 100 are within an orthographic projection of the gate dielectric layer 300 on the base 100. A part of the gate dielectric layer 300 that is uncovered by the spacer 700 and the gate 400 forms the boss 10 (as shown in Fig. 9 (d) ) . Therefore, the part of the gate dielectric layer 300 may be formed as the boss 10 through a simple method, and the channel region under the boss 10 can be electrostatically controlled by a part where the drain 600 covers the boss 10, so as to realize the adjustment of the energy band and reduce the excessive band bending.

In some embodiments of the present disclosure, a material for the gate dielectric material layer may include at least one of yttrium oxide, lanthanum oxide and aluminum oxide. Therefore, during the fabricating process, the gate dielectric material layer can protect the narrow-bandgap material layer, and the gate dielectric material layer formed of the above material can be patterned by chemical etching without damaging the narrow-bandgap material layer at the channel region. Moreover, impurities and molecules adsorbed on the surface of the narrow-bandgap material layer can be removed, so as to improve the performance of the narrow-bandgap material layer. Further, the above-mentioned material has a high dielectric constant, such that the transistor may have a high gate control capability. In this way, the gate dielectric material layer is used as a protective layer for the narrow-bandgap material layer and also used to form the gate dielectric layer.

In some embodiments of the present disclosure, when the material for the gate dielectric material layer include at least one of yttrium oxide, lanthanum oxide and aluminum oxide, the gate dielectric material layer is chemically etched by etching the protective material layer with a reactive solution or a reactive gas, and washing with water. The reactive solution includes an acidic solution or an alkaline solution. For example, the acidic solution includes at least one of hydrochloric acid, acetic acid, nitric acid, phosphoric acid, and sulfuric acid. The alkaline solution includes at least one of potassium hydroxide, sodium hydroxide and tetramethylammonium hydroxide. The reactive gas may be any suitable gas. For example, the reactive gas includes at least one of hydrogen chloride and hydrogen fluoride. Therefore, the gate dielectric material layer may be reacted with the reactive solution or the reactive gas to remove a part of the gate dielectric material layer, thus forming the gate dielectric layer with the boss without damaging a lattice structure of the narrow-bandgap material layer.

In an embodiment of the present disclosure, during the provision of the boss as described above, before depositing the gate dielectric material layer on the surface of the narrow-bandgap material layer away from the base, a protective material layer may be deposited on the surface of the narrow-bandgap material layer away from the base. The protective material layer is chemically etched to remove a part of the protective material layer, so as to remove impurity ions adsorbed on the surface of the narrow-bandgap material layer, thus improving the performance of the narrow-bandgap material layer. Further, the gate dielectric material layer is deposited on the cleaned surface of the narrow-bandgap material layer that is cleaned to form the gate dielectric layer.

In an embodiment of the present disclosure, during the provision of the boss 10 as described above, before depositing the gate dielectric material layer 310 on the surface of the narrow-bandgap material layer 200 away from the base 100, a protective material layer 810 is deposited on the surface of the narrow-bandgap material layer 200 away from the base 100 (as shown in Fig. 10 (g) ) , and the protective material layer 810 is chemically etched to expose the channel region. After this, the gate dielectric material layer 310 is deposited (as shown in Fig. 10 (h) ) . After the gate dielectric layer 300 is formed, the protective material layer 810 is removed. By arranging the protective material layer, the material for the gate dielectric layer may be selected from a wider range. For example, any one of Al ₂O ₃, HfO ₂, ZrO ₂, TiO ₂, HfO _xN _y, LaO _xN _y, Y ₂O ₃, La ₂O ₃ and any combination thereof can be used to form the gate dielectric layer. By removing the protective material layer at the channel region, impurities and molecules adsorbed on the surface of the narrow-bandgap material layer at the channel region can be removed, thus improving the performance of the narrow-bandgap material layer.

Material for the protective material layer is not particularly limited, as long as it can be patterned by a non-destructive etching method (such as wet etching or vapor etching) . For example, the material for the protective material layer may include at least one of yttrium oxide, lanthanum oxide, scandium oxide and silicon oxide. Therefore, the protective material layer can prevent the narrow-bandgap material layer from being damaged and polluted, and impurities and molecules adsorbed on the surface of the narrow-bandgap material layer can be removed. The protective material layer may be chemically etched with a reactive solution or a reactive gas in a same or similar way that the gate dielectric material layer made of at least one of yttrium oxide, lanthanum oxide and aluminium oxide is chemically etched, and thus will not be described in detail again. It should be noted that if the protective material layer is made of silicon oxide, the silicon oxide may be formed on the narrow-bandgap material layer by the spin coating, which is easy to operate. Alternatively, silicon oxide can be formed on the narrow-bandgap material layer by the thermal deposition without negatively affecting the performance of the narrow-bandgap material layer.

In an embodiment of the present disclosure, during the provision of the boss 10 as described above, after the spacer 700 is formed, a dielectric material layer 910 is deposited on the gate dielectric material layer 310, the spacer 700 and the gate 400 at their surfaces away from the base 100 (as shown in Fig. 11 (i) ) . The dielectric material layer 910 is patterned to expose a sidewall of the spacer 700 and a part of the gate dielectric material layer 310 (as shown in Fig. 11 (j) ) . The exposed part of the gate dielectric material layer 310 is chemically etched to expose a part of the narrow-bandgap material layer 200 and to form the gate dielectric layer 300. A part of the gate dielectric layer 300 that is uncovered by the spacer 700 and the gate 400 forms the boss (as shown in Fig. 11 (k) ) . Therefore, the arrangement of the dielectric material layer may benefit the provision of the source and the drain.

In some other embodiments of the present disclosure, as shown in Figs. 12 and 13, the boss may be provided by the following operations.

A gate dielectric material layer 310 is deposited on the surface of the narrow-bandgap material layer 200 away from the base 100, and a first photoresist layer 30 and a second photoresist layer 40 are deposited in sequence on the surface of the gate dielectric material layer 310 away from the base 100 (as shown in Fig. 12 (a) ) .

The second photoresist layer 40 and the first photoresist layer 30 are exposed and developed to expose a part of the gate dielectric material layer 310 in such a way that a length of an opening of the first photoresist layer 30 is greater than a length of an opening of the second photoresist layer 40 in an extension direction of the first photoresist layer 30 (as shown in Fig. 12 (b) ) . Specific materials and formation methods of the first photoresist layer 30 and the second photoresist layer 40 are not particularly limited, as long as the length of the opening of the first photoresist layer 30 is greater than the length of the opening of the second photoresist layer 40. For example, under an illumination condition, the second photoresist layer 40 changes, but the first photoresist layer 30 does not change. In this case, the properties of the second photoresist layer 40 are changed by the exposure, and the second photoresist layer 40 is developed by a corresponding developer to form the opening in the layer. Then, a developer that reacts with the first photoresist layer 30 is selected and used to form the opening in the first photoresist layer to allow the length of the opening of the first photoresist layer 30 to be greater than the length of the opening in the second photoresist layer 40. Alternatively, both the first photoresist layer 30 and the second photoresist layer 40 are changed by the illumination condition, and are respectively developed with different developers, to allow the length of the opening of the first photoresist layer 30 to be greater than the length of the opening of the second photoresist layer 40. Alternatively, both the first photoresist layer 30 and the second photoresist layer 40 are changed by the illumination condition. The same developer is used for both layers, and development periods of the first photoresist layer 30 and the second photoresist layer 40 are controlled so that the length of the opening of the first photoresist layer 30 is greater than that of the second photoresist layer 40. Alternatively, electron beam lithography is applied. The first photoresist layer 30 is made of a material that is more sensitive to electron beam lithography, so that the length of the opening of the first photoresist layer 30 is greater than the length of the opening of the second photoresist layer 40.

The gate 400 is formed on the part of the gate dielectric material layer 310 that is exposed. An orthographic projection of the gate 400 on the base 100 is within an orthographic projection of the opening of the second photoresist layer 40 on the base 100. A length of the gate 400 is the same as the length of the opening of the second photoresist layer 40 in an extension direction of the second photoresist layer 40, and a height of the first photoresist layer 30 is greater than that of the gate 400 (as shown in Fig. 12 (c) ) . A method for forming the gate 400 may be electron beam evaporation coating or magnetic sputtering. These methods may provide a high collimation and is convenient for forming the gate on the exposed part of the gate dielectric material layer. The orthographic projection of the gate on the base is within the orthographic projection of the opening of the second photoresist layer on the base, and the height of the first photoresist layer is greater than the height of the gate, such that sufficient space can be reserved for the subsequent provision of the spacer.

A spacer material layer 710 is deposited on a surface and a sidewall of the second photoresist layer 40, a sidewall of the first photoresist layer 30, the surface of the gate dielectric material layer 310, and a surface and a sidewall of the gate 400. Specifically, a first part of the spacer material layer 710 covering the sidewall of the first photoresist layer 30 is spaced apart by a clearance from a second part of the spacer material layer 710 covering the sidewall of the gate 400 (as shown in Fig. 13 (d) ) . The spacer material layer 710 may be formed by atomic layer deposition.

The first photoresist layer 30 and the second photoresist layer 40 are peeled off to form the spacer 700 in such a way that a part of the spacer 700 below the clearance remains and forms the boss 10 (as shown in Fig. 13 (e) ) . Therefore, the spacer 700 covering the gate 400 and extending along the gate dielectric material layer 310 can be synchronously formed by the self-alignment process, thus simplifying the operations and reducing the cost. The boss is formed by the extension part of the spacer 700, the channel region under the boss 10 can be electrostatically controlled by the drain 600 covering the boss 10, so as to realize the adjustment of the energy band and reduce the excessive band bending at the drain side.

In an embodiment of the present disclosure, the extension part of the spacer has a fixed charge or a dipole, or an interface between an extension part of the spacer and the gate dielectric layer has a dipole. Therefore, the channel region below the boss can be electrostatically controlled by the fixed charge or the dipole of the extension part of the spacer, or by the dipole of the interface between the extension part of the spacer and the gate dielectric layer, thus realizing the adjustment of the energy band and further alleviating the excessive band bending at the drain side. The extension part of the spacer has the fixed charge. The extension part of the spacer may be made of a material having a fixed charge. Alternatively, the spacer is made of a material having a fixed charge, and thus is easy for preparation. The extension part of the spacer has the dipole. The extension part of the spacer is made of two materials and the dipole is provided at an interface between the two materials. Alternatively, the spacer is made of two materials, which is easy for preparation, and the dipole is provided at an interface between the two materials. For example, first spacer material and second spacer material are sequentially deposited (e.g., by atomic layer deposition) , and the dipole is formed at the interface of the first spacer material and the second spacer material. Specific materials of the first and second spacer materials may be adjusted so that the extension part has the dipole. Alternatively, the dipole may be formed at the interface between the extension part of the spacer and the gate dielectric layer by adjusting materials of the extension part of the spacer and the gate dielectric layer.

In some other embodiments of the present disclosure, as shown in Fig. 14, the boss may be provided by the following operations.

A gate dielectric material layer 310 is deposited on the surface of the narrow-bandgap material layer 200 away from the base 100, and the gate 400 is provided on a surface of the gate dielectric material layer 310 away from the base 100. The gate dielectric material layer 310 is chemically etched to form the gate dielectric layer 300 in such a way that an orthographic projection of the gate dielectric layer 300 on the base 100 coincides with an orthographic projection of the gate 400 on the base 100 (as shown in Fig. 14 (a) ) . During the formation of the gate dielectric layer, the gate can be used as a hard mask, thus omitting a provision of a mask.

A spacer material layer 710 is deposited on the gate 400 and the narrow-bandgap material layer 200 away from the base 100 (as shown in Fig. 14 (b) ) , and the spacer material layer 710 is chemically etched to form the spacer 700 in such a way that the spacer 700 covers sidewalls of the gate 400 and the gate dielectric layer 300 and extends along the narrow-bandgap material layer 200, i.e., away from the sidewall of the gate dielectric layer 300. The extension part of the spacer 700 forms the boss (as shown in Fig. 14 (c) ) . Therefore, the part of the spacer may be formed as the boss through a simple method, and the channel region under the boss can be electrostatically controlled by a part where the drain covers the boss, so as to realize the adjustment of the energy band and reduce the excessive band bending. Moreover, the spacer is formed by chemical etching, which will not damage the narrow-bandgap material layer.

In an embodiment of the present disclosure, the extension part of the spacer has a fixed charge or a dipole. Therefore, the channel region below the boss can be electrostatically controlled by the fixed charge or the dipole of the extension part of the spacer, thus realizing the adjustment of the energy band and further alleviating the excessive band bending at the drain side. The extension part of the spacer has the fixed charge. The extension part of the spacer may be made of a material having a fixed charge. Alternatively, the spacer is made of a material having a fixed charge, and thus is easy for preparation. The extension part of the spacer has the dipole. The extension part of the spacer is made of two materials and the dipole is provided at an interface between the two materials. Alternatively, the spacer is made of two materials, which is easy for preparation, and the dipole is provided at an interface between the two materials. For example, first spacer material and second spacer material are sequentially deposited (e.g., by atomic layer deposition) , and the dipole is formed at the interface of the first spacer material and the second spacer material. Specific materials of the first and second spacer materials may be adjusted so that the extension part has the dipole.

In some embodiments of the present disclosure, the spacer is made of an insulating dielectric material, thus realizing the insulation between the source/drain and the gate. The spacer may be made of any suitable high-K dielectric material or low-K dielectric material. For example, the high-K dielectric material includes at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide. For another example, the low-K dielectric material includes at least one of silicon oxide, silicon nitride and silicon oxynitride. The boss is formed by the extension part of the spacer. When the boss is made of the high-K dielectric material, the channel region below the boss can be electrostatically controlled by the drain metal, thus realizing the adjustment of the energy band and further alleviating excessive band bending at the drain side. When the boss is made of the low-K dielectric material, the gate control of the channel region below the boss can be reduced, and the excessive bending of the energy band at the drain side may be further alleviated. Moreover, the spacer made of the low-K dielectric material can reduce parasitic capacitance between the gate and the source/drain.

In an embodiment of the present disclosure, when the spacer is made of the high-K dielectric material, the high-K dielectric material may be deposited by thermal atomic layer deposition, and when the spacer is made of the low-K dielectric material, the low-K dielectric material may be deposited by atomic layer deposition.

In some other embodiments of the present disclosure, as shown in Figs. 15 and 16, the boss may be provided by the following operations.

A protective material layer 810 and a dielectric material layer 910 are deposited in sequence on the surface of the narrow-bandgap material layer 200 away from the base 100 (as shown in Fig. 15 (a) ) . The dielectric material layer 910 is patterned and the protective material layer 810 is chemically etched, to form a notch through the dielectric material layer 910 and the protective material layer 810 (as shown in Fig. 15(b) ) .

A gate dielectric material layer 310 and a gate material layer 410 are deposited in the notch and on a surface of the dielectric material layer 910 away from the base 100 (as shown in Fig. 15 (c) ) . The gate dielectric material layer 310 and the gate material layer 410 are patterned in sequence to form the gate dielectric layer 300 and the gate 400, respectively. The gate dielectric layer 300 has a U-shaped structure, and the gate 400 is disposed in a receiving space formed by the U-shaped structure (as shown in Fig. 16 (d) ) . Material of the protective material layer and chemical etching process may refer to the above embodiments of the protective material layer, which are not described in detail again. The gate dielectric material layer and the gate material layer can be formed by atomic layer deposition. In this operation, after the gate dielectric material layer is deposited and before the gate material layer is deposited, a dielectric material layer may be deposited, and the dielectric material layer may be patterned to form a dielectric layer so that the dielectric layer covers a sidewall of the gate dielectric material layer. After this, the gate material layer is deposited. The dielectric material layer may be made of any suitable low-K dielectric material. For example, the low-K dielectric material includes, but is not limited to, at least one of silicon oxide, silicon nitride and silicon oxynitride. Therefore, the parasitic capacitance between the source/drain and the gate can be reduced. The dielectric material layer may be provided by atomic layer deposition.

The dielectric material layer 910 is patterned to expose the sidewall of the gate dielectric layer 300 and a part of the protective material layer 810 (as shown in Fig. 16 (e) ) . An exposed part of the protective material layer 810 is chemically etched to form a protective structure 800 respectively in contact with the narrow-bandgap material layer 200 and the gate dielectric layer 300, and the protective structure 800 forms the boss (as shown in Fig. 16 (f) ) . Therefore, the protective structure may be provided by a simple method. The protective structure is used to form the boss, and the channel region below the boss is electrostatically controlled by a part where the drain covers the boss, thus adjusting the energy band and alleviating excessive band bending at the drain side.

In an embodiment of the present disclosure, the protective structure 800 has a fixed charge or a dipole. Therefore, the channel region below the protective structure can be electrostatically controlled by the fixed charge or the dipole of the protective structure, thus realizing the adjustment of the energy band and further alleviating the excessive band bending. Details of the fixed charge and the dipole of the protective structure may refer to the embodiments of the extension part of the spacer as described above.

In an embodiment of the present disclosure, a ratio of a length of the boss at an end of the layer to a length of the gate is in a range of 0.01 to 2. Therefore, the energy band at the drain side may be well-adjusted without significant increase in contact resistance at source and drain sides. It should be noted that a ratio of a length of the boss at the drain side to the length of the gate is in a range of 0.01 to 2 and a ratio of a length of the boss at the source side to the length of the gate is in a range of 0.01 to 2.

In S200, a source and a drain are provided on and in contact with the surface of the narrow-bandgap material layer away from the base. At least the drain covers the boss and the source and the drain are each made of a metal material.

In some embodiments of the present disclosure, the source and drain are located on the surface of the narrow-bandgap material layer away from the base, and both are in contact with the narrow-bandgap material layer. At least the drain of the source and drain covers the boss. The source and drain are each made of a metal material. As a result, the metal drain can be used to realize electrostatic control on the channel region below the boss, so as to adjust the energy band at the drain side and alleviate excessive band bending at the drain side. The metal materials for the source and drain have been described in detail above, and will not be described here again.

In some embodiments of the present disclosure, as shown in Fig. 9, a metal material is deposited on the narrow-bandgap material layer 200, the gate dielectric layer 300, the spacer 700 and the gate 400 (as shown in Fig. 9 (e) ) . The metal material layer 20 is patterned to form the source 500 and the drain 600 (as shown in Fig. 9 (f) ) . The metal material layer may be deposited by atomic layer deposition or physical vapor deposition. The metal material layer may be patterned by an etching process or a chemical mechanical polishing (CMP) process.

In some other embodiments of the present disclosure, as shown in Fig. 11, after the dielectric material layer 910 is patterned and the gate dielectric material layer 310 is chemically etched, the source and drain are deposited on the exposed part of the narrow-bandgap material layer 200. The source 500 and the drain 600 may be formed by an etching process or a chemical mechanical polishing process (as shown in Fig. 11 (l) ) .

In some other embodiments of the present disclosure, as shown in Fig. 13, after the first photoresist layer 30 and the second photoresist layer 40 are peeled off, the gate dielectric material layer 310 is chemically etched to expose a part of the narrow-bandgap material layer 200, and the metal material is deposited by electron beam evaporation coating or magnetron sputtering to form the source 500 and the drain 600 (as shown in Fig. 13 (f) ) .

In some other embodiments of the present disclosure, as shown in Fig. 16, after the protective structure 800 is formed, the metal material is deposited on the exposed part of the narrow-bandgap material layer 200, and the source 500 and the drain 600 are formed through an etching process or a chemical mechanical polishing process (as shown in Fig. 13 (g) ) .

The present disclosure is further described with the following examples.

Example 1

As shown in Fig. 4, a transistor includes a base 100, and a narrow-bandgap material layer 200, a gate dielectric layer 300 and a gate 400 provided on the base 100 in sequence. Orthographic projection of the gate 400 on the base 100 is within an orthographic projection of the gate dielectric layer 300 on the base 100. The spacer 700 covers a surface and a sidewall of the gate 400 and extends to a periphery of the gate dielectric layer 300, and the extension part of the spacer 700 forms a boss 10. A source 500 and a drain 600 are located on a surface of the narrow-bandgap material layer 200 away from the base 100, and both are in contact with the narrow-bandgap material layer 200. The source 500 and the drain 600 cover the boss 10, respectively. The gate dielectric layer 300 is made of yttrium oxide and the narrow-bandgap material layer 200 is made of carbon nanotube.

The source 500 and the drain 600 are made of Pd to constitute a P-type transistor (PMOS) . In the PMOS, an interface between the extension part of the spacer and the gate dielectric layer has a dipole. The source 500 and the drain 600 are made of Sc to constitute an N-type transistor (NMOS) . In the NMOS, the extension part of the spacer has a fixed charge and an interface between the extension part of the spacer and the gate dielectric layer has a dipole.

Comparative Example 1

As shown in Fig. 17, a transistor includes a base 100, a narrow-bandgap material layer 200 disposed on the base 100, a source 500 and a drain 600 disposed on a surface of the narrow-bandgap material layer 200 away from the base 100, a gate dielectric layer 300 covering a part of the source 500, a part of the narrow-bandgap material layer 200 between the source 500 and the drain 600 and a part of the drain 600, and a gate 400 covering the gate dielectric layer 300. The gate dielectric layer 300 is made of HfO ₂, and the narrow-bandgap material layer 200 is made of carbon nanotubes.

The source 500 and the drain 600 are made of Pd to constitute a P-type transistor (PMOS) . The source 500 and the drain 600 are made of Sc to constitute an N-type transistor (NMOS) .

The transistor is fabricated as follows.

First, a layer of carbon nanotubes is formed on the base. Subsequently, a polymethyl methacrylate (PMMA) layer is provided on a surface of the layer of carbon nanotubes away from the base, and the PMMA layer is patterned to form grooves arranged at clearances. Subsequently, source and drain metals are deposited in the grooves, and the source and drain metals are patterned to form the source and the drain in the grooves, and the PMMA layer is removed. After this, a PMMA structure is formed at a side of the source away from the drain and at a side of the drain away from the source. The PMMA structure at the source side covers a part of the source and the PMMA structure at the drain side covers a part of the drain. Subsequently, HfO ₂ is deposited on the PMMA structure, the source, the drain and the layer of carbon nanotubes at a surface away from the base to form a continuous layer of gate dielectric material, and the gate metal is deposited on a surface of the HfO ₂ layer away from the base. Finally, the PMMA structure is removed, and the HfO ₂ layer along the side of the PMMA structure is simultaneously removed, thus fabricating the transistor.

Performance tests are performed on the transistors of Example 1 and Comparative Example 1, respectively. Figs. 18 and 19 show transfer characteristic curves of the two transistors to indicate switching characteristics of the two transistors under the gate voltage. Fig. 18 is a graph showing the transfer characteristic curve of the transistor of Example 1, and Fig. 19 is a graph showing the transfer characteristic curve of the transistor of Comparative Example 1.

It can be seen from Figs. 18 and 19 that compared with the transistor of Comparative Example 1 (i.e., a traditional high-K gate dielectric self-aligned carbon nanotube transistor) , the transistor of Example 1 has a significantly lower off-state current and a higher switch ratio, and at the same time has a more suitable threshold voltage.

It should be noted that in Figs. 18 and 19, I _ds represents a current between the source and the drain, V _ds represents a voltage between the source and the drain, V _gs represents a voltage between the gate and the source, and L/W represents a ratio of a length of the gate to a width of the channel region.

In the present disclosure, unless specified or limited otherwise, a structure in which a first feature is “on” or “below” a second feature may include an embodiment in which the first feature is in direct contact with the second feature, and may also include an embodiment in which the first feature and the second feature are not in direct contact with each other, but are contacted via an additional feature formed therebetween. Furthermore, a first feature “on, ” “above, ” or “on top of” a second feature may include an embodiment in which the first feature is right or obliquely “on, ” “above, ” or “on top of” the second feature, or just means that the first feature is at a height higher than that of the second feature; while a first feature “below, ” “under, ” or “on bottom of” a second feature may include an embodiment in which the first feature is right or obliquely “below, ” “under, ” or “on bottom of” the second feature, or just means that the first feature is at a height lower than that of the second feature.

Reference throughout this specification to “an embodiment, ” “some embodiments, ” “one embodiment” , “another example, ” “an example, ” “a specific example, ” or “some examples, ” means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. Thus, the appearances of the phrases such as “in some embodiments, ” “in one embodiment” , “in an embodiment” , “in another example, ” “in an example, ” “in a specific example, ” or “in some examples, ” in various places throughout this specification are not necessarily referring to the same embodiment or example of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. Although explanatory embodiments have been shown and described, it would be appreciated by those skilled in the art that changes, alternatives, and modifications may be made in the embodiments without departing from spirit and principles of the disclosure. In addition, it should be noted that terms such as “first” and “second” are used herein for purposes of description and are not intended to indicate or imply relative importance or significance.

Although explanatory embodiments have been shown and described, it would be appreciated by those skilled in the art that the above embodiments cannot be construed to limit the present disclosure, and changes, alternatives, and modifications can be made in the embodiments without departing from spirit, principles and scope of the present disclosure.

Claims

A transistor, comprising:

a base;

a narrow-bandgap material layer, a gate dielectric layer and a gate provided on the base in sequence, wherein the narrow-bandgap material layer has a channel region, and a boss is provided in a layer on a surface of the narrow-bandgap material layer away from the base and at the channel region;

a source and a drain provided on and in contact with the surface of the narrow-bandgap material layer away from the base, wherein at least the drain covers the boss and the source and the drain are each made of a metal material.
The transistor according to claim 1, wherein a ratio of a length of the boss at an end of the layer to a length of the gate is in a range of 0.01 to 2,

optionally, a material for the narrow-bandgap material layer comprises at least one of carbon nanotubes, nanowires, and two-dimensional materials.
The transistor according to claim 1 or 2, further comprising a spacer covering a sidewall of the gate, wherein orthographic projections of the spacer and the gate on the base are within an orthographic projection of the gate dielectric layer on the base, and a part of the gate dielectric layer that is uncovered by the spacer and the gate forms the boss.
The transistor according to claim 1 or 2, wherein an orthographic projection of the gate on the base is within an orthographic projection of the gate dielectric layer on the base, and the transistor comprises a spacer covering a surface of the gate away from the base and a sidewall of the gate and extending along the gate dielectric layer to form the boss,

optionally, an extension part of the spacer has a fixed charge or a dipole, or an interface between the extension part of the spacer and the gate dielectric layer has a dipole.
The transistor according to claim 1 or 2, wherein an orthographic projection of the gate on the base coincides with an orthographic projection of the gate dielectric layer on the base, and the transistor comprises a spacer covering a sidewall of the gate and a sidewall of the gate dielectric layer and extending away from the gate dielectric layer to form the boss,

optionally, an extension part of the spacer has a fixed charge or a dipole.
The transistor according to claim 1 or 2, wherein the gate dielectric layer has a U-shaped structure, the gate is disposed in a receiving space formed by the U-shaped structure, and the transistor comprises a protective structure in contact with the narrow-bandgap material layer and the gate dielectric layer to form the boss,

optionally, the protective structure has a fixed charge or a dipole.
The transistor according to claim 6, wherein a material for the protective structure is chemically etched to form a pattern,

optionally, the material for the protective structure comprises at least one of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide and aluminum oxide,

optionally, a dielectric layer is provided between a sidewall of the gate dielectric layer and a sidewall of the gate, the dielectric layer is made of a low-K dielectric material comprising at least one of silicon oxide, silicon nitride and silicon oxynitride.
The transistor according to any one of claims 1 to 7, wherein the gate dielectric layer is made of a high-K dielectric material comprising at least one of Al ₂O ₃, HfO ₂, ZrO ₂, TiO ₂, HfO _xN _y, LaO _xN _y, Y ₂O ₃ and La ₂O ₃, where 1 ≤ x/y ≤ 5, preferably 1.5 ≤ x/y ≤ 2, more preferably 1.6 ≤ x/y ≤ 1.8.
The transistor according to any one of claims 3 to 5, wherein the spacer is made of an insulating dielectric material,

optionally, the spacer is made of a high-K dielectric material comprising at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide,

optionally, the spacer is made of a low-K dielectric material comprising at least one of silicon oxide, silicon nitride and silicon oxynitride.
A method for fabricating a transistor, comprising:

providing a narrow-bandgap material layer, a gate dielectric layer and a gate in sequence on a base, wherein the narrow-bandgap material layer has a channel region, and a boss is provided in a layer on a surface of the narrow-bandgap material layer away from the base and at the channel region, and

providing a source and a drain on and in contact with the surface of the narrow-bandgap material layer away from the base, wherein at least the drain covers the boss, and the source and the drain are made of a metal material, respectively.
The method according to claim 10, wherein the boss is formed by:

depositing a gate dielectric material layer on the surface of the narrow-bandgap material layer away from the base, and providing the gate and a spacer covering a sidewall of the gate on a surface of the gate dielectric material layer away from the base,

chemically etching the gate dielectric material layer to form the gate dielectric layer in such a way that orthographic projections of the spacer and the gate on the base are within an orthographic projection of the gate dielectric layer on the base, and

forming the boss by a part of the gate dielectric layer that is uncovered by the spacer and the gate.
The method according to claim 11, wherein

before depositing the gate dielectric material layer on the surface of the narrow-bandgap material layer away from the base, the method further comprises:

depositing a protective material layer on the surface of the narrow-bandgap material layer away from the base, and

chemically etching the protective material layer to expose the channel region;

and

after the gate dielectric layer is formed, the method further comprises:

removing the protective material layer.
The method according to claim 11, wherein after the spacer is provided, the method further comprises:

depositing a dielectric material layer on the gate dielectric material layer, the spacer and the gate, and patterning the dielectric material layer to expose a sidewall of the spacer and a part of the gate dielectric material layer, and

chemically etching the exposed part of the gate dielectric material layer to expose a part of the narrow-bandgap material layer and to form the gate dielectric layer, and forming the boss by a part of the gate dielectric layer that is uncovered by the spacer and the gate.
The method of claim 10, wherein the boss is formed by:

depositing a gate dielectric material layer on the surface of the narrow-bandgap material layer away from the base, and depositing a first photoresist layer and a second photoresist layer on a surface of the gate dielectric material layer away from the base in sequence,

exposing and developing the second photoresist layer and the first photoresist layer to expose a part of the gate dielectric material layer in such a way that a length of an opening of the first photoresist layer is greater than a length of an opening of the second photoresist layer in an extension direction of the first photoresist layer,

providing the gate on the exposed part of the gate dielectric material layer in such a way that an orthographic projection of the gate on the base is within an orthographic projection of the opening of the second photoresist layer on the base, a length of the gate is the same as the length of the opening of the second photoresist layer in an extension direction of the second photoresist layer, and a height of the first photoresist layer is greater than a height of the gate,

depositing a spacer material layer on a surface and a sidewall of the second photoresist layer, a sidewall of the first photoresist layer, the surface of the gate dielectric material layer, and a surface and a sidewall of the gate, wherein a first part of the spacer material layer covering the sidewall of the first photoresist layer is spaced apart by a clearance from a second part of the spacer material layer covering the sidewall of the gate, and

peeling off the first photoresist layer and the second photoresist layer to form the spacer in such a way that an extension part of the spacer below the clearance remains and forms the boss;

optionally, the extension part of the spacer has a fixed charge or a dipole, or an interface between the extension part of the spacer and the gate dielectric layer has a dipole.
The method according to claim 10, wherein the boss the boss is formed by:

depositing a gate dielectric material layer on the surface of the narrow-bandgap material layer away from the base, providing the gate on a surface of the gate dielectric material layer away from the base, and chemically etching the gate dielectric material layer to form the gate dielectric layer in such a way that an orthographic projection of the gate dielectric layer on the base coincides with an orthographic projection of the gate on the base, and

depositing a spacer material layer on the gate and the narrow-bandgap material layer, chemically etching the spacer material layer to form the spacer in such a way that the spacer covers sidewalls of the gate and the gate dielectric layer and extends away from the sidewall of the gate dielectric layer, and forming the boss by an extension part of the spacer;

optionally, the extension part of the spacer has a fixed charge or a dipole.
The method according to claim 10, wherein the boss is formed by:

depositing a protective material layer and a dielectric material layer in sequence on the surface of the narrow-bandgap material layer away from the base, patterning the dielectric material layer and chemically etching the protective material layer, to form a notch through the dielectric material layer and the protective material layer,

depositing a gate dielectric material layer and a gate material layer in the notch and on a surface of the dielectric material layer away from the base, patterning the gate dielectric material layer and the gate material layer in sequence to form the gate dielectric layer and the gate, wherein the gate dielectric layer has a U-shaped structure, and the gate is disposed in a receiving space formed by the U-shaped structure, and

patterning the dielectric material layer to expose the sidewall of the gate dielectric layer and a part of the protective material layer, chemically etching the exposed part of the protective material layer to form a protective structure in contact with the narrow-bandgap material layer and the gate dielectric layer, respectively, and forming the boss by the protective structure;

optionally, the protective structure has a fixed charge or a dipole.
The method according to claim 12 or 16, wherein the protective material layer is chemically etched with a reactive solution or a reactive gas;

optionally, the reactive solution comprises an acidic solution or an alkaline solution;

optionally, the acidic solution comprises at least one of hydrochloric acid, acetic acid, nitric acid, phosphoric acid, and sulfuric acid;

optionally, the alkaline solution comprises at least one of potassium hydroxide, sodium hydroxide and tetramethylammonium hydroxide;

optionally, the reactive gas comprises at least one of hydrogen chloride and hydrogen fluoride;

optionally, a material for the protective material layer comprises at least one of yttrium oxide, lanthanum oxide, scandium oxide, silicon oxide and aluminum oxide.
The method according to any one of claims 10 to 17, wherein a ratio of a length of the boss at an end of the layer to a length of the gate is in a range of 0.01 to 2;

optionally, the spacer is made of an insulating dielectric material,

optionally, the spacer is made of a high-K dielectric material comprising at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, titanium oxide, hafnium oxynitride, lanthanum oxynitride, yttrium oxide and lanthanum oxide,

optionally, the spacer is made of a low-K dielectric material comprising at least one of silicon oxide, silicon nitride and silicon oxynitride.