CN110957349B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN110957349B CN110957349B CN201811132992.8A CN201811132992A CN110957349B CN 110957349 B CN110957349 B CN 110957349B CN 201811132992 A CN201811132992 A CN 201811132992A CN 110957349 B CN110957349 B CN 110957349B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims description 54
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims abstract description 16
- 239000000463 material Substances 0.000 claims description 23
- 125000006850 spacer group Chemical group 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 75
- 230000008569 process Effects 0.000 description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 238000002955 isolation Methods 0.000 description 12
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000001465 metallisation Methods 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- JMANVNJQNLATNU-UHFFFAOYSA-N oxalonitrile Chemical compound N#CC#N JMANVNJQNLATNU-UHFFFAOYSA-N 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- -1 silicon carbide nitride Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention provides a semiconductor device and a method of manufacturing the same. The device comprises a semiconductor substrate with a high-voltage well, a gate dielectric layer positioned on the semiconductor substrate, a T-shaped gate positioned on the gate dielectric layer, wherein the T-shaped gate is provided with a plurality of protruding structures extending beyond the neck part of the T-shaped gate, a dielectric neck part support arranged below the protruding structures of the T-shaped gate, an etching stop part arranged below the dielectric neck part support, a pair of drift regions arranged in the high-voltage well at two sides of the T-shaped gate, and a pair of source/drain regions positioned in the pair of drift regions. The semiconductor device can increase the breakdown voltage thereof.
Description
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a high voltage semiconductor device having an etch stop member.
Background
The high voltage semiconductor device technology is applicable to the field of high voltage and high power integrated circuits, and the term "high voltage" herein refers to a high breakdown voltage (breakdown voltage). Conventional high voltage semiconductor devices, such as Double Diffused Drain MOSFET (DDDMOS) and Lateral Diffused metal oxide semiconductor field effect transistor (LDMOS), are mainly used in device applications above or around 18V. The high voltage semiconductor device technology has advantages of cost effectiveness, and is easily compatible with other manufacturing processes, and has been widely used in the fields of display driver IC devices, power supplies, power management, communications, automotive electronics, or industrial control.
A double diffused drain metal oxide semiconductor field effect transistor (DDDMOS) has characteristics of a small size and a large output current, and is widely used in a switch regulator (switch regulator). The double diffusion drain is formed by two doped regions and is used for a source electrode or a drain electrode of the high-voltage metal oxide semiconductor field effect transistor.
Generally, when designing the DDDMOS, a low on-resistance (R) is a major consideration on ) And high breakdownVoltage (break down voltage, BV). In DDDMOS design, if the space (space) between the drain and the channel region is shortened (e.g., the drain is self-aligned to the gate spacer by a self-aligned process), the on-resistance of DDDMOS can be reduced. However, the breakdown voltage of DDDMOS decreases and leakage current increases.
Thus, while existing high voltage semiconductor devices are generally satisfactory for their intended purposes, they are not entirely satisfactory in all respects.
Disclosure of Invention
An embodiment of the present invention provides a semiconductor device, including: a semiconductor substrate having a high voltage well; a gate dielectric layer on the semiconductor substrate; a T-shaped gate overlying the gate dielectric layer, the T-shaped gate having a plurality of protrusions (overhangs) extending beyond a neck portion of the T-shaped gate; a dielectric neck support disposed below the plurality of protruding structures of the T-shaped gate; an etch stop member disposed below the dielectric neck support; a pair of drift regions disposed in the high voltage well on both sides of the T-shaped gate; and a pair of source/drain regions located within the drift region.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, including: providing a semiconductor substrate having a high voltage well; forming a gate dielectric layer on the substrate; forming a pair of drift regions in the high-voltage well; forming an etch stop layer on the gate dielectric layer; forming a dielectric neck support on the etch stop layer, wherein the etch stop layer serves as an etch stop point when the dielectric neck support is formed; forming a T-shaped gate on the gate dielectric layer, wherein the T-shaped gate has a plurality of protrusions (overhangs) extending beyond a neck portion of the T-shaped gate on the dielectric neck support; and forming a pair of source/drain regions in the drift region.
Drawings
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale and are merely illustrative. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to clearly illustrate the features of the present invention.
Fig. 1 to 3, 4A, 4B, 5 and 6 are cross-sectional views illustrating a method for manufacturing a high voltage semiconductor device according to an embodiment of the present invention.
FIG. 7A is a top view of a high voltage semiconductor device in accordance with one embodiment of the present invention.
FIG. 7B is a top view of a high voltage semiconductor device in accordance with another embodiment of the present invention.
Fig. 8A-8B are graphs illustrating the current-voltage relationship of the drain of the high voltage semiconductor device according to one embodiment of the present invention.
Reference numerals:
10-a high voltage semiconductor device;
100-a semiconductor substrate;
100 a-active region;
102-high voltage well region;
104-an isolation structure;
106-gate dielectric layer;
108-a drift region;
110-etching stop layer;
110 a-an etch stop feature;
112-dielectric support layer;
112a dielectric neck support;
120-T type grid;
120 b-horizontal parts;
120b' -protruding structures;
120 n-neck;
120 s-side wall;
122-sidewall spacers;
132-source/drain region;
134-top doped region;
d1-a first distance;
d2-a second distance;
d3 to a third distance;
d4 to a fourth distance;
e, edge;
s-distance;
w-width.
Detailed Description
The following disclosure provides many different embodiments, or examples, for illustrating different features of the invention. Specific examples of components and arrangements thereof are disclosed below to simplify the present disclosure. Of course, these specific examples are not intended to limit the present invention. For example, the following summary of the present specification describes forming a first feature over or on a second feature, i.e., embodiments in which the formed first and second features are in direct contact, and embodiments in which additional features may be formed between the first and second features, i.e., the first and second features are not in direct contact. In addition, various examples of the present disclosure may use repeated reference characters and/or words. These repeated symbols or words are provided for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the described configurations.
Also, spatially relative terms, such as "under 823030, below", "under", "over" and the like, may be used herein for convenience in describing the relationship of one element or component to another element(s) or component(s) in the figures. Spatially relative terms may encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to a different orientation (e.g., rotated 90 degrees or otherwise), the spatially relative adjectives used herein will also be interpreted in terms of the turned orientation.
The high-voltage semiconductor device and the method for manufacturing the same according to the embodiments of the present invention will be described below. It is to be understood, however, that the following examples are included merely for purposes of illustration and description of specific methods of making and using the embodiments of the present invention and are not intended to limit the scope of the invention. Those skilled in the art will readily appreciate that various modifications are possible within the scope of other embodiments. Moreover, although the method embodiments described below are described in a particular order, other method embodiments may be performed in another logical order and may include fewer or more steps than those discussed herein.
Embodiments of the present invention provide a high voltage semiconductor device, such as a double diffused drain metal oxide semiconductor field effect transistor (DDDMOS), that utilizes a dielectric neck support located below the edge of a T-shaped gate to increase the breakdown voltage of the high voltage semiconductor device. Therefore, when the space between the channel region and the drain is increased and the size of the high-voltage semiconductor device is reduced to improve the on-resistance and reduce the leakage current, the high-voltage semiconductor device still has proper or required breakdown voltage.
In addition, in some embodiments, the present invention utilizes an end Point Detection (end mode) etch process (also referred to as end Point mode etch) to form the dielectric neck support. Unlike the time mode (time mode) etching process for forming the dielectric neck support, the end-point mode etching process can control the thickness of the dielectric neck support more efficiently and precisely, and can expand the operation margin.
Fig. 1-6 are cross-sectional views of a process for forming the high voltage semiconductor device 10 of fig. 6 at various stages according to some embodiments of the present invention. Fig. 7A and 7B are top views illustrating a high voltage semiconductor device according to various embodiments of the present invention, and not all of the components are shown in fig. 7A and 7B for the sake of simplicity and clarity. Referring to fig. 1, a semiconductor substrate 100 having a high voltage well 102 and at least one isolation structure 104 is provided. The isolation structure 104 is used to define an active region 100a in the high voltage well 102 of the semiconductor substrate 100 and electrically isolate various device structures formed in and/or on the semiconductor substrate 100 in the active region. In one embodiment, the semiconductor substrate 100 may be a silicon substrate, a silicon germanium (SiGe) substrate, a compound semiconductor (compound semiconductor) substrate, a bulk semiconductor (bulk semiconductor) substrate, a Silicon On Insulator (SOI) substrate, or the like.
In some embodiments, the isolation structure 104 includes a Shallow Trench Isolation (STI) structure, a silicon interconnectA local oxidation of silicon (LOCOS) structure, other suitable isolation structure components, or combinations thereof. In some embodiments, the semiconductor substrate 100 may have a first conductivity type, such as P-type or N-type. Further, the high voltage well 102 has a first conductivity type. In one example, the high voltage well 102 is P-type and has a range of about 1.0 x 10 15 ions/cm 3 To about 1.0X 10 17 ions/cm 3 Doping concentration of, for example, about 5.0X 10 16 ions/cm 3 . In another example, the high voltage well 102 is N-type and ranges from about 1.0 x 10 15 ions/cm 3 To about 1.0X 10 17 ions/cm 3 Doping concentration of (2), e.g. about 6.0X 10 16 ions/cm 3 。
Referring to fig. 2, a gate dielectric layer 106 is formed on the high voltage well 102. In some embodiments, the gate dielectric layer 106 covers the entire active region 100a and extends over the isolation structure 104. The gate dielectric layer 106 may be or include silicon oxide (silicon nitride), silicon oxynitride (silicon oxynitride), high-k dielectric material (material having a dielectric constant greater than about 7.0), or any other suitable dielectric material, or combinations thereof. For example, the gate dielectric layer 106 may comprise silicon dioxide. In one embodiment, the gate dielectric layer 106 has a thickness in the range of about
To about->
Is measured. The gate dielectric layer 106 may be formed by thermal oxidation (CVD), chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), atomic Layer Deposition (ALD), and/or other suitable methods.
Next, with continued reference to fig. 2, a drift region 108 is formed in the high voltage well 102 corresponding to the active region 100a. In an embodiment, the depth of the drift region 108 is less than the depth of the isolation structure 104. The drift region 108 has a second conductivity type different from the first conductivity type. In one example, the first conductivity type can be P-type and the second conductivity type can be N-type. In another example, the first conductivity type can be N-type and the second conductivity type P-type. An implantation mask (not shown) may be formed on the high voltage well 102 by a photolithography process, and then ion implantation is performed to form the drift regions 108, and a channel region (not shown) is defined between the drift regions 108. Further, after the drift region 108 is formed, an annealing process, such as a Rapid Thermal Anneal (RTA), may be performed on the drift region 108 for a duration of about 5 seconds to about 20 seconds, such as about 10 seconds.
Referring to fig. 3, an etch stop layer (etch stop layer) 110 is formed to cover the gate dielectric layer 106, and a dielectric support layer 112 (also referred to as a dielectric layer 112) is formed on the etch stop layer 110, wherein the etch stop layer 110 and the dielectric layer 112 are formed as an etch stop member 110a and a dielectric neck support 112a, respectively, in the subsequent process (as shown in fig. 4A to 4B).
The etch stop layer 110 may serve as an etch endpoint mechanism to stop the etch process during the etch process, which is referred to as an end point detection (end point detection) etch process. Unlike the etching process in the time-limited mode, the end-point detection etching process can control the thickness of the dielectric neck support more efficiently and precisely, and can enlarge the window of the manufacturing process. Etch stop layer 110 may be formed of a material having a different etch selectivity from that of adjacent film layers or features, i.e., dielectric layer 112 and/or gate dielectric layer 106. In some embodiments, this etch stop layer 110 may comprise or may be a dielectric material, such as a nitrogen-containing material, a silicon-containing material, and/or a carbon-containing material. For example, the etch stop layer 110 may comprise or be silicon nitride (silicon nitride), silicon carbonitride (silicon carbide nitride), carbon nitride (carbon nitride), silicon oxynitride (silicon oxynitride), silicon oxycarbide (silicon carbide oxide), the like, or combinations thereof.
In other embodiments, the etch stop layer 110 may comprise or may be a conductive material or a semiconductor material, such as polysilicon (polysilicon). After the etch stop layer 110 is formed as the etch stop 110a, the etch stop 110a including a conductive material or a semiconductor material may operate as a field plate (field plate). The field plate can reconstruct the electric field intensity distribution condition of the channel, and can reduce the electric field peak value of the grid (close to the drain end) so as to improve the breakdown voltage. The etch stop layer 110 may be formed by a deposition process, electroplating, and/or other suitable methods, such as Chemical Vapor Deposition (CVD), physical vapor deposition (e.g., sputtering), atomic Layer Deposition (ALD), or other deposition methods.
In some embodiments, the dielectric layer 112 and the gate dielectric layer 106 comprise the same material, for example, both the dielectric layer 112 and the gate dielectric layer 106 may comprise silicon dioxide. In other embodiments, the dielectric layer 112 and the gate dielectric layer 106 may comprise different materials. For example, the gate dielectric layer 106 may comprise silicon dioxide, and the dielectric layer 112 may comprise silicon nitride, silicon oxynitride, or other high-k dielectric material (e.g., hfO) 2 、ZrO 2 、Al 2 O 3 Or TiO 2 2 Etc.). The dielectric layer 112 may be formed by a deposition method, such as Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD), or other deposition techniques. In a specific embodiment, the gate dielectric layer 106 is silicon dioxide. In a specific embodiment, the dielectric layer 112 is silicon dioxide. In a specific embodiment, the etch stop layer 110 is silicon nitride. In another specific embodiment, the etch stop layer 110 is polysilicon.
Referring to fig. 4A, the etch stop layer 110 and the dielectric layer 112 are respectively formed as an etch stop member 110a and a dielectric neck support 112a by using photolithography and etching processes. Generally, the photolithography process includes depositing a photoresist material (not shown), exposing and developing to remove a portion of the photoresist material. The residual photoresist material protects the underlying materials (e.g., the dielectric layer 112 and the etch stop layer 110) from subsequent processing steps (e.g., etching). In some embodiments, a photoresist layer (not shown) is formed overlying dielectric layer 112, and the photoresist is patterned by exposing the photoresist to light using an appropriate photomask. The exposed or unexposed portions of the photoresist may then be removed by development, depending on whether a positive or negative photoresist is used. The patterned photoresist may then be used to etch the dielectric layer 112 and the etch stop layer 110, thereby forming an etch stop feature 110a and a dielectric neck support 112a, respectively. The dielectric neck support 112a may reduce an electric field under an edge of a gate electrode (to be formed in a subsequent manufacturing process) and reduce a gate-drain capacitance, thereby improving a breakdown voltage of the high voltage semiconductor device and increasing a switching characteristic of the high voltage semiconductor device. In addition, the method of forming the dielectric neck support 112a by etching the dielectric layer 112 using the etch stop layer 110 as an etch end (i.e., the end mode etch process) has several advantages, for example, the use of the end mode etch process enables more efficient and precise control of the thickness of the dielectric neck support 112a and an expanded operating margin, unlike the use of a time mode etch process to form the dielectric neck support 112a. In some embodiments, the etch stop feature 110a comprising a conductive material or a semiconductor material may operate as a field plate (field plate) to further increase the breakdown voltage of the high voltage semiconductor device.
In one embodiment, the dielectric neck support 112a has a thickness of about
To/is>
The range of (1). In one embodiment, the etch stop 110a has a thickness that is approximately @>
To/is>
In (c) is used. The etching process may be a dry etching process or a wet etching process, such as reactive ion etching (reactive ion et)ch, RIE), neutral Beam Etching (NBE), similar manufacturing processes, or combinations thereof. The etch may be anisotropic. In one embodiment, the dielectric neck support 112a has a U-shaped top profile (as shown in fig. 7A), and the dielectric neck support 112a has a width W. In other embodiments, the dielectric neck support 112a has a top profile of a ring (loop) type (as shown in fig. 7B). Furthermore, in some embodiments, as shown in fig. 4A, the etch stop feature 110a and the dielectric neck support 112a may have the same dimensions. For example, the etch stop 110a and the dielectric neck support 112a may be formed simultaneously in a single etch step. In other embodiments, as shown in fig. 4B, the etch stop feature 110a and the dielectric neck support 112a may have different dimensions. For example, additional patterned photoresist may be formed by additional photolithography processes to form etch stop feature 110a and dielectric neck support 112a in two different etch steps, respectively.
Referring to fig. 5, a T-shaped gate 120 is formed on the gate dielectric layer 106. Next, sidewall spacers 122 are formed on two opposite sidewalls 120s of the T-gate 120. The T-shaped gate 120 includes a bar portion 120b and a neck portion 120n, wherein a portion of the bar portion 120b extending beyond the neck portion 120n is a protrusion structure 120b'. In one embodiment, as shown in fig. 7A and 7B, the dielectric neck support 112a having a U-shaped or ring-shaped top profile protrudes a first distance D1 from the sidewall 122a of the T-shaped gate 120, wherein the first distance D1 is greater than the width of the sidewall spacer 122. In addition, the dielectric neck support 112a extends from the sidewall 122a of the T-shaped gate 120 to a second distance D2 (i.e., the width of the protruding structure 120 b') below the T-shaped gate 120 that is greater than the first distance D1. Thus, the electric field below the edge of the T-Gate 120 and the Gate-Drain Capacitance (Cgd) are reduced by the dielectric neck support 112a having a U-shaped or ring-shaped top profile. Furthermore, from the top view, the portion of the dielectric neck support 112a perpendicular to the T-shaped gate 120 protrudes outward from an edge E of the active region 100a by a third distance D3. In addition, a fourth distance D4 extending from an edge E of the active region 100a to the active region 100a of the dielectric neck support 112a is less than the third distance D3.
In some embodiments, the T-gate 120 comprises polysilicon, a metal material, a metal silicide, other suitable conductive material, or a combination thereof. The T-gate 120 may be formed by a suitable deposition process (e.g., chemical vapor deposition, physical vapor deposition, metal-organic chemical vapor deposition (MOCVD)) and/or silicidation (silicidation) process, photolithography process, and etching process (e.g., dry etching process or wet etching process). The sidewall spacers 122 comprise a different material than the material used for the T-gate 120. In some embodiments, the sidewall spacers 122 comprise a dielectric material, such as silicon nitride (silicon nitride) or silicon oxynitride (silicon oxynitride). In one embodiment, after forming the T-gate 120, one or more layers (not shown) are formed by conformally depositing a dielectric material over the high voltage semiconductor device 10. Next, an anisotropic etching process is performed to remove a portion of the one or more layers to form the sidewall spacers 122.
Referring to fig. 6, source/drain regions 132 of the first conductivity type are formed in the corresponding drift regions 108, and a top doped region 134 is formed on top of the T-gate 120. In one embodiment, the source/drain region 132 has a doping concentration greater than the drift region 108, which is a double diffused drain region. Furthermore, the source/drain regions 132 and the top doped region 134 have the same conductivity type and the same doping concentration. In one embodiment, the source/drain regions 132 may be laterally spaced apart from the sidewall spacers 122 by a distance S (i.e., the source/drain regions 132 are not self-aligned to the sidewall spacers 122) to reduce leakage current of the high voltage semiconductor device 10. The distance S may range from about 0.15 microns to about 0.30 microns. In addition, the top doped region 134 can reduce the contact resistance of the T-shaped gate 120.
An implantation mask (not shown) may be formed over the high voltage well 102 using a photolithography process, followed by ion implantation to form the source/drain regions 132 and a top doped region 134 on top of the T-gate 120. After the formation of source/drain regions 132, a metallization layer (not shown) may be formed over the structure of fig. 6 using conventional metallization processes. Thus, the high voltage semiconductor device 10 is formed. In one embodiment, the metallization layer may include an inter-layer dielectric (ILD) layer and an interconnect structure within the ILD layer. In one embodiment, the interconnect structure comprises a metal electrode coupled to the source/drain regions 132 and the top doped region 134.
Fig. 8A/8B are current-voltage curves of the drains of the double-diffused drain mosfet with the N-type/P-type high voltage wells, respectively, according to an embodiment of the present invention. The dashed lines represent a double diffused drain mosfet without a field plate, an embodiment where the etch stop is a dielectric material, such as silicon nitride. The solid line represents a double diffused drain mosfet with a field plate, an embodiment where the etch stop is a conductive or semiconductor material, such as polysilicon. As can be seen from fig. 8A to 8B, the double-diffused drain mosfet with the field plate has a higher breakdown voltage than the double-diffused drain mosfet without the field plate, regardless of the double-diffused drain mosfet with the N-type/P-type high voltage well.
Referring to fig. 6, in the embodiment of the invention, the high voltage semiconductor device 10 includes a semiconductor substrate 100 having a high voltage well 102 and at least one isolation structure 104. The isolation structure 104 defines an active region 100a in the high voltage well 102 of the semiconductor substrate 100.
In the present embodiment, the high voltage semiconductor device 10 further includes a gate dielectric layer 106 disposed on the semiconductor substrate 100, and a T-shaped gate 120 disposed on the gate dielectric layer 106. In one embodiment, the gate dielectric layer 106 is disposed on the high voltage well 102, covering the entire active region 100a and extending over the isolation structure 104. In a particular embodiment, the gate dielectric layer 106 may include silicon dioxide. The T-shaped gate 120 includes a bar portion 120b and a neck portion 120n, wherein a portion of the bar portion 120b extending beyond the neck portion 120n is a protruding structure 120b', as shown in fig. 6. In one embodiment, the T-gate 120 may comprise polysilicon. In one embodiment, the T-gate 120 has a top doped region 134 to reduce the contact resistance of the T-gate 120.
In the present embodiment, the high voltage semiconductor device 10 further includes a dielectric neck support 112a disposed under the protrusion 120b 'of the T-shaped gate 120, wherein the dielectric neck support 112a extends beyond the edge of the protrusion 120b'. A dielectric neck support 112a is located on the high voltage well 102. The dielectric neck support 112a is a patterned dielectric layer that does not cover the entire active region 100a or extend over the isolation structure 104. As shown in fig. 7A and 7B, the dielectric neck support 112a at least partially surrounds the T-gate 120. In some embodiments, the dielectric neck support 112a can have a U-shaped top profile, and in other embodiments, the dielectric neck support 112a can have a ring-shaped top profile. In one embodiment, the dielectric neck support 112a and the gate dielectric layer 106 comprise the same material, such as silicon dioxide. In other embodiments, the dielectric neck support 112a and the gate dielectric layer 106 may comprise different materials.
In the present embodiment, the high voltage semiconductor device 10 further includes an etch stop member 110a disposed below the dielectric neck support 112a. In some embodiments, the etch stop feature 110a has the same dimensions as the dielectric neck support 112a, while in other embodiments, the etch stop feature 110a is wider than the width of the dielectric neck support 112a. In some embodiments, the etch stop feature 110a comprises a conductive or semiconductor material to act as a field plate. In a specific embodiment, the etch stop 110a is polysilicon.
In the present embodiment, the high voltage semiconductor device 10 further includes a pair of drift regions 108 disposed in the high voltage well 102 on both sides of the T-shaped gate 120, and a pair of source/drain regions 132 disposed in the drift regions 108.
In the present embodiment, the high voltage semiconductor device 10 further includes a sidewall spacer 122 covering the dielectric neck support 112a and extending along the protrusion 120b' of the T-gate 120, wherein the dielectric neck support 112a is wider than the sidewall spacer 122. In one embodiment, the source/drain regions 132 are laterally spaced apart from the sidewall spacers 122 by a distance S.
According to the above embodiments, the method of forming the dielectric neck support by etching the dielectric support layer using the etch stop layer as an etch end point (i.e., the end point mode etch process) in forming the high voltage semiconductor device having the U-shaped or ring-shaped dielectric layer has some advantages, for example, the thickness of the dielectric neck support can be more efficiently and precisely controlled and the operation margin can be enlarged using the end point mode etch process, unlike the method of forming the dielectric neck support by using the time mode etch process. In addition, the etching stop component comprising the conductive material or the semiconductor material can have the effect of a field plate, and the breakdown voltage of the device can be further improved. Therefore, in the design of the high-voltage semiconductor device, the source/drain region can be laterally separated from the side wall spacer by a distance so as to increase the distance between the channel region and the source/drain region and further reduce the leakage current of the high-voltage semiconductor device. Further, the on-resistance of the high-voltage semiconductor device can be reduced by reducing the planar size of the high-voltage semiconductor device.
The foregoing has outlined features of several embodiments of the present invention so that those skilled in the art may better understand the present invention. It should be appreciated by those skilled in the art that the present disclosure may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes and/or achieving the same advantages of the embodiments of the present invention. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (18)
1. A semiconductor device, comprising
A semiconductor substrate having a high voltage well;
a gate dielectric layer on the semiconductor substrate;
a T-gate on the gate dielectric layer, the T-gate having a plurality of protruding structures extending beyond a neck of the T-gate;
a dielectric neck support disposed below the plurality of protruding structures of the T-shaped gate;
an etch stop disposed below the dielectric neck support;
a pair of drift regions arranged in the high voltage wells at both sides of the T-shaped gate; and
a pair of source/drain regions located within the pair of drift regions;
the etch stop feature comprises a conductive or semiconductor material to act as a field plate.
2. The semiconductor device of claim 1, further comprising a sidewall spacer covering the dielectric neck support and extending along sidewalls of the plurality of protruding structures of the T-gate.
3. The semiconductor device of claim 2, wherein the sidewall spacer is laterally spaced a distance from the source/drain region.
4. The semiconductor device of claim 2, wherein the dielectric neck support is wider than a width of the sidewall spacer.
5. The semiconductor device of claim 1, wherein the dielectric neck support at least partially surrounds the T-shaped gate.
6. The semiconductor device of claim 5, wherein the dielectric neck support has a U-shaped top profile.
7. The semiconductor device of claim 5, wherein the dielectric neck support has a ring-shaped top view profile.
8. The semiconductor device of claim 1, wherein the dielectric neck support extends beyond edges of the plurality of protruding structures.
9. The semiconductor device of claim 1, wherein the etch stop feature is wider than a width of the dielectric neck support.
10. The semiconductor device according to claim 1, wherein the etch stopper is polysilicon.
11. A method for manufacturing a semiconductor device, comprising
Providing a semiconductor substrate having a high voltage well;
forming a gate dielectric layer on the semiconductor substrate;
forming a pair of drift regions in the high-voltage well;
forming an etch stop feature on the gate dielectric layer;
forming a dielectric neck support on the etch stop feature, wherein the etch stop feature serves as an etch endpoint when the dielectric neck support is formed;
forming a T-shaped gate on the gate dielectric layer, wherein the T-shaped gate has a plurality of protruding structures extending beyond a neck of the T-shaped gate on the dielectric neck support; and
forming a pair of source/drain regions in the drift region;
the etch stop feature comprises a conductive or semiconductor material to act as a field plate.
12. The method of claim 11, further comprising forming a sidewall spacer covering the dielectric neck support and extending along sidewalls of the plurality of protruding structures of the T-shaped gate.
13. The method of claim 12, wherein the dielectric neck support is wider than a width of the sidewall spacer.
14. The method of claim 11, wherein the dielectric neck support at least partially surrounds the T-gate.
15. The method of claim 11, wherein the dielectric neck support extends beyond edges of the plurality of protruding structures.
16. The method of manufacturing a semiconductor device according to claim 11, wherein the etch stop member is wider than a width of the dielectric neck support.
17. The method for manufacturing a semiconductor device according to claim 11, wherein the etching stopper is polysilicon.
18. The method of claim 11, wherein the T-gate has a top doped region, and the top doped region has the same conductivity type and the same doping concentration as the source/drain region.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5290720A (en) * | 1990-12-07 | 1994-03-01 | At&T Bell Laboratories | Transistor with inverse silicide T-gate structure |
| US6710416B1 (en) * | 2003-05-16 | 2004-03-23 | Agere Systems Inc. | Split-gate metal-oxide-semiconductor device |
| KR20070064859A (en) * | 2005-12-19 | 2007-06-22 | 매그나칩 반도체 유한회사 | Semiconductor device driving in high voltage and method for manufacturing the same |
| CN104979390A (en) * | 2014-04-04 | 2015-10-14 | 联华电子股份有限公司 | High voltage metal oxide semiconductor transistor and manufacturing method thereof |
| US9876069B1 (en) * | 2017-05-18 | 2018-01-23 | Vanguard International Semiconductor Corporation | High-voltage semiconductor device and method for manufacturing the same |
-
2018
- 2018-09-27 CN CN201811132992.8A patent/CN110957349B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5290720A (en) * | 1990-12-07 | 1994-03-01 | At&T Bell Laboratories | Transistor with inverse silicide T-gate structure |
| US6710416B1 (en) * | 2003-05-16 | 2004-03-23 | Agere Systems Inc. | Split-gate metal-oxide-semiconductor device |
| KR20070064859A (en) * | 2005-12-19 | 2007-06-22 | 매그나칩 반도체 유한회사 | Semiconductor device driving in high voltage and method for manufacturing the same |
| CN104979390A (en) * | 2014-04-04 | 2015-10-14 | 联华电子股份有限公司 | High voltage metal oxide semiconductor transistor and manufacturing method thereof |
| US9876069B1 (en) * | 2017-05-18 | 2018-01-23 | Vanguard International Semiconductor Corporation | High-voltage semiconductor device and method for manufacturing the same |
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