CN111933708B - Gallium nitride MIS-HEMT passivation design and preparation method thereof - Google Patents
Gallium nitride MIS-HEMT passivation design and preparation method thereof Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Abstract
The invention belongs to the technical field of semiconductor devices and discloses a passivation design and a preparation method of gallium nitride MIS-HEMT, wherein a passivation structure comprises a silicon-doped hafnium oxide HfSiO material and P-type CuO which are laminated twice. Preferably, the MIS-HEMT device adopts a groove gate structure; the gate dielectric is made of silicon-doped hafnium oxide material with high dielectric constant; the source and drain electrodes are prepared by a low-temperature gold-free contact process. According to the invention, through the key composition and specific structure of the passivation structure and the improvement of the gate dielectric material of the gallium nitride MIS-HEMT device, the passivation structure is constructed by using the high dielectric constant material (HfSiO) and the low dielectric constant P-type oxide material (CuO) which are laminated twice, and compared with the prior art, the passivation structure can realize better electrical performance.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a gallium nitride MIS-HEMT (High Electron Mobility Transistor HEMT comprising metal-insulator-semiconductor MIS), wherein MIS represents metal-insulator-semiconductor and HEMT represents High Electron Mobility Transistor) passivation design and a preparation method thereof, and the gallium nitride MIS-HEMT device with excellent electrical performance can be obtained.
Background
Since the advent of metal oxide semiconductor field effect transistors, silicon materials dominate the semiconductor industry, mainly due to the low cost of silicon semiconductors and the high quality native oxide layer on their surfaces. However, the narrow forbidden band width of silicon limits the development of silicon in the direction of power electronics, and the search for semiconductor materials with better performance is inevitable. Gallium nitride as third generation semiconductor has higher critical breakdown electric field (3.3MV/cm) and higher saturation velocity (2.7 × 10) than conventional silicon semiconductor7cm/s), wide forbidden band (3.4 eV). In addition, when gallium nitride is used as a power electronic device, a heterojunction structure is formed between the gallium nitride and AlGaN, and high mobility (2 multiplied by 10) can be generated at the interface3cm2V · s) 2DEG channel.
The current gallium nitride power device faces the following problems:
1. gallium nitride electronic devices in a conventional manner are depletion type devices, and the devices are turned on under zero bias, so that potential safety hazards exist in power electronic applications.
2. The ohmic contact of the gallium nitride device introduces gold and the annealing temperature is high, which is not compatible with the existing CMOS process. The search for low temperature, gold-free, low contact resistance ohmic contact processes is also the direction of current research.
3. When the gallium nitride device is switched from an off state to an on state, the phenomena of reduction of saturation current and increase of on-resistance, namely current collapse, can occur, which greatly influences the reliability of the application of the gallium nitride device.
4. At present, the voltage-resisting level of the gallium nitride device is favorable compared with that of a silicon device, but the voltage-resisting level of the gallium nitride device has a great promotion space from the theoretical value of the gallium nitride device.
Disclosure of Invention
In view of the above problems in the prior art, an object of the present invention is to provide a passivation design for a gallium nitride MIS-HEMT and a method for manufacturing the same, in which a passivation structure is constructed by using a secondary stacked high dielectric constant material (HfSiO) and a low dielectric constant P-type oxide material (CuO) by improving key components and internal structures of the passivation structure in cooperation with detailed structures and materials (such as gate dielectric materials) of the gallium nitride MIS-HEMT device, thereby achieving better electrical properties compared to the prior art.
To achieve the above object, according to one aspect of the present invention, there is provided a passivation structure for gallium nitride MIS-HEMT, characterized in that the passivation structure comprises a silicon-doped hafnium oxide HfSiO material and P-type CuO stacked twice;
the passivation structure is used for passivating the HEMT device on the basis of gallium nitride and containing a metal-insulator-semiconductor MIS structure; and the gate dielectric of the HEMT device is made of silicon-doped hafnium oxide HfSiO material.
As a further optimization of the invention, the silicon-doped hafnium oxide HfSiO material in the passivation structure is directly contacted with the gate dielectric silicon-doped hafnium oxide HfSiO material, so that the electric field distribution in the channel can be relaxed, and the withstand voltage of the device can be improved.
As a further preferred embodiment of the present invention, the HEMT device has a recessed gate structure, and the electron concentration below the gate is reduced by reducing the polarization strength, so that the device is converted from a depletion mode to an enhancement mode.
According to still another aspect of the present invention, there is provided a method for manufacturing a gallium nitride MIS-HEMT device having a passivation structure, characterized in that the gallium nitride MIS-HEMT device is a gallium nitride-based HEMT device including a metal-insulator-semiconductor structure MIS, and the passivation structure is the above-described gallium nitride MIS-HEMT passivation structure;
depositing a silicon-doped hafnium oxide HfSiO material as a gate dielectric layer of the gallium nitride MIS-HEMT device by utilizing an atomic layer deposition ALD (atomic layer deposition) technology, then depositing gate metal, and then depositing a layer of silicon-doped hafnium oxide HfSiO material as an intermediate layer; then, growing P-type CuO between the grid and the drain; finally, a layer of silicon-doped hafnium oxide HfSiO material is deposited.
As a further preferable aspect of the present invention, the gallium nitride MIS-HEMT device has a recessed gate structure formed by thinning an AlGaN barrier layer under a gate; the thinning is specifically that after a gallium nitride substrate is cleaned, aluminum nitride is deposited as a mask, and then inductively coupled plasma dry etching, namely ICP dry etching, is carried out in a circulating atmosphere of oxygen and chlorine-based gas, so that the AlGaN barrier layer is thinned.
As a further preferred aspect of the present invention, the drain and the source of the HEMT device are both based on low temperature gold-free ohmic contact, enabling compatibility with CMOS processes; the low temperature does not exceed 550 ℃.
As a further preferred aspect of the present invention, the drain and the source of the gallium nitride MIS-HEMT device are both based on low-temperature gold-free ohmic contact, specifically, the method comprises the steps of etching the AlGaN barrier layer by using inductively coupled plasma dry etching, namely, an ICP dry etching method, then performing surface deoxidation treatment on the etched ohmic region, sputtering Ti/Al/TiN laminated metal by using a magnetron sputtering apparatus, and finally performing annealing treatment, wherein the annealing temperature is preferably controlled not to exceed 550 ℃, so as to form low-temperature gold-free ohmic contact.
Compared with the prior art, the technical scheme of the invention can achieve the following beneficial effects on the whole:
1. the HfSiO medium has the advantages of high dielectric constant and low leakage current when used as a gate medium, and simultaneously passivates a device together with the P-type CuO with low dielectric constant, so that the reliability and the breakdown voltage of the device are improved.
2. The invention provides a low-temperature ohmic contact preparation method, which can finally form better ohmic contact after a series of processes such as deoxidation treatment of an ohmic region, subsequent metal deposition annealing and the like on the basis of ensuring accurate etching depth.
3. The groove gate provided by the invention is simple in preparation method, and the etching depth is accurately controlled and low damage of the etching surface is ensured through a digital ICP (inductively coupled plasma) etching process, so that the interface state is reduced.
The invention mainly researches a gallium nitride power electronic device, particularly adopts a device structure of a groove gate to realize an enhanced working mode of the device, can adopt a low-temperature gold-free technology to prepare an ohmic electrode to realize compatibility with a CMOS (complementary metal oxide semiconductor) process, adopts a high dielectric constant material (HfSiO) as a gate dielectric layer and simultaneously combines with a P-type oxide (CuO) as a passivation layer, reduces the current collapse effect of the device and improves the breakdown voltage of the device.
The invention provides a passivation design and a preparation method of a high-dielectric-constant-gate-dielectric-gallium-nitride-based device, and particularly relates to a high-dielectric-constant-dielectric layer formed by depositing a silicon-doped hafnium oxide (HfSiO) material by utilizing an Atomic Layer Deposition (ALD) technology, wherein the HfSiO material is not only used as a gate dielectric layer to inhibit gate leakage, but also can passivate the surface of AlGaN and reduce surface defects. The atomic layer deposition method has high step coverage rate and uniform coverage thickness, and can realize the film deposition on the multidimensional complex structure. Atomic Layer Deposition (ALD) can achieve layer-by-layer deposition on the substrate surface from a single atom precision, thereby ensuring the compactness and uniformity of the thin film. After the gate metal is deposited, a layer of HfSiO material with proper thickness is deposited, so that the electric field distribution in the channel can be smoothed, and the withstand voltage of the device is improved. P-type CuO intercalation with certain width and thickness is grown between the grid electrode and the drain electrode, and a large number of holes in the P-type CuO can neutralize electrons trapped by surface traps, so that the virtual grid effect of the device is weakened, and the current collapse phenomenon of the device is improved. And finally, depositing a high-dielectric-constant HfSiO material with a certain thickness as passivation, and improving the electric field below the interface of the high/low-dielectric-constant material (HfSiO/CuO), so that the original channel electric field distribution is changed, and the voltage resistance of the device is improved.
In addition, the gallium nitride device in the invention preferably has a groove gate structure, and the groove gate structure can be, for example, by thinning the AlGaN barrier layer below the gate, the polarization strength is reduced, and the electron concentration below the gate is reduced, so that the forward shift of the threshold voltage is realized. After cleaning the gallium nitride substrate, depositing aluminum nitride as a mask, carrying out Inductively Coupled Plasma (ICP) dry etching in an oxygen and chlorine-based gas circulating atmosphere, accurately controlling the etching depth, and thinning the AlGaN barrier layer.
The gallium nitride device can also form low-temperature ohmic contact, and the preparation method can be, for example, etching the AlGaN barrier layer by adopting an ICP method, controlling to obtain the optimal etching depth, processing the etched ohmic region, sputtering Ti/Al/TiN laminated metal by adopting a magnetron sputtering instrument, finally exploring the optimal annealing condition, and controlling the annealing temperature to be below 550 ℃, thereby achieving the purpose of low-temperature non-gold contact.
The device gate dielectric is the best gate dielectric material selected from silicon-doped hafnium oxide HfSiO material after comparing common gate dielectric materials SiNx, Al2O3 and Hf-based high dielectric constant materials (HfO, HfLaO and the like). According to the invention, the silicon-doped hafnium oxide HfSiO material with the same type as the gate dielectric material is selected to construct a twice-laminated structure, and the gallium nitride MIS-HEMT passivation structure can be effectively formed by matching with the P-type CuO.
Drawings
FIG. 1 is a cross-sectional view of a silicon-based gallium nitride substrate.
Fig. 2 is a cross-sectional view of an active region formed by etching.
Fig. 3 is a cross-sectional view after etching the gate recess.
FIG. 4 is a cross-sectional view of ohmic contact formation.
Fig. 5 is a cross-sectional view after deposition of a high-k gate dielectric layer.
Fig. 6 is a cross-sectional view of the gate metal deposited thereon.
Fig. 7 is a cross-sectional view after sputtering P-type CuO.
Fig. 8 is a cross-sectional view of an optimized passivated enhancement mode gan power device with a high-k dielectric gate dielectric, in accordance with a disclosed embodiment of the invention.
Fig. 9 is an AFM characterization diagram of the grooved gate after the dry etching process, wherein (a) the etched depth of the grooved gate is characterized, and (b) the surface roughness of the grooved gate after etching is characterized.
Fig. 10 is a test chart of a device IV using a recessed gate structure, and the size of the device is 50/3/3.5/21 μm in terms of gate width W/gate length Lg/gate source distance Lgs/gate drain distance Lgd.
Fig. 11 is a device breakdown characteristic curve and a gate leakage curve graph of HfSiO as a gate dielectric.
The meaning of the respective reference numerals in fig. 1 to 8 is as follows: 1 is a Si (111) substrate; 2a is an epitaxial gallium nitride buffer layer, and 2b is an epitaxial gallium nitride channel layer; 3 is epitaxial AlGaN barrier layer; 4 is an ohmic metal; 5a is a first-deposited high-dielectric-constant HfSiO material (i.e., a gate dielectric layer), 5b is a second-deposited high-dielectric-constant HfSiO material (i.e., a first layer of the HfSiO material stacked twice in the passivation structure), and 5c is a third-deposited high-dielectric-constant HfSiO material (i.e., a second layer of the HfSiO material stacked twice in the passivation structure); 6 is a gate stack metal; and 7 is a P-type CuO material.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
Generally, the preparation of the dielectric gate dielectric with high dielectric constant provided by the invention can optimize the passivated enhanced gallium nitride power device and can be divided into 8 main steps, which are respectively as follows: processing a substrate, etching and isolating, etching a gate groove, sputtering ohmic metal, depositing a gate medium, evaporating gate metal, sputtering a P-type CuO passivation layer and depositing the passivation layer.
The embodiment specifically comprises the following steps:
And 3, step 3, a cross-sectional view of the etched groove gate is shown in fig. 3. Firstly, depositing aluminum nitride as a mask, forming a groove gate pattern after carrying out a photoetching process, and removing redundant photoresist. BCl can be etched by ICP dry method at low gas flow3And O2The grooves are etched slowly in the atmosphere, which is helpful for reducing the roughness of the etched area. An Atomic Force Microscope (AFM) is used for representing the depth and the roughness of the etched groove under different conditions (gas flow, pressure and etching cycle number), and the optimal etching condition can be obtained (in the embodiment, the etching depth of the device is 27.5nm, and the roughness RMS is 0.104 nm). Removing the aluminum nitride mask layer after the etching is finished, namely formingAnd (5) a groove gate structure of the device.
The gate groove structure reduces the polarization strength and reduces the electron concentration below the gate by thinning the AlGaN barrier layer below the gate, thereby realizing the positive shift of the threshold voltage.
Step 8, fig. 8 is a cross-sectional view of the finally prepared gan power device, and fig. 5c shows the third deposited HfSiO material with high dielectric constant. The three-time deposited high-dielectric-constant HfSiO materials of 5a, 5b and 5c and the P-type CuO material are jointly used as a passivation layer of the gallium nitride device (wherein, 5a is mainly used as a gate dielectric of the HEMT device, so 5b and 5c are silicon-doped hafnium oxide HfSiO materials which completely play a role in passivation and are stacked twice), the breakdown voltage of the device is improved, the current collapse effect of the device is relieved, and the reliability of the gallium nitride power device is further improved.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A preparation method of a gallium nitride MIS-HEMT device with a passivation structure is characterized in that the gallium nitride MIS-HEMT device is a gallium nitride-based HEMT device which comprises a metal-insulator-semiconductor structure MIS; the passivation structure comprises a silicon-doped hafnium oxide HfSiO material and P-type CuO which are laminated twice; the passivation structure is used for passivating the HEMT device on the basis of gallium nitride and containing a metal-insulator-semiconductor MIS structure; moreover, the gate dielectric of the HEMT device is made of silicon-doped hafnium oxide HfSiO material;
depositing a silicon-doped hafnium oxide HfSiO material as a gate dielectric layer of the gallium nitride MIS-HEMT device by utilizing an atomic layer deposition ALD (atomic layer deposition) technology, then depositing gate metal, and then depositing a layer of silicon-doped hafnium oxide HfSiO material as an intermediate layer; then, growing P-type CuO between the grid and the drain; finally, a layer of silicon-doped hafnium oxide HfSiO material is deposited.
2. The method of manufacturing of claim 1, wherein the gallium nitride MIS-HEMT device has a recessed gate structure formed by thinning an AlGaN barrier layer under a gate; the thinning is specifically that after a gallium nitride substrate is cleaned, aluminum nitride is deposited as a mask, and then inductively coupled plasma dry etching, namely ICP dry etching, is carried out in a circulating atmosphere of oxygen and chlorine-based gas, so that the AlGaN barrier layer is thinned.
3. The method according to claim 1, wherein the drain and the source of the HEMT device are based on low temperature gold-free ohmic contacts, enabling compatibility with CMOS processes; the low temperature does not exceed 550 ℃.
4. The preparation method according to claim 3, wherein the drain and the source of the gallium nitride MIS-HEMT device are based on low-temperature gold-free ohmic contact, and specifically, the AlGaN barrier layer is etched by adopting an inductively coupled plasma dry etching (ICP dry etching) method, then, the surface of the etched ohmic region is subjected to deoxidation treatment, Ti/Al/TiN laminated metal is sputtered by adopting a magnetron sputtering instrument, and finally, annealing treatment is carried out, and the annealing temperature is controlled not to exceed 550 ℃, so that the low-temperature gold-free ohmic contact is formed.
5. The preparation method of claim 1, wherein the silicon-doped hafnium oxide HfSiO material in the passivation structure is in direct contact with the gate dielectric silicon-doped hafnium oxide HfSiO material, so that electric field distribution in a channel can be smoothed, and the withstand voltage of a device is improved.
6. The method according to claim 1, wherein the HEMT device has a recessed gate structure, and the concentration of electrons under the gate is reduced by reducing the polarization strength, so that the device is converted from a depletion mode to an enhancement mode.
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