CN111933708A - Gallium nitride MIS-HEMT passivation design and preparation method thereof - Google Patents

Gallium nitride MIS-HEMT passivation design and preparation method thereof Download PDF

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CN111933708A
CN111933708A CN202010752951.XA CN202010752951A CN111933708A CN 111933708 A CN111933708 A CN 111933708A CN 202010752951 A CN202010752951 A CN 202010752951A CN 111933708 A CN111933708 A CN 111933708A
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gallium nitride
mis
gate
hemt
hfsio
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CN111933708B (en
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吴燕庆
詹丹
李学飞
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Huazhong University of Science and Technology
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The invention belongs to the technical field of semiconductor devices and discloses a passivation design and a preparation method of gallium nitride MIS-HEMT, wherein a passivation structure comprises a silicon-doped hafnium oxide HfSiO material and P-type CuO which are laminated twice. Preferably, the MIS-HEMT device adopts a groove gate structure; the gate dielectric is made of silicon-doped hafnium oxide material with high dielectric constant; the source and drain electrodes are prepared by a low-temperature gold-free contact process. According to the invention, through the key composition and specific structure of the passivation structure and the improvement of the gate dielectric material of the gallium nitride MIS-HEMT device, the passivation structure is constructed by using the high dielectric constant material (HfSiO) and the low dielectric constant P-type oxide material (CuO) which are laminated twice, and compared with the prior art, the passivation structure can realize better electrical performance.

Description

Gallium nitride MIS-HEMT passivation design and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a gallium nitride MIS-HEMT (High Electron Mobility Transistor HEMT comprising metal-insulator-semiconductor MIS), wherein MIS represents metal-insulator-semiconductor and HEMT represents High Electron Mobility Transistor) passivation design and a preparation method thereof, and the gallium nitride MIS-HEMT device with excellent electrical performance can be obtained.
Background
Since the advent of metal oxide semiconductor field effect transistors, silicon materials dominate the semiconductor industry, mainly due to the low cost of silicon semiconductors and the high quality native oxide layer on their surfaces. However, the narrow forbidden band width of silicon limits the development of silicon in the direction of power electronics, and the search for semiconductor materials with better performance is inevitable. Gallium nitride as third generation semiconductor has higher critical breakdown electric field (3.3MV/cm) and higher saturation velocity (2.7 × 10) than conventional silicon semiconductor7cm/s), wide forbidden band (3.4 eV). In addition, when gallium nitride is used as a power electronic device, a heterojunction structure is formed between the gallium nitride and AlGaN, and high mobility (2 multiplied by 10) can be generated at the interface3cm2V · s) 2DEG channel.
The current gallium nitride power device faces the following problems:
1. gallium nitride electronic devices in a conventional manner are depletion type devices, and the devices are turned on under zero bias, so that potential safety hazards exist in power electronic applications.
2. The ohmic contact of the gallium nitride device introduces gold and the annealing temperature is high, which is not compatible with the existing CMOS process. The search for low temperature, gold-free, low contact resistance ohmic contact processes is also the direction of current research.
3. When the gallium nitride device is switched from an off state to an on state, the phenomena of reduction of saturation current and increase of on-resistance, namely current collapse, can occur, which greatly influences the reliability of the application of the gallium nitride device.
4. At present, the voltage-resisting level of the gallium nitride device is favorable compared with that of a silicon device, but the voltage-resisting level of the gallium nitride device has a great promotion space from the theoretical value of the gallium nitride device.
Disclosure of Invention
In view of the above problems in the prior art, an object of the present invention is to provide a passivation design for a gallium nitride MIS-HEMT and a method for manufacturing the same, in which a passivation structure is constructed by using a secondary stacked high dielectric constant material (HfSiO) and a low dielectric constant P-type oxide material (CuO) by improving key components and internal structures of the passivation structure in cooperation with detailed structures and materials (such as gate dielectric materials) of the gallium nitride MIS-HEMT device, thereby achieving better electrical properties compared to the prior art.
To achieve the above object, according to one aspect of the present invention, there is provided a passivation structure for gallium nitride MIS-HEMT, characterized in that the passivation structure comprises a silicon-doped hafnium oxide HfSiO material and P-type CuO stacked twice;
the passivation structure is used for passivating the HEMT device on the basis of gallium nitride and containing a metal-insulator-semiconductor MIS structure; and the gate dielectric of the HEMT device is made of silicon-doped hafnium oxide HfSiO material.
As a further optimization of the invention, the silicon-doped hafnium oxide HfSiO material in the passivation structure is directly contacted with the gate dielectric silicon-doped hafnium oxide HfSiO material, so that the electric field distribution in the channel can be relaxed, and the withstand voltage of the device can be improved.
As a further preferred embodiment of the present invention, the HEMT device has a recessed gate structure, and the electron concentration below the gate is reduced by reducing the polarization strength, so that the device is converted from a depletion mode to an enhancement mode.
According to still another aspect of the present invention, there is provided a method for manufacturing a gallium nitride MIS-HEMT device having a passivation structure, characterized in that the gallium nitride MIS-HEMT device is a gallium nitride-based HEMT device including a metal-insulator-semiconductor structure MIS, and the passivation structure is the above-described gallium nitride MIS-HEMT passivation structure;
depositing a silicon-doped hafnium oxide HfSiO material as a gate dielectric layer of the gallium nitride MIS-HEMT device by utilizing an atomic layer deposition ALD (atomic layer deposition) technology, then depositing gate metal, and then depositing a layer of silicon-doped hafnium oxide HfSiO material as an intermediate layer; then, growing P-type CuO between the grid and the drain; finally, a layer of silicon-doped hafnium oxide HfSiO material is deposited.
As a further preferable aspect of the present invention, the gallium nitride MIS-HEMT device has a recessed gate structure formed by thinning an AlGaN barrier layer under a gate; the thinning is specifically that after a gallium nitride substrate is cleaned, aluminum nitride is deposited as a mask, and then inductively coupled plasma dry etching, namely ICP dry etching, is carried out in a circulating atmosphere of oxygen and chlorine-based gas, so that the AlGaN barrier layer is thinned.
As a further preferred aspect of the present invention, the drain and the source of the HEMT device are both based on low temperature gold-free ohmic contact, enabling compatibility with CMOS processes; the low temperature does not exceed 550 ℃.
As a further preferred aspect of the present invention, the drain and the source of the gallium nitride MIS-HEMT device are both based on low-temperature gold-free ohmic contact, specifically, the method comprises the steps of etching the AlGaN barrier layer by using inductively coupled plasma dry etching, namely, an ICP dry etching method, then performing surface deoxidation treatment on the etched ohmic region, sputtering Ti/Al/TiN laminated metal by using a magnetron sputtering apparatus, and finally performing annealing treatment, wherein the annealing temperature is preferably controlled not to exceed 550 ℃, so as to form low-temperature gold-free ohmic contact.
Compared with the prior art, the technical scheme of the invention can achieve the following beneficial effects on the whole:
1. the HfSiO medium has the advantages of high dielectric constant and low leakage current when used as a gate medium, and simultaneously passivates a device together with the P-type CuO with low dielectric constant, so that the reliability and the breakdown voltage of the device are improved.
2. The invention provides a low-temperature ohmic contact preparation method, which can finally form better ohmic contact after a series of processes such as deoxidation treatment of an ohmic region, subsequent metal deposition annealing and the like on the basis of ensuring accurate etching depth.
3. The groove gate provided by the invention is simple in preparation method, and the etching depth is accurately controlled and low damage of the etching surface is ensured through a digital ICP (inductively coupled plasma) etching process, so that the interface state is reduced.
The invention mainly researches a gallium nitride power electronic device, particularly adopts a device structure of a groove gate to realize an enhanced working mode of the device, can adopt a low-temperature gold-free technology to prepare an ohmic electrode to realize compatibility with a CMOS (complementary metal oxide semiconductor) process, adopts a high dielectric constant material (HfSiO) as a gate dielectric layer and simultaneously combines with a P-type oxide (CuO) as a passivation layer, reduces the current collapse effect of the device and improves the breakdown voltage of the device.
The invention provides a passivation design and a preparation method of a high-dielectric-constant-gate-dielectric-gallium-nitride-based device, and particularly relates to a high-dielectric-constant-dielectric layer formed by depositing a silicon-doped hafnium oxide (HfSiO) material by utilizing an Atomic Layer Deposition (ALD) technology, wherein the HfSiO material is not only used as a gate dielectric layer to inhibit gate leakage, but also can passivate the surface of AlGaN and reduce surface defects. The atomic layer deposition method has high step coverage rate and uniform coverage thickness, and can realize the film deposition on the multidimensional complex structure. Atomic Layer Deposition (ALD) can achieve layer-by-layer deposition on the substrate surface from a single atom precision, thereby ensuring the compactness and uniformity of the thin film. After the gate metal is deposited, a layer of HfSiO material with proper thickness is deposited, so that the electric field distribution in the channel can be smoothed, and the withstand voltage of the device is improved. P-type CuO intercalation with certain width and thickness is grown between the grid electrode and the drain electrode, and a large number of holes in the P-type CuO can neutralize electrons trapped by surface traps, so that the virtual grid effect of the device is weakened, and the current collapse phenomenon of the device is improved. And finally, depositing a high-dielectric-constant HfSiO material with a certain thickness as passivation, and improving the electric field below the interface of the high/low-dielectric-constant material (HfSiO/CuO), so that the original channel electric field distribution is changed, and the voltage resistance of the device is improved.
In addition, the gallium nitride device in the invention preferably has a groove gate structure, and the groove gate structure can be, for example, by thinning the AlGaN barrier layer below the gate, the polarization strength is reduced, and the electron concentration below the gate is reduced, so that the forward shift of the threshold voltage is realized. After cleaning the gallium nitride substrate, depositing aluminum nitride as a mask, carrying out Inductively Coupled Plasma (ICP) dry etching in an oxygen and chlorine-based gas circulating atmosphere, accurately controlling the etching depth, and thinning the AlGaN barrier layer.
The gallium nitride device can also form low-temperature ohmic contact, and the preparation method can be, for example, etching the AlGaN barrier layer by adopting an ICP method, controlling to obtain the optimal etching depth, processing the etched ohmic region, sputtering Ti/Al/TiN laminated metal by adopting a magnetron sputtering instrument, finally exploring the optimal annealing condition, and controlling the annealing temperature to be below 550 ℃, thereby achieving the purpose of low-temperature non-gold contact.
The device gate dielectric is the best gate dielectric material selected from silicon-doped hafnium oxide HfSiO material after comparing common gate dielectric materials SiNx, Al2O3 and Hf-based high dielectric constant materials (HfO, HfLaO and the like). According to the invention, the silicon-doped hafnium oxide HfSiO material with the same type as the gate dielectric material is selected to construct a twice-laminated structure, and the gallium nitride MIS-HEMT passivation structure can be effectively formed by matching with the P-type CuO.
Drawings
FIG. 1 is a cross-sectional view of a silicon-based gallium nitride substrate.
Fig. 2 is a cross-sectional view of an active region formed by etching.
Fig. 3 is a cross-sectional view after etching the gate recess.
FIG. 4 is a cross-sectional view of ohmic contact formation.
Fig. 5 is a cross-sectional view after deposition of a high-k gate dielectric layer.
Fig. 6 is a cross-sectional view of the gate metal deposited thereon.
Fig. 7 is a cross-sectional view after sputtering P-type CuO.
Fig. 8 is a cross-sectional view of an optimized passivated enhancement mode gan power device with a high-k dielectric gate dielectric, in accordance with a disclosed embodiment of the invention.
Fig. 9 is an AFM characterization diagram of the grooved gate after the dry etching process, wherein (a) the etched depth of the grooved gate is characterized, and (b) the surface roughness of the grooved gate after etching is characterized.
Fig. 10 is a test chart of a device IV using a recessed gate structure, and the size of the device is 50/3/3.5/21 μm in terms of gate width W/gate length Lg/gate source distance Lgs/gate drain distance Lgd.
Fig. 11 is a device breakdown characteristic curve and a gate leakage curve graph of HfSiO as a gate dielectric.
The meaning of the respective reference numerals in fig. 1 to 8 is as follows: 1 is a Si (111) substrate; 2a is an epitaxial gallium nitride buffer layer, and 2b is an epitaxial gallium nitride channel layer; 3 is epitaxial AlGaN barrier layer; 4 is an ohmic metal; 5a is a first-deposited high-dielectric-constant HfSiO material (i.e., a gate dielectric layer), 5b is a second-deposited high-dielectric-constant HfSiO material (i.e., a first layer of the HfSiO material stacked twice in the passivation structure), and 5c is a third-deposited high-dielectric-constant HfSiO material (i.e., a second layer of the HfSiO material stacked twice in the passivation structure); 6 is a gate stack metal; and 7 is a P-type CuO material.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
Generally, the preparation of the dielectric gate dielectric with high dielectric constant provided by the invention can optimize the passivated enhanced gallium nitride power device and can be divided into 8 main steps, which are respectively as follows: processing a substrate, etching and isolating, etching a gate groove, sputtering ohmic metal, depositing a gate medium, evaporating gate metal, sputtering a P-type CuO passivation layer and depositing the passivation layer.
The embodiment specifically comprises the following steps:
step 1, processing a substrate, wherein fig. 1 is a cross-sectional view of a silicon-based gallium nitride substrate, and fig. 1 is a Si (111) substrate. In the figure, 2a is an epitaxial gallium nitride buffer layer, because Si and O atoms are introduced into a substrate in the epitaxial process to form vacancies, namely donor state defects in the buffer layer, electrons are released under the leakage voltage, and the leakage current of the device is large. At the moment, acceptor traps are introduced through a process means, such as a carbon doping technology, and a buffer layer is formed, so that the electric leakage of the device is improved. In the figure 2b, the epitaxial gallium nitride channel layer, and in the figure 3, the epitaxial aluminum gallium nitride barrier layer, the GaN/AlGaN heterojunction will generate a high concentration of 2DEG (i.e., two-dimensional electron gas) at its interface, which is also a source of high electron mobility for gallium nitride. In addition, the gallium nitride substrate needs to be cleaned to remove impurities and oxides on the surface, and acetone ultrasonic cleaning can be adopted.
Step 2, etching isolation, and fig. 2 is a cross-sectional view after etching isolation. Photoetching to form active region pattern, and dry etching with Inductively Coupled Plasma (ICP) to form BCl pattern3And Cl2And etching in the atmosphere to obtain an active region.
And 3, step 3, a cross-sectional view of the etched groove gate is shown in fig. 3. Firstly, depositing aluminum nitride as a mask, forming a groove gate pattern after carrying out a photoetching process, and removing redundant photoresist. BCl can be etched by ICP dry method at low gas flow3And O2The grooves are etched slowly in the atmosphere, which is helpful for reducing the roughness of the etched area. An Atomic Force Microscope (AFM) is used for representing the depth and the roughness of the etched groove under different conditions (gas flow, pressure and etching cycle number), and the optimal etching condition can be obtained (in the embodiment, the etching depth of the device is 27.5nm, and the roughness RMS is 0.104 nm). And removing the aluminum nitride mask layer after the etching is finished, thus forming the groove gate structure of the device.
The gate groove structure reduces the polarization strength and reduces the electron concentration below the gate by thinning the AlGaN barrier layer below the gate, thereby realizing the positive shift of the threshold voltage.
Step 4, fig. 4 is a cross-sectional view after sputtering ohmic metal, and fig. 4 is ohmic metal. And photoetching and developing the gallium nitride substrate to obtain an ohmic contact pattern, and then removing the AlGaN barrier layer by adopting ICP dry etching. Diluted HCl (HCl: deionized water 1:9, wherein 1:9 refers to a volume ratio, that is, 1 part by volume of concentrated HCl solution needs to be diluted with 9 parts by volume of deionized water) + BOE solution to clean an ohmic region (2min), remove impurities such as oxide on the surface, grow Ti/Al/TiN laminated metal (in this embodiment, the specific thickness of each layer of metal is 2nm/120nm/30nm), strip off the photoresist mask, and remove the photoresist mask, then add N2And performing rapid annealing treatment at 550 ℃ for 90s in the atmosphere to obtain good ohmic contact.
Step 5, fig. 5 is a cross-sectional view after depositing a gate dielectric, in which fig. 5a is a high-k HfSiO material (i.e., a first-deposited high-k HfSiO material) mainly used as a gate dielectric layer and also used for passivating the semiconductor surface. Atomic Layer Deposition (ALD) of HfSiO material is based on two self-limiting cycles, and the thickness of each cycle can be precisely controlled to obtain the optimum gate dielectric layer thickness (20 nm in this embodiment).
Step 6, fig. 6 is a cross-sectional view after the gate is deposited, and fig. 6 shows a gate stack metal. The gate pattern is formed by photolithography, and gate metal (Ni/Au) is evaporated by electron beam evaporation, for example, a T-type gate can be used according to the prior art, thereby obtaining advantages such as increasing the cut-off frequency of the device and reducing the gate resistance.
Step 7, fig. 7 is a cross-sectional view after sputtering a P-type CuO passivation layer, and fig. 5b shows a second deposition of high dielectric constant HfSiO material, the deposition method being the same as before. In the figure, 7 is a P-type CuO material. The growth is carried out by a magnetron sputtering method, a stripping method after the growth of a photoresist serving as a mask can be adopted, and a post-growth etching method can also be adopted.
Step 8, fig. 8 is a cross-sectional view of the finally prepared gan power device, and fig. 5c shows the third deposited HfSiO material with high dielectric constant. The three-time deposited high-dielectric-constant HfSiO materials of 5a, 5b and 5c and the P-type CuO material are jointly used as a passivation layer of the gallium nitride device (wherein, 5a is mainly used as a gate dielectric of the HEMT device, so 5b and 5c are silicon-doped hafnium oxide HfSiO materials which completely play a role in passivation and are stacked twice), the breakdown voltage of the device is improved, the current collapse effect of the device is relieved, and the reliability of the gallium nitride power device is further improved.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (7)

1. The passivation structure is characterized by comprising a silicon-doped hafnium oxide (HfSiO) material and P-type CuO which are laminated twice;
the passivation structure is used for passivating the HEMT device on the basis of gallium nitride and containing a metal-insulator-semiconductor MIS structure; and the gate dielectric of the HEMT device is made of silicon-doped hafnium oxide HfSiO material.
2. The gallium nitride MIS-HEMT passivation structure of claim 1, wherein the silicon-doped hafnium oxide HfSiO material in the passivation structure is in direct contact with the gate dielectric silicon-doped hafnium oxide HfSiO material, which can smooth the electric field distribution in the channel and improve the withstand voltage of the device.
3. The gallium nitride MIS-HEMT passivation structure of claim 1, wherein said HEMT device has a notched gate structure that reduces the concentration of electrons under the gate by reducing the polarization to effect a transition from depletion mode to enhancement mode of the device.
4. A method for manufacturing a gallium nitride MIS-HEMT device having a passivation structure, wherein the gallium nitride MIS-HEMT device is a gallium nitride-based HEMT device including a metal-insulator-semiconductor MIS structure, and the passivation structure is the gallium nitride MIS-HEMT passivation structure according to any one of claims 1 to 3;
depositing a silicon-doped hafnium oxide HfSiO material as a gate dielectric layer of the gallium nitride MIS-HEMT device by utilizing an atomic layer deposition ALD (atomic layer deposition) technology, then depositing gate metal, and then depositing a layer of silicon-doped hafnium oxide HfSiO material as an intermediate layer; then, growing P-type CuO between the grid and the drain; finally, a layer of silicon-doped hafnium oxide HfSiO material is deposited.
5. The method of manufacturing of claim 4, wherein the gallium nitride MIS-HEMT device has a recessed gate structure formed by thinning an AlGaN barrier layer under a gate; the thinning is specifically that after a gallium nitride substrate is cleaned, aluminum nitride is deposited as a mask, and then inductively coupled plasma dry etching, namely ICP dry etching, is carried out in a circulating atmosphere of oxygen and chlorine-based gas, so that the AlGaN barrier layer is thinned.
6. The method according to claim 4, wherein the drain and the source of the HEMT device are based on low-temperature gold-free ohmic contact and are compatible with CMOS process; the low temperature does not exceed 550 ℃.
7. The preparation method according to claim 6, wherein the drain and the source of the gallium nitride MIS-HEMT device are both based on low-temperature gold-free ohmic contact, and specifically, the method comprises the steps of etching the AlGaN barrier layer by adopting an inductively coupled plasma dry etching (ICP dry etching) method, then carrying out surface deoxidation treatment on the etched ohmic region, sputtering Ti/Al/TiN laminated metal by adopting a magnetron sputtering instrument, and finally carrying out annealing treatment, wherein the annealing temperature is preferably controlled not to exceed 550 ℃, so that the low-temperature gold-free ohmic contact is formed.
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CN114068677A (en) * 2021-11-19 2022-02-18 西南交通大学 Enhancement mode high pressure gaN base vertical HFET device of AlGaN slot

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