CN109728087B - Method for preparing low-ohmic contact GaN-based HEMT based on nanosphere mask - Google Patents
Method for preparing low-ohmic contact GaN-based HEMT based on nanosphere mask Download PDFInfo
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Abstract
The invention discloses a method for preparing a low-ohmic-contact GaN-based high-electron-mobility transistor based on a nanosphere mask, which mainly solves the problem that the ohmic contact resistance of the GaN-based high-electron-mobility transistor is higher. The realization is as follows: depositing SiO on the cleaned epitaxial wafer2(ii) a On deposition of SiO2Sequentially carrying out source-drain region photoetching and coating micro-nano alumina micro-nano spheres on the epitaxial wafer; etching off SiO of source and drain regions on epitaxial wafer by nanosphere mask2Forming a source drain region graphical nano through hole and cleaning the layer and the AlGaN layer; growing n on the cleaned epitaxial wafer+-GaN and removed n+Residual SiO on epitaxial wafers of GaN2A layer; performing source-drain metal deposition and thermal annealing; and manufacturing a grid electrode on the annealed epitaxial wafer. The invention has low ohmic contact resistance and simple etching process, and can be used for manufacturing power electronic devices.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a preparation method of a low-ohmic contact transistor, which can be used for manufacturing a GaN-based high-electron-mobility transistor device.
Technical Field
The GaN material can form a modulation doped AlGaN/GaN heterostructure which has large conduction band discontinuity, and strong spontaneous polarization and piezoelectric polarization are generated near a heterostructure interface, so that strong interface charges and electric fields are induced, and high-density two-dimensional electron gas is accumulated. The two-dimensional electron gas can be generated by electron transfer in the undoped barrier layer, the separation reduces the coulomb effect of the parent body on electrons, eliminates the influence of ionization scattering centers, and improves the electron mobility. And the GaN material has large breakdown electric field and high temperature resistance, and the GaN-based HEMT device (high electron mobility transistor) is very suitable for high-voltage, high-power and high-frequency application. The larger the conduction band discontinuity of the heterojunction, the better the confinement of the introduced two-dimensional electrons, and the larger the current density. However, the large forbidden band width of the barrier layer makes it difficult to form good ohmic contact on the device, resulting in reduced output current capability. Making high performance ohmic contacts is therefore critical to achieving large output current densities.
In order to improve Ohmic contact, various researchers have adopted different approaches, see the inorganic contacts to Gallium Nitride materials, Applied Surface Science, 383(2016), 324-. Although the ohmic contact resistance is reduced by the ohmic contact optimization methods, the contact area between the counter electrode and the two-dimensional electron gas is still small, the reduction effect of ohmic contact is not obvious, and high-temperature thermal annealing can bring about lattice damage, so that the leakage current is increased, and the power loss of the device is increased.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a method for preparing a low-ohmic contact GaN-based HEMT based on a nanosphere mask, so that the contact area between two-dimensional electron gas and a source electrode and a drain electrode is increased, ohmic contact resistance is greatly reduced, current output density is improved, annealing temperature is reduced, lattice damage is reduced, leakage current is reduced, and power loss is reduced.
The key technology for realizing the invention is as follows: and (3) etching densely arranged columnar through holes at the source and drain electrodes by adopting the nanosphere mask layer, wherein the through holes are close to the two-dimensional electron gas. By using n+-GaN regrown filled vias, achieving n+GaN is in contact with a two-dimensional electron gas. At the source and drainPolar deposition of metal and n+-a GaN layer ohmic contact. The method comprises the following specific steps:
(1) epitaxial wafer cleaning
Soaking an epitaxial wafer with an AlGaN/GaN structure in an HF acid solution or an HCl acid solution for 30s, sequentially placing the epitaxial wafer in an acetone solution, an absolute ethyl alcohol solution and deionized water, respectively ultrasonically cleaning for 2-10min, and then drying by using nitrogen;
(2) the cleaned epitaxial wafer is placed into a plasma enhanced chemical vapor deposition PECVD reaction chamber, and SiO with the thickness of 100-300nm is deposited at the temperature of 250-350 DEG C2；
(3) Manufacturing a source drain region graphical nano through hole:
(3a) on deposition of SiO2Carrying out source-drain region photoetching on the epitaxial wafer;
(3b) coating a layer of micro-nano alumina micro-nano spheres on the epitaxial wafer after photoetching;
(3c) placing the epitaxial wafer coated with the nanospheres into a plasma etcher to etch off SiO at the source and drain electrodes2Etching AlGaN with the thickness of 20-30nm to form a source drain region graphical nano through hole embedded in the GaN layer;
(4)n+-GaN regrowth:
sequentially placing the epitaxial wafer etched with the source drain region nano through holes into an acetone solution, an absolute ethyl alcohol solution and deionized water, respectively ultrasonically cleaning for 2-10min, and finally drying by using nitrogen; then placing the mixture in a Metal Organic Chemical Vapor Deposition (MOCVD) reaction chamber to grow n with the thickness of 25-35nm+-GaN；
(5) Will regrow n+Soaking the GaN wafer in HF acid solution for 1-5min to remove residual SiO2A layer;
(6) after SiO is removed2Performing source and drain electrode photoetching on the epitaxial wafer of the layer, depositing a metal layer with the work function of 4.2eV to form a source and drain electrode, and performing thermal annealing treatment;
(7) and performing gate photoetching on the annealed epitaxial wafer, and then depositing metal with the work function of 4.6eV to form a gate electrode, thereby finishing the manufacture of the whole device.
The invention has the following advantages:
1. the invention avoids the bad influence of the photoetching and etching process on the small graph by adopting the nanosphere mask, and simultaneously can realize the nano-level contact through hole and greatly increase n because the nanosphere has small diameter+The contact area of GaN with the channel reduces the contact resistance.
2. In the invention, n is adopted in the source-drain region+GaN regrowth allows the annealing temperature of the ohmic metal to be significantly lowered, reducing the lattice damage and thus the leakage current.
The technical solution and effect of the present invention can be further illustrated by the following drawings and examples.
Drawings
Fig. 1 is a schematic flow chart of the implementation of the invention.
Detailed Description
The invention is described in further detail below with reference to the attached drawing figures:
the invention is implemented on the existing AlGaN/GaN epitaxial wafer which comprises a sapphire substrate, an AlN nucleating layer, a GaN buffer layer and an AlGaN barrier layer from bottom to top, wherein the thickness of the sapphire substrate is 500 mu m, the thickness of the AlN nucleating layer is 20-100nm, the thickness of the GaN buffer layer is 0.5-2 mu m, and the thickness of the AlGaN barrier layer is 20-30 nm.
Referring to fig. 1, the present invention is given by the following three examples:
example 1 preparation of SiO2Layer thickness of 100nm, n+GaN-based high electron mobility transistors with a GaN source drain thickness of 25 nm:
step 1, cleaning the epitaxial wafer, as shown in fig. 1 (a).
And selecting an epitaxial wafer with an AlGaN/GaN structure, soaking the epitaxial wafer in an HF acid solution for 30s, then placing the epitaxial wafer in an acetone solution for ultrasonic cleaning for 7min, then placing the epitaxial wafer in an absolute ethyl alcohol solution for ultrasonic cleaning for 5min, then placing the epitaxial wafer in deionized water for ultrasonic cleaning for 2min, and finally blowing the epitaxial wafer by using nitrogen.
Step 2, depositing SiO2As shown in fig. 1 (b).
The cleaned epitaxial wafer is placed into a plasma enhanced chemical vapor deposition PECVD system at 250 deg.CDepositing 120nm thick SiO at a temperature of DEG C2。
And 3, manufacturing the source and drain region graphical nano through holes as shown in figures 1(c) - (e).
To deposit SiO2The ohmic region lithography is performed on the epitaxial wafer of (a), as shown in fig. 1 (c);
mixing the alumina nanospheres with water to form a suspension, and dripping the suspension on the SiO deposited layer by using a dropper2Placing the epitaxial wafer on a hot plate at 100 ℃ for drying water, and leaving nanospheres as an etching mask of a through hole pattern at a source-drain position, as shown in fig. 1 (d);
then the epitaxial wafer coated with the nanospheres is placed into a plasma etching machine, and SiO with the thickness of 100nm is etched2And a 20nm thick AlGaN barrier layer, as in fig. 1 (e).
Step 4, n+GaN regrowth, fig. 1 (f).
Putting the etched wafer into an acetone solution for ultrasonic cleaning for 5min, then putting the etched wafer into an absolute ethyl alcohol solution for ultrasonic cleaning for 5min, then putting the etched wafer into deionized water for ultrasonic cleaning for 5min, and finally blowing the etched wafer by nitrogen;
putting the cleaned wafer into a metal organic chemical vapor deposition MOCVD system, introducing a gallium source with the flow of 60 mu mol/min, silane with the flow of 15 mu mol/min, hydrogen with the flow of 1200sccm and ammonia with the flow of 3000sccm into a reaction chamber at the same time under the conditions that the pressure of the chamber is 40Torr and the temperature is 1000 ℃, and growing n with the thickness of 25nm+-GaN。
Step 5, removing SiO2Layer, as in FIG. 1 (g).
Will grow n+Soaking the GaN epitaxial wafer in HF acid solution for 2min, and blowing with nitrogen gas to remove residual SiO2And (3) a layer.
And 6, manufacturing a source electrode and a drain electrode, as shown in the figure 1 (h).
After removing the residual SiO2Photoetching a source drain region on the epitaxial wafer of the layer, and then putting the epitaxial wafer into an electron beam evaporation table to sequentially deposit Ti/Al/Ni/Au metal layers with the thicknesses of 40/140/25/50nm respectively;
and (3) placing the epitaxial wafer deposited with the source and drain metal into a thermal annealing furnace, and annealing at the temperature of 450 ℃ for 30s to form a source and drain electrode.
And 7, manufacturing a gate electrode, as shown in the figure 1 (i).
And performing gate photoetching on the annealed epitaxial wafer, putting the epitaxial wafer into an electron beam evaporation table, and sequentially depositing Ti/Au metal layers with the thicknesses of 50/100nm to form a gate electrode so as to finish the manufacture of the whole device.
Example 2 preparation of SiO2Layer thickness of 200nm, n+-GaN-based high electron mobility transistor with GaN source drain region thickness of 30 nm:
step one, the epitaxial wafer is cleaned, as shown in fig. 1 (a).
The specific implementation of this step is the same as step 1 of example 1.
Step two, depositing SiO2See FIG. 1(b)
Placing the cleaned epitaxial wafer into a plasma enhanced chemical vapor deposition PECVD system, and depositing SiO with the thickness of 200nm at the temperature of 300 DEG C2。
And step three, manufacturing the source drain region graphical nano through holes as shown in figures 1(c) - (e).
3a) To deposit SiO2The ohmic region lithography is performed on the epitaxial wafer of (a), as shown in fig. 1 (c);
3b) forming alumina nanosphere and water into suspension, and dripping on SiO deposited by dropper2Placing the epitaxial wafer on a hot plate at 100 ℃ for drying water, and leaving nanospheres as an etching mask of a through hole pattern at a source-drain position, as shown in fig. 1 (d);
3c) the epitaxial wafer coated with the nanospheres is placed into a plasma etcher to etch SiO with the thickness of 200nm2And 25nm thick AlGaN barrier layers, as in fig. 1 (e).
Step four, n+GaN regrowth, fig. 1 (f).
4a) Cleaning the etched wafer: putting the etched wafer into an acetone solution for ultrasonic cleaning for 5min, then putting the etched wafer into an absolute ethyl alcohol solution for ultrasonic cleaning for 5min, then putting the etched wafer into deionized water for ultrasonic cleaning for 2min, and finally blowing the etched wafer by nitrogen;
4b) putting the cleaned wafer into a Metal Organic Chemical Vapor Deposition (MOCVD) system, and keeping the pressure of a reaction chamber atUnder the conditions of 80Torr and 950 ℃, simultaneously introducing a gallium source with the flow rate of 100 mu mol/min, silane with the flow rate of 60 mu mol/min, hydrogen with the flow rate of 2000sccm and ammonia with the flow rate of 6000sccm into the reaction chamber, and growing n with the thickness of 30nm+-GaN。
Step five, removing SiO2Layer, as in FIG. 1 (g).
Will grow n+Soaking the GaN epitaxial wafer in HF acid solution for 4min, and blowing with nitrogen gas to remove residual SiO2And (3) a layer.
And sixthly, manufacturing a source electrode and a drain electrode, as shown in the figure 1 (h).
6a) After removing the residual SiO2Photoetching a source drain region on the epitaxial wafer of the layer, and then putting the epitaxial wafer into an electron beam evaporation table to sequentially deposit Ti/Al/Ni/Au metal layers with the thicknesses of 40/140/25/50nm respectively;
6b) and (3) placing the epitaxial wafer deposited with the source and drain metal into a thermal annealing furnace, and annealing at the temperature of 400 ℃ for 30s to form a source and drain electrode.
And step seven, manufacturing a gate electrode, as shown in fig. 1 (i).
And performing gate photoetching on the annealed epitaxial wafer, putting the epitaxial wafer into an electron beam evaporation table, and sequentially depositing Ti/Au metal layers with the thicknesses of 50/100nm to form a gate electrode so as to finish the manufacture of the whole device.
Example 3 preparation of SiO2Layer thickness of 300nm, n+GaN-based high electron mobility transistors with a GaN source drain thickness of 28 nm:
step A, cleaning the epitaxial wafer, as shown in FIG. 1 (a).
And selecting an epitaxial wafer with an AlGaN/GaN structure, soaking the epitaxial wafer in an HF acid solution for 30s, then placing the epitaxial wafer in an acetone solution for ultrasonic cleaning for 10min, then placing the epitaxial wafer in an absolute ethyl alcohol solution for ultrasonic cleaning for 5min, then placing the epitaxial wafer in deionized water for ultrasonic cleaning for 5min, and finally blowing the epitaxial wafer by using nitrogen.
Step B, depositing SiO2See FIG. 1(b)
Placing the cleaned epitaxial wafer into a plasma enhanced chemical vapor deposition PECVD system, and depositing 300nm SiO at 350 DEG C2。
And step C, manufacturing the source and drain region graphical nano through holes as shown in figures 1(C) - (e).
Firstly to deposit SiO2The ohmic region lithography is performed on the epitaxial wafer of (a), as shown in fig. 1 (c); mixing the alumina nanospheres with water to form a suspension, and dripping the suspension on the SiO deposited layer by using a dropper2Drying water on the epitaxial wafer at 100 ℃ on a hot plate, and leaving nanospheres as an etching mask of a through hole pattern at the source and drain positions, as shown in fig. 1 (d); then the epitaxial wafer coated with the nanospheres is placed into a plasma etcher to etch SiO with the thickness of 250nm2And 25nm thick AlGaN barrier layers, as in fig. 1 (e).
Step D, n+GaN regrowth, fig. 1 (f).
Firstly, cleaning the etched wafer in three steps: firstly, putting the etched wafer into an acetone solution for ultrasonic cleaning for 10min, secondly, putting the etched wafer into an absolute ethyl alcohol solution for ultrasonic cleaning for 5min, thirdly, putting the etched wafer into deionized water for ultrasonic cleaning for 5min, and finally, drying the etched wafer by using nitrogen;
then, the cleaned wafer is put into a metal organic chemical vapor deposition MOCVD system, and a gallium source with the flow rate of 40 mu mol/min, silane with the flow rate of 10 mu mol/min, hydrogen with the flow rate of 1000sccm and ammonia with the flow rate of 3000sccm are simultaneously introduced into a reaction chamber under the conditions that the pressure of the reaction chamber is 10Torr and the temperature is 1050 ℃, so that n with the thickness of 28nm is grown+-GaN。
Step E, removing SiO2Layer, as in FIG. 1 (g).
Will grow n+Soaking the GaN epitaxial wafer in HF acid solution for 5min, and blowing with nitrogen gas to remove residual SiO2And (3) a layer.
And F, manufacturing a source electrode and a drain electrode, as shown in figure 1 (h).
First, the remaining SiO is removed2Photoetching a source drain region on the epitaxial wafer of the layer, and then putting the epitaxial wafer into an electron beam evaporation table to sequentially deposit Ti/Al/Ni/Au metal layers with the thicknesses of 40/140/25/50nm respectively; and then, putting the epitaxial wafer deposited with the source and drain metal into a thermal annealing furnace, and annealing at the temperature of 500 ℃ for 30s to form a source and drain electrode.
And G, manufacturing a gate electrode, as shown in figure 1 (i).
And performing gate photoetching on the annealed epitaxial wafer, putting the epitaxial wafer into an electron beam evaporation table, depositing Ti with the thickness of 50nm, and depositing an Au metal layer with the thickness of 100nm to form a gate electrode, thereby finishing the manufacture of the whole device.
The foregoing description is only three specific examples of the present invention and should not be construed as limiting the invention in any way, and it will be apparent to those skilled in the art that various modifications and variations in form and detail can be made without departing from the principle and structure of the invention, but these modifications and variations will still fall within the scope of the appended claims.
Claims (4)
1. A method for preparing a low-ohmic contact GaN-based HEMT based on a nanosphere mask comprises the following steps:
(1) epitaxial wafer cleaning
Soaking an epitaxial wafer with an AlGaN/GaN structure in an HF acid solution for 30 times, sequentially placing the epitaxial wafer in an acetone solution, an absolute ethyl alcohol solution and deionized water, respectively ultrasonically cleaning for 2-10min, and then drying by using nitrogen;
(2) the cleaned epitaxial wafer is placed into a plasma enhanced chemical vapor deposition PECVD reaction chamber, and SiO with the thickness of 100-300nm is deposited at the temperature of 250-350 DEG C2；
(3) Manufacturing a source drain region graphical nano through hole:
(3a) on deposition of SiO2Carrying out source-drain region photoetching on the epitaxial wafer;
(3b) coating a layer of micro-nano alumina nanospheres on the epitaxial wafer after photoetching;
(3c) placing the epitaxial wafer coated with the nanospheres into a plasma etcher to etch off SiO at the source and drain electrodes2Etching AlGaN with the thickness of 20-30nm to form a source drain region graphical nano through hole embedded in the GaN layer;
(4)n+-GaN regrowth:
sequentially placing the epitaxial wafer etched with the source drain region nano through holes into an acetone solution, an absolute ethyl alcohol solution and deionized water, respectively ultrasonically cleaning for 2-10min, and finally drying by using nitrogen;then placing the mixture in a Metal Organic Chemical Vapor Deposition (MOCVD) reaction chamber to grow n with the thickness of 25-35nm+-GaN；
(5) Will regrow n+Soaking the GaN wafer in HF acid solution for 1-5min to remove residual SiO2A layer;
(6) after SiO is removed2Performing source and drain electrode photoetching on the epitaxial wafer of the layer, depositing a metal layer with the work function of 4.2eV to form a source and drain electrode, and performing thermal annealing treatment;
(7) and performing gate photoetching on the annealed epitaxial wafer, and then depositing metal with the work function of 4.6eV to form a gate electrode, thereby finishing the manufacture of the whole device.
2. The method of claim 1, wherein the micro-nano alumina nanospheres are coated on the photo-etched epitaxial wafer in (3b) by suspending the alumina nanospheres with water and dripping the suspension on the epitaxial wafer deposited with SiO by using a dropper2And placing the epitaxial wafer on a hot plate at 100 ℃ for drying water, and leaving the nanospheres as an etching mask of the through hole pattern at the source and drain positions.
3. The method of claim 1, wherein n is grown in (4) to a thickness of 25-35nm+-GaN, with the following process conditions:
pressure in the reaction chamber: 10-80 Torr;
temperature of the reaction chamber: 900 ℃ and 1100 ℃;
gallium source flow rate: 40-100 mu mol/min;
ammonia gas flow rate: 3000-6000 sccm;
hydrogen flow rate: 1000-;
silicon source flow rate: 10-60 mu mol/min;
doping concentration 8 × 1018cm-3-1×1020cm-3。
4. The method according to claim 1, wherein in (6), the thermal annealing treatment is carried out under the following process conditions:
annealing temperature: 400-500 ℃;
annealing time: for 30 s.
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