CN116259660A - E-HEMT epitaxial wafer and preparation method thereof - Google Patents
E-HEMT epitaxial wafer and preparation method thereof Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
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- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention discloses an E-HEMT epitaxial wafer which comprises a substrate, and a U-GaN buffer layer, a P-GaN layer, a U-GaN channel layer, an AlGaN barrier layer and a gate dielectric layer which are sequentially stacked on the substrate. The P-GaN layer is not positioned at the top layer of the epitaxial wafer, but is positioned below the AlGaN barrier layer and the U-GaN channel layer, so that the problem that the AlGaN barrier layer is damaged to influence the 2DEG due to inaccurate control of the P-GaN etching depth is avoided, and the reliability and the stability are improved. Meanwhile, the possibility of generating an extra leakage path on the side wall of the interface can be avoided, and the grid leakage is reduced.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an E-HEMT (enhanced high electron mobility transistor) epitaxial wafer and a preparation method thereof.
Background
In recent years, gaN-based high electron mobility transistors have received great attention in the field of power electronics because of the superior characteristics of GaN (gallium nitride) intrinsic materials and the advantages of high carrier areal density, high electron mobility, high breakdown field strength, low channel resistance, etc. of AlGaN (aluminum gallium nitride)/GaN heterogeneous materials composed of the same. Because the conventional GaN-based HEMT devices are all depletion mode devices, the conventional GaN-based HEMT devices can be directly applied to the field of power electronics, so that the complexity of circuit design can be increased, and the conversion power consumption can be increased. Therefore, the E-HEMT device is always a hotspot in the research of nitride devices, and in many applications, the E-HEMT device not only meets the failure mode of safety-failure, but also can simplify the circuit design and power loss caused by circuit use.
The HEMT epitaxial wafer is the basis for preparing HEMT devices, and the quality of the epitaxial wafer is one of key factors for determining the performance of the HEMT devices.
In the prior art, various technologies for realizing an E-HEMT device exist, such as a P-type gate technology, a concave gate structure, a Cascade structure, a fluoride ion treatment method, a thin barrier layer and the like. Among them, in addition to the P-type gate technology, conventional epitaxial wafers are mostly grown on a substrate with a buffer layer laminated with a channel layer and a barrier layer. The epitaxial wafer with the structure can introduce etching damage and interface states in the subsequent etching process, and the performance reliability of the device is seriously affected. The P-GaN type gate HEMT device is a promising enhanced HEMT device, and an E-HEMT epitaxial wafer structure used by the device comprises a substrate, and a buffer layer, a channel layer, a barrier layer and a P-GaN cap layer which are sequentially laminated on the substrate. However, when the P-GaN cap layer is etched, since the etching depth is difficult to precisely control, etching damage and interface states are also introduced, so that adverse effects are caused on the 2DEG (two-dimensional electron gas) at the interface between the P-GaN layer below and the barrier layer, and the epitaxial wafer based on the P-type gate technology has the same problems in performance and reliability.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an E-HEMT epitaxial wafer and a preparation method thereof.
The technical problems to be solved by the invention are realized by the following technical scheme:
an E-HEMT epitaxial wafer comprises a substrate, and a U-GaN buffer layer, a P-GaN layer, a U-GaN channel layer, an AlGaN barrier layer and a gate dielectric layer which are sequentially stacked on the substrate.
Preferably, the U-GaN buffer layer has a thickness of 3 μm to 8 μm and a carrier concentration of-2×10 16 cm -3 To-8×10 16 cm -3 。
Preferably, the thickness of the P-GaN layer is 0.5 μm to 2 μm, and the carrier concentration is 9×10 17 cm -3 Up to 3X 10 18 cm -3 。
Preferably, the thickness of the U-GaN channel layer is 50 nm-200 nm, and the carrier concentration is-3×10 16 cm -3 To-9×10 16 cm -3 。
Preferably, the thickness of the AlGaN barrier layer is 20 nm-28 nm, and the doping component of Al is controlled to be 20% -25%.
The invention also provides a preparation method of the E-HEMT epitaxial wafer, which comprises the following steps:
preparing a substrate;
growing U-GaN on the substrate to obtain a U-GaN buffer layer;
P-GaN is deposited on the U-GaN buffer layer, and a P-GaN layer is obtained;
growing U-GaN on the P-GaN layer to obtain a U-GaN channel layer;
AlGaN grows on the U-GaN channel layer to obtain an AlGaN barrier layer;
growing a gate dielectric on the AlGaN barrier layer to obtain a gate dielectric layer;
and carrying out annealing treatment on the current sample to obtain the prepared E-HEMT epitaxial wafer.
Preferably, the temperature range of growing the U-GaN channel layer is controlled at 1050-1150 ℃ or 1100-1180, and the growth time is 0.5-2 min;
the temperature range of growing the AlGaN barrier layer is controlled between 1000 ℃ and 1050 ℃ and the growth time is 5min to 8min.
Preferably, when the AlGaN barrier layer is grown, the gas flow rate of nitrogen serving as a carrier gas is controlled to be 95-105 slm, the gas flow rate of ammonia serving as a nitrogen source is controlled to be 10-20 slm, and the doping component of Al is controlled to be 20-25%.
Preferably, growing U-GaN on the substrate to obtain a U-GaN buffer layer, comprising:
growing a GaN nucleation sublayer on the substrate at a temperature ranging from 530 ℃ to 560 ℃;
annealing and recrystallizing the GaN nucleation layer at the temperature of 1000-1080 ℃;
and continuously growing GaN on the GaN nucleation sub-layer after annealing and recrystallization in the temperature range of 1050-1150 ℃ or 1100-1180 to obtain the U-GaN buffer layer.
Preferably, the temperature range of growing the P-GaN layer is controlled to 900-980 ℃ and the growing time is 100-120 min.
In the E-HEMT epitaxial wafer provided by the invention, the AlGaN barrier layer is positioned at the top of the device and is close to the gate dielectric layer, the P-GaN layer is positioned below the AlGaN barrier layer and the U-GaN channel layer, and is positioned between the U-GaN buffer layer and the U-GaN channel layer at the bottom of the device; therefore, under the influence of no external bias voltage, the P-GaN layer and the upper U-GaN channel layer form a P-N junction; according to the second law of thermodynamics, carriers automatically want to diffuse from a high concentration position to a low concentration position, so that a built-in electric field with the electric field direction pointing from N-GaN (AlGaN) to P-GaN is generated inside the device; the built-in electric field has a good depletion effect on the 2DEG at the interface of the AlGaN heterojunction and the U-GaN heterojunction, and prevents the 2DEG from further diffusion along with the balance of the carrier concentration, so that an electron trap rises above the Fermi level, and the device is effectively turned off under no external bias. In addition, as the AlGaN barrier layer is positioned at the top and the P-GaN layer is positioned below the AlGaN barrier layer, and the U-GaN channel layer is arranged between the AlGaN barrier layer and the P-GaN barrier layer, the problem that the concentration of the 2DEG is affected due to inaccurate control of the depth of etching the P-GaN cap layer in the prior art is solved.
In addition, the grid electrode of the E-HEMT device prepared on the basis of the E-HEMT epitaxial wafer is positioned on the grid electrode dielectric layer, and compared with the situation that the grid electrode of the P-GaN type grid HEMT device is positioned on etched P-GaN in the prior art, the E-HEMT device prepared on the basis of the E-HEMT epitaxial wafer is positioned on the grid electrode dielectric layer, the extra leakage path is not generated, and the possibility of grid electrode leakage of the device is reduced.
The present invention will be described in further detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic structural diagram of an E-HEMT epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a flowchart of a method for preparing an E-HEMT epitaxial wafer according to an embodiment of the present invention;
FIG. 3 is a topography of sample 1 prepared based on the method shown in FIG. 2;
FIG. 4 is an electron micrograph of sample 2 and sample 3 prepared based on the method shown in FIG. 2 under a magnification objective;
FIG. 5 is an Atomic Force Microscope (AFM) test chart of samples 1-3 prepared based on the method shown in FIG. 2.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
In order to solve the problem that the concentration of 2DEG is affected due to inaccurate control of the etching depth of a P-GaN cap layer in the prior art, the embodiment of the invention provides an E-HEMT epitaxial wafer; as shown in fig. 1, the E-HEMT epitaxial wafer includes: a substrate 10, and a U-GaN buffer layer 20, a P-GaN layer 30, a U-GaN channel layer 40, an AlGaN barrier layer 50, and a gate dielectric layer 60 sequentially stacked on the substrate 10.
It is understood that U-GaN refers to undoped GaN, and P-GaN layer refers to P-doped GaN.
Based on fig. 1, in the E-HEMT epitaxial wafer provided by the embodiment of the invention, the AlGaN barrier layer 50 is located at the top of the device close to the gate dielectric layer 60, while the P-GaN layer 30 is located below the AlGaN barrier layer 50 and the U-GaN channel layer 40 and between the U-GaN buffer layer 20 and the U-GaN channel layer 40 at the bottom of the device; thus, the P-GaN layer 30 and the upper U-GaN channel layer 40 form a P-N junction without the influence of external bias; according to the second law of thermodynamics, carriers automatically want to diffuse from a high concentration position to a low concentration position, so that a built-in electric field with the electric field direction pointing from N-GaN (AlGaN) to P-GaN is generated inside the device; the built-in electric field has a good depletion effect on two-dimensional electron gas at the interface of AlGaN and U-GaN heterojunction, and prevents the electron gas from further diffusing along with the balance of carrier concentration, so that an electron trap rises above a fermi level, and the device is effectively turned off without external bias. In addition, since the AlGaN barrier layer 50 is located at the top of the device, the P-GaN layer 30 is located below, and the U-GaN channel layer 40 is also spaced between the AlGaN barrier layer 50, the problem that the concentration of 2DEG is affected due to inaccurate control of the depth of etching the P-GaN cap layer in the prior art is solved.
In addition, according to the E-HEMT device prepared by the E-HEMT epitaxial wafer provided by the embodiment of the invention, the grid electrode is positioned on the grid electrode dielectric layer 60, compared with the situation that the grid electrode of the P-GaN type grid HEMT device is positioned on etched P-GaN in the prior art, after the P-GaN is etched in the prior art, the side wall of the interface can possibly generate an extra leakage path, and the grid electrode of the E-HEMT device prepared by the E-HEMT epitaxial wafer provided by the embodiment of the invention is positioned on the grid electrode dielectric layer 60, so that the extra leakage path can not be generated, and the possibility of grid electrode leakage of the device is reduced.
Preferably, the substrate 10 may include a (0001) plane sapphire substrate, although not limited thereto.
Preferably, the U-GaN buffer layer 20 may have a thickness of 3 μm to 8 μm and a carrier concentration of-2×10 16 cm -3 To-8×10 16 cm -3 。
Preferably, the thickness of the P-GaN layer 30 may be 0.5 μm to 2 μm with a carrier concentration of 9×10 17 cm -3 Up to 3X 10 18 cm -3 。
Preferably, the U-GaN channel layer 40 may have a thickness of 50nm to 200nm and a carrier concentration of-3×10 16 cm -3 To-9×10 16 cm -3 。
Preferably, the thickness of the AlGaN barrier layer 50 may be 20nm to 28nm, and the doping composition of Al thereof is controlled to be 20% -25%.
Preferably, the gate dielectric layer 60 may comprise SiO 2 (silicon oxide) gate dielectric layer, alN (aluminum nitride) gate dielectric or Si 3 N 4 A (silicon nitride) gate dielectric layer, etc. For example, gate dielectric layer 60 may be SiO with a thickness of 100nm 2 And a gate dielectric layer.
In one embodiment, based on the structure of the E-HEMT epitaxial wafer shown in fig. 1, by controlling the growth temperature, preheating time and gas flow of AlGaN and U-GAN, an AlGaN barrier layer 50 with better crystal quality and flatness can be obtained, and the surface roughness is lower, so that the polarization effect of the heterojunction in the device is stronger, thereby increasing the concentration and mobility of 2DEG in the device.
Specifically, when the U-GaN channel layer 40 is grown, the temperature range of the grown U-GaN channel layer 40 is controlled to 1050-1150 ℃ or 1100-1180 ℃ and the growth time is controlled to 0.5-2 min; correspondingly, when the AlGaN barrier layer 50 is grown, the temperature range of growing the AlGaN barrier layer 50 is controlled between 1000 ℃ and 1050 ℃ and the growth time is controlled between 5min and 8min. Therefore, the growth temperature of the AlGaN barrier layer is reduced, the preheating time for growth of the AlGaN barrier layer is increased, and the difference of growth conditions of the U-GaN channel layer and the AlGaN barrier layer is reduced. Since the thermal expansion coefficient of GaN is higher than that of AlGaN, the AlGaN receives larger tensile stress, so that the operation reduces the thermal stress generated by overlarge temperature difference, reduces the possibility of crack generation, and can effectively avoid the phenomenon that an epitaxial wafer generates larger cracks and cracks.
It should be noted that, when the temperature range of the grown U-GaN channel layer 40 is controlled between 1100 ℃ and 1180 ℃, the black spot coverage at the edge of the epitaxial wafer caused by threading dislocation generated during the growth of U-GaN can be effectively reduced, and the number of hexagonal defects in the wafer can be reduced.
In addition, when the AlGaN barrier layer 50 is grown, the flow rate of nitrogen gas as a carrier gas is controlled to 95 to 105slm, the flow rate of ammonia gas as a nitrogen source is controlled to 10 to 20slm, and the doping component of al is controlled to 20 to 25%. Thus, the AlGaN barrier layer 50 having a suitable thickness is grown by controlling the flow rates of the nitrogen gas and the ammonia gas in accordance with the growth time of the AlGaN barrier layer 50.
Corresponding to the E-HEMT epitaxial wafer, the embodiment of the invention also provides a preparation method of the E-HEMT epitaxial wafer, and the method adopts high-purity hydrogen (H) 2 ) And high purity nitrogen (N) 2 ) As carrier gas, high-purity ammonia (NH) 3 ) As a nitrogen source, trimethylgallium (TMGa) is used as a gallium source, trimethylaluminum (TMAl) is used as an aluminum source, and a Metal Organic Chemical Vapor Deposition (MOCVD) technology is used to sequentially grow a composite layer on a substrate, thereby forming an E-HEMT epitaxial wafer.
Referring to fig. 2, the preparation method of the E-HEMT epitaxial wafer provided by the embodiment of the invention comprises the following steps:
s1: a substrate is prepared.
Specifically, the temperature in the reaction cavity is raised to 1100-1150 ℃, the substrate is heated, and the reaction cavity is heated in H 2 And cleaning and purging the cavity for 5-10 min under the environment, so that the interior of the cavity reaches a proper environment to be grown.
The substrate may include a sapphire substrate, but is not limited thereto.
S2: and growing U-GaN on the substrate to obtain the U-GaN buffer layer.
The step S2 may specifically comprise the following sub-steps:
s21: and growing a GaN nucleation sublayer on the substrate at a temperature ranging from 530 ℃ to 560 ℃.
Specifically, following step S1, in step S21, the internal temperature of the reaction chamber is first reduced to 530-560 ℃, and the temperature is kept for 5min; and then introducing a gallium source and growing a GaN nucleation sublayer under the mixed gas atmosphere of nitrogen, hydrogen and ammonia at 530-560 ℃.
S22: and (3) annealing and recrystallizing the GaN nucleation layer at the temperature of 1000-1080 ℃.
Specifically, following step S21, the atmosphere of the mixed gas is closed, the temperature in the reaction cavity is raised to 1000-1080 ℃, and the temperature is kept for 6-8 min, so that the GaN nucleation layer is annealed and recrystallized.
S23: and continuously growing GaN on the GaN nucleation sub-layer after annealing and recrystallization in the temperature range of 1050-1150 ℃ or 1100-1180 ℃ to obtain the U-GaN buffer layer.
Specifically, in the following step S22, the atmosphere of the mixed gas is opened, the temperature in the reaction cavity is up-regulated to 1050-1150 ℃ or 1100-1180 ℃ within the temperature range, gaN continues to grow on the GaN nucleation sublayer after annealing and recrystallization, and the grown GaN is stacked on the basis of the GaN nucleation sublayer, so that the GaN grows from a two-dimensional form to a three-dimensional form, and the growth time is about 70-90 min, and the U-GaN buffer layer is obtained.
S3: and depositing P-GaN on the U-GaN buffer layer to obtain the P-GaN layer.
Specifically, following step S23, the temperature in the reaction chamber is reduced to 900-980 ℃, then P-GaN is grown on the U-GaN buffer layer for 100-120 min, and the P-GaN layer is obtained.
S4: and growing U-GaN on the P-GaN layer to obtain the U-GaN channel layer.
Specifically, following step S3, the temperature in the reaction chamber is again adjusted up to 1050-1150 ℃ or 1100-1180 ℃, and a layer of U-GaN is grown on the P-GaN layer for 0.5-2 min, so as to obtain the U-GaN channel layer.
S5: alGaN grows on the U-GaN channel layer to obtain an AlGaN barrier layer.
Specifically, following step S4, the temperature in the reaction chamber is adjusted down to 1000 ℃ to 1050 ℃, hydrogen is turned off, and an aluminum source is introduced in a mixed gas atmosphere of nitrogen and ammonia, wherein the gas flow of nitrogen serving as a carrier gas is controlled to be 95slm to 105slm, the gas flow of ammonia serving as a nitrogen source is controlled to be 10slm to 20slm, and the doping component of al is controlled to be 20% -25%. Thereby, a layer of AlGaN grows on the U-GaN channel layer, and the growth time is 5 min-8 min, so that the AlGaN barrier layer is obtained.
S6: and growing a gate dielectric on the AlGaN barrier layer to obtain a gate dielectric layer.
Specifically, following step S5, the temperature in the reaction chamber is adjusted down to 280 ℃, ammonia gas is closed, a layer of gate dielectric is grown on the AlGaN barrier layer in a nitrogen atmosphere, and the growth time is about 20min, so as to obtain a gate dielectric layer.
S7: and carrying out annealing treatment on the current sample to obtain the prepared E-HEMT epitaxial wafer.
Specifically, following step S6, maintaining nitrogen atmosphere, adjusting the temperature inside the reaction cavity to 750-800 ℃, and annealing the sample prepared in step S6 for 15-20 min in the temperature range to obtain the prepared E-HEMT epitaxial wafer.
According to the preparation method of the E-HEMT epitaxial wafer, provided by the embodiment of the invention, the AlGaN barrier layer with better crystal quality and flatness can be obtained by controlling the growth temperature, the preheating time and the gas flow of AlGaN and U-GAN, the surface roughness is lower, the polarization effect of a heterojunction in a device is stronger, and the concentration and the mobility of 2DEG in the device are increased.
Specifically, the main control means capable of achieving the above beneficial effects is mainly that in step S4, the temperature range of the grown U-GaN channel layer is controlled to 1050-1150 ℃ or 1100-1180 ℃ (preferably 1100-1180 ℃), and the growth time is 0.5-2 min; the corresponding temperature range of growing the AlGaN barrier layer in the step S50 is controlled at 1000-1050 ℃ and the growth time is 5-8 min, and the two steps are matched, so that the growth temperature of the AlGaN barrier layer is reduced, the growth preheating time of the AlGaN barrier layer is increased, the difference of growth conditions of the U-GaN channel layer and the AlGaN barrier layer is reduced, the thermal stress generated by overlarge temperature difference is reduced, the possibility of crack generation is reduced, and the phenomenon that an epitaxial wafer generates larger cracks and cracks can be effectively avoided. On the basis, in the step S5, the growth time of the AlGaN barrier layer is matched by controlling the gas flow rates of the nitrogen and the ammonia, so that the AlGaN barrier layer with proper thickness is grown.
In addition, when the temperature range of the grown U-GaN channel layer 40 is controlled to 1100 ℃ to 1180 ℃ in step S4, the black spot coverage at the edge of the epitaxial wafer caused by threading dislocation generated during the growth of U-GaN can be effectively reduced, and the number of hexagonal defects inside the wafer can be reduced.
In order to verify the effectiveness of the above process control means, 3 different epitaxial wafer samples were prepared using 3 different growth parameters, respectively, the specific growth parameters were as follows:
TABLE 1
Wherein, samples 2 and 3 are prepared according to the preparation method shown in fig. 2 and specific process parameters thereof, and the preparation flow of sample 1 is the same as that of fig. 2, except that the growth temperature, growth time, growth temperature of U-GaN, gas flow rate of ammonia gas, and gas flow rate of nitrogen gas are different from those of samples 2 and 3.
The morphology of the samples 1 to 3 was observed, and it was found that the part of the chips on the long disc of the sample 1 had cracks or even cracked, as shown in the sub-graph (a) of fig. 3. This phenomenon is mainly due to insufficient time in the preheating stage when the AlGaN barrier layer is grown, and the growth temperature of the AlGaN barrier layer is high, so that the thermal stress of the composite layer is increased, and cracking is generated. Fig. 3 (b) is a surface topography of sample 1 under a 20X magnification electron microscope, from which it is apparent that there are some protrusions on the surface of sample 1 and cracks caused by defects, indicating that the quality of sample 1 obtained under the growth parameters of sample 1 is poor.
In fig. 4, electron microscopy topography of sample 2 and sample 3 under a multiple objective is shown, wherein subplot (a) is the electron microscopy topography of sample 2 under a multiple objective of 10, subplot (b) is the electron microscopy topography of sample 2 under a multiple objective of 20, subplot (c) is the electron microscopy topography of sample 3 under a multiple objective of 10, and subplot (d) is the electron microscopy topography of sample 3 under a multiple objective of 20.
As can be seen from fig. 4, in the implementation of the present invention, by reducing the growth temperature of the AlGaN barrier layer 50, increasing the preheating time for growth, reducing the difference of growth conditions of the GaN layer and the AlGaN layer, effectively improving the phenomenon of cracking or cracking of the epitaxial wafer, and the prepared samples 2 and 3 have no more scratches on the surface of the macroscopic layer, have smooth mirror surfaces and have few cracks.
Furthermore, as can be seen from the sub-graph (a) in fig. 4, the surface of the sample 2 has small black spots densely distributed at the edge position, which is distributed at a distance of 4 to 5cm from the edge position, and the surface black spots decrease as moving toward the center region of the sample. It has been found that the formation of such dark spots is related to threading dislocation generated during growth of the bottom U-GaN channel layer, and has a large relationship with growth temperature and intra-cavity pressure. The eddy current in the reaction chamber is easy to cause uneven heating temperature, and the growth temperature of the central area of the wafer is higher than that of the edge area, so that the growth coverage rate of the central area of the wafer is more sufficient, the defect density is relatively low, and the number of black spots is relatively small. Therefore, on the basis of the technological parameters of the sample 2, the growth temperature of the U-GaN is increased by about 30 ℃, namely, the growth temperature of the U-GaN is controlled to be 1100-1180 ℃, so that the sample 3 is prepared according to the process. As can be seen from the graphs (c) and (d) in fig. 4, after raising the growth temperature of U-GaN by 30 ℃, the number of black spots at the edge of the epitaxial wafer is significantly reduced, the coverage is about 1cm from the edge, and the number of hexagonal defects inside the wafer is significantly reduced.
FIG. 5 is an Atomic Force Microscope (AFM) test chart of samples 1 to 3. Wherein, the sub-graphs (a 1) to (a 3) are respectively a surface topography map in a 15×5 μm range, a surface topography map in a2×2 μm range and a 3D topography map of the sample, the sub-graphs (b 1) to (b 3) are respectively a surface topography map in a 15×5 μm range, a surface topography map in a2×2 μm range and a 3D topography map of the sample 2, and the sub-graphs (c 1) to (c 3) are respectively a surface topography map in a 15×5 μm range, a surface topography map in a2×2 μm range and a 3D topography map of the sample 3. R in FIG. 4 q The roughness root mean square value of the sample test area is shown.
From the sub-graphs (a 1) and (a 2) of fig. 5, white scratches can be seen, since the surface of sample 1 is rough, thereby affecting the test probe. In addition, sample 1 had significant black holes on the surface of the corrugated AlGaN material, because the growth conditions resulted in poor or even incomplete growth of the local area of the sample.
As can be seen from the sub-graphs (b 1) and (b 2) of fig. 5, the modified sample 2 has fewer surface defects, is smoother and has fewer holes. And, R of 5X 5 μm and 2X 2 μm regions of comparative sample 1 q It was found that sample 2 had a roughness root mean square value less than sample 1, which is indicativeThe surface of the sample 2 is smoother and smoother, the roughness is lower, and the preparation of a later device is facilitated.
As can be seen from the graphs (c 1) and (c 2) of FIG. 5, the surface wave texture of sample 3 is relatively uniform, which indicates good growth of the material, R in both graphs q The surface roughness is reduced to a certain extent by 0.203nm and 0.146nm respectively.
Furthermore, as can be seen by comparing the sub-graphs (a 3), (b 3), (c 3) of fig. 5, the uniformity of the surface of sample 3 is significantly improved.
The test results of fig. 3 to 5 show that the growth rate of the U-GaN is increased, the surface coverage is increased, and the density of threading dislocation is reduced by increasing the growth temperature of the U-GaN in the embodiment of the present invention.
In addition, in order to verify the improvement effect of the embodiment of the present invention on the two-dimensional electron gas concentration and mobility of the AlGaN barrier layer and the U-GaN channel layer, a portion of the AlGaN barrier layer of samples 1 to 3 was etched by an inductively coupled plasma etching technique (ICP), the ICP etching rate was 2.5 to 3nm/s, and the 2DEG mobility (cm 2/Vs) in the samples was tested using a hall tester, and the test results are shown in table 2:
TABLE 2
The 2DEG mobility of the three samples was compared and found to decrease and then increase with increasing etching time. When etching for 8 s-10 s, the etching depth is about 20 nm-30 nm, and the etching depth is in the area at the interface of AlGaN and U-GaN, and belongs to the area with more two-dimensional electron gas distribution. It can be seen that the minimum 2DEG mobility of sample 3 can reach 36.5cm2/Vs, indicating that sample 3 has lower defects at this time, and the underlying P-N junction can better deplete the two-dimensional electron gas at the interface.
In addition, by performing XRD (X-Ray diffraction) test on samples 1 to 3, it was found that the (0002) plane full width at half maximum, that is, ga plane full width at half maximum, of the AlGaN barrier layer of sample 3 was minimum, which indicates that the crystallinity of sample 3 was optimal, and the test results are shown in table 3:
TABLE 3 Table 3
In summary, in the E-HEMT epitaxial wafer prepared by the preparation method of the E-HEMT epitaxial wafer provided by the embodiment of the invention, the AlGaN barrier layer is positioned at the position where the top of the device is close to the gate dielectric layer, and the P-GaN layer is positioned below the AlGaN barrier layer and the U-GaN channel layer and between the U-GaN buffer layer and the U-GaN channel layer at the bottom of the device; therefore, under the influence of no external bias voltage, the P-GaN layer and the upper U-GaN channel layer form a P-N junction; according to the second law of thermodynamics, carriers automatically want to diffuse from a high concentration position to a low concentration position, so that a built-in electric field with the electric field direction pointing from N-GaN (AlGaN) to P-GaN is generated inside the device; the built-in electric field has a good depletion effect on the 2DEG at the interface of the AlGaN heterojunction and the U-GaN heterojunction, and prevents the 2DEG from further diffusion along with the balance of the carrier concentration, so that an electron trap rises above the Fermi level, and the device is effectively turned off under no external bias. In addition, as the AlGaN barrier layer is positioned at the top and the P-GaN layer is positioned below the AlGaN barrier layer, and the U-GaN channel layer is arranged between the AlGaN barrier layer and the P-GaN barrier layer, the problem that the concentration of the 2DEG is affected due to inaccurate control of the depth of etching the P-GaN cap layer in the prior art is solved.
In addition, in the preparation method of the E-HEMT epitaxial wafer provided by the embodiment of the invention, the AlGaN barrier layer with better crystal quality and flatness can be obtained by controlling the growth temperature, the preheating time and the gas flow of AlGaN and U-GaN, the surface roughness is lower, the polarization effect of the heterojunction in the device can be stronger, and the concentration and the mobility of the 2DEG in the device are increased
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings and the disclosure. In the description of the present invention, the word "comprising" does not exclude other elements or steps, the "a" or "an" does not exclude a plurality, and the "a" or "an" means two or more, unless specifically defined otherwise. Moreover, some measures are described in mutually different embodiments, but this does not mean that these measures cannot be combined to produce a good effect.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (10)
1. The E-HEMT epitaxial wafer is characterized by comprising a substrate, and a U-GaN buffer layer, a P-GaN layer, a U-GaN channel layer, an AlGaN barrier layer and a gate dielectric layer which are sequentially stacked on the substrate.
2. The E-HEMT epitaxial wafer according to claim 1, wherein the U-GaN buffer layer has a thickness of 3 μm to 8 μm and a carrier concentration of-2 x 10 16 cm -3 To-8×10 16 cm -3 。
3. The E-HEMT epitaxial wafer according to claim 1, wherein the P-GaN layer has a thickness of 0.5 μm to 2 μm and a carrier concentration of 9 x 10 17 cm -3 Up to 3X 10 18 cm -3 。
4. The E-HEMT epitaxial wafer according to claim 1, wherein the U-GaN channel layer has a thickness of 50nm to 200nm and a carrier concentration of-3 x 10 16 cm -3 To-9×10 16 cm -3 。
5. The E-HEMT epitaxial wafer of claim 1, wherein the AlGaN barrier layer has a thickness of 20nm to 28nm and a doping composition of al is controlled to 20% to 25%.
6. The preparation method of the E-HEMT epitaxial wafer is characterized by comprising the following steps of:
preparing a substrate;
growing U-GaN on the substrate to obtain a U-GaN buffer layer;
P-GaN is deposited on the U-GaN buffer layer, and a P-GaN layer is obtained;
growing U-GaN on the P-GaN layer to obtain a U-GaN channel layer;
AlGaN grows on the U-GaN channel layer to obtain an AlGaN barrier layer;
growing a gate dielectric on the AlGaN barrier layer to obtain a gate dielectric layer;
and carrying out annealing treatment on the current sample to obtain the prepared E-HEMT epitaxial wafer.
7. The method for producing an E-HEMT epitaxial wafer according to claim 6, wherein,
the temperature range of growing the U-GaN channel layer is controlled to be 1050-1150 ℃ or 1100-1180, and the growing time is 0.5-2 min;
the temperature range of growing the AlGaN barrier layer is controlled between 1000 ℃ and 1050 ℃ and the growth time is 5min to 8min.
8. The method according to claim 7, wherein the flow rate of nitrogen gas as a carrier gas is controlled to be 95 to 105slm, the flow rate of ammonia gas as a nitrogen source is controlled to be 10 to 20slm, and the doping component of al is controlled to be 20 to 25% when the AlGaN barrier layer is grown.
9. The method for preparing the E-HEMT epitaxial wafer according to claim 6, wherein the step of growing U-GaN on the substrate to obtain the U-GaN buffer layer comprises the following steps:
growing a GaN nucleation sublayer on the substrate at a temperature ranging from 530 ℃ to 560 ℃;
annealing and recrystallizing the GaN nucleation layer at the temperature of 1000-1080 ℃;
and continuously growing GaN on the GaN nucleation sub-layer after annealing and recrystallization in the temperature range of 1050-1150 ℃ or 1100-1180 to obtain the U-GaN buffer layer.
10. The method for preparing an E-HEMT epitaxial wafer according to claim 6, wherein the temperature range for growing the P-GaN layer is controlled to be 900-980 ℃ and the growth time is 100-120 min.
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