CN101203947A - Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate - Google Patents
Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate Download PDFInfo
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- CN101203947A CN101203947A CNA2006800221845A CN200680022184A CN101203947A CN 101203947 A CN101203947 A CN 101203947A CN A2006800221845 A CNA2006800221845 A CN A2006800221845A CN 200680022184 A CN200680022184 A CN 200680022184A CN 101203947 A CN101203947 A CN 101203947A
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- gate electrode
- method comprises
- source drain
- formation
- stop layer
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 37
- 239000002184 metal Substances 0.000 title claims abstract description 37
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- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 10
- 150000004706 metal oxides Chemical class 0.000 title abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 35
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- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract 2
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- 238000005240 physical vapour deposition Methods 0.000 description 4
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- 239000000243 solution Substances 0.000 description 4
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
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- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 238000002242 deionisation method Methods 0.000 description 2
- 229910000449 hafnium oxide Inorganic materials 0.000 description 2
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 2
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 239000011133 lead Substances 0.000 description 2
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- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
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- IATRAKWUXMZMIY-UHFFFAOYSA-N strontium oxide Chemical compound [O-2].[Sr+2] IATRAKWUXMZMIY-UHFFFAOYSA-N 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
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- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910052580 B4C Inorganic materials 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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- PXNDALNSUJQINT-UHFFFAOYSA-N [Sc].[Ta] Chemical compound [Sc].[Ta] PXNDALNSUJQINT-UHFFFAOYSA-N 0.000 description 1
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- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
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- INAHAJYZKVIDIZ-UHFFFAOYSA-N boron carbide Chemical compound B12B3B4C32B41 INAHAJYZKVIDIZ-UHFFFAOYSA-N 0.000 description 1
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- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
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- 229910000464 lead oxide Inorganic materials 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910001510 metal chloride Inorganic materials 0.000 description 1
- 239000012702 metal oxide precursor Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
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- 229910052757 nitrogen Inorganic materials 0.000 description 1
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- 238000007254 oxidation reaction Methods 0.000 description 1
- YEXPOXQUZXUXJW-UHFFFAOYSA-N oxolead Chemical compound [Pb]=O YEXPOXQUZXUXJW-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
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- 239000010948 rhodium Substances 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- CZXRMHUWVGPWRM-UHFFFAOYSA-N strontium;barium(2+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Sr+2].[Ba+2] CZXRMHUWVGPWRM-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- OCGWQDWYSQAFTO-UHFFFAOYSA-N tellanylidenelead Chemical compound [Pb]=[Te] OCGWQDWYSQAFTO-UHFFFAOYSA-N 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- -1 yittrium oxide Chemical compound 0.000 description 1
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to a complementary metal oxide semiconductor integrated circuit may be formed with a PMOS device formed using a replacement metal gate and a raised source drain. The raised source drain may be formed of epitaxially deposited silicon germanium material that is doped p-type. The replacement metal gate process results in a metal gate electrode and may involve the removal of a nitride etch stop layer.
Description
Background technology
The present invention relates generally to the manufacturing of integrated circuit.
In the CMOS technology, in order to improve NMOS and the transistorized performance of PMOS deep-submicron, prior art is used compression in the transistorized raceway groove of PMOS, and pair nmos transistor then uses tension stress.
Use the prior art of strained-channel to be subjected to a lot of restrictions.For example in the PMOS device, may produce the depletion of polysilicon effect.In addition, in the PMOS device stretching strain may take place.Remaining stretching strain reduces the hole mobility of PMOS device.
Therefore, need a kind of manufacturing process of better CMOS (Complementary Metal Oxide Semiconductor), particularly a kind of process that can improve the PMOS device performance.
The accompanying drawing summary
Fig. 1 is the sectional view that is in the transistorized amplification of PMOS of making initial stage;
Fig. 2 is the sectional view that is in the transistorized amplification of PMOS of next fabrication stage;
Fig. 3 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 2 according to an embodiment of the invention;
Fig. 4 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 3 according to an embodiment of the invention;
Fig. 5 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 4 according to an embodiment of the invention;
Fig. 6 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 5 according to an embodiment of the invention;
Fig. 7 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 6 according to an embodiment of the invention;
Fig. 8 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 7 according to an embodiment of the invention;
Fig. 9 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 8 according to an embodiment of the invention;
Figure 10 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 9 according to an embodiment of the invention;
Figure 11 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 10 according to an embodiment of the invention;
Figure 12 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 11 according to an embodiment of the invention;
Figure 13 is the sectional view of the transistorized amplification of PMOS in the next stage that is in the fabrication stage shown in Figure 12 according to an embodiment of the invention;
Figure 14 has shown the embodiment of a nmos pass transistor, and this nmos pass transistor is used for using with PMOS transistor as shown in figure 13 according to an embodiment of the invention.
Describe in detail
The complementary transistorized manufacturing of a pair of PMOS is shown in Fig. 1-13 and carry out.In one embodiment, in NMOS side and PMOS side on these two, can deposition of silica gate oxide 105.This gate oxide 105 can by grid material 104 for example polysilicon cover, and then covered, to be used to generate pattern (patterning) by hard mask 130.Grid material 104 and gate dielectric (gate dielectric) 105 then, for example oxide is generated pattern, to produce the structure shown in Figure 1 on the PMOS side 10a.It is thick that gate dielectric may be about 15 dusts, and can carry out the heat growth in one embodiment.
Most advanced and sophisticated that mix or a little impure source drain electrode (source drain) 60 can adopt grid structure to form as mask.Can use ion implantation to form source drain 60.
When grid material 104 comprises polysilicon, and hard mask 130 is when comprising silicon nitride, and the structure among Fig. 1 can be made by following method.On substrate 100, form the pseudo-dielectric layer (for example by traditional hot growth technique) that may comprise silicon dioxide, then on dielectric layer, form polysilicon layer (for example by traditional depositing operation).Utilize traditional deposition technique, silicon nitride layer is formed on the polysilicon layer.Silicon nitride, polysilicon and pseudo-dielectric layer (dummydielectric layer) are generated pattern, with the silicon nitride layer that forms patterning, the polysilicon layer of patterning, and the dielectric layer of patterning.When dielectric layer is made of silicon dioxide, can uses conventional engraving method and come polysilicon and pseudo-dielectric layer are carried out patterning.
Nitrogen insolated layer materials 134 can be deposited up (Fig. 2), and is anisotropically carried out etching, forms sidewall spacers (spacer) 108,109, sees Fig. 3.Separator 108,109 can reach the thickness of the 1000 dust orders of magnitude.
Raceway groove (trench) 24 is formed in the substrate 100, sees Fig. 4.Raceway groove 24 can form by the reactive ion etching that utilizes the SF6 chemical agent.Be etched on the side and suppressed, and in one embodiment, on opposite side, roughly isotropically grid structure is not carried out undercutting by dielectric layer 20.Therefore can on the inward flange of raceway groove 24, produce isotropic etching outline, see Fig. 4, and stay a part by impure source drain electrode 60 a little.In this step, NMOS side 10b may oxide mask (not shown) cover.
Then, can growing epitaxial SiGe source drain 40, it has been filled raceway groove 24 and has extended thereon as illustrated in fig. 5.Raceway groove 24 can be filled with the SiGe of the germanium that contains the 10-40 atomic percent.Can mix by the in-situ doped source drain that carries out that utilizes diborane source.40 growths in raceway groove 24 of this epitaxial source drain electrode are because all other material is all by masked or covered.This source drain 40 raises and continued growth is joined up to face (facet).In certain embodiments, can then use source drain to inject.
As shown in Figure 6, after the mask of NMOS side is removed, can cover the structure of Fig. 3 with dielectric layer 112, dielectric layer 112 for example is the etch stopper (NESL) 120 of the lower material of dielectric constant such as oxide and nitride.This layer 112 can mix phosphorus, boron or other material, and it can be formed by the plasma-deposited of high concentration.This dielectric layer 112 can flattened (planarize) be reduced to the upper surface of grid material 104 then, thereby hard mask 130 and NESL120 are removed, as shown in Figure 7.This layer 120 can be a nitride.It assists the NMOS side as etch stopper and shell of tension, but may PMOS side 10a performance be reduced owing to having produced strain.Therefore the NESL120 of PMOS side is removed, can improve performance.
As shown in Figure 8, can remove grid material 104 and on remaining gate oxide 105, form raceway groove 113.Remove grid material 104 and can realize that for example the grid material with respect to nmos pass transistor carries out optionally etching to grid material 104, perhaps shelters nmos pass transistor in technical process shown in Figure 8 by a lot of methods.
Remove grid material 104, produce the raceway groove 113 between sidewall spacers 108,109, thereby produce structure as shown in Figure 8.In one embodiment, wet etch process is optionally to the material 104 that is positioned on the corresponding N MOS transistor material (not shown), can remove material 104 by adopting said method, and can not remove the major part of NMOS material.
In certain embodiments, can selectively remove this layer 104.In one embodiment, layer 104 is exposed in the aqueous solution that has comprised the deionization of by volume calculating about Tetramethylammonium hydroxide of 20% to 30% (TMAH) with adequate time and sufficient temperature (for example being about 60 ℃ to 90 ℃), application of sonic energy is removed all layers 106, can not remove the major part of any nmos pass transistor structure (not shown) simultaneously.
As alternative, can use dry-etching method and optionally remove layer 104.When grid layer 104 is doped P-type (for example having boron), a kind of like this dry-etching method can comprise: the gate electrode layer 104 of sacrifice property is exposed to is derived from sulphur hexafluoride (" SF
6In the plasma of "), hydrogen bromide (" HBr "), hydrogen iodide (" HI "), chlorine, argon and/or helium.Optionally dry-etching method like this can carry out in parallel metal sheet reactor or electron cyclotron resonace etcher.
After removing material 104, remove dielectric layer 105.When dielectric layer 105 was made up of silicon dioxide, dielectric layer 105 can utilize etch process and remove, and this etch process can optionally produce structure shown in Figure 9 for silicon dioxide.Such etch process comprises: layer 105 is exposed in hydrofluoric acid (HF) aqueous solution that contains 1% the deionization of having an appointment, or uses the dry etching process that uses based on the plasma of fluorocarbon.Layer 105 may only expose the limited time, because remove the dielectric layer 112 that the etching process procedure of layer 105 also can be removed a part.Remove layer 105 if should be kept in mind that the solution that utilizes based on 1%HF, the time that this device is exposed in the solution can not surpass about 60 seconds, for example about 30 seconds or still less.If layer 105 is thick less than about 30 dusts when initial deposition, then can removes layer 105, and not remove the dielectric layer 112 of main amount.
Next, the parallel planesization of going forward side by side that new gate dielectric 114 depositions can be got on, to obtain the U-shaped shape, its opening 113 comes into line, as shown in figure 10.Although gate dielectric 114 can comprise any material (wherein gate dielectric is used to include the PMOS transistor of metal gate electrode) that can be used as gate dielectric, but gate dielectric 114 can comprise that dielectric constant is greater than 10 high dielectric constant (k) metal oxide dielectric section material.Some materials that can be used for making the gate dielectric 114 of high k value comprise: hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum and lead niobate zinc.Especially the metal oxide of Shi Yonging comprises hafnium oxide, zirconia and aluminium oxide.Although described the example that some can be used for forming the metal oxide of high-K gate utmost point dielectric layer 114 here,, this dielectric layer also can form by other metal oxide.
Utilize traditional deposition process, for example traditional chemical vapour deposition (CVD) (" CVD "), low pressure chemical vapor deposition or physical vapour deposition (PVD) (" PVD ") technology can be formed at high-K gate utmost point dielectric layer 114 on the substrate 100.Preferably utilize traditional atomic layer CVD technology.In this technology, metal oxide precursor (for example metal chloride) and steam are introduced in the CVD reactor with selected flow velocity, reactor moves under chosen temperature and pressure, to be created in (atomically) level and smooth interface on the atomic level between substrate 100 and high-K gate utmost point dielectric layer 114.The CVD reactor should move time enough, forms the layer with desired thickness.In most application scenario, high-K gate utmost point dielectric layer 114 can be for example thick less than about 60 dusts, and thickness is that about 5 dusts are to about 40 dusts in one embodiment.
When atomic layer CVD process quilt is used for forming the gate dielectric 114 of high k value, except in the bottom of raceway groove 113, this layer also will be formed on the vertical side of raceway groove.If high-K gate utmost point dielectric layer 114 comprises oxide, so it may be from the teeth outwards at random place oxide space (oxygen vacancy) and unwelcome impure degree (this depends on its manufacturing process) appear.May after layer 114 deposition, remove its impurity, and, have the metal of near idealization on the chemical equivalent with generation: the metal oxide layer of oxide ratio its oxidation.
In order to remove impurity and to improve its oxygen content, can carry out wet-chemical treatment to high-K gate utmost point dielectric layer 114 from this layer.This wet-chemical treatment can comprise: under enough temperature, the gate dielectric 114 of high k value is exposed to comprises in the solution that hydrogen peroxide forms and reach sufficient a period of time, with the impurity of removal high-K gate utmost point dielectric layer 114, and the oxygen content of raising high-K gate utmost point dielectric layer 114.High-K gate utmost point dielectric layer 114 is exposed to appropriate time and temperature wherein, can be decided by thickness and other character of desirable high-K gate utmost point dielectric layer 114.
When the solution that the gate dielectric 114 of high k value is exposed to based on hydrogen peroxide, can use by volume to calculate to contain about 2% to about 30% aqueous hydrogen peroxide solution.This exposing step can occur between about 15 ℃ to about 40 ℃, minimum about one minute of time.In a particularly preferred embodiment, the gate dielectric 114 of high k value being exposed to temperature is that about 25 ℃ calculating by volume contains 6.7%H approximately
2O
2The aqueous solution in reach about 10 minutes time.In this exposing step, wish frequency of utilization at about 10KHz to about 2000KHz and with about 1Watts/cm
2To about 10Watts/cm
2The acoustic energy that dissipates.In one embodiment, can applying frequency be the acoustic energy of about 1000KHz with the 5Watts/cm2 dissipation.
P type metal level 115 can produce by filling raceway groove 113.P type metal level 115 can comprise any P-type conduction material, can bear metal PMOS gate electrode by this P-type conduction material, and it makes raceway groove produce compressive strain for this purpose.The thermal coefficient of expansion of P type metal level may be greater than substrate 100 (for example silicon).The example of the metal that is fit to comprises the silicide of boron carbide, tungsten, molybdenum, rhodium, vanadium, platinum, ruthenium, beryllium, palladium, cobalt, titanium, nickel, copper, tin, aluminium, lead, zinc, alloy and these materials.In one embodiment, use the thermal coefficient of expansion (0.4 * 10 of thermal coefficient of expansion greater than tungsten
-5In./in./℃) material be favourable.Higher relatively depositing temperature, can produce compressive strain with in certain embodiments, and improve animal migration by for example 400 ℃ in conduit.P type metal level 115 preferably has thermal stability property, so that it is suitable for making the metal PMOS gate electrode of semiconductor device.
The material that can be used for forming P type metal level 115 comprises: the metal oxide of ruthenium, palladium, platinum, cobalt, nickel and conduction, for example ruthenium-oxide.The metal of layer 115 can be identical or different with the metal ingredient of metal-oxide dielectric layer 105.P type metal level 115 can utilize well-known PVD or CVD technology, and for example traditional sputter or atomic layer CVD technology form on gate dielectric 105.Except the place of filling raceway groove 113, other P type metal level 115 parts all are removed.Layer 115 can be operated from the other parts of device and remove by wet etching or dry etching process or suitable CMP, and dielectric section 112 stops structure as etching or polishing simultaneously.
P type metal level 115 can compensate the threshold voltage shift that the source drain 40 raised by SiGe is brought.Can regulate or select the work function of this metal level 115, to compensate the threshold voltage shift that must cause owing to using the source drain of raising 40.In general, the source drain of raising 40 causes the rising of valence, and has reduced threshold voltage.Therefore, crack metal (mid-gap metal) is as layer 115 in wishing to use, and its work function can compensate the drift of threshold voltage.
P type metal level 115 can be that about 4.9eV arrives the metal PMOS gate electrode between about 5.2eV as work function, and can have for example about 10 dusts to the thickness between about 2000 dusts, and its thickness is that about 500 dusts are between about 1600 dusts in one embodiment.
Then, structure shown in Figure 13 can be finished by forming silicide contacts portion 46 and nitride etch stop layer 42.Can after forming, contact site 46 provide nitride etch stop layer 42.
In some embodiments of the invention, the source drain 40 that epitaxial sige is raised makes the PMOS raceway groove produce compressive strain, so that improve mobility and reduce outside impedance.This can be achieved like this in certain embodiments, and is promptly in-situ doped by with boron source drain 40 being carried out, and injects (hole injection) for the hole and reduce the superfine energy barrier of Xiao, thereby improves contact resistance.
During polysilicon opening polishing (Fig. 7) and/or being used to form the etching of nitride etch stop layer 42 of contact site, replacement metal gate process can reduce exhausting of polysilicon.And be released in stretching strain in the PMOS device simultaneously.Stretching strain by minimizing reduces hole mobility can help the PMOS device.
Can adjust and replace gate electrode 115, being used for PMOS transistor (when using or not using high dielectric constant (greater than 10) dielectric section or gate dielectric 114), to eliminate exhausting and reducing the grid leakage of polysilicon.Flow through in the journey in replacement metal gate, polishing on PMOS device 10a and/or the NESL120 that has removed stretching strain can improve the mobility of PMOS.
See Figure 14, the manufacturing of nmos pass transistor 10b is carried out according to traditional technology.
For example, nmos pass transistor 10b can have into the joint portion of gradient, and the joint portion of this one-tenth gradient comprises shallow tip/source/drain 39 and dark source drain 22, and it can inject by ion and make.Can introduce or not introduce strain in certain embodiments.In certain embodiments, grid 37 is replacement metal gate, and may adopt traditional polysilicon gate in further embodiments.Grid 37 can be covered by silicide contacts portion 38.NESL120 can be retained in NMOS side 10b.
Although invention has been described for the embodiment only by limited quantity, those skilled in the art can therefrom figure out a large amount of modifications and variations.Appended claim is intended to comprise that all these fall into the modifications and variations in the spirit and scope of the present invention.
Claims (20)
1. method comprises:
Form replacement metal gate; And
The P type source drain that formation is raised.
2. method according to claim 1 is characterized in that, described method comprises and forms dielectric constant greater than 10 gate dielectric.
3. method according to claim 1 is characterized in that, described method comprises formation dummy poly gate electrode, removes described dummy poly gate electrode selectively, and utilizes metal gate electrode to replace described dummy poly gate electrode.
4. method according to claim 1 is characterized in that, described method comprises that formation is positioned at the nitride etch stop layer on the described dummy poly gate electrode.
5. method according to claim 4 is characterized in that, described method comprises the described nitride etch stop layer of removing on the PMOS side that is positioned at complementary structure.
6. method according to claim 5 is characterized in that, described method comprises formation U-shaped gate dielectric.
7. semiconductor structure comprises:
Substrate, described substrate have the P type source drain of raising; And
Metal gate electrode.
8. structure according to claim 7 is characterized in that, the described source drain of raising is formed by silicon and germanium.
9. structure according to claim 7 is characterized in that described structure comprises the U-shaped gate electrode.
10. structure according to claim 7 is characterized in that, described structure comprises that dielectric constant is greater than 10 gate electrode.
11. a method comprises:
Form pseudo-gate electrode;
Utilize nitride etch stop layer to cover described pseudo-gate electrode;
Remove described nitride etch stop layer;
Remove described pseudo electrode, and replace described pseudo electrode with metal gate electrode; And
Form the P type source drain of extension.
12. method according to claim 11 is characterized in that, described method comprises the source drain that formation is raised.
13. method according to claim 11 is characterized in that, described method comprises and forms dielectric constant greater than 10 gate dielectric.
14. method according to claim 11 is characterized in that, described method comprises formation U type gate dielectric.
15. method according to claim 11 is characterized in that, described method comprises the described source drain of raising that forms P type doped silicon germanium.
16. method according to claim 11 is characterized in that, described method is included in and forms described nitride etch stop layer on the hard mask.
17. method according to claim 11 is characterized in that, described method comprises the described pseudo-gate electrode that forms polysilicon.
18. method according to claim 11 is characterized in that, described method comprises the formation CMOS integrated circuit.
19. method according to claim 11 is characterized in that, described method comprises utilizes metal gate electrode to make mask and etch in the Semiconductor substrate, and by dopant deposition the SiGe epitaxial material of boron form described P type source drain.
20. method according to claim 11 is characterized in that, described method comprises from the PMOS structure denitrify etch stopper that gets on, and keeps described nitride etch stop layer simultaneously on the NMOS structure.
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PCT/US2006/024517 WO2007002427A1 (en) | 2005-06-21 | 2006-06-21 | Complementary metal oxide semiconductor integrated circuit using raised source drain and replacement metal gate |
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---|---|---|---|---|
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Families Citing this family (144)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060086977A1 (en) | 2004-10-25 | 2006-04-27 | Uday Shah | Nonplanar device with thinned lower body portion and method of fabrication |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US7547637B2 (en) | 2005-06-21 | 2009-06-16 | Intel Corporation | Methods for patterning a semiconductor film |
US7902008B2 (en) * | 2005-08-03 | 2011-03-08 | Globalfoundries Inc. | Methods for fabricating a stressed MOS device |
US8101485B2 (en) | 2005-12-16 | 2012-01-24 | Intel Corporation | Replacement gates to enhance transistor strain |
US7439120B2 (en) * | 2006-08-11 | 2008-10-21 | Advanced Micro Devices, Inc. | Method for fabricating stress enhanced MOS circuits |
US7416931B2 (en) * | 2006-08-22 | 2008-08-26 | Advanced Micro Devices, Inc. | Methods for fabricating a stress enhanced MOS circuit |
US20080050879A1 (en) * | 2006-08-23 | 2008-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of forming metal-containing gate structures |
US7442601B2 (en) * | 2006-09-18 | 2008-10-28 | Advanced Micro Devices, Inc. | Stress enhanced CMOS circuits and methods for their fabrication |
US8304342B2 (en) * | 2006-10-31 | 2012-11-06 | Texas Instruments Incorporated | Sacrificial CMP etch stop layer |
US20080124874A1 (en) * | 2006-11-03 | 2008-05-29 | Samsung Electronics Co., Ltd. | Methods of Forming Field Effect Transistors Having Silicon-Germanium Source and Drain Regions |
JP5380827B2 (en) | 2006-12-11 | 2014-01-08 | ソニー株式会社 | Manufacturing method of semiconductor device |
KR100825809B1 (en) * | 2007-02-27 | 2008-04-29 | 삼성전자주식회사 | Semiconductor device structure with strain layer and method for fabrication of the same |
US7642603B2 (en) * | 2007-06-29 | 2010-01-05 | Intel Corporation | Semiconductor device with reduced fringe capacitance |
JP5165954B2 (en) * | 2007-07-27 | 2013-03-21 | セイコーインスツル株式会社 | Semiconductor device |
DE102007041207B4 (en) * | 2007-08-31 | 2015-05-21 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | CMOS device with gate insulation layers of different type and thickness and method of manufacture |
DE102007046849B4 (en) * | 2007-09-29 | 2014-11-06 | Advanced Micro Devices, Inc. | Method of making large-gate-gate structures after transistor fabrication |
US7955909B2 (en) * | 2008-03-28 | 2011-06-07 | International Business Machines Corporation | Strained ultra-thin SOI transistor formed by replacement gate |
US7838366B2 (en) * | 2008-04-11 | 2010-11-23 | United Microelectronics Corp. | Method for fabricating a metal gate structure |
US8362566B2 (en) * | 2008-06-23 | 2013-01-29 | Intel Corporation | Stress in trigate devices using complimentary gate fill materials |
US8008145B2 (en) * | 2008-09-10 | 2011-08-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | High-K metal gate structure fabrication method including hard mask |
US7994014B2 (en) * | 2008-10-10 | 2011-08-09 | Advanced Micro Devices, Inc. | Semiconductor devices having faceted silicide contacts, and related fabrication methods |
US7768074B2 (en) * | 2008-12-31 | 2010-08-03 | Intel Corporation | Dual salicide integration for salicide through trench contacts and structures formed thereby |
JP5668277B2 (en) * | 2009-06-12 | 2015-02-12 | ソニー株式会社 | Semiconductor device |
DE102009039521B4 (en) * | 2009-08-31 | 2018-02-15 | Globalfoundries Dresden Module One Llc & Co. Kg | Improved filling conditions in an exchange gate process using a tensioned topcoat |
US20110140229A1 (en) * | 2009-12-16 | 2011-06-16 | Willy Rachmady | Techniques for forming shallow trench isolation |
US8211772B2 (en) | 2009-12-23 | 2012-07-03 | Intel Corporation | Two-dimensional condensation for uniaxially strained semiconductor fins |
US8368052B2 (en) * | 2009-12-23 | 2013-02-05 | Intel Corporation | Techniques for forming contacts to quantum well transistors |
US20110149667A1 (en) * | 2009-12-23 | 2011-06-23 | Fatih Hamzaoglu | Reduced area memory array by using sense amplifier as write driver |
US8283653B2 (en) * | 2009-12-23 | 2012-10-09 | Intel Corporation | Non-planar germanium quantum well devices |
DE102009055392B4 (en) * | 2009-12-30 | 2014-05-22 | Globalfoundries Dresden Module One Limited Liability Company & Co. Kg | Semiconductor component and method for producing the semiconductor device |
TWI487070B (en) * | 2010-07-05 | 2015-06-01 | United Microelectronics Corp | Method of fabricating complementary metal-oxide-semiconductor (cmos) device |
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KR20120019214A (en) * | 2010-08-25 | 2012-03-06 | 삼성전자주식회사 | Semiconductor integrated circuit device |
US8558279B2 (en) | 2010-09-23 | 2013-10-15 | Intel Corporation | Non-planar device having uniaxially strained semiconductor body and method of making same |
US8629426B2 (en) * | 2010-12-03 | 2014-01-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Source/drain stressor having enhanced carrier mobility manufacturing same |
US8647952B2 (en) | 2010-12-21 | 2014-02-11 | Globalfoundries Inc. | Encapsulation of closely spaced gate electrode structures |
DE102011004322B4 (en) * | 2011-02-17 | 2012-12-06 | Globalfoundries Dresden Module One Llc & Co. Kg | A method of manufacturing a semiconductor device having self-aligned contact elements and an exchange gate electrode structure |
US8574990B2 (en) | 2011-02-24 | 2013-11-05 | United Microelectronics Corp. | Method of manufacturing semiconductor device having metal gate |
US8361854B2 (en) | 2011-03-21 | 2013-01-29 | United Microelectronics Corp. | Fin field-effect transistor structure and manufacturing process thereof |
US8519487B2 (en) | 2011-03-21 | 2013-08-27 | United Microelectronics Corp. | Semiconductor device |
US8802524B2 (en) | 2011-03-22 | 2014-08-12 | United Microelectronics Corp. | Method of manufacturing semiconductor device having metal gates |
US8614152B2 (en) | 2011-05-25 | 2013-12-24 | United Microelectronics Corp. | Gate structure and a method for forming the same |
US8772860B2 (en) | 2011-05-26 | 2014-07-08 | United Microelectronics Corp. | FINFET transistor structure and method for making the same |
US8432002B2 (en) * | 2011-06-28 | 2013-04-30 | International Business Machines Corporation | Method and structure for low resistive source and drain regions in a replacement metal gate process flow |
US8383485B2 (en) * | 2011-07-13 | 2013-02-26 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial process for forming semiconductor devices |
US9184100B2 (en) | 2011-08-10 | 2015-11-10 | United Microelectronics Corp. | Semiconductor device having strained fin structure and method of making the same |
US9105660B2 (en) | 2011-08-17 | 2015-08-11 | United Microelectronics Corp. | Fin-FET and method of forming the same |
US8853013B2 (en) | 2011-08-19 | 2014-10-07 | United Microelectronics Corp. | Method for fabricating field effect transistor with fin structure |
US8674433B2 (en) | 2011-08-24 | 2014-03-18 | United Microelectronics Corp. | Semiconductor process |
US8691651B2 (en) | 2011-08-25 | 2014-04-08 | United Microelectronics Corp. | Method of forming non-planar FET |
US8441072B2 (en) | 2011-09-02 | 2013-05-14 | United Microelectronics Corp. | Non-planar semiconductor structure and fabrication method thereof |
US8497198B2 (en) | 2011-09-23 | 2013-07-30 | United Microelectronics Corp. | Semiconductor process |
US8426277B2 (en) | 2011-09-23 | 2013-04-23 | United Microelectronics Corp. | Semiconductor process |
DE112011105751B4 (en) | 2011-10-18 | 2024-05-08 | Intel Corporation | Antifuse element using non-planar topology |
US8722501B2 (en) | 2011-10-18 | 2014-05-13 | United Microelectronics Corp. | Method for manufacturing multi-gate transistor device |
US8575708B2 (en) | 2011-10-26 | 2013-11-05 | United Microelectronics Corp. | Structure of field effect transistor with fin structure |
US8871575B2 (en) | 2011-10-31 | 2014-10-28 | United Microelectronics Corp. | Method of fabricating field effect transistor with fin structure |
US8278184B1 (en) | 2011-11-02 | 2012-10-02 | United Microelectronics Corp. | Fabrication method of a non-planar transistor |
US8426283B1 (en) | 2011-11-10 | 2013-04-23 | United Microelectronics Corp. | Method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate |
US8440511B1 (en) | 2011-11-16 | 2013-05-14 | United Microelectronics Corp. | Method for manufacturing multi-gate transistor device |
US8604548B2 (en) | 2011-11-23 | 2013-12-10 | United Microelectronics Corp. | Semiconductor device having ESD device |
CN103137488B (en) * | 2011-12-01 | 2015-09-30 | 中国科学院微电子研究所 | Semiconductor device and method for manufacturing the same |
US8803247B2 (en) | 2011-12-15 | 2014-08-12 | United Microelectronics Corporation | Fin-type field effect transistor |
US8698199B2 (en) | 2012-01-11 | 2014-04-15 | United Microelectronics Corp. | FinFET structure |
US9698229B2 (en) | 2012-01-17 | 2017-07-04 | United Microelectronics Corp. | Semiconductor structure and process thereof |
US8946031B2 (en) | 2012-01-18 | 2015-02-03 | United Microelectronics Corp. | Method for fabricating MOS device |
US20130181265A1 (en) | 2012-01-18 | 2013-07-18 | Globalfoundries Inc. | Methods of Forming a Gate Cap Layer Above a Replacement Gate Structure and a Semiconductor Device That Includes Such a Gate Structure and Cap Layer |
US8664060B2 (en) | 2012-02-07 | 2014-03-04 | United Microelectronics Corp. | Semiconductor structure and method of fabricating the same |
US8822284B2 (en) | 2012-02-09 | 2014-09-02 | United Microelectronics Corp. | Method for fabricating FinFETs and semiconductor structure fabricated using the method |
US9159809B2 (en) | 2012-02-29 | 2015-10-13 | United Microelectronics Corp. | Multi-gate transistor device |
US9006107B2 (en) | 2012-03-11 | 2015-04-14 | United Microelectronics Corp. | Patterned structure of semiconductor device and fabricating method thereof |
US9159626B2 (en) | 2012-03-13 | 2015-10-13 | United Microelectronics Corp. | FinFET and fabricating method thereof |
US8946078B2 (en) | 2012-03-22 | 2015-02-03 | United Microelectronics Corp. | Method of forming trench in semiconductor substrate |
US9559189B2 (en) | 2012-04-16 | 2017-01-31 | United Microelectronics Corp. | Non-planar FET |
US9142649B2 (en) | 2012-04-23 | 2015-09-22 | United Microelectronics Corp. | Semiconductor structure with metal gate and method of fabricating the same |
US8766319B2 (en) | 2012-04-26 | 2014-07-01 | United Microelectronics Corp. | Semiconductor device with ultra thin silicide layer |
US8709910B2 (en) | 2012-04-30 | 2014-04-29 | United Microelectronics Corp. | Semiconductor process |
US8691652B2 (en) | 2012-05-03 | 2014-04-08 | United Microelectronics Corp. | Semiconductor process |
US8877623B2 (en) * | 2012-05-14 | 2014-11-04 | United Microelectronics Corp. | Method of forming semiconductor device |
US8470714B1 (en) | 2012-05-22 | 2013-06-25 | United Microelectronics Corp. | Method of forming fin structures in integrated circuits |
US9012975B2 (en) | 2012-06-14 | 2015-04-21 | United Microelectronics Corp. | Field effect transistor and manufacturing method thereof |
US8796695B2 (en) | 2012-06-22 | 2014-08-05 | United Microelectronics Corp. | Multi-gate field-effect transistor and process thereof |
US8969163B2 (en) * | 2012-07-24 | 2015-03-03 | International Business Machines Corporation | Forming facet-less epitaxy with self-aligned isolation |
US8872280B2 (en) | 2012-07-31 | 2014-10-28 | United Microelectronics Corp. | Non-planar FET and manufacturing method thereof |
JP2014038738A (en) * | 2012-08-13 | 2014-02-27 | Sumitomo Heavy Ind Ltd | Cyclotron |
US9281359B2 (en) * | 2012-08-20 | 2016-03-08 | Infineon Technologies Ag | Semiconductor device comprising contact trenches |
US8962407B2 (en) * | 2012-08-28 | 2015-02-24 | Globalfoundries Inc. | Method and device to achieve self-stop and precise gate height |
US9318567B2 (en) | 2012-09-05 | 2016-04-19 | United Microelectronics Corp. | Fabrication method for semiconductor devices |
US9159831B2 (en) | 2012-10-29 | 2015-10-13 | United Microelectronics Corp. | Multigate field effect transistor and process thereof |
US8835237B2 (en) | 2012-11-07 | 2014-09-16 | International Business Machines Corporation | Robust replacement gate integration |
US9029208B2 (en) | 2012-11-30 | 2015-05-12 | International Business Machines Corporation | Semiconductor device with replacement metal gate and method for selective deposition of material for replacement metal gate |
US8877604B2 (en) * | 2012-12-17 | 2014-11-04 | International Business Machines Corporation | Device structure with increased contact area and reduced gate capacitance |
CN103915385B (en) | 2013-01-08 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | CMOS transistor and forming method thereof, fin formula field effect transistor and forming method thereof |
US9536792B2 (en) | 2013-01-10 | 2017-01-03 | United Microelectronics Corp. | Complementary metal oxide semiconductor field effect transistor, metal oxide semiconductor field effect transistor and manufacturing method thereof |
US9076870B2 (en) | 2013-02-21 | 2015-07-07 | United Microelectronics Corp. | Method for forming fin-shaped structure |
US8841197B1 (en) | 2013-03-06 | 2014-09-23 | United Microelectronics Corp. | Method for forming fin-shaped structures |
US9059217B2 (en) | 2013-03-28 | 2015-06-16 | International Business Machines Corporation | FET semiconductor device with low resistance and enhanced metal fill |
US9196500B2 (en) | 2013-04-09 | 2015-11-24 | United Microelectronics Corp. | Method for manufacturing semiconductor structures |
US9711368B2 (en) | 2013-04-15 | 2017-07-18 | United Microelectronics Corp. | Sidewall image transfer process |
US8853015B1 (en) | 2013-04-16 | 2014-10-07 | United Microelectronics Corp. | Method of forming a FinFET structure |
US8709901B1 (en) | 2013-04-17 | 2014-04-29 | United Microelectronics Corp. | Method of forming an isolation structure |
US9147747B2 (en) | 2013-05-02 | 2015-09-29 | United Microelectronics Corp. | Semiconductor structure with hard mask disposed on the gate structure |
US9000483B2 (en) | 2013-05-16 | 2015-04-07 | United Microelectronics Corp. | Semiconductor device with fin structure and fabrication method thereof |
US9263287B2 (en) | 2013-05-27 | 2016-02-16 | United Microelectronics Corp. | Method of forming fin-shaped structure |
US8802521B1 (en) | 2013-06-04 | 2014-08-12 | United Microelectronics Corp. | Semiconductor fin-shaped structure and manufacturing process thereof |
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US9070710B2 (en) | 2013-06-07 | 2015-06-30 | United Microelectronics Corp. | Semiconductor process |
US8993384B2 (en) | 2013-06-09 | 2015-03-31 | United Microelectronics Corp. | Semiconductor device and fabrication method thereof |
US9401429B2 (en) | 2013-06-13 | 2016-07-26 | United Microelectronics Corp. | Semiconductor structure and process thereof |
US9263282B2 (en) | 2013-06-13 | 2016-02-16 | United Microelectronics Corporation | Method of fabricating semiconductor patterns |
US9123810B2 (en) | 2013-06-18 | 2015-09-01 | United Microelectronics Corp. | Semiconductor integrated device including FinFET device and protecting structure |
US9048246B2 (en) | 2013-06-18 | 2015-06-02 | United Microelectronics Corp. | Die seal ring and method of forming the same |
US9190291B2 (en) | 2013-07-03 | 2015-11-17 | United Microelectronics Corp. | Fin-shaped structure forming process |
US9105685B2 (en) | 2013-07-12 | 2015-08-11 | United Microelectronics Corp. | Method of forming shallow trench isolation structure |
US9093565B2 (en) | 2013-07-15 | 2015-07-28 | United Microelectronics Corp. | Fin diode structure |
US9019672B2 (en) | 2013-07-17 | 2015-04-28 | United Microelectronics Corporation | Chip with electrostatic discharge protection function |
US8981487B2 (en) | 2013-07-31 | 2015-03-17 | United Microelectronics Corp. | Fin-shaped field-effect transistor (FinFET) |
US9006805B2 (en) | 2013-08-07 | 2015-04-14 | United Microelectronics Corp. | Semiconductor device |
US9105582B2 (en) | 2013-08-15 | 2015-08-11 | United Microelectronics Corporation | Spatial semiconductor structure and method of fabricating the same |
US9385048B2 (en) | 2013-09-05 | 2016-07-05 | United Microelectronics Corp. | Method of forming Fin-FET |
US9373719B2 (en) | 2013-09-16 | 2016-06-21 | United Microelectronics Corp. | Semiconductor device |
US9018066B2 (en) | 2013-09-30 | 2015-04-28 | United Microelectronics Corp. | Method of fabricating semiconductor device structure |
US9166024B2 (en) | 2013-09-30 | 2015-10-20 | United Microelectronics Corp. | FinFET structure with cavities and semiconductor compound portions extending laterally over sidewall spacers |
US9306032B2 (en) | 2013-10-25 | 2016-04-05 | United Microelectronics Corp. | Method of forming self-aligned metal gate structure in a replacement gate process using tapered interlayer dielectric |
US8980701B1 (en) | 2013-11-05 | 2015-03-17 | United Microelectronics Corp. | Method of forming semiconductor device |
US9299843B2 (en) | 2013-11-13 | 2016-03-29 | United Microelectronics Corp. | Semiconductor structure and manufacturing method thereof |
US8951884B1 (en) | 2013-11-14 | 2015-02-10 | United Microelectronics Corp. | Method for forming a FinFET structure |
US9397177B2 (en) | 2013-11-25 | 2016-07-19 | Globalfoundries Inc. | Variable length multi-channel replacement metal gate including silicon hard mask |
CN104752215B (en) * | 2013-12-30 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
US9425099B2 (en) | 2014-01-16 | 2016-08-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Epitaxial channel with a counter-halo implant to improve analog gain |
US9224814B2 (en) | 2014-01-16 | 2015-12-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Process design to improve transistor variations and performance |
US9419136B2 (en) * | 2014-04-14 | 2016-08-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dislocation stress memorization technique (DSMT) on epitaxial channel devices |
US9812323B2 (en) | 2014-09-08 | 2017-11-07 | Internaitonal Business Machines Corporation | Low external resistance channels in III-V semiconductor devices |
US9484255B1 (en) | 2015-11-03 | 2016-11-01 | International Business Machines Corporation | Hybrid source and drain contact formation using metal liner and metal insulator semiconductor contacts |
US9741577B2 (en) | 2015-12-02 | 2017-08-22 | International Business Machines Corporation | Metal reflow for middle of line contacts |
FR3048816B1 (en) * | 2016-03-09 | 2018-04-13 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | METHOD FOR MANUFACTURING DEVICE WITH VOLTAGE CONSTANT NMOS TRANSISTOR AND PMOS TRANSISTOR CONSTRAINED IN UNI-AXIAL COMPRESSION |
US9806170B1 (en) | 2016-05-11 | 2017-10-31 | Globalfoundries Inc. | Differential SG/EG spacer integration with equivalent NFET/PFET spacer widths and dual raised source drain expitaxial silicon and triple-nitride spacer integration enabling high-voltage EG device on FDSOI |
US10269714B2 (en) | 2016-09-06 | 2019-04-23 | International Business Machines Corporation | Low resistance contacts including intermetallic alloy of nickel, platinum, titanium, aluminum and type IV semiconductor elements |
US9960078B1 (en) | 2017-03-23 | 2018-05-01 | International Business Machines Corporation | Reflow interconnect using Ru |
KR102414182B1 (en) * | 2017-06-29 | 2022-06-28 | 삼성전자주식회사 | Semiconductor device |
US10672649B2 (en) | 2017-11-08 | 2020-06-02 | International Business Machines Corporation | Advanced BEOL interconnect architecture |
US10541199B2 (en) | 2017-11-29 | 2020-01-21 | International Business Machines Corporation | BEOL integration with advanced interconnects |
US11948981B2 (en) * | 2021-07-15 | 2024-04-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Seam-filling of metal gates with Si-containing layers |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5376578A (en) | 1993-12-17 | 1994-12-27 | International Business Machines Corporation | Method of fabricating a semiconductor device with raised diffusions and isolation |
US6638829B1 (en) | 1998-11-25 | 2003-10-28 | Advanced Micro Devices, Inc. | Semiconductor structure having a metal gate electrode and elevated salicided source/drain regions and a method for manufacture |
US6737716B1 (en) * | 1999-01-29 | 2004-05-18 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
KR100307636B1 (en) | 1999-10-07 | 2001-11-02 | 윤종용 | FET device having elevated source/drain and method for fabricating with partial facet control |
KR100333372B1 (en) | 2000-06-21 | 2002-04-19 | 박종섭 | Method of manufacturing metal gate mosfet device |
JP2002026310A (en) | 2000-06-30 | 2002-01-25 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
US6787424B1 (en) * | 2001-02-09 | 2004-09-07 | Advanced Micro Devices, Inc. | Fully depleted SOI transistor with elevated source and drain |
US6770521B2 (en) * | 2001-11-30 | 2004-08-03 | Texas Instruments Incorporated | Method of making multiple work function gates by implanting metals with metallic alloying additives |
US6504214B1 (en) | 2002-01-11 | 2003-01-07 | Advanced Micro Devices, Inc. | MOSFET device having high-K dielectric layer |
US6620664B2 (en) | 2002-02-07 | 2003-09-16 | Sharp Laboratories Of America, Inc. | Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same |
JP3654285B2 (en) | 2002-10-04 | 2005-06-02 | セイコーエプソン株式会社 | Manufacturing method of semiconductor device |
US6908850B2 (en) | 2003-09-10 | 2005-06-21 | International Business Machines Corporation | Structure and method for silicided metal gate transistors |
US6939751B2 (en) * | 2003-10-22 | 2005-09-06 | International Business Machines Corporation | Method and manufacture of thin silicon on insulator (SOI) with recessed channel |
KR100514166B1 (en) * | 2004-01-20 | 2005-09-13 | 삼성전자주식회사 | Method of forming cmos |
US7413957B2 (en) * | 2004-06-24 | 2008-08-19 | Applied Materials, Inc. | Methods for forming a transistor |
US7479684B2 (en) * | 2004-11-02 | 2009-01-20 | International Business Machines Corporation | Field effect transistor including damascene gate with an internal spacer structure |
-
2005
- 2005-06-21 US US11/159,430 patent/US7569443B2/en active Active
-
2006
- 2006-06-21 CN CN2006800221845A patent/CN101203947B/en active Active
- 2006-06-21 DE DE112006001705T patent/DE112006001705B4/en active Active
- 2006-06-21 WO PCT/US2006/024517 patent/WO2007002427A1/en active Application Filing
-
2009
- 2009-06-29 US US12/493,291 patent/US8148786B2/en active Active
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US20060286729A1 (en) | 2006-12-21 |
DE112006001705T5 (en) | 2008-05-08 |
US8148786B2 (en) | 2012-04-03 |
WO2007002427A1 (en) | 2007-01-04 |
US7569443B2 (en) | 2009-08-04 |
US20090261391A1 (en) | 2009-10-22 |
CN101203947B (en) | 2010-10-06 |
DE112006001705B4 (en) | 2009-07-02 |
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