US7138323B2 - Planarizing a semiconductor structure to form replacement metal gates - Google Patents

Planarizing a semiconductor structure to form replacement metal gates Download PDF

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US7138323B2
US7138323B2 US10900582 US90058204A US7138323B2 US 7138323 B2 US7138323 B2 US 7138323B2 US 10900582 US10900582 US 10900582 US 90058204 A US90058204 A US 90058204A US 7138323 B2 US7138323 B2 US 7138323B2
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layer
metal
sacrificial
gate
high
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US20060022277A1 (en )
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Jack Kavalieros
Justin K. Brask
Mark L. Doczy
Uday Shah
Chris E. Barns
Matthew V. Metz
Suman Datta
Robert S. Chau
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Intel Corp
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Intel Corp
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Abstract

A sacrificial gate structure, including nitride and fill layers, may be replaced with a metal gate electrode. The metal gate electrode may again be covered with a nitride layer covered by a fill layer. The replacement of the nitride and fill layers may reintroduce strain and provide an etch stop.

Description

BACKGROUND

The present invention relates to methods for making semiconductor devices, in particular, semiconductor devices with metal gate electrodes.

MOS field-effect transistors with very thin gate dielectrics made from silicon dioxide may experience unacceptable gate leakage currents. Forming the gate dielectric from certain high dielectric constant (K) dielectric materials, instead of silicon dioxide, can reduce gate leakage. As used herein, high-k dielectric means having a dielectric constant higher than 10. When, however, a high-k dielectric film is initially formed, it may have a slightly imperfect molecular structure. To repair such a film, it may be necessary to anneal it at a relatively high temperature.

Because such a high-k dielectric layer may not be compatible with polysilicon, it may be desirable to use metal gate electrodes in devices that include high-k gate dielectrics. When making a CMOS device that includes metal gate electrodes, it may be necessary to make the NMOS and PMOS gate electrodes from different materials. A replacement gate process may be used to form gate electrodes from different metals. In that process, a first polysilicon layer, bracketed by a pair of spacers, is removed selectively to a second polysilicon layer to create a trench between the spacers. The trench is filled with a first metal. The second polysilicon layer is then removed, and replaced with a second metal that differs from the first metal.

Thus, there is a need for alternate ways to form replacement metal gate electrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A–1R represent cross-sections of structures that may be formed when carrying out an embodiment of the present invention.

Features shown in these figures are not intended to be drawn to scale.

DETAILED DESCRIPTION

FIGS. 1A–1R illustrate structures that may be formed when carrying out an embodiment of the method of the present invention. Initially, high-k gate dielectric layer 170 and a sacrificial metal layer 169 are formed on substrate 100, generating the FIG. 1A structure. Alternatively, although not shown, a dummy gate dielectric (e.g. a 20–30 Angstroms SiO2 layer) may be carried through this portion of the flow and replaced by a high K dielectric at the time of the replacement gate process. Substrate 100 may comprise a bulk silicon or silicon-on-insulator substructure. Alternatively, substrate 100 may comprise other materials—which may or may not be combined with silicon—such as: germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Although a few examples of materials from which substrate 100 may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present invention.

Some of the materials that may be used to make high-k gate dielectric layer 170 include: hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. Particularly preferred are hafnium oxide, zirconium oxide, titanium oxide and aluminum oxide. Although a few examples of materials that may be used to form high-k gate dielectric layer 170 are described here, that layer may be made from other materials that serve to reduce gate leakage. The layer 170 has a dielectric constant higher than 10 and from 15 to 25 in one embodiment of the present invention.

High-k gate dielectric layer 170 may be formed on substrate 100 using a conventional deposition method, e.g., a conventional chemical vapor deposition (“CVD”), low pressure CVD, or physical vapor deposition (“PVD”) process. Preferably, a conventional atomic layer CVD process is used. In such a process, a metal oxide precursor (e.g., a metal chloride) and steam may be fed at selected flow rates into a CVD reactor, which is then operated at a selected temperature and pressure to generate an atomically smooth interface between substrate 100 and high-k gate dielectric layer 170. The CVD reactor should be operated long enough to form a layer with the desired thickness. In most applications, high-k gate dielectric layer 170 may be less than about 60 Angstroms thick, for example, and, in one embodiment, between about 5 Angstroms and about 40 Angstroms thick.

A sacrificial metal layer 169 may be formed over the dielectric layer 170. The sacrificial metal layer 169 may be any metal that is capable of withstanding high temperatures (greater than 450° C.) without reaction with overlying materials. As one example, the sacrificial metal layer 169 may be formed of titanium nitride. In one embodiment, the layer 169 may be formed by sputtering. In another embodiment, the layer 169 may be formed by atomic layer deposition.

After high-k gate dielectric layer 170 and sacrificial metal layer 169 are formed on substrate 100, sacrificial layer 171 is formed on high-k gate dielectric layer 170 as shown in FIG. 1B. In this embodiment, hard mask layer 172 is then formed on sacrificial layer 171, generating the FIG. 1B structure. Sacrificial layer 171 may comprise polysilicon, silicon nitride, silicon germanium, or germanium and may be deposited on sacrificial metal layer 169 using a conventional deposition process. Sacrificial layer 171 may be, for example, between about 100 and about 2,000 Angstroms thick, and, in one embodiment, between about 500 and about 1,600 Angstroms thick. In another embodiment, sacrificial layer 171 may be formed on a dummy gate dielectric, which is later replaced at the time of gate replacement.

Hard mask layer 172 may comprise silicon nitride between about 100 and about 1000 Angstroms thick, for example, and between about 200 and about 350 Angstroms thick in one embodiment. Hard mask layer 172 may be formed on sacrificial layer 171.

Sacrificial layer 171 and hard mask layer 172 are then patterned to form patterned hard mask layers 130, 131, and patterned sacrificial layers 104, 106, and 169—as FIG. 1C illustrates. Conventional wet or dry etch processes may be used to remove unprotected parts of hard mask layer 172, sacrificial metal layer 169 and sacrificial layer 171. In this embodiment, after those layers have been etched, exposed part 174 of high-k gate dielectric layer 170 is removed.

Although exposed part 174 of high-k gate dielectric layer 170 may be removed using dry or wet etch techniques, it may be difficult to etch that layer using such processes without adversely affecting adjacent structures. It may be difficult to etch high-k gate dielectric layer 170 selectively to the underlying substrate using a dry etch process, and wet etch techniques may etch high-k gate dielectric layer 170 isotropically—undercutting overlying sacrificial layers 104, 106 in an undesirable fashion.

To reduce the lateral removal of high-k gate dielectric layer 170, as exposed part 174 of that layer is etched, exposed part 174 of high-k gate dielectric layer 170 may be modified to facilitate its removal selectively to covered part 175 of that layer. Exposed part 174 may be modified by adding impurities to that part of high-k gate dielectric layer 170 after sacrificial layer 171 has been etched. A plasma enhanced chemical vapor deposition (“PECVD”) process may be used to add impurities to exposed part 174 of high-k gate dielectric layer 170. In such a PECVD process, a halogen or halide gas (or a combination of such gases) may be fed into a reactor prior to striking a plasma. The reactor should be operated under the appropriate conditions (e.g., temperature, pressure, radio frequency, and power) for a sufficient time to modify exposed part 174 to ensure that it may be removed selectively to other materials. In one embodiment, a low power PECVD process, e.g., one taking place at less than about 200 Watts, is used.

In one embodiment, hydrogen bromide (“HBr”) and chlorine (“Cl2”) gases are fed into the reactor at appropriate flow rates to ensure that a plasma generated from those gases will modify exposed part 174 in the desired manner. Between about 50 and about 100 Watts wafer bias (for example, about 100 Watts) may be applied for a sufficient time to complete the desired transformation of exposed part 174. Plasma exposure lasting less than about one minute, and perhaps as short as 5 seconds, may be adequate to cause that conversion.

After exposed part 174 has been modified, it may be removed. The presence of the added impurities enables that exposed part to be etched selectively to covered part 175 to generate the FIG. 1D structure. In one embodiment, exposed part 174 is removed by exposing it to a relatively strong acid, e.g., a halide based acid (such as hydrobromic or hydrochloric acid) or phosphoric acid. When a halide based acid is used, the acid preferably contains between about 0.5% and about 10% HBr or HCl by volume—and more preferably about 5% by volume. An etch process that uses such an acid may take place at or near room temperature, and last for between about 5 and about 30 minutes—although a longer exposure may be used if desired. When phosphoric acid is used, the acid may contain between about 75% and about 95% H3PO4 by volume. An etch process that uses such an acid may, for example, take place at between about 140° C. and about 180° C., and, in one embodiment, at about 160° C. When such an acid is used, the exposure step may last between about 30 seconds and about 5 minutes—and for about one minute for a 20 Angstrom thick film.

FIG. 1D represents an intermediate structure that may be formed when making a complementary metal oxide semiconductor (“CMOS”). That structure includes first part 101 and second part 102 of substrate 100 shown in FIG. 1E. Isolation region 103 separates first part 101 from second part 102. Isolation region 103 may comprise silicon dioxide, or other materials that may separate the transistor's active regions. First sacrificial layer 104 is formed on first high-k gate dielectric layer 105, and second sacrificial layer 106 is formed on second high-k gate dielectric layer 107. Hard masks 130, 131 are formed n sacrificial layers 104, 106.

After forming the FIG. 1D structure, spacers may be formed on opposite sides of sacrificial layers 104, 106. When those spacers comprise silicon nitride, they may be formed in the following way. First, a silicon nitride layer of substantially uniform thickness, for example, less than about 1000 Angstroms thick—is deposited over the entire structure, producing the structure shown in FIG. 1E. Conventional deposition processes may be used to generate that structure.

In one embodiment, silicon nitride layer 134 is deposited directly on substrate 100 and opposite sides of sacrificial layers 104, 106—without first forming a buffer oxide layer on substrate 100 and layers 104, 106. In alternative embodiments, however, such a buffer oxide layer may be formed prior to forming layer 134. Similarly, although not shown in FIG. 1E, a second oxide may be formed on layer 134 prior to etching that layer. If used, such an oxide may enable the subsequent silicon nitride etch step to generate an L-shaped spacer.

Silicon nitride layer 134 may be etched using a conventional process for anisotropically etching silicon nitride to create the FIG. 1F structure. As a result of that etch step, sacrificial layer 104 is bracketed by a pair of sidewall spacers 108, 109, and sacrificial layer 106 is bracketed by a pair of sidewall spacers 110, 111.

The structure of FIG. 1F may then be covered with a nitride etch stop layer 180 to form the structure of FIG. 1G. The layer 180 may be formed in the same way as the layer 134.

As is typically done, it may be desirable to perform multiple masking and ion implantation steps (FIG. 1H) to create lightly implanted regions 135 a138 a near layers 104, 106 (that will ultimately serve as tip regions for the device's source and drain regions), prior to forming spacers 108, 109, 110, 111 on sacrificial layers 104, 106. Also as is typically done, the source and drain regions 135138 may be formed, after forming spacers 108, 109, 110, 111, by implanting ions into parts 101 and 102 of substrate 100, followed by applying an appropriate anneal step.

An ion implantation and anneal sequence used to form n-type source and drain regions within part 101 of substrate 100 may dope sacrificial layer 104 n-type at the same time. Similarly, an ion implantation and anneal sequence used to form p-type source and drain regions within part 102 of substrate 100 may dope sacrificial layer 106 p-type. When doping sacrificial layer 106 with boron, that layer should include that element at a sufficient concentration to ensure that a subsequent wet etch process, for removing n-type sacrificial layer 104, will not remove a significant amount of p-type sacrificial layer 106.

The anneal will activate the dopants that were previously introduced into the source and drain regions and tip regions and into sacrificial layers 104, 106. In a preferred embodiment, a rapid thermal anneal is applied that takes place at a temperature that exceeds about 1,000° C.—and, optimally, that takes place at 1,080° C. In addition to activating the dopants, such an anneal may modify the molecular structure of high-k gate dielectric layers 105, 107 to create gate dielectric layers that may demonstrate improved performance.

Because of the imposition of the sacrificial metal layer 169, better performing dielectric layers 170 may result from these high temperature steps without significant reaction between the high dielectric constant dielectric layer 170 and the sacrificial layer 171.

After forming spacers 108, 109, 110, 111, and layer 180, dielectric layer 112 may be deposited over the device, generating the FIG. 1H structure. Dielectric layer 112 may comprise silicon dioxide, or a low-k material. Dielectric layer 112 may be doped with phosphorus, boron, or other elements, and may be formed using a high density plasma deposition process. By this stage of the process, source and drain regions 135, 136, 137, 138, which are capped by silicided regions 139, 140, 141, 142, have already been formed. Those source and drain regions may be formed by implanting ions into the substrate, then activating them. Alternatively, an epitaxial growth process may be used to form the source and drain regions, as will be apparent to those skilled in the art.

Dielectric layer 112 is removed from hard masks 130, 131, which are, in turn, removed from patterned sacrificial layers 104, 106, producing the FIG. 1I structure. A conventional chemical mechanical polishing (“CMP”) operation may be applied to remove that part of dielectric layer 112 and hard masks 130, 131. Hard masks 130, 131 may be removed to expose patterned sacrificial layers 104, 106. Hard masks 130, 131 may be polished from the surface of layers 104, 106, when dielectric layer 112 is polished—as they will have served their purpose by that stage in the process.

After forming the FIG. 1I structure, sacrificial layer 104 is removed to generate trench 113 that is positioned between sidewall spacers 108, 109—producing the structure shown in FIG. 1J.

In one embodiment, a wet etch process that is selective for layer 104 over sacrificial layer 106 is applied to remove layers 104 and 169 without removing significant portions of layer 106.

When sacrificial layer 104 is doped n-type, and sacrificial layer 106 is doped p-type (e.g., with boron), such a wet etch process may comprise exposing sacrificial layer 104 to an aqueous solution that comprises a source of hydroxide for a sufficient time at a sufficient temperature to remove substantially all of layer 104. That source of hydroxide may comprise between about 2 and about 30 percent ammonium hydroxide or a tetraalkyl ammonium hydroxide, e.g., tetramethyl ammonium hydroxide (“TMAH”), by volume in deionized water.

Any remaining sacrificial layer 104 may be selectively removed by exposing it to a solution, which is maintained at a temperature between about 15° C. and about 90° C. (for example, below about 40° C.), that comprises between about 2 and about 30 percent ammonium hydroxide by volume in deionized water. During that exposure step, which preferably lasts at least one minute, it may be desirable to apply sonic energy at a frequency of between about 10 kHz and about 2,000 kHz, while dissipating at between about 1 and about 10 Watts/cm2.

In one embodiment, sacrificial layer 104, with a thickness of about 1,350 Angstroms, may be selectively removed by exposing it at about 25° C. for about 30 minutes to a solution that comprises about 15 percent ammonium hydroxide by volume in deionized water, while applying sonic energy at about 1,000 kHz—dissipating at about 5 Watts/cm2. Such an etch process should remove substantially all of an n-type sacrificial layer 104 without removing a meaningful amount of a p-type sacrificial layer 106.

As an alternative, sacrificial layer 104 may be selectively removed by exposing it for at least one minute to a solution, which is maintained at a temperature between about 60° C. and about 90° C., that comprises between about 20 and about 30 percent TMAH by volume in deionized water, while applying sonic energy. Removing sacrificial layer 104, with a thickness of about 1,350 Angstroms, by exposing it at about 80° C. for about 2 minutes to a solution that comprises about 25 percent TMAH by volume in deionized water, while applying sonic energy at about 1,000 kHz—dissipating at about 5 Watts/cm2—may remove substantially all of layer 104 without removing a significant amount of layer 106. First high-k gate dielectric layer 105 should be sufficiently thick to prevent the etchant that is applied to remove sacrificial layer 104 from reaching the channel region that is located beneath first high-k gate dielectric layer 105.

The sacrificial metal layer 169 may also be removed by selective etching. In some embodiments, the layer 169 may not be removed. In some embodiments, the dielectric layer 105 may be removed before forming the replacement metal gate. In such case, a metal oxide gate dielectric may be formed before forming the replacement gate.

In the illustrated embodiment, n-type metal layer 115 is formed directly on layer 105 to fill trench 113 and to generate the FIG. 1K structure. N-type metal layer 115 may comprise any n-type conductive material from which a metal NMOS gate electrode may be derived. N-type metal layer 115 preferably has thermal stability characteristics that render it suitable for making a metal NMOS gate electrode for a semiconductor device.

Materials that may be used to form n-type metal layer 115 include: hafnium, zirconium, titanium, tantalum, aluminum, and their alloys, e.g., metal carbides that include these elements, i.e., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. N-type metal layer 115 may be formed on first high-k gate dielectric layer 105 using well known PVD or CVD processes, e.g., conventional sputter or atomic layer CVD processes. As shown in FIG. 1L, n-type metal layer 115 is removed except where it fills trench 113. Layer 115 may be removed from other portions of the device via a wet or dry etch process, or an appropriate CMP operation. Dielectric 112 may serve as an etch or polish stop, when layer 115 is removed from its surface.

N-type metal layer 115 may serve as a metal NMOS gate electrode that has a workfunction that is between about 3.9 eV and about 4.2 eV, and that is between about 100 Angstroms and about 2,000 Angstroms thick and, in one embodiment, may particularly be between about 500 Angstroms and about 1,600 Angstroms thick. Although FIGS. 1J and 1K represent structures in which n-type metal layer 115 fills all of trench 113, in alternative embodiments, n-type metal layer 115 may fill only part of trench 113, with the remainder of the trench being filled with a material that may be easily polished, e.g., tungsten, aluminum, titanium, or titanium nitride. Using a higher conductivity fill metal in place of the workfunction metal may improve the overall conductivity of the gate stack. In such an alternative embodiment, n-type metal layer 115, which serves as the workfunction metal, may be between about 50 and about 1,000 Angstroms thick and, for example, at least about 100 Angstroms thick.

In embodiments in which trench 113 includes both a workfunction metal and a trench fill metal, the resulting metal NMOS gate electrode may be considered to comprise the combination of both the workfunction metal and the trench fill metal. If a trench fill metal is deposited on a workfunction metal, the trench fill metal may cover the entire device when deposited, forming a structure like the FIG. 1K structure. That trench fill metal must then be polished back so that it fills only the trench, generating a structure like the FIG. 1L structure.

In the illustrated embodiment, after forming n-type metal layer 115 within trench 113, sacrificial layer 106 is removed to generate trench 150 that is positioned between sidewall spacers 110, 111—producing the structure shown in FIG. 1M. In a preferred embodiment, layer 106 is exposed to a solution that comprises between about 20 and about 30 percent TMAH by volume in deionized water for a sufficient time at a sufficient temperature (e.g., between about 60° C. and about 90° C.), while applying sonic energy, to remove all of layer 106 without removing significant portions of n-type metal layer 115.

Alternatively, a dry etch process may be applied to selectively remove layer 106. When sacrificial layer 106 is doped p-type (e.g., with boron), such a dry etch process may comprise exposing sacrificial layer 106 to a plasma derived from sulfur hexafluoride (“SF6”), hydrogen bromide (“HBr”), hydrogen iodide (“HI”), chlorine, argon, and/or helium. Such a selective dry etch process may take place in a parallel plate reactor or in an electron cyclotron resonance etcher.

After removing sacrificial layer 106, it may be desirable to clean second high-k gate dielectric layer 107, e.g., by exposing that layer to the hydrogen peroxide based solution described above. Optionally, as mentioned above, a capping layer (which may be oxidized after it is deposited) may be formed on second high-k gate dielectric layer 107 prior to filling trench 150 with a p-type metal. In this embodiment, however, p-type metal layer 116 is formed directly on layer 107 to fill trench 150 and to generate the FIG. 1N structure. P-type metal layer 116 may comprise any p-type conductive material from which a metal PMOS gate electrode may be derived. P-type metal layer 116 preferably has thermal stability characteristics that render it suitable for making a metal PMOS gate electrode for a semiconductor device.

Materials that may be used to form p-type metal layer 116 include: ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. P-type metal layer 116 may be formed on second high-k gate dielectric layer 107 using well known PVD or CVD processes, e.g., conventional sputter or atomic layer CVD processes. As shown in FIG. 10, p-type metal layer 116 is removed except where it fills trench 150. Layer 116 may be removed from other portions of the device via a wet or dry etch process, or an appropriate CMP operation, with dielectric 112 serving as an etch or polish stop.

P-type metal layer 116 may serve as a metal PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV, and that is between about 100 Angstroms and about 2,000 Angstroms thick, and more preferably is between about 500 Angstroms and about 1,600 Angstroms thick. Although FIGS. 1N and 1O represent structures in which p-type metal layer 116 fills all of trench 150, in alternative embodiments, p-type metal layer 116 may fill only part of trench 150. As with the metal NMOS gate electrode, the remainder of the trench may be filled with a material that may be easily polished, e.g., tungsten, aluminum, titanium, or titanium nitride. In such an alternative embodiment, p-type metal layer 116, which serves as the workfunction metal, may be between about 50 and about 1,000 Angstroms thick. Like the metal NMOS gate electrode, in embodiments in which trench 150 includes a workfunction metal and a trench fill metal, the resulting metal PMOS gate electrode may be considered to comprise the combination of both the workfunction metal and the trench fill metal.

Next, the dielectric layer 112 may be removed to form the structure shown in FIG. 1P. A new nitride etch stop layer 181 may then be deposited as shown in FIG. 1Q. The layer 181 may, in one embodiment, be identical to the layer 180. Then, the dielectric layer 214 may be deposited as shown in FIG. 1R to form an interlayer dielectric. The layer 214 may be formed of the same material and in the same fashion as the layer 112.

Because a portion of the nitride etch stop layer 180 was removed in the course of removing the layers 104 and 106, the benefits that such a layer could have provided in reducing strain are eliminated. Therefore, by re-adding a layer 181 and a layer 214, the benefits of a strain reducing layer and an etch stop layer may be resurrected. In some embodiments, any dielectric 214 may be utilized. For example, the dielectric 214 may be a low-K dielectric layer such as porous or non-porous carbon-doped oxide having a dielectric constant less than about 5, for example about 3.2.

While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims (6)

1. A method comprising:
forming a sacrificial gate structure;
removing said sacrificial gate structure;
replacing said sacrificial gate structure with a metal gate electrode;
covering said metal gate electrode with a nitride layer; and
covering said nitride layer with a carbon doped oxide.
2. The method of claim 1 including forming a pair of sacrifical gate structures and replacing said sacrifical gate structure with metal gate electrodes adated to from NMOS and PMOS transistors.
3. The method of claim 1 wherein forming a sacrifical gate structure includes forming a polysilicon gate structure with sidewall spacers.
4. A method comprising:
forming a pair of sacrificial gate structures;
removing said sacrificial gate structures;
replacing said sacrificial gate structures with metal gate electrodes;
covering said metal gate electrodes with a nitride layer; and
covering said nitride layer with a carbon doped oxide.
5. The method of claim 4 including forming a pair of sacrificial gate structures and replacing said sacrificial gate structures with metal gate electrodes adapted to form NMOS and PMOS transistors.
6. The method of claim 4 wherein forming a sacrificial gate structure includes forming a polysilicon gate structure with sidewall spacers.
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DE200511001828 DE112005001828B4 (en) 2004-07-28 2005-07-14 A method of producing semiconductor devices with planarize a semiconductor structure for forming replacement metal gates as well as corresponding semiconductor structure
KR20077003160A KR100865885B1 (en) 2004-07-28 2005-07-14 Planarizing a semiconductor structure to form replacement metal gates
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Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080160737A1 (en) * 2006-12-27 2008-07-03 Hynix Semiconductor Inc. Method for forming metal pattern and method for forming gate electrode in semiconductor device using the same
US20080224238A1 (en) * 2007-03-13 2008-09-18 International Business Machines Corporation ADVANCED HIGH-k GATE STACK PATTERNING AND STRUCTURE CONTAINING A PATTERNED HIGH-k GATE STACK
US20090206406A1 (en) * 2008-02-15 2009-08-20 Willy Rachmady Multi-gate device having a t-shaped gate structure
US20090212376A1 (en) * 2008-02-27 2009-08-27 James William Adkisson Semiconductor transistors having high-k gate dielectric layers and metal gate electrodes
US20100087055A1 (en) * 2008-10-06 2010-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method for gate height control in a gate last process
US20100087038A1 (en) * 2008-10-06 2010-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method for n/p patterning in a gate last process
US20110020994A1 (en) * 2009-07-27 2011-01-27 United Microelectronics Corp. Manufacturing method of semiconductor device
US20110189847A1 (en) * 2010-01-29 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method for metal gate n/p patterning
US8211775B1 (en) 2011-03-09 2012-07-03 United Microelectronics Corp. Method of making transistor having metal gate
US8252675B2 (en) 2009-12-08 2012-08-28 Samsung Electronics Co., Ltd. Methods of forming CMOS transistors with high conductivity gate electrodes
US8486790B2 (en) 2011-07-18 2013-07-16 United Microelectronics Corp. Manufacturing method for metal gate
US8519487B2 (en) 2011-03-21 2013-08-27 United Microelectronics Corp. Semiconductor device
US8519454B2 (en) 2011-03-30 2013-08-27 International Business Machines Corporation Structure and process for metal fill in replacement metal gate integration
US8574990B2 (en) 2011-02-24 2013-11-05 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gate
US8647941B2 (en) 2011-08-17 2014-02-11 United Microelectronics Corp. Method of forming semiconductor device
US8691659B2 (en) 2011-10-26 2014-04-08 United Microelectronics Corp. Method for forming void-free dielectric layer
US8765561B2 (en) 2011-06-06 2014-07-01 United Microelectronics Corp. Method for fabricating semiconductor device
US8772120B2 (en) 2012-05-24 2014-07-08 United Microelectronics Corp. Semiconductor process
US8802524B2 (en) 2011-03-22 2014-08-12 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gates
US8835243B2 (en) 2012-05-04 2014-09-16 United Microelectronics Corp. Semiconductor process
US8883623B2 (en) 2012-10-18 2014-11-11 Globalfoundries Inc. Facilitating gate height uniformity and inter-layer dielectric protection
US8895396B1 (en) 2013-07-11 2014-11-25 United Microelectronics Corp. Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures
US8921944B2 (en) 2011-07-19 2014-12-30 United Microelectronics Corp. Semiconductor device
US8951876B2 (en) 2012-06-20 2015-02-10 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US9041076B2 (en) 2013-02-03 2015-05-26 International Business Machines Corporation Partial sacrificial dummy gate with CMOS device with high-k metal gate
US9331148B1 (en) 2015-12-08 2016-05-03 International Business Machines Corporation FinFET device with channel strain
US20160172367A1 (en) * 2014-12-15 2016-06-16 Powerchip Technology Corporation Manufacturing method of non-volatile memory
US9741577B2 (en) 2015-12-02 2017-08-22 International Business Machines Corporation Metal reflow for middle of line contacts
US9960078B1 (en) 2017-03-23 2018-05-01 International Business Machines Corporation Reflow interconnect using Ru

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7256349B2 (en) * 2004-08-11 2007-08-14 3M Innovative Properties Company Telecommunications cable enclosure
US7338907B2 (en) * 2004-10-04 2008-03-04 Sharp Laboratories Of America, Inc. Selective etching processes of silicon nitride and indium oxide thin films for FeRAM device applications
DE102004052617B4 (en) * 2004-10-29 2010-08-05 Advanced Micro Devices, Inc., Sunnyvale exhibit method of manufacturing a semiconductor device and semiconductor device comprising semiconductor regions, the channel regions differently deformed
JP5380827B2 (en) 2006-12-11 2014-01-08 ソニー株式会社 A method of manufacturing a semiconductor device
JP2008198935A (en) 2007-02-15 2008-08-28 Sony Corp Method for manufacturing insulating gate field effect transistor
US7781288B2 (en) * 2007-02-21 2010-08-24 International Business Machines Corporation Semiconductor structure including gate electrode having laterally variable work function
DE102007041207B4 (en) 2007-08-31 2015-05-21 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg CMOS device with gate insulating layers of different kind and thickness and processes for preparing
DE102008046761A1 (en) * 2007-09-14 2009-04-09 Infineon Technologies Ag Semiconductor device with conductive connection assembly
US7986023B2 (en) * 2007-09-17 2011-07-26 Infineon Technologies Ag Semiconductor device with inductor
US7955964B2 (en) 2008-05-14 2011-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Dishing-free gap-filling with multiple CMPs
US8524588B2 (en) * 2008-08-18 2013-09-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process
US8237227B2 (en) 2008-08-29 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy gate structure for gate last process
JP4744576B2 (en) * 2008-09-10 2011-08-10 パナソニック株式会社 A method of manufacturing a semiconductor device
US8163655B2 (en) * 2008-09-15 2012-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a sacrificial sandwich structure
JP2010129978A (en) * 2008-12-01 2010-06-10 Rohm Co Ltd Method of manufacturing semiconductor device
US7838356B2 (en) * 2008-12-31 2010-11-23 Texas Instruments Incorporated Gate dielectric first replacement gate processes and integrated circuits therefrom
DE102009006802B3 (en) 2009-01-30 2010-06-17 Advanced Micro Devices, Inc., Sunnyvale The method and semiconductor device including adjustment of the work function in a gate electrode structure with large ε after the transistor production using Lanthanum
KR101574107B1 (en) * 2010-02-11 2015-12-04 삼성전자 주식회사 Method for manufacturing semiconductor device
DE102010003451B4 (en) 2010-03-30 2013-12-24 Globalfoundries Dresden Module One Llc & Co. Kg Replacement gate process for metal gate stack with large ε by avoiding a polishing process to expose the placeholder material
CN102468238A (en) * 2010-11-04 2012-05-23 联华电子股份有限公司 Semiconductor element with metal gate, and manufacturing method for semiconductor element
CN102800576B (en) * 2011-05-26 2015-09-02 中芯国际集成电路制造(上海)有限公司 Film patterning methods, a method of forming the gate, the MOS transistor
CN103681498B (en) * 2012-09-12 2016-03-30 中芯国际集成电路制造(上海)有限公司 A method of manufacturing a semiconductor device
US8889540B2 (en) 2013-02-27 2014-11-18 International Business Machines Corporation Stress memorization in RMG FinFets
CN104037073B (en) * 2013-03-04 2016-12-28 中芯国际集成电路制造(上海)有限公司 A method of manufacturing a semiconductor device
CN104465518B (en) * 2013-09-24 2017-09-22 中芯国际集成电路制造(上海)有限公司 The gate production methods
US9368592B2 (en) * 2014-01-28 2016-06-14 Taiwan Semiconductor Manufacturing Company Ltd. Metal gate structure
US9231067B2 (en) 2014-02-26 2016-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and fabricating method thereof
US9698019B2 (en) * 2014-03-14 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. N-work function metal with crystal structure
US9847347B1 (en) 2016-11-07 2017-12-19 Globalfoundries Inc. Semiconductor structure including a first transistor at a semiconductor-on-insulator region and a second transistor at a bulk region and method for the formation thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6171910B1 (en) * 1999-07-21 2001-01-09 Motorola Inc. Method for forming a semiconductor device
US20050236694A1 (en) * 2004-04-27 2005-10-27 Zhen-Cheng Wu Silicon oxycarbide and silicon carbonitride based materials for MOS devices

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6211026B1 (en) * 1998-12-01 2001-04-03 Micron Technology, Inc. Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors
US6235568B1 (en) * 1999-01-22 2001-05-22 Intel Corporation Semiconductor device having deposited silicon regions and a method of fabrication
KR20010004598A (en) * 1999-06-29 2001-01-15 김영환 method of forming gate for semiconductor device
JP2001044421A (en) * 1999-07-27 2001-02-16 Mitsubishi Electric Corp Manufacture of misfet
US6800512B1 (en) * 1999-09-16 2004-10-05 Matsushita Electric Industrial Co., Ltd. Method of forming insulating film and method of fabricating semiconductor device
US6410462B1 (en) * 2000-05-12 2002-06-25 Sharp Laboratories Of America, Inc. Method of making low-K carbon doped silicon oxide
US6258735B1 (en) * 2000-10-05 2001-07-10 Applied Materials, Inc. Method for using bypass lines to stabilize gas flow and maintain plasma inside a deposition chamber
US6436822B1 (en) * 2000-11-20 2002-08-20 Intel Corporation Method for making a carbon doped oxide dielectric material
JP3669919B2 (en) * 2000-12-04 2005-07-13 シャープ株式会社 A method of manufacturing a semiconductor device
US6482754B1 (en) * 2001-05-29 2002-11-19 Intel Corporation Method of forming a carbon doped oxide layer on a substrate
US6677253B2 (en) * 2001-10-05 2004-01-13 Intel Corporation Carbon doped oxide deposition
JP2003133549A (en) * 2001-10-29 2003-05-09 Nec Corp Mosfet and manufacturing method therefor
JP2003133547A (en) * 2001-10-29 2003-05-09 Nec Kansai Ltd Method for manufacturing high withstand voltage semiconductor device
US6713335B2 (en) * 2002-08-22 2004-03-30 Chartered Semiconductor Manufacturing Ltd. Method of self-aligning a damascene gate structure to isolation regions
JP2004095611A (en) * 2002-08-29 2004-03-25 Fujitsu Ltd Semiconductor device and its manufacturing method
US7126198B2 (en) * 2002-09-03 2006-10-24 Agere Systems Inc. Protruding spacers for self-aligned contacts
JP2004152995A (en) * 2002-10-30 2004-05-27 Toshiba Corp Method of manufacturing semiconductor device
JP4197607B2 (en) * 2002-11-06 2008-12-17 株式会社東芝 The method of manufacturing a semiconductor device including an insulated gate field effect transistor
US6709911B1 (en) 2003-01-07 2004-03-23 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric
US6927146B2 (en) * 2003-06-17 2005-08-09 Intel Corporation Chemical thinning of epitaxial silicon layer over buried oxide
US20050035455A1 (en) * 2003-08-14 2005-02-17 Chenming Hu Device with low-k dielectric in close proximity thereto and its method of fabrication
US20050116360A1 (en) * 2003-12-01 2005-06-02 Chien-Chao Huang Complementary field-effect transistors and methods of manufacture
US7220635B2 (en) * 2003-12-19 2007-05-22 Intel Corporation Method for making a semiconductor device with a metal gate electrode that is formed on an annealed high-k gate dielectric layer
US7078282B2 (en) * 2003-12-30 2006-07-18 Intel Corporation Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6171910B1 (en) * 1999-07-21 2001-01-09 Motorola Inc. Method for forming a semiconductor device
US20050236694A1 (en) * 2004-04-27 2005-10-27 Zhen-Cheng Wu Silicon oxycarbide and silicon carbonitride based materials for MOS devices

Cited By (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7572704B2 (en) * 2006-12-27 2009-08-11 Hynix Semiconductor Inc. Method for forming metal pattern and method for forming gate electrode in semiconductor device using the same
US20080160737A1 (en) * 2006-12-27 2008-07-03 Hynix Semiconductor Inc. Method for forming metal pattern and method for forming gate electrode in semiconductor device using the same
US20080224238A1 (en) * 2007-03-13 2008-09-18 International Business Machines Corporation ADVANCED HIGH-k GATE STACK PATTERNING AND STRUCTURE CONTAINING A PATTERNED HIGH-k GATE STACK
WO2008112263A1 (en) * 2007-03-13 2008-09-18 International Business Machines Corporation Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack
US7820552B2 (en) 2007-03-13 2010-10-26 International Business Machines Corporation Advanced high-k gate stack patterning and structure containing a patterned high-k gate stack
US8264048B2 (en) 2008-02-15 2012-09-11 Intel Corporation Multi-gate device having a T-shaped gate structure
US20090206406A1 (en) * 2008-02-15 2009-08-20 Willy Rachmady Multi-gate device having a t-shaped gate structure
US20100314697A1 (en) * 2008-02-27 2010-12-16 International Business Machines Corporation Semiconductor transistors having high-k gate dielectric layers and metal gate electrodes
US20090212376A1 (en) * 2008-02-27 2009-08-27 James William Adkisson Semiconductor transistors having high-k gate dielectric layers and metal gate electrodes
US7790559B2 (en) 2008-02-27 2010-09-07 International Business Machines Corporation Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes
US8227874B2 (en) 2008-02-27 2012-07-24 International Business Machines Corporation Semiconductor transistors having high-K gate dielectric layers and metal gate electrodes
US20100087038A1 (en) * 2008-10-06 2010-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method for n/p patterning in a gate last process
US7977181B2 (en) 2008-10-06 2011-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for gate height control in a gate last process
US20100087055A1 (en) * 2008-10-06 2010-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Method for gate height control in a gate last process
US8093116B2 (en) 2008-10-06 2012-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method for N/P patterning in a gate last process
US7915127B2 (en) 2009-07-27 2011-03-29 United Microelectronics Corp. Manufacturing method of semiconductor device
US20110020994A1 (en) * 2009-07-27 2011-01-27 United Microelectronics Corp. Manufacturing method of semiconductor device
US8252675B2 (en) 2009-12-08 2012-08-28 Samsung Electronics Co., Ltd. Methods of forming CMOS transistors with high conductivity gate electrodes
US8048810B2 (en) 2010-01-29 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Method for metal gate N/P patterning
US20110189847A1 (en) * 2010-01-29 2011-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Method for metal gate n/p patterning
US8574990B2 (en) 2011-02-24 2013-11-05 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gate
US8211775B1 (en) 2011-03-09 2012-07-03 United Microelectronics Corp. Method of making transistor having metal gate
US8723274B2 (en) 2011-03-21 2014-05-13 United Microelectronics Corp. Semiconductor device and method for fabricating the same
US8519487B2 (en) 2011-03-21 2013-08-27 United Microelectronics Corp. Semiconductor device
US8802524B2 (en) 2011-03-22 2014-08-12 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gates
US8519454B2 (en) 2011-03-30 2013-08-27 International Business Machines Corporation Structure and process for metal fill in replacement metal gate integration
US8765561B2 (en) 2011-06-06 2014-07-01 United Microelectronics Corp. Method for fabricating semiconductor device
US8486790B2 (en) 2011-07-18 2013-07-16 United Microelectronics Corp. Manufacturing method for metal gate
US8921944B2 (en) 2011-07-19 2014-12-30 United Microelectronics Corp. Semiconductor device
US8647941B2 (en) 2011-08-17 2014-02-11 United Microelectronics Corp. Method of forming semiconductor device
US8691659B2 (en) 2011-10-26 2014-04-08 United Microelectronics Corp. Method for forming void-free dielectric layer
US8835243B2 (en) 2012-05-04 2014-09-16 United Microelectronics Corp. Semiconductor process
US8772120B2 (en) 2012-05-24 2014-07-08 United Microelectronics Corp. Semiconductor process
US8951876B2 (en) 2012-06-20 2015-02-10 United Microelectronics Corp. Semiconductor device and manufacturing method thereof
US9269811B2 (en) 2012-06-20 2016-02-23 United Microelectronics Corp. Spacer scheme for semiconductor device
US8883623B2 (en) 2012-10-18 2014-11-11 Globalfoundries Inc. Facilitating gate height uniformity and inter-layer dielectric protection
US9853116B2 (en) 2012-10-28 2017-12-26 International Business Machines Corporation Partial sacrificial dummy gate with CMOS device with high-k metal gate
US9299795B2 (en) 2012-10-28 2016-03-29 International Business Machines Corporation Partial sacrificial dummy gate with CMOS device with high-k metal gate
US9041076B2 (en) 2013-02-03 2015-05-26 International Business Machines Corporation Partial sacrificial dummy gate with CMOS device with high-k metal gate
US8895396B1 (en) 2013-07-11 2014-11-25 United Microelectronics Corp. Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures
US20160172367A1 (en) * 2014-12-15 2016-06-16 Powerchip Technology Corporation Manufacturing method of non-volatile memory
US9466605B2 (en) * 2014-12-15 2016-10-11 Powerchip Technology Corporation Manufacturing method of non-volatile memory
US9741577B2 (en) 2015-12-02 2017-08-22 International Business Machines Corporation Metal reflow for middle of line contacts
US9331148B1 (en) 2015-12-08 2016-05-03 International Business Machines Corporation FinFET device with channel strain
US9960078B1 (en) 2017-03-23 2018-05-01 International Business Machines Corporation Reflow interconnect using Ru

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