CN101203947A - 采用抬高的源极漏极和替代金属栅极的互补型金属氧化物半导体集成电路 - Google Patents

采用抬高的源极漏极和替代金属栅极的互补型金属氧化物半导体集成电路 Download PDF

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CN101203947A
CN101203947A CNA2006800221845A CN200680022184A CN101203947A CN 101203947 A CN101203947 A CN 101203947A CN A2006800221845 A CNA2006800221845 A CN A2006800221845A CN 200680022184 A CN200680022184 A CN 200680022184A CN 101203947 A CN101203947 A CN 101203947A
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J·卡瓦利洛斯
A·卡佩拉尼
J·布雷斯克
S·达塔
M·多奇
M·梅茨
C·巴恩斯
R·曹
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Abstract

本发明涉及一种互补型金属氧化物半导体集成电路，其可以形成有PMOS器件，而该PMOS器件可利用替代金属栅极及抬高的源极漏极形成。抬高的源极漏极可以由掺杂了P型的外延沉积锗硅材料形成。替代金属栅极过程产生了金属栅电极，并且可能会涉及到氮化物蚀刻阻止层的去除。

Description

采用抬高的源极漏极和替代金属栅极的互补型金属氧化物半导体集成电路
背景技术
本发明大体上涉及集成电路的制造。
在CMOS技术中，为了提高NMOS和PMOS深亚微米晶体管的性能，现有技术在PMOS晶体管的沟道中使用压应力，而对NMOS晶体管则使用拉应力。
使用应变沟道的现有技术受到很多限制。例如在PMOS器件中可能产生多晶硅耗尽效应。另外，在PMOS器件中可能会发生拉应变。剩余的拉应变降低PMOS器件的空穴迁移率。
因此，需要一种更好的互补型金属氧化物半导体的制造工艺，特别是一种能提高PMOS器件性能的工艺方法。
附图简述
图1是处于制造初期阶段的PMOS晶体管的放大的截面图；
图2是处于下一个制造阶段的PMOS晶体管的放大的截面图；
图3是根据本发明的一个实施例的处于图2所示制造阶段的下一个阶段的PMOS晶体管的放大的截面图；
图4是根据本发明的一个实施例的处于图3所示制造阶段的下一个阶段的PMOS晶体管的放大的截面图；
图5是根据本发明的一个实施例的处于图4所示制造阶段的下一个阶段的PMOS晶体管的放大的截面图；
图6是根据本发明的一个实施例的处于图5所示制造阶段的下一个阶段的PMOS晶体管的放大的截面图；
图7是根据本发明的一个实施例的处于图6所示制造阶段的下一个阶段的PMOS晶体管的放大的截面图；
图8是根据本发明的一个实施例的处于图7所示制造阶段的下一个阶段的PMOS晶体管的放大的截面图；
图9是根据本发明的一个实施例的处于图8所示制造阶段的下一个阶段的PMOS晶体管的放大的截面图；
图10是根据本发明的一个实施例的处于图9所示制造阶段的下一个阶段的PMOS晶体管的放大的截面图；
图11是根据本发明的一个实施例的处于图10所示制造阶段的下一个阶段的PMOS晶体管的放大的截面图；
图12是根据本发明的一个实施例的处于图11所示制造阶段的下一个阶段的PMOS晶体管的放大的截面图；
图13是根据本发明的一个实施例的处于图12所示制造阶段的下一个阶段的PMOS晶体管的放大的截面图；
图14显示了一个NMOS晶体管的实施例，该NMOS晶体管用来与根据本发明的一个实施例的如图13所示的PMOS晶体管一起使用。
详细说明
互补的一对的PMOS晶体管的制造如图1-13所示而进行。在一个实施例中，在NMOS侧和PMOS侧这二者上，都可以沉积二氧化硅栅极氧化物105。该栅极氧化物105可以被栅极材料104例如多晶硅覆盖，并接着被硬质掩膜130覆盖，以用于生成图案(patterning)。然后栅极材料104和栅极介电部(gate dielectric)105，例如氧化物，被生成图案，以产生PMOS侧10a上的图1所示结构。栅极介电部可能约为15埃厚，并且在一个实施例中可以进行热生长。
衬底100可以包括块硅或者介电部上的硅(Silicon-on-insulator)的子结构。作为备选方案，衬底可以包括其它材料，这些材料可以和硅结合，也可以不和硅结合，所述的这些材料例如包括：锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或者锑化镓。尽管这里描述了一些可以形成衬底100的材料的例子，但是，任何可以作为半导体器件基底的材料都落在本发明的精神与范畴内。浅槽隔离区20可以由二氧化硅或其它可以把晶体管的有源区隔离开来的材料形成。
栅极材料104可以包括多晶硅，并且在一个实施例中可以是例如约100到约2000埃厚以及约500到约1600埃厚。硬质掩膜130可以包括氮化硅，并且在一个实施例中可以是例如约100到约500埃厚以及约200到约350埃厚。
尖端掺杂的或稍微掺杂的源极漏极(source drain)60可以采用作为掩膜的栅极结构来形成。可以使用离子注入法来形成源极漏极60。
当栅极材料104包括多晶硅，而硬质掩膜130包括氮化硅时，图1中的结构可以按下面的方法来制造。在衬底100上形成可能包括二氧化硅的伪介电层(例如通过传统的热生长工艺)，接着在介电层上形成多晶硅层(例如通过传统的沉积工艺)。利用传统的沉积技术，氮化硅层形成于多晶硅层上。氮化硅、多晶硅和伪介电层(dummydielectric layer)被生成图案，以形成图案化的氮化硅层、图案化的多晶硅层，以及图案化的介电层。当介电层由二氧化硅构成时，可以应用常规的蚀刻方法来对多晶硅以及伪介电层进行图案化。
氮隔离层材料134可以被沉积上去(图2)，并且被各向异性地进行蚀刻，来形成侧壁隔离层(spacer)108、109，见图3。隔离层108、109可以达到1000埃数量级的厚度。
沟道(trench)24形成于衬底100中，见图4。沟道24可以通过利用SF6化学药剂的反应性离子蚀刻来形成。蚀刻在一侧上被介电层20抑制，而在一个实施例中，在另一侧上并没有大致各向同性地对栅极结构进行底切。因此可在沟道24的内边缘上产生各向同性的蚀刻轮廓，见图4，而留下一部分被稍微掺杂的源极漏极60。在该步骤中，NMOS侧10b可能会被氧化物掩膜(未显示)覆盖。
然后，可以生长外延硅锗源极漏极40，其填充了沟道24并且如图5中所示地在其上延伸。沟道24可以用含有10-40原子百分比的锗的硅锗来填充。可以通过利用乙硼烷源的原位掺杂来进行源极漏极掺杂。该外延源极漏极40只在沟道24中生长，因为所有其它的材料都被掩膜掩盖或覆盖了。该源极漏极40升高并继续生长直到面(facet)会合。在一些实施例中，可以接着使用源极漏极注入。
如图6所示，在把NMOS侧的掩膜去除之后，可以把图3的结构用介电层112覆盖，介电层112例如是介电常数较低的材料如氧化物和氮化物的蚀刻阻止层(NESL)120。该层112可以掺入磷、硼或者其它材料，它可以由高浓度的等离子体沉积而成。然后该介电层112可以被平面化(planarize)降低到栅极材料104的上表面，从而将硬质掩膜130以及NESL120去除，如图7所示。该层120可以是氮化物。它作为蚀刻阻止层和张力层来辅助NMOS侧，但是可能会由于产生了应变而使PMOS侧10a性能降低。因此把PMOS侧的NESL120去除，可以提高性能。
如图8所示，可以去除栅极材料104而在剩余的栅极氧化物105上形成沟道113。去除栅极材料104可以通过很多方法来实现，例如相对于NMOS晶体管的栅极材料对栅极材料104进行选择性的蚀刻，或者在图8所示的工艺过程中掩蔽NMOS晶体管。
去除栅极材料104，来产生位于侧壁隔离层108、109之间的沟道113，从而产生如图8中所示的结构。在一个实施例中，湿蚀刻方法对位于相应的NMOS晶体管材料(未显示)上的材料104是选择性的，可以应用此方法来去除材料104，而不会去除NMOS材料的主要部分。
在一些实施例中，可以对该层104进行有选择的去除。在一个实施例中，层104以充分的时间和充分的温度(例如约为60℃到90℃)暴露于包括了按体积计算约20％到30％的四甲基氢氧化铵(TMAH)的去电离的水溶液中，应用声能去除所有的层106，同时不会去除任何NMOS晶体管结构(未显示)的主要部分。
作为备选方案，可以应用干蚀刻方法来选择性地去除层104。当栅极层104是掺杂的P型(例如带有硼)，这样一种干蚀刻方法可以包含：把牺牲性的栅电极层104暴露在源自六氟化硫(″SF6″)、溴化氢(″HBr″)、碘化氢(″HI″)、氯、氩、及/或氦的等离子体中。这样的选择性的干蚀刻方法可以在平行金属板反应器或者电子回旋共振蚀刻器中进行。
在去除材料104之后，去除介电层105。当介电层105由二氧化硅组成时，介电层105可以利用蚀刻工艺而去除，这种蚀刻工艺对于二氧化硅来说可以选择性地产生图9所示的结构。这样的蚀刻工艺包括：把层105暴露于含有约1％的去电离的氢氟酸(HF)水溶液中，或应用使用基于碳氟化合物的等离子体的干蚀刻工艺。层105可能只暴露有限的时间，因为去除层105的蚀刻工艺过程也会去除一部分的介电层112。应当记住，假如利用基于1％HF的溶液来去除层105，该器件暴露在溶液中的时间不能超过约60秒，例如约30秒或更少。当最初沉积时如果层105不到约30埃厚，则可去除层105，而不去除主要量的介电层112。
接下来，可以将新的栅极介电部114沉积上去并进行平面化，以得到U形形状，其把开口113排齐，如图10所示。尽管栅极介电层114可以包括任何可作为栅极介电部的材料(其中栅极介电部用于包括有金属栅电极的PMOS晶体管)，但是，栅极介电层114可以包括介电常数大于10的高电介常数(k)金属氧化物介电部材料。一些可以用来制造高k值的栅极介电部114的材料包括：氧化铪、氧化铪硅，氧化镧，氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽、以及铌酸铅锌。尤其适用的金属氧化物包括氧化铪、氧化锆以及氧化铝。尽管这里描述了一些可以用来形成高k值栅极介电层114的金属氧化物的示例，但是，该介电层也可由其它金属氧化物来形成。
利用传统的沉积方法，例如传统的化学气相沉积(″CVD″)、低压CVD、或者物理气相沉积(″PVD″)工艺，可以把高k值栅极介电层114形成于衬底100上。优选利用传统的原子层CVD工艺。在此工艺中，金属氧化物前体(例如金属氯化物)和蒸气以选定的流速引入CVD反应器中，反应器在选定的温度和压力下运行，以在衬底100和高k值栅极介电层114之间产生在原子级别上(atomically)平滑的界面。CVD反应器应运行足够的时间，来形成具有所需厚度的层。在大多数的应用场合中，高k值栅极介电层114可以是例如小于约60埃厚的，并且在一个实施例中厚度为大约5埃到大约40埃。
当原子层CVD工艺被用来形成高k值的栅极介电层114时，除了在沟道113的底部，此层还将形成于沟道的垂直侧上。假如高k值栅极介电层114包括氧化物，那么它可能会在表面上随机的地方出现氧化物空隙(oxygen vacancy)和不受欢迎的不纯程度(这取决于其制造工艺)。可能需要在层114沉积之后去掉它的不纯性，并把它氧化，以产生具有化学当量上近乎理想化的金属：氧化物比的金属氧化物层。
为了从该层上去除不纯性并提高其含氧量，可以对高k值栅极介电层114进行湿化学处理。该湿化学处理可以包含：在足够的温度下，把高k值的栅极介电层114暴露于包括过氧化氢形成的溶液中达充分的一段时间，以去除高k值栅极介电层114的不纯性，并提高高k值栅极介电层114的含氧量。高k值栅极介电层114所暴露于其中的适当时间和温度，可以由所希望的高k值栅极介电层114的厚度和其它性质来决定。
当把高k值的栅极介电层114暴露在基于过氧化氢的溶液时，可以使用按体积计算含约2％到约30％的过氧化氢水溶液。该暴露步骤可以发生在约15℃到约40℃之间，时间最少约一分钟。在一个特别优选的实施例中，把高k值的栅极介电层114暴露于温度为大约25℃的按体积计算约含6.7％H2O2的水溶液里达约10分钟的时间。在该暴露步骤中，希望使用频率在约10KHz到约2000KHz、而以约1Watts/cm2到约10Watts/cm2消散的声能。在一个实施例中，可以应用频率为约1000KHz的以5Watts/cm2消散的声能。
栅极金属115可以沉积到沟道113中，与介电材料112重叠，见图11。可以对栅极金属进行平面化，以形成金属栅电极115，见图12。
P型金属层115可以通过填充沟道113来产生。P型金属层115可以包括任何P型导电材料，由这种P型导电材料可以生出金属PMOS栅电极，并且它为此目的使沟道产生压应变。P型金属层的热膨胀系数可能大于衬底100(例如硅)。适合的金属的示例包括碳化硼、钨、钼、铑、钒、铂、钌、铍、钯、钴、钛、镍、铜、锡、铝、铅、锌、合金以及这些材料的硅化物。在一个实施例中，使用热膨胀系数大于钨的热膨胀系数(0.4×10-5in./in./℃)的材料是有利的。相对较高的沉积温度，例如400℃，可以用在一些实施例中，在槽道中产生压应变，并且提高迁移性。P型金属层115优选具有热稳定特性，以使它适合于制作半导体器件的金属PMOS栅电极。
可以用来形成P型金属层115的材料包括：钌、钯、铂、钴、镍、以及导电的金属氧化物，例如氧化钌。层115的金属可以与金属氧化物介电层105的金属成分相同或不同。P型金属层115可以利用众所周知的PVD或CVD工艺，例如传统的溅射或原子层CVD工艺在栅极介电层105上形成。除了填充沟道113的地方外，其它的P型金属层115部分都被去除。层115可以通过湿蚀刻或干蚀刻工艺、或者适当的CMP操作来从器件的其它部分去除，同时介电部112作为蚀刻或者抛光阻止结构。
P型金属层115可以补偿由硅锗抬高的源极漏极40所带来的阈值电压漂移。可以调节或者选择此金属层115的功函数，以补偿由于使用抬高的源极漏极40而必然导致的阈值电压漂移。一般来说，抬高的源极漏极40导致原子价的升高，并降低了阈值电压。因此，希望使用中隙金属(mid-gap metal)作为层115，其功函数可以补偿阈值电压的漂移。
P型金属层115可以用作功函数为约4.9eV到约5.2eV之间的金属PMOS栅电极，并且可以具有例如约10埃到约2000埃之间的厚度，并且在一个实施例中其厚度为约500埃到约1600埃之间。
接着，图13所示的结构可以通过形成硅化物接触部46和氮化物蚀刻阻止层42来完成。可以在接触部46形成之后提供氮化物蚀刻阻止层42。
在本发明的一些实施例中，外延硅锗抬高的源极漏极40使PMOS沟道产生压应变，以便提高迁移率并降低外部的阻抗。这在一些实施例中可以这样来实现，即通过用硼对源极漏极40进行原位掺杂，并为空穴注入(hole injection)降低肖特级能量势垒，从而改善接触电阻。
在多晶硅开口抛光(图7)和/或用于形成接触部的氮化物蚀刻阻止层42的蚀刻期间，替代金属栅极工艺可以减少多晶硅的耗尽。而同时释放在PMOS器件中的拉应变。通过减少使空穴迁移率降低的拉应变，可有利于PMOS器件。
可以调整取代栅电极115，以用于PMOS晶体管(在使用或不使用高电介常数(大于10)介电部或者栅极介电部114时)，以消除多晶硅的耗尽并减少栅极泄露。在替代金属栅极流过程中，在PMOS器件10a上的抛光和/或去除了拉应变的NESL120可以提高PMOS的迁移率。
见图14，NMOS晶体管10b的制造按照传统的技术进行。
例如，NMOS晶体管10b可以具有成梯度的结合部，该成梯度的结合部包括浅的尖端/源极/漏极39以及深的源极漏极22，它可以通过离子注入来制造。在一些实施例中可以引入或不引入应变。在一些实施例中，栅极37是替代金属栅极，而在另一些实施例中可能会采用传统的多晶硅栅极。栅极37可以被硅化物接触部38覆盖。NESL120可以被保留在NMOS侧10b。
尽管只通过有限数量的实施例对本发明进行了描述，但是本领域技术人员可以从中领会到大量的修改和变化。所附的权利要求旨在包括所有这些落入本发明的精神和范围内的修改和变化。

Claims (20)

1.一种方法，包括：
形成替代金属栅极；以及
形成抬高的P型源极漏极。
2.根据权利要求1所述的方法，其特征在于，所述方法包括形成介电常数大于10的栅极介电部。
3.根据权利要求1所述的方法，其特征在于，所述方法包括形成伪多晶硅栅电极，有选择地去除所述伪多晶硅栅电极，以及利用金属栅电极代替所述伪多晶硅栅电极。
4.根据权利要求1所述的方法，其特征在于，所述方法包括形成位于所述伪多晶硅栅电极之上的氮化物蚀刻阻止层。
5.根据权利要求4所述的方法，其特征在于，所述方法包括去除位于互补结构的PMOS侧上的所述氮化物蚀刻阻止层。
6.根据权利要求5所述的方法，其特征在于，所述方法包括形成U形栅极介电部。
7.一个半导体结构，包括：
衬底，所述衬底具有抬高的P型源极漏极；以及
金属栅电极。
8.根据权利要求7所述的结构，其特征在于，所述抬高的源极漏极由硅和锗形成。
9.根据权利要求7所述的结构，其特征在于，所述结构包括U形栅电极。
10.根据权利要求7所述的结构，其特征在于，所述结构包括介电常数大于10的栅电极。
11.一种方法，包括：
形成伪栅电极；
利用氮化物蚀刻阻止层覆盖所述伪栅电极；
去除所述氮化物蚀刻阻止层；
去除所述伪电极，并用金属栅电极来取代所述伪电极；以及
形成外延的P型源极漏极。
12.根据权利要求11所述的方法，其特征在于，所述方法包括形成抬高的源极漏极。
13.根据权利要求11所述的方法，其特征在于，所述方法包括形成介电常数大于10的栅极介电部。
14.根据权利要求11所述的方法，其特征在于，所述方法包括形成U型栅极介电部。
15.根据权利要求11所述的方法，其特征在于，所述方法包括形成P型掺杂硅锗的所述抬高的源极漏极。
16.根据权利要求11所述的方法，其特征在于，所述方法包括在硬质掩膜上形成所述氮化物蚀刻阻止层。
17.根据权利要求11所述的方法，其特征在于，所述方法包括形成多晶硅的所述伪栅电极。
18.根据权利要求11所述的方法，其特征在于，所述方法包括形成互补型金属氧化物半导体集成电路。
19.根据权利要求11所述的方法，其特征在于，所述方法包括利用金属栅电极作掩膜而蚀刻到半导体衬底内，并且通过沉积掺杂了硼的硅锗外延材料来形成所述P型源极漏极。
20.根据权利要求11所述的方法，其特征在于，所述方法包括从PMOS结构上去除氮化物蚀刻阻止层，同时在NMOS结构上保留所述氮化物蚀刻阻止层。
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