CN103000522A - Nmos晶体管的制造方法 - Google Patents
Nmos晶体管的制造方法 Download PDFInfo
- Publication number
- CN103000522A CN103000522A CN2011102701750A CN201110270175A CN103000522A CN 103000522 A CN103000522 A CN 103000522A CN 2011102701750 A CN2011102701750 A CN 2011102701750A CN 201110270175 A CN201110270175 A CN 201110270175A CN 103000522 A CN103000522 A CN 103000522A
- Authority
- CN
- China
- Prior art keywords
- layer
- dummy gate
- semiconductor substrate
- manufacture method
- pass transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 150000002500 ions Chemical class 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 72
- 239000000463 material Substances 0.000 claims description 10
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 230000008021 deposition Effects 0.000 claims description 5
- 239000011229 interlayer Substances 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 claims 4
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims 2
- 229910003818 SiH2Cl2 Inorganic materials 0.000 claims 2
- NEHMKBQYUWJMIP-UHFFFAOYSA-N chloromethane Chemical compound ClC NEHMKBQYUWJMIP-UHFFFAOYSA-N 0.000 claims 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims 2
- 230000005012 migration Effects 0.000 abstract 1
- 238000013508 migration Methods 0.000 abstract 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 15
- 238000002513 implantation Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000002800 charge carrier Substances 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical group [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000002829 reductive effect Effects 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000003542 behavioural effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本发明涉及一种NMOS晶体管的制造方法,该种方法包括以下步骤,提供半导体衬底,所述半导体衬底上具有包括栅介质层和伪栅极层的栅堆叠;在栅堆叠两侧的半导体衬底上掺杂N型离子,形成源极轻掺杂和漏极轻掺杂区;在栅堆叠侧壁形成侧墙,在源极区、漏极区选择性外延SiC层,从而对NMOS晶体管的沟道区施加拉应力;在栅堆叠两侧的半导体衬底上掺杂N型离子,形成源极重掺杂和漏极重掺杂区;移除所述伪栅极层。本发明的优点是选择性外延SiC层能够对NMOS晶体管的沟道区施加拉应力,并且移除伪栅极层后使得沟道内的拉应力进一步增强,载流子迁移率增大。
Description
技术领域
本发明涉及半导体领域,尤其涉及一种NMOS晶体管的制造方法。
背景技术
随着半导体制造技术的飞速发展,半导体器件为了达到更快的运算速度、更大的数据存储量以及更多的功能,半导体晶片朝向高集成度方向发展,MOS器件的栅极特征尺寸已经进入深亚微米阶段,栅极下的导电沟道变得越来越细且长度变得更短,这样就对工艺的要求越来越高。
然而,当诸如晶体管的集成电路元件的尺寸缩小时,不可避免地损害了它们的恒定材料特性和物理效应,从一定程度上降低了这些元件的性能。因此,已经对晶体管的设计进行了很多新的创新,以便把这些元件的性能保持到合适的水平。
场效应晶体管(FET)中保持性能的重要因素为载流子迁移率,在通过非常簿的栅介质层来与沟道隔离的栅极上施加电压的情况下,载流子迁移率可以影响掺杂半导体沟道中流动的电流或电荷量。
已经知道,根据载流子的类型和应力方向,FET的沟道区中的机械应力可以显著地提高或降低载流子的迁移率。在FET中,拉应力能够提高电子迁移率,降低空穴迁移率,可以显著提高NMOS的性能;而压应力可以提高空穴的迁移率,降低电子迁移率,可以有力地提高PMOS的性能。现有技术中已经提出了大量的结构和材料的改进,以用于在半导体材料中引入拉应力和压应力,例如在US2006/0160307中,就提出了一种在MOSFET器件上通过沉积应力层,并选择性地刻蚀全部或部分栅极层,来提高沟道中的载流子迁移率的方案。
然而,现有技术通常通过单独的应力层或者应力界面来改变载流子的迁移率,这将不利于器件尺寸的持续缩小,并且导致复杂的制造工艺。而且随着目前半导体器件尺寸的减小,相应的沟道区域也随之减小。因此,当应力材料膨胀时,对于施加在沟道区域两侧的源极区和漏极区应力材料,其相应增加的应力非常有限。从而不能够很好的改善MOSFET晶体管,尤其是N-FET晶体管的性能,这样,其对应构成的CMOS电路的性能也相应地较差。因此,需要提供一种新的半导体器件的制造方法,能够使得在不适用单独的应力层的情况下,提高NMOS器件的沟道区的载流子迁移率,降低器件的尺寸并简化工艺。
发明内容
本发明的目的是提供一种NMOS晶体管的制造方法,以在不增加单独的应力层的情况下增强N沟道应力。
本发明的技术解决方案是一种NMOS晶体管的制造方法,包括以下步骤:
提供半导体衬底,所述半导体衬底上具有包括栅介质层和伪栅极层的栅堆叠,所述伪栅极层包括至少两层不同材料;
在栅堆叠两侧的半导体衬底中掺杂N型离子,形成源极轻掺杂区和漏极轻掺杂区;
在栅堆叠侧壁上形成侧墙;
在源极区、漏极区选择性外延SiC层;
在栅堆叠两侧的半导体衬底中掺杂N型离子,形成源极重掺杂区和漏极重掺杂区;
移除所述伪栅极层。
作为优选:在形成源极重掺杂区和漏极重掺杂区后,还包括在半导体衬底上沉积层间介质层并通过化学机械抛光暴露出所述伪栅极层表面。
作为优选:在移除所述伪栅极层后,还包括在栅介质层上形成金属连接层。
作为优选:所述伪栅极层包括单层的单晶硅或多晶硅和至少一层SiC,所述单层的单晶硅或多晶硅的厚度为5nm-30nm,所述至少一层SiC的厚度为10nm-90nm,所述至少一层SiC中C的含量为0.1%-10%。
作为优选:所述伪栅极层包括多层SiC,且各层SiC中的C含量为相同值或呈梯度值。
作为优选:所述选择性外延SiC层的工艺条件包括:温度为500℃-1000℃,压强为1T-500T。
作为优选:所述选择性外延SiC层的工艺气体为SiH4或DCS(SiH2Cl2)、CH4、CH3Cl、CH2Cl2、HCl和H2;其中SiH4或DCS(SiH2Cl2)、CH4、CH3Cl、CH2Cl2、HCl的流量均为1sccm-1000sccm,H2的流量为0.1slm-50slm。
与现有技术相比,本发明的NMOS晶体管在沟道区域两侧的源极区、漏极区选择性外延SiC层后,使得沟道区域具有拉应力,通过移除具有张应力的伪栅极层后使得沟道内的拉应力大大增强,载流子迁移率增大,并且本发明不需要采用单独的应力层,制造工艺简单、成本低。
附图说明
图1示出了本发明的N型场效应晶体管的制造方法的流程图。
图2-10示出了本发明的N型场效应晶体管制造中的各个工艺步骤中的剖面图。
具体实施方式
本发明下面将结合附图作进一步详述:
在下面的描述中阐述了很多具体细节以便于充分理解本发明。但是本发明能够以很多不同于在此描述的其它方式来实施,本领域技术人员可以在不违背本发明内涵的情况下做类似推广,因此本发明不受下面公开的具体实施的限制。
其次,本发明利用示意图进行详细描述,在详述本发明实施例时,为便于说明,表示器件结构的剖面图会不依一般比例作局部放大,而且所述示意图只是实例,其在此不应限制本发明保护的范围。此外,在实际制作中应包含长度、宽度及深度的三维空间尺寸。
参考图1,图1示出了根据本发明的实施例的NMOS晶体管的制造方法,包括以下步骤:
在步骤101中,提供半导体衬底,所述半导体衬底上具有包括栅介质层和伪栅极层的栅堆叠。
如图2所示,首先提供半导体衬底1,所述半导体衬底1可以是单晶、多晶或非晶结构的硅或硅锗(SiGe),也可以是绝缘体上硅(SOI),或者其它的材料。在本实施例中选用单晶硅,在半导体衬底1中通过掺杂工艺例如离子注入工艺形成P阱(图中未示),再在半导体衬底1中形成隔离区11,例如浅沟槽隔离(STI)结构,以便电隔离连续的场效应晶体管器件。接着在衬底1上形成栅介质层21,所述栅介质层21通过沉积高K材料来形成,例如HfO2或HfSiO或HfTaO或HfTiO,栅介质层的厚度大约在2-10nm。而后在栅介质层21上形成伪栅极层22,所述伪栅极层通过沉积单层多晶硅或单晶硅221,然后沉积单层或多层SiC222来形成,沉积单层多晶硅或单晶硅221、单层或多层SiC222可以在同一腔室内完成,也可以在同一机台不同腔室内,也可以在不同机台内完成,所述机台可以选用单片或批量生产的炉台。所述单层多晶硅或单晶硅221厚度为5nm-30nm,所述单层或多层SiC222厚度为10nm-90nm,所述单层或多层SiC222中C的含量为0.1%-10%。多层SiC222中各层的C含量为相同值或从上往下递增或递减呈梯度值。如图3所示,然后通过刻蚀单层或多层SiC222、单层多晶硅或单晶硅221、栅介质层21,以形成包括栅介质层21和伪栅极层22的栅堆叠3。
在步骤102中,如图4所示,在栅堆叠3两侧的半导体衬底1中掺杂N型离子,形成源极轻掺杂区12a和漏极轻掺杂区12b;对于NMOS晶体管采用的N型杂质为磷和/或砷,通过第一N型离子注入工艺进行掺杂,掺杂杂质的原子被离化、分离、加速,形成离子流,扫描单晶硅衬底表面,杂质离子对单晶硅衬底表面进行物理轰击,进入表面并在表面以下停下,所述第一N型离子注入的工艺条件包括:注入剂量为1E13~1E14/cm2,注入能量为2~15Kev。
在步骤103中,如图5所示,在所述栅堆叠3的侧壁上形成侧墙4,所述侧墙4可以为但不限于氮化物材料,可以通过本领域公知的形成方法来完成。
而后,在步骤104中,如图6所示,在源极区、漏极区选择性外延生长SiC层5,从而对所述器件的沟道区施加拉应力;所述在源极区、漏极区选择性外延生长SiC层5的工艺条件包括:温度为500℃-1000℃,压强在1T-500T,选择性外延SiC层5工艺气体包括SiH4或DCS(SiH2Cl2)、CH4、CH3Cl、CH2Cl2、HCl和H2;其中SiH4或DCS(SiH2Cl2)、CH4、CH3Cl、CH2Cl2、HCl的每一个流量都为lsccm-1000sccm,H2的流量为0.1slm-50slm。
此后,在步骤105中,如图7所示,在栅堆叠3两侧的半导体衬底1中掺杂N型离子,形成源极重掺杂区13a和漏极重掺杂区13b,对于NMOS晶体管采用的N型杂质为磷和/或砷通过第二N型离子注入工艺进行掺杂,所述第二N型离子注入的工艺条件包括:注入剂量为2E15~5E15/cm2,注入能量为2~15Kev。
可选的,如图8所示,在选择性外延SiC层5后,在半导体衬底表面沉积层间介质层6并对栅堆叠3上方的层间介质层6进行化学机械抛光,以暴露出所述伪栅极层22表面。
在步骤106中,如图9所示,移除所述伪栅极层22,由于伪栅极层22的材料为多晶硅221和碳化硅222,可以采用反应离子刻蚀(RIE)或化学湿法刻蚀。当伪栅极层22被移除后,栅堆叠3中的反作用力进一步减小,从而进一步提高沟道区的拉应力,载流子迁移率增大。
可选的,如图10所示,在所述栅介质层21上沉积金属连接层7,所述金属连接层7的材料为AL,由此完成NMOS的制作。
本发明的NMOS晶体管在沟道区域两侧的源极区、漏极区选择性外延SiC层后,使得沟道区域具有拉应力,通过移除具有张应力的伪栅极层后使得沟道内的拉应力大大增强,载流子迁移率增大,并且本发明不需要采用单独的应力层,制造工艺简单、成本低。
以上所述仅为本发明的较佳实施例,凡依本发明权利要求范围所做的均等变化与修饰,皆应属本发明权利要求的涵盖范围。
Claims (7)
1.一种NMOS晶体管的制造方法,其特征在于,包括:
提供半导体衬底,所述半导体衬底上具有包括栅介质层和伪栅极层的栅堆叠,所述伪栅极层包括至少两层不同材料;
在栅堆叠两侧的半导体衬底中掺杂N型离子,形成源极轻掺杂区和漏极轻掺杂区;
在栅堆叠侧壁上形成侧墙;
在源极区、漏极区选择性外延SiC层;
在栅堆叠两侧的半导体衬底中掺杂N型离子,形成源极重掺杂区和漏极重掺杂区;
移除所述伪栅极层。
2.根据权利要求1所述NMOS晶体管的制造方法,其特征在于:在形成源极重掺杂区和漏极重掺杂区后,还包括在半导体衬底上沉积层间介质层并通过化学机械抛光暴露出所述伪栅极层表面。
3.根据权利要求1所述NMOS晶体管的制造方法,其特征在于:在移除所述伪栅极层后,还包括在栅介质层上形成金属连接层。
4.根据权利要求1所述NMOS晶体管的制造方法,其特征在于:所述伪栅极层包括单层的单晶硅或多晶硅和至少一层SiC,所述单层的单晶硅或多晶硅的厚度为5nm-30nm,所述至少一层SiC的厚度为10nm-90nm,所述至少一层SiC中C的含量为0.1%-10%。
5.根据权利要求4所述NMOS晶体管的制造方法,其特征在于:所述伪栅极层包括多层SiC,且各层SiC中的C含量为相同值或呈梯度值。
6.根据权利要求1所述NMOS晶体管的制造方法,其特征在于:所述选择性外延SiC层的工艺条件包括:温度为500℃-1000℃,压强为1T-500T。
7.根据权利要求1所述NMOS晶体管的制造方法,其特征在于:所述选择性外延SiC层的工艺气体为SiH4或DCS(SiH2Cl2)、CH4、CH3Cl、CH2Cl2、HCl和H2;其中SiH4或DCS(SiH2Cl2)、CH4、CH3Cl、CH2Cl2、HCl的流量均为1sccm-1000sccm,H2的流量为0.1slm-50slm。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110270175.0A CN103000522B (zh) | 2011-09-13 | 2011-09-13 | Nmos晶体管的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201110270175.0A CN103000522B (zh) | 2011-09-13 | 2011-09-13 | Nmos晶体管的制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN103000522A true CN103000522A (zh) | 2013-03-27 |
CN103000522B CN103000522B (zh) | 2015-04-01 |
Family
ID=47928949
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110270175.0A Active CN103000522B (zh) | 2011-09-13 | 2011-09-13 | Nmos晶体管的制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN103000522B (zh) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010049183A1 (en) * | 2000-03-30 | 2001-12-06 | Kirklen Henson | Method for forming MIS transistors with a metal gate and high-k dielectric using a replacement gate process and devices obtained thereof |
KR20050009497A (ko) * | 2003-07-16 | 2005-01-25 | 매그나칩 반도체 유한회사 | 반도체 소자의 트랜지스터 제조 방법 |
CN101203947A (zh) * | 2005-06-21 | 2008-06-18 | 英特尔公司 | 采用抬高的源极漏极和替代金属栅极的互补型金属氧化物半导体集成电路 |
CN101789368A (zh) * | 2008-09-12 | 2010-07-28 | 台湾积体电路制造股份有限公司 | 半导体元件及其制造方法 |
CN102034758A (zh) * | 2009-10-07 | 2011-04-27 | 台湾积体电路制造股份有限公司 | 集成电路元件的制造方法 |
CN102110612A (zh) * | 2009-12-29 | 2011-06-29 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
-
2011
- 2011-09-13 CN CN201110270175.0A patent/CN103000522B/zh active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010049183A1 (en) * | 2000-03-30 | 2001-12-06 | Kirklen Henson | Method for forming MIS transistors with a metal gate and high-k dielectric using a replacement gate process and devices obtained thereof |
KR20050009497A (ko) * | 2003-07-16 | 2005-01-25 | 매그나칩 반도체 유한회사 | 반도체 소자의 트랜지스터 제조 방법 |
CN101203947A (zh) * | 2005-06-21 | 2008-06-18 | 英特尔公司 | 采用抬高的源极漏极和替代金属栅极的互补型金属氧化物半导体集成电路 |
CN101789368A (zh) * | 2008-09-12 | 2010-07-28 | 台湾积体电路制造股份有限公司 | 半导体元件及其制造方法 |
CN102034758A (zh) * | 2009-10-07 | 2011-04-27 | 台湾积体电路制造股份有限公司 | 集成电路元件的制造方法 |
CN102110612A (zh) * | 2009-12-29 | 2011-06-29 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN103000522B (zh) | 2015-04-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10361201B2 (en) | Semiconductor structure and device formed using selective epitaxial process | |
US8853792B2 (en) | Transistors and semiconductor devices with oxygen-diffusion barrier layers | |
CN102656672B (zh) | 具有自对准外延源和漏的多栅半导体器件及其制造方法 | |
US10079279B2 (en) | FET with local isolation layers on S/D trench sidewalls | |
KR101474100B1 (ko) | 수직형 파워 mos 트랜지스터를 갖는 집적 회로 | |
CN101241932B (zh) | 金属氧化物半导体装置 | |
US7670914B2 (en) | Methods for fabricating multiple finger transistors | |
US8993395B2 (en) | Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers | |
KR20060103462A (ko) | 도전체 물질층을 갖는 트랜지스터 게이트 전극 형성 방법및 장치 | |
CN101140932A (zh) | 具有拉应力膜和压应力膜的cmos半导体器件 | |
CN103066122A (zh) | Mosfet及其制造方法 | |
CN106298665B (zh) | 半导体器件的制造方法 | |
CN101894799A (zh) | 提高nmos晶体管电子迁移率的方法 | |
US20230037719A1 (en) | Methods of forming bottom dielectric isolation layers | |
CN102347237B (zh) | 用于制造包含应力层的半导体器件结构的方法 | |
CN107591368B (zh) | 多阈值电压鳍式场效应晶体管及其形成方法 | |
US9514996B2 (en) | Process for fabricating SOI transistors for an increased integration density | |
CN103000522B (zh) | Nmos晶体管的制造方法 | |
TWI756018B (zh) | 半導體元件及半導體方法 | |
US8329540B2 (en) | Semiconductor device and manufacturing method thereof | |
US9337296B2 (en) | Integrated circuits having a metal gate structure and methods for fabricating the same | |
CN105006434A (zh) | 制造具有无掺杂沟道的mosfet的方法 | |
CN103681457A (zh) | 浅沟槽隔离结构的形成方法 | |
CN103871890A (zh) | Mos晶体管及其形成方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |