TWI756018B - 半導體元件及半導體方法 - Google Patents
半導體元件及半導體方法 Download PDFInfo
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- TWI756018B TWI756018B TW110100943A TW110100943A TWI756018B TW I756018 B TWI756018 B TW I756018B TW 110100943 A TW110100943 A TW 110100943A TW 110100943 A TW110100943 A TW 110100943A TW I756018 B TWI756018 B TW I756018B
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- 238000000034 method Methods 0.000 title claims abstract description 249
- 239000004065 semiconductor Substances 0.000 title claims abstract description 174
- 230000008569 process Effects 0.000 claims abstract description 218
- 238000005530 etching Methods 0.000 claims abstract description 93
- 125000006850 spacer group Chemical group 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 46
- 239000012212 insulator Substances 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 238000001312 dry etching Methods 0.000 claims description 13
- 238000001039 wet etching Methods 0.000 claims description 7
- LBIFSAULKFXGGV-UHFFFAOYSA-N O=[O+][O-].[F] Chemical compound O=[O+][O-].[F] LBIFSAULKFXGGV-UHFFFAOYSA-N 0.000 claims description 6
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 6
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 5
- 239000000460 chlorine Substances 0.000 claims description 5
- 229910052801 chlorine Inorganic materials 0.000 claims description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 2
- 229910052731 fluorine Inorganic materials 0.000 claims 2
- 239000011737 fluorine Substances 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 24
- 239000010703 silicon Substances 0.000 abstract description 24
- 239000010410 layer Substances 0.000 description 242
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 23
- 239000000463 material Substances 0.000 description 23
- 230000003647 oxidation Effects 0.000 description 11
- 238000007254 oxidation reaction Methods 0.000 description 11
- 239000003989 dielectric material Substances 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 238000001459 lithography Methods 0.000 description 7
- 230000003071 parasitic effect Effects 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000005336 cracking Methods 0.000 description 6
- 239000000243 solution Substances 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000004020 conductor Substances 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 239000005388 borosilicate glass Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000008367 deionised water Substances 0.000 description 3
- 229910021641 deionized water Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 125000004122 cyclic group Chemical group 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 2
- 238000000407 epitaxy Methods 0.000 description 2
- 230000009969 flowable effect Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- KDELTXNPUXUBMU-UHFFFAOYSA-N 2-[2-[bis(carboxymethyl)amino]ethyl-(carboxymethyl)amino]acetic acid boric acid Chemical compound OB(O)O.OB(O)O.OB(O)O.OC(=O)CN(CC(O)=O)CCN(CC(O)=O)CC(O)=O KDELTXNPUXUBMU-UHFFFAOYSA-N 0.000 description 1
- 229910015900 BF3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000005864 Sulphur Substances 0.000 description 1
- -1 Sulphur peroxide Chemical class 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000011066 ex-situ storage Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- IWTIUUVUEKAHRM-UHFFFAOYSA-N germanium tin Chemical compound [Ge].[Sn] IWTIUUVUEKAHRM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 229910052914 metal silicate Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 235000011007 phosphoric acid Nutrition 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910003468 tantalcarbide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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- H01L21/31111—Etching inorganic layers by chemical means
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
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- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
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Abstract
一種方法包括在絕緣體上矽基底上方形成閘極結構。絕
緣體上矽基底包括:基礎半導體層;絕緣層,位於基礎半導體層上方;以及頂部半導體層,位於絕緣層上方。所述方法更包括:在頂部表面上方且沿著閘極結構的側壁沉積閘極間隙壁層;蝕刻閘極間隙壁以界定閘極結構的側壁上的閘極間隙壁;在蝕刻閘極間隙壁層之後,使用第一蝕刻製程將凹槽蝕刻至頂部半導體層中;以及在第一蝕刻製程之後,使用第二蝕刻製程將凹槽進一步延伸至頂部半導體層中。第一蝕刻製程不同於第二蝕刻製程。所述方法更包括在第二蝕刻製程之後在凹槽中形成源極/汲極區。
Description
本發明實施例是關於半導體元件及半導體方法。
半導體元件用於多種電子應用中,諸如個人電腦、手機、數位相機以及其他電子設備。半導體元件通常藉由以下來製造:在半導體基底上依序地沉積材料的絕緣層或介電層、導電層以及半導體層,以及使用微影來圖案化各種材料層以在其上形成電路組件及部件。
半導體產業繼續藉由連續降低最小特徵大小來改良各種電子組件(例如,電晶體、二極體、電阻器、電容器等)的整合密度,從而允許更多組件整合至給定區域中。然而,隨著最小特徵大小減小,出現了應解決的額外問題。
在一些實施例中,一種半導體方法包括:在絕緣體上矽(SOI)基底上方形成閘極結構,絕緣體上矽基底包括基底半導體層、位於基底半導體層上方的絕緣層以及位於絕緣層上方的頂部半導體層;在頂部表面上方且沿著閘極結構的側壁沉積閘極間隙壁層;蝕刻閘極間隙壁層以界定閘極結構的側壁上的閘極間隙
壁;在蝕刻閘極間隙壁層之後,使用第一蝕刻製程將凹槽蝕刻至頂部半導體層中;在第一蝕刻製程之後,使用第二蝕刻製程將凹槽進一步延伸至頂部半導體層中,第一蝕刻製程不同於第二蝕刻製程;以及在第二蝕刻製程之後,在凹槽中形成源極/汲極區。
在一些實施例中,一種半導體方法包括:在絕緣體上矽(SOI)基底上形成閘極堆疊,SOI基底包括絕緣層上的頂部半導體層;在閘極堆疊的側壁上形成閘極間隙壁;在形成閘極間隙壁之後,蝕刻頂部半導體層以界定頂部半導體層的凹槽;使用氟-臭氧混合(FOM)製程將凹槽進一步延伸至頂部半導體層中,其中FOM製程的每一循環包括:在頂部半導體層中形成氧化區,氧化區在凹槽的側壁及底部表面上;以及蝕刻掉氧化區;以及在FOM製程之後,在凹槽中生長源極/汲極區。
在一些實施例中,一種半導體元件包括:絕緣體上矽(SOI)基底,SOI基底包括基礎半導體層、位於基礎半導體層上方的絕緣層以及位於絕緣層上方的頂部半導體層;閘極堆疊,位於SOI基底上;源極/汲極區,位於閘極堆疊的一側上,其中源極/汲極區將第一距離延伸至頂部半導體層中,第一距離在10埃至100埃的範圍內,頂部半導體層的一部分在源極/汲極區下且將源極/汲極區與絕緣層分隔開,且頂部半導體層的部分的厚度在10埃至50埃的範圍內。
100:元件
102:基底
104:基礎半導體層
106:絕緣層
108:頂部半導體層
108':暴露表面
110:虛設介電層
112:虛設閘極層
114:罩幕層
115:罩幕
116:虛設閘極介電質
118:虛設閘極電極
120:虛設閘極
122:閘極間隙壁層
124:閘極間隙壁
126、128、136:蝕刻製程
130:凹槽
132:氧化製程
134:氧化區
138:乾式蝕刻製程
140:濕式蝕刻製程
142:源極/汲極區
144:接觸蝕刻終止層
146:第一層間介電質
148:凹槽
150:通道區
152:閘極介電層
154:閘極電極
154A:襯層
154B:功函數調諧層
154C:填充材料
155:閘極罩幕
156:第二層間介電質
158:閘極接觸件
160:源極/汲極接觸件
D1、D2:深度
T1、T3:厚度
結合隨附圖式閱讀以下具體實施方式時將最佳地理解本揭露內容的態樣。應注意,根據業界中的標準慣例,各種特性未
按比例繪製。事實上,出於論述清晰起見,可任意地增加或縮減各種特徵的尺寸。
圖1至圖6、圖7A、圖7B、圖7C以及圖10至圖15說明根據一些實施例的製造電晶體元件的各種中間步驟。
圖8說明根據一些實施例的製造電晶體元件的中間步驟。
圖9說明根據一些實施例的製造電晶體元件的中間步驟。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的具體實例以簡化本揭露內容。當然,這些組件及配置僅為實例且並不意欲為限制性的。舉例而言,在以下描述中,第一特徵形成於第二特徵上方或第二特徵上可包括第一特徵及第二特徵直接接觸地形成的實施例,且亦可包括額外特徵可形成於第一特徵與第二特徵之間以使得第一特徵與第二特徵可不直接接觸的實施例。另外,本揭露內容可在各種實例中重複參考標號及/或字母。此重複是出於簡單性及清晰的目的,且本身不規定所論述的各種實施例及/或組態之間的關係。
另外,為易於描述,本文中可使用諸如「在...之下」、「在...下方」、「下部」、「在...上方」、「上部」以及類似者的空間相對術語,以描述如諸圖中所說明的一個部件或特徵相對於另一(一些)部件或特徵的關係。除圖式中所描繪的定向以外,空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。裝置可以其他方式定向(旋轉90度或處於其他定向),且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
各種實施例包括具有凸起的源極/汲極區(例如,在基底的頂部表面上方延伸)的全空乏絕緣體上矽(fully depleted silicon on insulator;FDSOI)電晶體。FDSOI電晶體可形成於絕緣體上矽(SOI)基底的頂部矽層上。為了形成源極/汲極區,頂部矽層可例如使用氟-臭氧混合(fluorine-ozone mixture;FOM)製程進行蝕刻以界定源極/汲極凹槽。蝕刻提供允許源極/汲極區更深地延伸至頂部矽層中的源極/汲極凹槽,進而減小所得電晶體中的寄生電阻且改良電氣效能。此外,頂部矽層的足夠厚部分保留在源極/汲極區之下,有利地在後續處理步驟期間為上覆特徵提供支撐。舉例而言,在各種實施例中,頂部矽層的約10埃至約50埃(諸如約20埃至約30埃)保留在源極/汲極凹槽下。因此,可有利地減少製造缺陷(例如,由於頂部矽層與底層內埋氧化物(buried oxide;BOX)層之間的熱膨脹係數(coefficient of thermal expansion;CTE)失配所引起的SOI基底破裂)。
雖然本文在平面電晶體的內容背景下描述了各種實施例,但應瞭解實施例不限於平面電晶體。舉例而言,各種實施例亦可應用於雙閘極元件、鰭式場效電晶體(fin field effect transistor;FinFET)元件、奈米結構(亦稱作環繞式閘極)元件或類似者。
圖1至圖6、圖7A、圖7B、圖7C以及圖10至圖15說明根據各種實施例的製造元件100的中間步驟的橫截面圖。在各種實施例中,元件100可經製造為具有多個元件區的半導體晶圓的一部分。電晶體製造於元件區中的每一者中,且內連線結構形成於電晶體上方以提供功能電路。在製造功能電路之後,可使用
合適的單體化製程將個別元件區與半導體晶圓中的其他元件區分隔開。因此,個別半導體晶粒(有時稱作裸晶粒)自單體化元件區的電路形成。
參考圖1,說明基底102。基底102可為包括基礎半導體層104、絕緣層106以及頂部半導體層108的SOI基底。一般而言,SOI基底為形成於絕緣層(例如,絕緣層106)上的半導體材料層(例如,頂部半導體層108)。基礎半導體層104提供支撐基底,所述支撐基底上形成其他特徵(包括絕緣層106及頂部半導體層108)。在一些實施例中,基礎半導體層104為矽基底或玻璃基底。亦可使用其他材料。
絕緣層106可為例如內埋氧化物(BOX)層、氧化矽層或類似者。在一些實施例中,絕緣層106可相對較薄。因而,可經由基礎半導體層104將體偏置更有效地施加至隨後形成的電晶體,且可改良所得電晶體的切換速度。此外,包括絕緣層106允許施加更高的偏置電壓,其允許更有效地控制所得電晶體。舉例而言,所得電晶體的電性能可經由其閘極以及經由極化底層的基礎半導體層104進行控制。因而,所得電晶體可在功能上與雙閘極元件相似。舉例而言,在一實施例中,絕緣層106的厚度T1可在約50奈米至約300奈米的範圍內。在其他實施例中,絕緣層106可具有其他尺寸。
頂部半導體層108可為半導體層,諸如矽層。在一些實施例中,頂部半導體層108相對較薄以改良形成於頂部半導體層108上的電晶體的遷移率。舉例而言,在一實施例中,頂部半導體層108的厚度T1可在約6奈米至約8奈米的範圍內。在其他實施
例中,頂部半導體層108可具有其他尺寸。由於頂部半導體層108較薄,故所得電晶體的通道區可為完全地未經摻雜的且無需執行袋形植入(pocket implantation)。此外,薄頂部半導體層108與底層絕緣層106限制所得電晶體的源極區與汲極區之間的電子的流速,從而減少漏電流。
儘管說明基底102的一個區,但應瞭解,基底102可包括其中製造不同類型的元件(例如,n型元件及p型元件)的諸多區。可在n型元件區與p型元件區之間安置任何數目個特徵(例如,隔離區及類似者)。剩餘的圖所說明的結構可適用於n型元件區及p型元件區兩者。n型元件區與p型元件區在結構上的差異(若存在)描述於隨附各圖式的文字中。
在圖2中,虛設介電層110形成於頂部半導體層108上。虛設介電層110可為例如氧化矽、氮化矽、其組合或類似者,且可根據可接受的技術進行沉積或熱生長。
虛設閘極層112形成於虛設介電層110上方。虛設閘極層112可為導電材料且可由包括以下的群組選出:多晶矽(polycrystalline-silicon/polysilicon)、多晶矽-鍺(多晶SiGe)、金屬氮化物、金屬矽化物、金屬氧化物以及金屬。在一個實施例中,非晶矽經沉積且再結晶以產生多晶矽。虛設閘極層112可藉由物理氣相沉積(physical vapor deposition;PVD)、化學氣相沉積(chemical vapor deposition;CVD)、濺鍍沉積或用於沉積導電材料的其他技術進行沉積。
罩幕層114可沉積於虛設閘極層112上方。罩幕層114可包括例如SiN、SiON或類似者。在此實例中,形成單個虛設閘
極層112及單個罩幕層114。在一些實施例中,分離虛設閘極層可形成於n型元件區與p型元件區中,且分離罩幕層可形成於n型元件區與p型元件區中。
在圖3中,可使用可接受的微影及蝕刻技術來圖案化罩幕層114(參看圖7)以形成罩幕115。罩幕115的圖案可隨後經轉移至虛設閘極層112以形成虛設閘極電極118。罩幕115的圖案亦可藉由可接受的蝕刻技術轉移至虛設介電層110以形成虛設閘極介電質116。因此,形成包括虛設閘極電極118及虛設閘極介電質116的虛設閘極120。虛設閘極120覆蓋頂部半導體層108的相應通道區150。罩幕115的圖案可用以將虛設閘極120中的每一者與相鄰的虛設閘極實體地分隔開。純粹地為了易於說明,僅說明單個虛設閘極120,但應瞭解,多個虛設閘極120形成於基底102上。
在一些實施例中,通道區150為未經摻雜的。舉例而言,可不對頂部半導體層108執行植入製程直至生長隨後形成的源極/汲極區為止(參看圖10)。在一些實施例中,經輕度摻雜的汲極區(lightly-doped drain region;LDD區)並未形成於頂部半導體層108中,且並不執行袋形植入。
儘管說明罩幕115的一個層,但用以形成虛設閘極120的各種圖案化技術可使用罩幕115的多個層。舉例而言,可使用包括雙重圖案化或多重圖案化製程的一或多個微影製程來圖案化虛設閘極120。一般而言,雙重圖案化製程或多重圖案化製程組合微影製程與自對準製程,從而使得產生具有例如比可另外使用單個、直接微影製程所獲得的小的間距的圖案。舉例而言,在一個
實施例中,犧牲層形成於基底上方且使用微影製程進行圖案化。間隙壁使用自對準製程在經圖案化犧牲層旁邊形成間隙壁。隨後移除犧牲層,且剩餘的間隙壁可隨後用以圖案化虛設閘極120。
在所說明的實施例中,罩幕115可保留在虛設閘極120上。在其他實施例中,可在形成虛設閘極120之後及在形成其他特徵(例如,閘極間隙壁層122,參看圖4)之前移除罩幕115。
在圖4中,閘極間隙壁層122在虛設閘極120的側壁上方且沿著虛設閘極120的側壁沉積。在並未移除罩幕115的實施例中,閘極間隙壁層122亦沉積於罩幕115上方。閘極間隙壁層122藉由使用合適的製程(諸如,CVD、原子層沉積(atomic layer deposition;ALD)或類似者)共形地沉積而形成。閘極間隙壁層122的絕緣材料可為氧化矽、氮化矽、氮氧化矽、碳氮化矽、其多層或類似者。
在圖5中,閘極間隙壁層122經圖案化以界定閘極堆疊(虛設閘極120)的側壁上的閘極間隙壁124。圖案化閘極間隙壁層122可包括例如非等向性蝕刻製程126。在一些實施例中,蝕刻製程126為使用合適的蝕刻劑(諸如氯基蝕刻劑)的乾式蝕刻製程。蝕刻製程126在一些實施例中可為電漿製程。在一些實施例中,蝕刻製程126可為使用在約10千瓦至約100千瓦的範圍內的RF功率的高功率蝕刻製程。此外,蝕刻製程126可為時控蝕刻製程(timed etching process)以界定閘極間隙壁124的形狀。舉例而言,蝕刻製程126的時長可在約30秒至約150秒的範圍內。在其他實施例中,用以界定間隙壁124的蝕刻製程126可包括不同參數集。
在圖6中,可施加額外的蝕刻製程128。蝕刻製程128可在蝕刻製程126之後原位形成(例如在同一處理腔室中)。在一些實施例中,圖5中所描述的蝕刻製程126可損壞頂部半導體層108的暴露表面108'(例如,未由虛設閘極120或閘極間隙壁124覆蓋的頂部半導體層108的表面)。蝕刻製程128可蝕刻頂部半導體層108的暴露表面108'以減少頂部半導體層108的表面損壞。舉例而言,蝕刻製程128可減少暴露表面108'的粗糙度,使得隨後形成的源極/汲極區(參看圖10中的源極/汲極區142)可生長以具有較少缺陷。
在一些實施例中,蝕刻製程128為使用合適的蝕刻劑(諸如氯基蝕刻劑)的乾式蝕刻製程。蝕刻製程128在一些實施例中可為電漿製程。蝕刻製程128可為使用比蝕刻製程126更低的RF功率的低功率蝕刻製程。舉例而言,蝕刻製程128可使用在約15瓦至約1千瓦的範圍內的RF功率。此外,蝕刻製程128可為時控蝕刻製程。舉例而言,蝕刻製程128的時長可在約5秒至約150秒的範圍內。在其他實施例中,蝕刻製程128可包括不同參數集。
在其他實施例中,蝕刻製程128可包括除了乾式蝕刻製程外或代替乾式蝕刻製程的一或多個濕式蝕刻製程。舉例而言,可在乾式蝕刻製程之後施加濕式蝕刻製程,或可施加濕式蝕刻製程代替乾式蝕刻製程。濕式蝕刻製程可為移除形成於頂部半導體層108的暴露表面108'上的表面顆粒、原生氧化物層或類似者的清潔製程。濕式蝕刻製程可進一步鈍化頂部半導體層108的暴露表面108'。濕式蝕刻製程可使用以下蝕刻劑的任意組合:三硼酸乙二胺四乙酸(tris-borate-ethylene diamine tetraacetic acid;
TBE)、過氧化硫混合物(Sulphur peroxide mixture;SPM)、SC-1溶液(例如,包括氨、去離子水以及過氧化氫)、SC-2溶液(例如,包括氨、去離子水以及過氧化氫)或類似者。舉例而言,可將使用TBE、SC-1溶液以及SC-2溶液的第一濕式蝕刻製程施加至暴露表面108',且可隨後將使用SPM及SC-1溶液的第二濕式蝕刻製程施加至暴露表面108'。在使用濕式蝕刻製程的實施例中,可在濕式製程之後將乾燥製程及旋轉製程施加至半導體晶圓。
蝕刻製程126及蝕刻製程128的組合可凹入頂部半導體層108的暴露表面108'。舉例而言,蝕刻製程126及蝕刻製程128可在頂部半導體層108中形成凹槽130。凹槽130可延伸深度D1,所述深度D1為頂部半導體層108的最頂部表面與凹槽130的底部表面之間的高度差異。在一些實施例中,深度D1可在約5埃至約50埃的範圍內。在一些實施例中,深度D1可在大於零且小於6埃的範圍內。在其他實施例中,凹槽130可延伸至不同深度。蝕刻製程128可為用於移除頂部半導體層108的表面上的缺陷且略微平坦化頂部半導體層108的略微蝕刻製程。
在蝕刻製程128中,閘極間隙壁124可遮蔽閘極堆疊(虛設閘極120)鄰近的頂部半導體層108的一或多個部分。因此,每一凹槽130藉由頂部半導體層108與閘極堆疊(虛設閘極120)及其底層虛設閘極介電質116分隔開。舉例而言,凹槽130可不水平地延伸至虛設閘極介電質116。
在圖7A至圖7C中,凹槽130進一步延伸至頂部半導體層108中。藉由延伸凹槽130,在凹槽130中隨後生長的源極/汲極區(例如,源極/汲極區142,參看圖10)可進一步延伸至基底
102中。因而,可改良所得電晶體的電氣效能。舉例而言,已觀測到,與並未深入延伸至基底102中的源極/汲極區相比,可減少所得元件的寄生電容。
延伸凹槽130可包括循環FOM製程。FOM製程可在蝕刻製程128之後原位執行,或FOM製程可異位執行(例如,在不同處理腔室中)為蝕刻製程128。
圖7A及圖7B說明FOM製程的一個循環。首先,如由圖7A所說明,可將氧化製程132施加至凹槽130的暴露表面。氧化製程132在藉由凹槽130暴露的頂部半導體層108的部分中形成氧化區134。在頂部半導體層108為矽層的實施例中,氧化區134為氧化矽區。
氧化製程132可包括使製程氣體流動,所述製程氣體包括凹槽130的表面上方的臭氧(O3)。製程氣體可具有濃度在百萬分之(parts per million;ppm)20至百萬分之40範圍內的臭氧。在一些實施例中,可執行氧化製程132歷時20秒至30秒的持續時間。氧化製程132可為自限制製程(self-limiting process)。舉例而言,氧化製程132繼續在頂部半導體層108中形成氧化區134直至頂部半導體層108的上部部分氧飽和為止。由於凹槽130在蝕刻製程128之後與閘極堆疊(虛設閘極120)分隔開,且閘極間隙壁124亦遮蔽閘極堆疊(虛設閘極120)鄰近的頂部半導體層108的一或多個部分,故每一氧化區134仍可藉由頂部半導體層108與閘極堆疊(虛設閘極120)及其底層虛設閘極介電質116分隔開。氧化區134可不水平地延伸至虛設閘極介電質116。
接著,如在圖7B中所說明,蝕刻製程136移除氧化區
134。蝕刻製程136可為例如使用經稀釋的氟化氫(hydrogen fluoride;dHF)的濕式蝕刻。氟化氫可在水(例如,去離子水或類似者)中稀釋為約50:1至約150:1範圍內的稀釋液。在其他實施例中,可使用不同的蝕刻劑。在一些實施例中,可執行蝕刻製程136歷時20秒至40秒的持續時間。可在氧化區134與頂部半導體層108之間選擇性地進行蝕刻製程136,使得蝕刻製程136移除氧化區134而無需顯著蝕刻剩餘的(例如,未氧化的)頂部半導體層108。
由於氧化製程132為自限制製程且蝕刻製程136為選擇性製程(selective process),故可精確地控制在FOM製程的每一循環期間所移除的頂部半導體層108的量。圖7A及圖7B中所說明的循環(例如,氧化製程132及蝕刻製程136)可重覆任何數目次直至凹槽130將所需厚度延伸至頂部半導體層108中為止。在一實例中,執行氧化及蝕刻的兩個循環以將凹槽130延伸至頂部半導體層108中。在其他實施例中,可使用不同數目個循環。
在執行FOM製程的所要數目個循環之後,在圖7C中說明所得結構。作為FOM製程的結果,凹槽130將深度D2延伸至頂部半導體層108中。在一些實施例中,深度D2在約10埃至約100埃的範圍內,諸如在約20埃至約30埃之間或在約17埃至約25埃之間。已觀測到,藉由將凹槽130延伸至頂部半導體層108中至上述範圍內的深度,可改良所得電晶體的電氣效能。舉例而言,源極/汲極區(參看圖10)隨後形成於凹槽130中。更深的凹槽130(例如,具有上述深度的凹槽)允許源極/汲極區進一步延伸至頂部半導體層108中,其減少摻雜劑自源極/汲極區至電晶體
的未經摻雜通道區(例如,區150,參看圖15)中的擴散。藉由減少摻雜劑擴散,可有利地減少通道區150的寄生電阻。舉例而言,在模擬資料中已觀測到,當凹槽130具有約20埃的深度D2時,寄生電阻減少約40歐每微米。亦已在模擬資料中觀測到,可在具有至頂部半導體層108中延伸上文所描述的深度的實施例源極/汲極區的nMOS電晶體中實現6%或大於6%的效能提昇。因此,頂部半導體層108的凹槽130水平地延伸至閘極間隙壁124下方,且並未在FOM製程之後延伸至虛設閘極介電質116。
然而,亦觀測到,需要將頂部半導體層108的一部分保留在凹槽130之下。舉例而言,凹槽130可藉由頂部半導體層108與絕緣層106分隔開,且凹槽130與絕緣層106之間的頂部半導體層108的厚度T3可在約10埃至約50埃的範圍內,諸如約20埃至約30埃。由於頂部半導體層108(例如,包括矽)及絕緣層106(例如,包括氧化矽)在CTE上的差異,故頂部半導體層108可在其過薄時易於破裂。破裂的風險可在涉及加熱晶圓的後續製程期間增加。藉由在上述厚度範圍內保留頂部半導體層108的一部分,可避免製造缺陷(例如,破裂)。已觀測到,當凹槽130更深地延伸至頂部半導體層108中以使得厚度T3超出上述範圍時,導致基底102的破裂增加。
圖7A及圖7B說明實現圖7C的實施例結構的一個方法。亦可使用其他方法。舉例而言,圖8說明根據另一實施例的在元件中延伸凹槽130的方法。在圖8中,結構可與圖7A相似且類似參考標號指示使用類似製程形成的類似部件。乾式蝕刻製程138用以延伸凹槽130。乾式蝕刻製程138使用合適的蝕刻劑,諸如氯
基蝕刻劑。乾式蝕刻製程138可為電漿製程。在一些實施例中,乾式蝕刻製程138可為使用例如在約15瓦至約1千瓦的範圍內的RF功率的低功率蝕刻製程。此外,乾式蝕刻製程138可為時控蝕刻製程。舉例而言,乾式蝕刻製程138的時長可在約5秒至約150秒的範圍內。在其他實施例中,乾式蝕刻製程138可包括不同參數集。乾式蝕刻製程138產生與圖7C中所說明的相似的結構。可執行後續處理(例如,如下文在圖10至圖15中所描述)以完成元件。
圖9說明延伸凹槽130的又一方法。在圖9中,濕式蝕刻製程140用以延伸凹槽130。在圖9中,結構可與圖7A相似且類似參考標號指示使用類似製程形成的類似部件。濕式蝕刻製程140使用合適的蝕刻劑,諸如包括H3PO4或類似者的溶液。此外,濕式蝕刻製程140可為時控蝕刻製程。舉例而言,濕式蝕刻製程140的時長可在約10秒至約180秒的範圍內。在其他實施例中,濕式蝕刻製程140可包括不同參數集。濕式蝕刻製程140產生與圖7C中所說明的相似的結構。可執行後續處理(例如,如下文在圖10至圖15中所描述)以完成元件。
在圖10中,磊晶源極/汲極區142形成於凹槽130中。磊晶源極/汲極區142可在所得電晶體的相應通道區中施加應力,進而改良效能。磊晶源極/汲極區142形成於頂部半導體層108中,使得每一虛設閘極120安置在磊晶源極/汲極區142的相應鄰近對之間。在一些實施例中,閘極間隙壁124用於以適合的側向距離將磊晶源極/汲極區142與虛設閘極120分隔開,使得磊晶源極/汲極區142不使所得電晶體的隨後形成的閘極短路。磊晶源極/汲
極區142可稱作凸起的源極/汲極區,此是因為所述源極/汲極區在基底102的最頂部表面上方延伸。因此,磊晶源極/汲極區142可在閘極間隙壁124的底部端下方及上方水平地延伸,磊晶源極/汲極區142可不延伸至虛設閘極介電質116。
晶圓的n型元件區中的磊晶源極/汲極區142可藉由以下來形成:遮蔽晶圓的p型元件區,以及蝕刻n型元件區中的頂部半導體層108以在頂部半導體層108中形成凹槽130(例如,如上文所描述)。隨後,n型元件區中的磊晶源極/汲極區142磊晶生長於凹槽130中。在一些實施例中,用以形成磊晶源極/汲極區142的磊晶生長製程可為低溫製程。舉例而言,磊晶生長製程可在約400℃至約600℃的溫度下執行。藉由在此溫度範圍內執行磊晶,可有利地減少施加於基底上的應力。
磊晶源極/汲極區142可包括任何可接受的材料,諸如適用於n型電晶體的材料。舉例而言,n型元件區中的磊晶源極/汲極區142可包括在通道區中施加拉伸應變的材料,諸如矽、碳化矽、摻磷碳化矽、磷化矽或類似者。n型元件區中的磊晶源極/汲極區142可具有自頂部半導體層108的相應表面凸起的表面且可具有琢面。
晶圓的p型元件區中的磊晶源極/汲極區142可藉由以下來形成:遮蔽晶圓的n型元件區,以及蝕刻p型元件區中的頂部半導體層108以在頂部半導體層108中形成凹槽130(例如,如上文所描述)。隨後,p型元件區中的磊晶源極/汲極區142磊晶生長於凹槽130中。在一些實施例中,用以形成磊晶源極/汲極區142的磊晶生長製程可為低溫製程。舉例而言,磊晶生長製程可在約
400℃至約600℃的溫度下執行。藉由在此溫度範圍內執行磊晶,可有利地減少施加於基底上的應力。
磊晶源極/汲極區142可包括任何可接受的材料,諸如適用於p型電晶體的材料。舉例而言,p型元件區中的磊晶源極/汲極區142可包括在通道區中施加壓縮應變的材料,諸如矽-鍺、摻硼矽-鍺、鍺、鍺錫或類似者。p型元件區中的磊晶源極/汲極區142可亦具有自頂部半導體層108的相應表面凸起的表面且可具有琢面。
磊晶源極/汲極區142可植入有摻雜劑以形成源極/汲極區,緊接著退火。源極/汲極區可具有在約1019立方公分與約1021立方公分之間的雜質濃度。p型雜質可為硼、氟化硼、銦或類似者。n型雜質可為磷、砷、銻或類似者。在一些實施例中,磊晶源極/汲極區142可在生長期間經原位摻雜。
磊晶源極/汲極區142將深度D2延伸至頂部半導體層108中。如上文所論述,深度D2可在約10埃至約100埃的範圍內。藉由將源極/汲極區142更深地延伸於頂部半導體層108中,可減少摻雜劑自源極/汲極區142至電晶體的未經摻雜通道區150中的擴散。藉由減少摻雜劑擴散,可有利地減少通道區150的寄生電阻。舉例而言,在模擬資料中已觀測到,當源極/汲極區142延伸約20埃的深度D2時,寄生電阻減少約40歐每微米。亦已在模擬資料中觀測到,可在具有至頂部半導體層108中延伸上文所描述的深度D2的實施例源極/汲極區142的nMOS電晶體中實現6%或大於6%的效能提昇。
在圖11中,第一層間介電質(interlayer dielectric;ILD)
146沉積於圖10中所說明的結構上方。第一ILD 146可由介電材料形成,且可藉由任何適合的方法沉積,所述方法諸如CVD、電漿增強型CVD(plasma-enhanced CVD;PECVD)或FCVD。介電材料可包括:磷矽酸鹽玻璃(Phospho-Silicate Glass;PSG)、硼矽酸鹽玻璃(Boro-Silicate Glass;BSG)、硼摻雜磷矽酸鹽玻璃(Boron-Doped Phospho-Silicate Glass;BPSG)、未摻雜矽酸鹽玻璃(undoped Silicate Glass;USG)或類似者。可使用藉由任何可接受的製程形成的其他絕緣材料。在一些實施例中,接觸蝕刻終止層(contact etch stop layer;CESL)144安置於第一ILD 146與磊晶源極/汲極區142、罩幕115以及閘極間隙壁124之間。CESL 144可包括介電材料,諸如氮化矽、氧化矽、氮氧化矽或類似者,所述介電材料具有與上覆第一ILD 146的材料不同的蝕刻速率。
在圖12中,可執行平坦化製程(諸如CMP)以使第一ILD 146的頂部表面與虛設閘極120或罩幕115的頂部表面齊平。平坦化製程亦可沿著罩幕115的側壁移除虛設閘極120上的罩幕115及閘極間隙壁124。在平坦化製程之後,虛設閘極120的頂部表面、閘極間隙壁124以及第一ILD 146齊平。因此,虛設閘極120的頂部表面經由第一ILD 146暴露。在一些實施例中,罩幕115可保留,在此狀況下平坦化製程使第一ILD 146的頂部表面與罩幕115的頂部表面齊平。
在圖13中,在蝕刻步驟中移除虛設閘極電極118及罩幕115(若存在),使得凹槽148形成。在一些實施例中,僅移除虛設閘極電極118,且虛設閘極介電質116保留且由凹槽148暴露。在一些實施例中,虛設閘極介電質116自晶粒的第一區(例如,
核心邏輯區)中的凹槽148移除且保留在晶粒的第二區(例如,輸入/輸出區)中的凹槽148中。在一些實施例中,藉由非等向性乾式蝕刻製程移除虛設閘極電極118。舉例而言,蝕刻製程可包括使用反應氣體的乾式蝕刻製程,所述乾式蝕刻製程選擇性地蝕刻虛設閘極電極118而不蝕刻第一ILD 146或閘極間隙壁124。每一凹槽148暴露且/或上覆於頂部半導體層108的通道區150。當蝕刻虛設閘極電極118時,安置在虛設閘極介電質116的鄰近對之間的每一通道區150可用作蝕刻停止層。在移除虛設閘極電極118之後,可隨後視情況移除虛設閘極介電質116。
在圖14中,形成閘極介電層152及閘極電極154以供替換閘極。閘極介電層152共形地沉積於凹槽148中,諸如頂部半導體層108的頂部表面上及閘極間隙壁124的側壁上。閘極介電層152亦可形成於第一ILD 146的頂部表面上。根據一些實施例,閘極介電層152包括氧化矽、氮化矽或其多層。在一些實施例中,閘極介電層152包括高k介電材料,且在這些實施例中,閘極介電層152可具有大於約7.0的k值,且可包括鉿、鋁、鋯、鑭、錳、鋇、鈦、鉛以及其組合的金屬氧化物或矽酸鹽。閘極介電層152的形成方法可包括分子束沉積(Molecular-Beam Deposition;MBD)、ALD、PECVD以及類似者。在虛設閘極介電質116的部分保留在凹槽148中的實施例中,閘極介電層152包括虛設閘極介電質116(例如,SiO2)的材料。
閘極電極154分別沉積於閘極介電層152上方且填充凹槽148的剩餘部分。閘極電極154可包括含金屬材料,諸如氮化鈦、氧化鈦、氮化鉭、碳化鉭、鈷、釕、鋁、鎢、其組合或其多
層。舉例而言,閘極電極154可包括任何數目個襯層154A、任何數目個功函數調諧層154B以及填充材料154C。在填充凹槽148之後,可執行平坦化製程(諸如CMP)以移除閘極介電層152及閘極電極154的材料的多餘部分,所述多餘部分位於ILD 146的頂部表面上方。閘極電極154及閘極介電層152的材料的剩餘部分因而形成所得電晶體的替換閘極。閘極電極154及閘極介電層152可共同稱為「閘極堆疊」。
n型元件區及p型元件區中的閘極介電層152的形成可同時發生使得每一區中的閘極介電層152由相同材料形成,且閘極電極154的形成可同時發生使得每種類型的區中的閘極電極154由相同材料形成。在一些實施例中,每種類型的區中的閘極介電層152可由不同製程形成以使得閘極介電層152可為不同材料,且/或每一區中的閘極電極154可由不同製程形成以使得閘極電極154可為不同材料。當使用獨特製程時,各種遮蔽步驟可用於遮蔽及暴露適當的區。
圖13及圖14說明替換閘極製程。在其他實施例中,可省略替換閘極製程,且虛設閘極電極118及虛設閘極介電質116可用作所得電晶體的功能閘極電極及閘極介電層。
在圖15中,第二ILD 156沉積於第一ILD 146上方。在一些實施例中,第二ILD 156為由可流動CVD方法形成的可流動膜。在一些實施例中,第二ILD 156由介電材料形成,所述介電材料諸如PSG、BSG、BPSG、USG或類似者,且可藉由任何適合的方法沉積,所述方法諸如CVD及PECVD。根據一些實施例,在形成第二ILD 156之前,閘極堆疊(包括閘極介電層152及對
應上覆閘極電極154)經凹入,使得凹槽直接形成於閘極堆疊上方及閘極間隙壁124的相對部分之間,如在圖15中所說明。包括介電材料(諸如氮化矽、氮氧化矽或類似者)的一或多個層的閘極罩幕155填充於凹槽中,繼之以平坦化製程以移除在第一ILD 146上方延伸的介電材料的多餘部分。隨後形成的閘極接觸件158穿過閘極罩幕155以接觸凹入閘極電極154的頂部表面。
亦如由圖15所說明,根據一些實施例,閘極接觸件158及源極/汲極接觸件160經由第二ILD 156及第一ILD 146形成。源極/汲極接觸件160的開口穿過第一ILD 146及第二ILD 156形成,且閘極接觸件158的開口穿過第二ILD 156及閘極罩幕155形成。可使用可接受的微影及蝕刻技術形成開口。襯層(諸如擴散障壁層、黏著層或類似者)及導電材料形成於開口中。襯層可包括鈦、氮化鈦、鉭、氮化鉭或類似者。導電材料可為銅、銅合金、銀、金、鎢、鈷、鋁、鎳或類似者。可執行平坦化製程(諸如CMP)以自ILD 156的表面移除多餘材料。剩餘的襯層及導電材料在開口中形成源極/汲極接觸件160及閘極接觸件158。可執行退火製程以在磊晶源極/汲極區142與源極/汲極接觸件160之間的界面處形成矽化物。源極/汲極接觸件160實體耦接且電耦接至磊晶源極/汲極區142,且閘極接觸件158實體耦接且電耦接至閘極電極106。源極/汲極接觸件160及閘極接觸件158可形成於不同製程中,或可形成於相同製程中。儘管展示為形成於相同橫截面中,但應瞭解,源極/汲極接觸件160及閘極接觸件158中的每一者可形成於不同橫截面中,此可避免接觸短路。
因此,形成實施例元件100。元件可包括具有凸起的源極
/汲極區142的FDSOI電晶體。FDSOI電晶體可形成於絕緣體上矽基底102的頂部矽層(頂部半導體層108)上。為了形成源極/汲極區142,可例如使用多個蝕刻製程來蝕刻頂部矽層(頂部半導體層108)以界定源極/汲極凹槽130。所述蝕刻提供允許源極/汲極區142更深地延伸至頂部矽層(頂部半導體層108)中的源極/汲極凹槽130,進而減小電晶體中的寄生電阻且改良電氣效能。此外,至少約10埃至約50埃的頂部矽(頂部半導體層108)保留在源極/汲極區142下方,此有利地提供足夠厚的頂部矽層(頂部半導體層108)以在後續處理步驟期間支撐上覆特徵。因此,可有利地減少製造缺陷(例如,由頂部矽與底層內埋氧化物(BOX)層之間的CTE失配引起的絕緣體上矽基底破裂)。
在一些實施例中,一種方法包括:在絕緣體上矽(SOI)基底上方形成閘極結構,絕緣體上矽基底包括基底半導體層、位於基底半導體層上方的絕緣層以及位於絕緣層上方的頂部半導體層;在頂部表面上方且沿著閘極結構的側壁沉積閘極間隙壁層;蝕刻閘極間隙壁層以界定閘極結構的側壁上的閘極間隙壁;在蝕刻閘極間隙壁層之後,使用第一蝕刻製程將凹槽蝕刻至頂部半導體層中;在第一蝕刻製程之後,使用第二蝕刻製程將凹槽進一步延伸至頂部半導體層中,第一蝕刻製程不同於第二蝕刻製程;以及在第二蝕刻製程之後,在凹槽中形成源極/汲極區。在一些實施例中,在第一蝕刻製程之後且在第二蝕刻製程之前,凹槽延伸小於6埃的深度至頂部半導體層中。在一些實施例中,在第二蝕刻製程之後,凹槽延伸10埃至100埃的深度至頂部半導體層中。在一些實施例中,在第二蝕刻製程之後,凹槽下的頂部半導體層的
厚度在10埃至50埃的範圍內。在一些實施例中,在第二蝕刻製程之後,凹槽下的頂部半導體層的厚度在20埃至30埃的範圍內。在一些實施例中,第二蝕刻製程為氟-臭氧混合(FOM)製程。在一些實施例中,FOM製程為循環製程,且其中FOM製程的每一循環包括:使用臭氧來氧化藉由凹槽暴露的頂部半導體層的部分以在頂部半導體層中形成氧化區;以及使用經稀釋的氟化氫(dHF)蝕刻氧化區。在一些實施例中,第二蝕刻製程為使用含氯氣體的乾式蝕刻製程。在一些實施例中,第二蝕刻製程為使用H3PO4的濕式蝕刻製程。在一些實施例中,蝕刻閘極間隙壁層包括第三蝕刻製程,第三蝕刻製程及第一蝕刻製程各自為乾式蝕刻製程,且第三蝕刻製程以比第一蝕刻製程更高的RF功率執行。
在一些實施例中,一種方法包括:在絕緣體上矽(SOI)基底上形成閘極堆疊,SOI基底包括絕緣層上的頂部半導體層;在閘極堆疊的側壁上形成閘極間隙壁;在形成閘極間隙壁之後,蝕刻頂部半導體層以界定頂部半導體層的凹槽;使用氟-臭氧混合(FOM)製程將凹槽進一步延伸至頂部半導體層中,其中FOM製程的每一循環包括:在頂部半導體層中形成氧化區,氧化區在凹槽的側壁及底部表面上;以及蝕刻掉氧化區;以及在FOM製程之後,在凹槽中生長源極/汲極區。在一些實施例中,源極/汲極區延伸10埃至100埃的距離至頂部半導體層中。在一些實施例中,頂部半導體層的一部分在源極/汲極區下且將源極/汲極區與絕緣層分隔開,頂部半導體層的部分的厚度在10埃至50埃的範圍內。在一些實施例中,頂部半導體層的部分的厚度在20埃至30埃的範圍內。
在一些實施例中,一種元件包括:絕緣體上矽(SOI)基底,SOI基底包括基礎半導體層、位於基礎半導體層上方的絕緣層以及位於絕緣層上方的頂部半導體層;閘極堆疊,位於SOI基底上;源極/汲極區,位於閘極堆疊的一側上,其中源極/汲極區將第一距離延伸至頂部半導體層中,第一距離在10埃至100埃的範圍內,頂部半導體層的一部分在源極/汲極區下且將源極/汲極區與絕緣層分隔開,且頂部半導體層的部分的厚度在10埃至50埃的範圍內。在一些實施例中,源極/汲極區在頂部半導體層的最頂部表面上方延伸。在一些實施例中,頂部半導體層的部分的厚度在20埃至30埃的範圍內。在一些實施例中,第一距離在20埃至30埃的範圍內。在一些實施例中,第一距離在17埃至25埃的範圍內。在一些實施例中,元件更包括位於閘極堆疊的側壁上的閘極間隙壁,其中閘極間隙壁在源極/汲極區與閘極堆疊之間,且源極/汲極區在閘極間隙壁下延伸。
前文概述若干實施例的特徵,以使得所屬領域的技術人員可較好地理解本揭露內容的態樣。所屬領域的技術人員應瞭解,其可容易地使用本揭露內容作為設計或修改用於進行本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。所屬領域的技術人員亦應認識到,此類等效構造並不脫離本揭露內容的精神及範疇,且所屬領域的技術人員可在不脫離本揭露內容的精神及範疇的情況下在本文中作出改變、替代及更改。
100:元件
102:基底
104:基礎半導體層
106:絕緣層
108:頂部半導體層
142:源極/汲極區
144:接觸蝕刻終止層
146:第一層間介電質
150:通道區域
152:閘極介電層
154:閘極電極
155:閘極罩幕
156:第二層間介電質
158:閘極接觸件
160:源極/汲極接觸件
Claims (10)
- 一種半導體方法,包括:在絕緣體上矽基底上方形成閘極結構,所述絕緣體上矽基底包括:基礎半導體層;絕緣層,位於所述基礎半導體層上方;以及頂部半導體層,位於所述絕緣層上方;在頂部表面上方且沿著所述閘極結構的側壁沉積閘極間隙壁層;蝕刻所述閘極間隙壁層以界定所述閘極結構的所述側壁上的閘極間隙壁;在蝕刻所述閘極間隙壁層之後,使用第一蝕刻製程將凹槽蝕刻至所述頂部半導體層中;在所述第一蝕刻製程之後,使用第二蝕刻製程將所述凹槽進一步延伸至所述頂部半導體層中,所述第一蝕刻製程不同於所述第二蝕刻製程;以及在所述第二蝕刻製程之後,在所述凹槽中形成源極/汲極區。
- 如請求項1之半導體方法,其中在所述第一蝕刻製程之後及在所述第二蝕刻製程之前,所述凹槽延伸小於6埃的深度至所述頂部半導體層中。
- 如請求項1之半導體方法,其中在所述第二蝕刻製程之後,所述凹槽延伸10埃至100埃的深度至所述頂部半導體層中。
- 如請求項1之半導體方法,其中在所述第二蝕刻製 程之後,所述凹槽下的所述頂部半導體層的厚度在10埃至50埃的範圍內。
- 如請求項1之半導體方法,其中所述第二蝕刻製程為氟-臭氧混合製程。
- 如請求項1之半導體方法,其中所述第二蝕刻製程為使用含氯氣體的乾式蝕刻製程。
- 如請求項1之半導體方法,其中所述第二蝕刻製程為使用H3PO4的濕式蝕刻製程。
- 如請求項1之半導體方法,其中蝕刻所述閘極間隙壁層包括第三蝕刻製程,所述第三蝕刻製程及所述第一蝕刻製程各自為乾式蝕刻製程,且所述第三蝕刻製程在比所述第一蝕刻製程更高的RF功率下執行。
- 一種半導體方法,包括:在絕緣體上矽基底上形成閘極堆疊,所述絕緣體上矽基底包括絕緣層上的頂部半導體層;在所述閘極堆疊的側壁上形成閘極間隙壁;在形成所述閘極間隙壁之後,蝕刻所述頂部半導體層以界定所述頂部半導體層中的凹槽;使用氟-臭氧混合製程將所述凹槽進一步延伸至所述頂部半導體層中,其中所述氟-臭氧混合製程的每一循環包括:在所述頂部半導體層中形成氧化區,所述氧化區在所述凹槽的側壁及底部表面上;以及蝕刻掉所述氧化區;以及在所述氟-臭氧混合製程之後,在所述凹槽中生長源極/汲極 區。
- 一種半導體元件,包括:絕緣體上矽基底,所述絕緣體上矽基底包括:基礎半導體層;絕緣層,位於所述基礎半導體層上方;以及頂部半導體層,位於所述絕緣層上方;閘極堆疊,位於所述絕緣體上矽基底上;源極/汲極區,位於所述閘極堆疊的一側上,其中所述源極/汲極區延伸第一距離至所述頂部半導體層中,所述第一距離在10埃至100埃的範圍內,所述頂部半導體層的一部分在所述源極/汲極區下且將所述源極/汲極區與所述絕緣層分隔開,且所述頂部半導體層的所述部分的厚度在10埃至50埃的範圍內。
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