TWI831110B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TWI831110B
TWI831110B TW111100637A TW111100637A TWI831110B TW I831110 B TWI831110 B TW I831110B TW 111100637 A TW111100637 A TW 111100637A TW 111100637 A TW111100637 A TW 111100637A TW I831110 B TWI831110 B TW I831110B
Authority
TW
Taiwan
Prior art keywords
source
region
nanostructure
drain
layer
Prior art date
Application number
TW111100637A
Other languages
English (en)
Other versions
TW202232582A (zh
Inventor
世海 楊
王培宇
志安 徐
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202232582A publication Critical patent/TW202232582A/zh
Application granted granted Critical
Publication of TWI831110B publication Critical patent/TWI831110B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41733Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • H01L29/0673Nanowires or nanotubes oriented parallel to a substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66439Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742Thin film unipolar transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/775Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079Substrate region of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/161Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

在一個實施例中,一種半導體裝置包括:一第一奈米結構位於一基底的上方,此第一奈米結構包括一通道區和一第一輕摻雜源極/汲極區,此第一輕摻雜源極/汲極區與此通道區相鄰;一第一磊晶源極/汲極區係圍繞前述第一輕摻雜源極/汲極區的四個側面;一層間介電層,位於前述第一磊晶源極/汲極區的上方;一源極/汲極接觸件係延伸貫穿前述層間介電層,此源極/汲極接觸件係圍繞前述第一磊晶源極/汲極區的四個側面;以及一閘極堆疊,鄰近前述源極/汲極接觸件以及第一磊晶源極/汲極區,此閘極堆疊係圍繞前述通道區的四個側面。

Description

半導體裝置及其製造方法
本發明實施例內容是有關於一種半導體裝置及其製造方法,特別是有關於一種具有圍繞磊晶源極/汲極區的所有側面的源極/汲極接觸件的半導體裝置及其製造方法,可降低源極/汲極接觸件的接觸電阻。
半導體裝置係使用於各種不同的電子產品應用中,例如個人電腦、手機、數位相機及其他電子設備(electronic equipment)。半導體裝置的製造通常依序透過沉積絕緣層或介電層、導電層及半導體層材料於一半導體基底上方,並利用微影製程(lithography)來對各種不同的材料層進行圖案化,以在半導體基底的上方形成電路部件及元件。
半導體工業經由不斷縮小最小特徵部件尺寸(minimum feature size),其容許更多的部件整合於一給定區域,而可不斷地改進各種不同電子部件(例如,電晶體、二極體、電阻器、電容器等等)的積體密度。然而,當最小特徵部件的尺寸縮小時,也引發了待解決的其他問題。
本發明的一些實施例提供一種半導體裝置的製造方法。此半導體 裝置的製造方法包括圖案化複數個半導體層,以形成一第一奈米結構(first nanostructure)、一第二奈米結構(second nanostructure)和第三奈米結構(third nanostructure),前述第二奈米結構係設置在前述第一奈米結構和前述第三奈米結構之間。在一些實施例中,此半導體裝置的製造方法還包括在覆蓋前述第二奈米結構的一第二區域(second region)的同時,係摻雜一雜質於前述第二奈米結構的一第一區域(first region)。在一些實施例中,此半導體裝置的製造方法還包括去除前述第一奈米結構和前述第三奈米結構的部分,以暴露出前述第二奈米結構的前述第一區域的頂部和底部。在一些實施例中,此半導體裝置的製造方法還包括在前述第二奈米結構的前述第一區域的頂部和底部的周圍生長一磊晶源極/汲極區(epitaxial source/drain region)。在一些實施例中,此半導體裝置的製造方法還包括在前述第二奈米結構的前述第二區域的頂部和底部的周圍形成一閘極堆疊(gate stack)。
本發明的一些實施例又提供一種半導體裝置。此半導體裝置包括:一第一奈米結構(first nanostructure)位於一基底的上方,前述第一奈米結構包括一通道區(channel region)和一第一輕摻雜源極/汲極(lightly doped source/drain,LDD)區,前述第一輕摻雜源極/汲極區與前述通道區相鄰。在一些實施例中,此半導體裝置還包括一第一磊晶源極/汲極區(first epitaxial source/drain region)係圍繞前述第一輕摻雜源極/汲極區的四個側面。在一些實施例中,此半導體裝置還包括一層間介電層(ILD layer),位於前述第一磊晶源極/汲極區的上方;和一源極/汲極接觸件(source/drain contact)係延伸貫穿前述層間介電層,前述源極/汲極接觸件係圍繞前述第一磊晶源極/汲極區的四個側面。在一些實施例中,此半導體裝置還包括一閘極堆疊(gate stack),鄰近前述源極/汲極 接觸件以及前述第一磊晶源極/汲極區,前述閘極堆疊係圍繞前述通道區的四個側面。
本發明的一些實施例又提供一種半導體裝置。此半導體裝置包括:一奈米結構(nanostructure)位於一基底的上方,前述奈米結構包括一通道區(channel region)和一輕摻雜源極/汲極區(LDD region),前述輕摻雜源極/汲極區係與前述通道區相鄰,前述通道區係在一第一剖面(first cross-section)中具有一第一寬度以及一第一厚度,前述輕摻雜源極/汲極區係在一第二剖面(second cross-section)中具有一第二寬度和一第二厚度,前述第二寬度小於前述第一寬度,前述第二厚度小於前述第一厚度,前述第一剖面和前述第二剖面均垂直於前述奈米結構的一縱軸(longitudinal axis)。在一些實施例中,此半導體裝置還包括一閘極堆疊(gate stack),前述閘極堆疊在前述第一剖面中係完全圍繞前述通道區。在一些實施例中,此半導體裝置還包括一磊晶源極/汲極區(epitaxial source/drain region),前述磊晶源極/汲極區在前述第二剖面中係完全圍繞前述輕摻雜源極/汲極區。
50:基底
50N:n型區域
50P:p型區域
52:多層堆疊
52A:第一半導體層
52B:第二半導體層
54:鰭片
56:奈米結構
56A:第一奈米結構
56B:第二奈米結構
58:通道區
60:隔離區(淺溝槽隔離區)
62:虛置介電層
64:虛置閘極層
66:遮罩層
72:虛置介電質
74:虛置閘極
76:遮罩
80:閘極間隔物
82:輕摻雜源極/汲極區
84:源極/汲極開口
86:內部間隔物
88:磊晶源極/汲極區
88A:磊晶源極/汲極區的第一子集
88B:磊晶源極/汲極區的第二子集
92:虛置層
94:第一層間介電質(第一層間介電層)
94A:下部區域
94B:上部區域
96:凹槽
98:切割開口
100:閘極結構
102:閘極介電質
104:閘極電極
106:源極/汲極接觸開口
108:矽化物
112:源極/汲極接觸件
112A:下部源極/汲極接觸件
112B:上部源極/汲極接觸件
114:第二層間介電質(第二層間介電層)
116:閘極接觸件
T1:第一厚度
T2:第二厚度
T3:第三厚度
T4:厚度
W1:第一寬度
W2:第二寬度
A-A,B-B,C-C:剖面
藉由以下的詳細描述配合所附圖式,可以更加理解本發明實施例的內容。需強調的是,根據產業上的標準慣例,許多部件(feature)並未按照比例繪製。事實上,為了能清楚地討論,各種部件的尺寸可能被任意地增加或減少。
第1圖示出了根據一些實施例的一簡化的奈米場效電晶體(nano-FET)的示例。
第2、3、4、5、6圖是根據一些實施例的製造奈米場效電晶體(nano-FET)的 中間階段的立體視圖。
第7A、7B、7C、8A、8B、8C、9A、9B、9C、10A、10B、10C、11A、11B、11C、12A、12B、12C、13A、13B、13C、14A、14B、14C、15A、15B、15C、16A、16B、16C、17A、17B、17C、18A、18B、18C、19A、19B、19C、20A、20B、20C圖是根據一些實施例的奈米場效電晶體(nano-FET)在製造過程中進一步的多個中間階段的剖面圖。
第21、22、23圖是根據一些實施例的製造奈米場效電晶體(nano-FET)的中間階段的剖面圖。
第24圖是根據一些其他實施例的奈米場效電晶體(nano-FET)的剖面圖。
第25A、25B、25C圖是根據一些其他實施例的奈米場效電晶體(nano-FET)的剖面圖。
以下內容提供了很多不同的實施例或範例,用於實現本發明實施例的不同部件。組件和配置的具體範例描述如下,以簡化本發明實施例。當然,這些僅僅是範例,並非用以限定本發明實施例。舉例來說,敘述中若提及一第一特徵部件形成於一第二特徵部件之上方或位於其上,可能包含上述第一和第二特徵部件直接接觸的實施例,也可能包含額外的特徵部件形成於上述第一特徵和上述第二特徵部件之間,使得第一和第二特徵部件不直接接觸的實施例。另外,本發明實施例可能在許多範例中重複元件符號及/或字母。這些重複是為了簡化和清楚的目的,其本身並非代表所討論各種實施例及/或配置之間有特定的關係。
再者,文中可能使用空間上的相關用語,例如「在...之下」、「在...下方」、「下方的」、「在...上方」、「上方的」及其他類似的用語,以便描述如圖所示之一個元件或部件與其他的元件或部件之間的關係。此空間上的相關用語除了包含圖式繪示的方位外,也包含使用或操作中的裝置的不同方位。裝置可以被轉至其他方位(旋轉90度或其他方位),則在此所使用的空間相對描述可同樣依旋轉後的方位來解讀。
根據一些實施例,奈米場效電晶體(nano-FETs)的源極/汲極區圍繞奈米結構生長。源極/汲極區環繞奈米結構的所有側面(例如,四個側面)。隨後形成的接觸件(contacts)因此可以環繞源極/汲極區的所有側面(例如,四個側面)。因此,可以增加接觸面積,降低源極/汲極接觸的接觸電阻(contact resistance,RC),並且改善奈米場效電晶體的性能。
第1圖示出了根據一些實施例的一簡化的奈米場效電晶體(nano-FET)的示例。第1圖是剖切的三維視圖,其中為了清楚說明,係省略了奈米場效電晶體的某些部件。奈米場效電晶體(nano-FET)可以是奈米片場效電晶體(nanosheet field-effect transistors,NSFET)、奈米線場效電晶體(nanowire field-effect transistors,NWFET)、全繞式閘極場效電晶體(gate-all-around field-effect transistors,GAAFET)、或前述之類似物。
奈米場效電晶體(nano-FET)包括在基底50之上的奈米結構(nanostructures)56,例如在從基底50延伸的鰭片54之上。奈米結構56是半導體層,可做為奈米場效電晶體(nano-FET)的通道區(channel regions)。隔離區(isolation regions)60,例如淺溝槽隔離(shallow trench isolation,STI)區,設置在基底50上方和相鄰的鰭片54之間,這些鰭片54可以突出於相鄰的隔離區60之間。雖然隔 離區60被描述/說明為與基底50分離,如本文所述,但“基底”一詞可以表示單獨的半導體基底,或是表示半導體基底與隔離區的組合。此外,雖然鰭片54被敘述為與基底50是一種單一的且連續的材料,但是鰭片54以及/或基底50可以包括單一材料或多種材料。在此上下文中,鰭片54指的是在相鄰的隔離區60的上方和相鄰的隔離區60之間延伸的部分。
閘極結構(gate structures)100係包裹奈米結構56的周圍。閘極結構100包括閘極介電質(gate dielectrics)102和閘極電極(gate electrodes)104。閘極介電質102是沿著奈米結構56的頂面、側壁和底面並且可以沿著鰭片54的側壁和在鰭片54的頂面的上方設置。閘極電極104位於閘極介電質102的上方。磊晶源極/汲極區(epitaxial source/drain regions)88係包裹奈米結構56的周圍,並設置在閘極結構100的相對側上。在形成多個電晶體的實施例中,磊晶源極/汲極區88可以在各種電晶體之間共用。例如,相鄰的磊晶源極/汲極區88可以電性耦合,例如通過將一相同的源極/汲極接觸件耦合相鄰的磊晶源極/汲極區88。一個或多個層間介電層(interlayer dielectric layers,ILDs)(以下有更詳細地討論)係位於磊晶源極/汲極區88以及/或閘極結構100的上方,並形成穿過層間介電層(以下有更詳細地討論)的接觸件至磊晶源極/汲極區88和閘極電極104。
本文提出的一些實施例是在使用一閘極後置製程(gate-last process)形成的奈米場效電晶體(nano-FET)的背景下討論的。在一些其他實施例中,也可以使用一閘極先製製程(gate-first process)。此外,一些實施例考慮在平面裝置中使用的方面,例如平面場效電晶體(planar FETs),或鰭式場效電晶體(FinFETs)。
第1圖進一步說明了在後面的圖式中所使用的參考剖面。剖面 A-A係沿著一奈米結構56的縱軸,並且在例如一奈米場效電晶體(nano-FET)的磊晶源極/汲極區88之間的電流流動的方向上。剖面B-B垂直於剖面A-A,且剖面B-B係沿著一閘極電極104的縱軸。剖面C-C垂直於剖面A-A並且平行於剖面B-B,並且剖面C-C延伸穿過奈米場效電晶體(nano-FET)的磊晶源極/汲極區88。為清楚說明,隨後的圖式係參照了這些參考剖面。
第2圖至第6圖是根據一些實施例的製造奈米場效電晶體(nano-FET)的中間階段的立體視圖。第2圖至第6圖顯示了與第1圖類似的立體視圖。
在第2圖中,提供用於形成奈米場效電晶體(nano-FET)的一基底50。此基底50可以是一半導體基底,例如一塊狀半導體(bulk semiconductor)、一絕緣層上覆半導體(Semiconductor-On-Insulator;SOI)基底、或其類似物,其可以是摻雜(例如摻雜有p型或n型摻雜物)或未摻雜的基底。基底50可以是一晶圓,例如一矽晶圓。一般而言,一絕緣層上覆半導體(SOI)基底是在一絕緣層上形成的一半導體材料層。此絕緣層可例如是一埋入式的氧化物(buried oxide,BOX)層、一氧化矽層、或類似物。將上述絕緣層形成於一基底上,上述基底通常是一矽基底或一玻璃基底。也可以使用其他基底,例如多層或漸變基底。在一些實施例中,基底50的半導體材料可包含:矽;鍺;一化合物半導體(compound semiconductor),包含碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦及/或銻化銦;一合金半導體,包含矽鍺(silicon germanium)、磷化砷化鎵(gallium arsenide phosphide)、砷化鋁銦(aluminum indium arsenide)、砷化鋁鎵(aluminum gallium arsenide)、砷化鎵銦(gallium indium arsenide)、磷化鎵銦(gallium indium phosphide)以及/或磷化砷化鎵銦(gallium indium arsenide phosphide);或上述之組合。
基底50具有一n型區域50N和一p型區域50P。n型區域50N可用於形成n型裝置,例如NMOS電晶體,例如n型奈米場效電晶體(n-type nano-FETs),而p型區域50P可用於形成p型裝置,例如PMOS電晶體,例如p型奈米場效電晶體(p-type nano-FETs)。n型區域50N可以與p型區域50P物理性的分離(未示出兩區域的分離),並且可以在n型區域50N和p型區域50P之間設置任何數量的裝置部件(例如,其他的主動裝置、摻雜區、隔離結構等)。
基底50可以輕摻雜一p型雜質或一n型雜質。可以在基底50的上方部分進行一抗穿通(anti-punch-through,APT)佈植,以形成一抗穿通(APT)區域。在抗穿通佈植(APT implantation)期間,可以在n型區域50N和p型區域50P中植入摻雜物。摻雜物可以具有與隨後將在n型區域50N和p型區域50P的各個中形成的源極/汲極區的導電類型相反的導電類型。抗穿通(APT)區域可以在隨後形成的奈米場效電晶體(nano-FET)中的源極/汲極區下方延伸,抗穿通(APT)區域將在後續製程中形成。抗穿通(APT)區域可以用來減少從源極/汲極區到基底50的漏電流。在一些實施例中,抗穿通(APT)區域中的摻雜濃度可以在大約1018cm-3到大約1019cm-3的範圍內。
在基底50的上方形成一多層堆疊52。多層堆疊52包括交替設置的第一半導體層(first semiconductor layers)52A和第二半導體層52B。第一半導體層52A是由第一半導體材料形成,第二半導體層52B是由第二半導體材料形成。前述之半導體材料分別可選自基底50的候選的半導體材料。在所示實施例中,多層堆疊52包括三層的第一半導體層52A和三層的第二半導體層52B交替設置。應當理解的是,多層堆疊52可以包括任何數量的第一半導體層52A和第二半導體層52B。
在所示實施例中,第二半導體層52B將用於在n型區域50N和p型區域50P中形成奈米場效電晶體(nano-FET)的通道區(channel regions)。第一半導體層52A為犧牲層(sacrificial layers)(或虛置層(dummy layers)),在後續製程中將會被移除,以暴露出在兩個區域中的第二半導體層52B的頂面和底面。第二半導體層52B的第二半導體材料是可以同時適用於n型奈米場效電晶體(n-type nano-FET)和p型奈米場效電晶體(p-type nano-FET)的材料,例如矽;而相較於第二半導體材料(例如矽鍺)的蝕刻,第一半導體層52A的第一半導體材料是具有一高蝕刻選擇性(high etching selectivity)。
在另一實施例中,第一半導體層52A將用於在一個區域(例如,p型區域50P)中形成奈米場效電晶體(nano-FET)的通道區(channel regions),而第二半導體層52B將用於在另一個區域(例如,n型區域50N)中形成奈米場效電晶體的通道區。第一半導體層52A的第一半導體材料可適用於p型奈米場效電晶體(p-type nano-FETs),例如矽鍺(例如,SixGe1-x,其中x可在0至1的範圍內)、純鍺或實質上純鍺、III-V族化合物半導體、II-VI族化合物半導體、或前述之類似物,而第二半導體層52B的第二半導體材料可適用於n型奈米場效電晶體(n-type nano-FETs),例如矽、碳化矽(silicon carbide)、III族-V化合物半導體、II-VI化合物半導體、或前述之類似物。第一半導體材料和第二半導體材料可以相對於彼此的蝕刻具有高蝕刻選擇性,從而可以在不去除n型區域50N中的第二半導體層52B的情況下去除第一半導體層52A,並且可以在不去除p型區域50P中的第一半導體層52A的情況下去除第二半導體層52B。
多層堆疊52的每一層可以使用例如氣相磊晶(vapor phase epitaxy,VPE)、分子束磊晶(molecular beam epitaxy,MBE)、化學氣相沉積 (chemical vapor deposition,CVD)、原子層沉積(atomic layer deposition,ALD)、或類似之製程形成。多層堆疊52的每個層可以形成為小的厚度,例如在大約5nm至大約30nm範圍內的厚度。在一些實施例中,一組的層(例如,第二半導體層52B)形成為比另一組的層(例如,第一半導體層52A)更薄。例如,在第二半導體層52B用於形成通道區且第一半導體層52A為犧牲層(或虛設層)的實施例中,第一半導體層52A可形成為具有第一厚度T1,而第二半導體層52B可形成為具有第二厚度T2,其中第二厚度T2比第一厚度T1來得小大約30%至大約60%。將第二半導體層52B形成為較小的厚度,可使得能以更大的密度形成通道區。
在第3圖中,在基底50和多層堆疊52中蝕刻出溝槽(trenches),以形成鰭片54和奈米結構56。鰭片54是在基底50中圖案化的半導體條(semiconductor strips)。奈米結構56包括在鰭片54上的多層堆疊52的留下部分。具體而言,奈米結構56包括交替設置的第一奈米結構(first nanostructures)56A和第二奈米結構(second nanostructures)56B。第一奈米結構56A和第二奈米結構56B分別由第一半導體層52A的留下部分和第二半導體層52B的留下部分形成。在形成之後,在結構的中間處的第二奈米結構56B係分別設置在兩個第一奈米結構56A之間。前述蝕刻可以是任何可接受的蝕刻製程,例如反應離子蝕刻(reactive ion etch,RIE)、中性束蝕刻(neutral beam etch,NBE)、類似蝕刻製程、或前述蝕刻製程之組合。前述蝕刻可以是非等向性的(anisotropic)。
可以通過任何合適的方法來圖案化鰭片54和奈米結構56。例如,可以使用一道或多道光學微影製程(photolithography processes)進行圖案化以形成鰭片54和奈米結構56。上述光學微影製程包括雙重圖案化(double-patterning)或多重圖案化(multi-patterning)製程。一般而言,雙重圖案化或多重圖案化製程 是結合了光學微影及自對準製程,得以使形成的圖案的節距(pitch)小於使用單一、直接的微影製程所能得到的節距。例如,在一實施例中,在一基底上方形成一犧牲層,並使用光學微影製程將此犧牲層圖案化。使用自對準製程在圖案化的犧牲層旁邊形成間隔物(spacers)。然後去除犧牲層,然後可以使用留下的間隔物來圖案化鰭片54和奈米結構56。
鰭片54和奈米結構56的寬度可以在大約8nm至大約40nm的範圍內。為了說明的目的,n型區域50N和p型區域50P中的鰭片54和奈米結構56被繪示為具有基本上相等的寬度。在一些實施例中,一個區域(例如,n型區域50N)中的鰭片54和奈米結構56可以比另一個區域(例如,p型區域50P)中的鰭片54和奈米結構56更寬或更窄。
在第4圖中,淺溝槽隔離(STI))區60與鰭片54相鄰形成。淺溝槽隔離區60可以通過在基底50和奈米結構56的上方以及在相鄰的鰭片54之間沉積一絕緣材料而形成。絕緣材料可以是一氧化物例如氧化矽、或是一氮化物例如氮化矽、或類似物、或前述之組合,並且可以藉由高密度電漿化學氣相沉積(HDP-CVD)、流動式化學氣相沉積(flowable chemical vapor deposition,FCVD)、類似方法、或前述之組合而形成。上述絕緣材料也可以是使用通過任何可接受的製程形成的其他絕緣材料。在例示的實施例中,絕緣材料是通過一流動式化學氣相沉積(FCVD)製程形成的氧化矽。一旦形成絕緣材料,就可以進行退火製程(anneal process)。在一實施例中,可採用以過量的絕緣材料覆蓋奈米結構56的方式形成絕緣材料。雖然絕緣材料被繪示為單層,但一些實施例可以利用多層絕緣材料。例如,在一些實施例中,可以先沿著基底50、鰭片54和奈米結構56的表面形成一襯層(liner)。之後,可以在襯層的上方形成如上述的一填充材料(fill material)。
然後對絕緣材料進行一去除製程(removal process),以去除奈米結構56上方多餘的絕緣材料。在一些實施例中,可使用一平坦化製程(planarization process),例如化學機械研磨(chemical mechanical polish,CMP)、回蝕製程(etch-back process)、前述之組合、或類似製程,進行絕緣材料的去除。上述之平坦化製程暴露出奈米結構56,使得在平坦化製程完成之後,奈米結構56的頂面和絕緣材料的頂面是共平面的(在製程變異範圍內)。
然後,使絕緣材料下凹(recess),以形成淺溝槽隔離區60。下凹絕緣材料可使得鰭片54的上方部分從相鄰的淺溝槽隔離區60之間突出。在所示之實施例中,淺溝槽隔離區60的頂面係在鰭片54的頂面之下。在一些實施例中,淺溝槽隔離區60的頂面在鰭片54的頂面之上或與鰭片54的頂面共平面(在製程變化內)。此外,淺溝槽隔離區60的頂面可以具有如圖所示的一平坦表面、一凸形(convex)表面、一凹形(concave)表面(例如為淺碟凹陷(dishing))、或前述形狀之組合。可以通過適當的蝕刻以使淺溝槽隔離區60的頂面形成為平坦表面、凸形表面及/或凹形表面。可以使用可接受的蝕刻製程使淺溝槽隔離區60凹陷,例如使用對絕緣材料的材料具有選擇性的蝕刻製程(例如,以比對鰭片54和奈米結構56的材料更快的蝕刻速率對絕緣材料的材料進行蝕刻)。舉例來說,可以使用使用例如稀釋氫氟酸(dilute hydrofluoric acid;dHF acid),來進行氧化物的移除。
上述製程僅是可以如何形成鰭片54和奈米結構56的一個例子。在一些實施例中,鰭片54和奈米結構56可以通過磊晶生長製程(epitaxial growth process)形成。例如,可以在基底50的頂面上方形成一介電層(dielectric layer),並且可以通過對介電層蝕刻形成溝槽(trenches)以暴露出下面的基底50。可以在 溝槽中磊晶生長磊晶結構(epitaxial structures),並且介電層可以是下凹的,使得磊晶結構從介電層突出以形成鰭片54和奈米結構56。磊晶結構可以包括上面討論的交替設置的半導體材料,例如第一半導體材料和第二半導體材料。在以磊晶生長形成磊晶結構的實施例中,磊晶生長的材料可以在生長期間進行原位摻雜(in situ doped),這可以避免之前以及/或之後的佈植,雖然原位摻雜和佈植摻雜也可以一起進行。
再者,可以在基底50、鰭片54以及/或奈米結構56中形成適當的井區(wells)。在一些實施例中,可以在n型區域50N中形成一p型井區(p-type well),且可以在p型區域50P中形成一n-型井區。在另一實施例中,可在n型區域50N和p型區域50P兩者中形成p型井區或n型井區。
在不同井區類型的實施例中,n型區域50N和p型區域50P的不同佈植步驟可以通過一光阻或其他遮罩(masks)而實現。例如,可以在鰭片54、奈米結構56和n型區域50N中的淺溝槽隔離區60的上方形成一光阻。係對光阻進行圖案化,以暴露出p型區域50P。光阻可以通過使用一旋轉塗佈技術形成,並且可以使用可接受的光學微影技術進行圖案化。一旦光阻被圖案化,在p型區域50P中進行一n型雜質佈植(n-type impurity implant),並且光阻可以做為一遮罩,以基本上防止n型雜質植入到n型區域50N中。n型雜質可以是磷(phosphorus)、砷(arsenic)、銻(antimony)、或類似物,以植入該區域中,其濃度在大約1013cm-3至大約1014cm-3的範圍內。在佈植之後,係去除光阻,例如可通過可接受的灰化製程(ashing process)去除光阻。
在p型區域50P的佈植之後,在p型區域50P中的鰭片54、奈米結構56和淺溝槽隔離區60上方形成光阻。對光阻進行圖案化以暴露出n型區域 50N。可以藉由使用旋轉塗佈技術(spin-on technique)形成光阻,並且可以使用可接受的光學微影技術對光阻進行圖案化。在光阻被圖案化之後,就可以在n型區域50N中進行p型雜質的佈植,並且光阻可以做為一遮罩,以實質上避免p型雜質被植入到p型區域50P中。p型雜質可以是硼(boron)、氟化硼(boron fluoride)、銦(indium)、或類似物植入於n型區域50N中,且其濃度在大約1013cm-3至大約1014cm-3的範圍內。在植入之後,可以去除光阻,例如通過可接受的灰化製程(ashing process)以去除光阻。
在n型區域50N和p型區域50P的佈植之之後,可以進行一退火製程以修復佈植造成的損壞,並活化植入的p型雜質以及/或n型雜質。在一些實施例中,可以對磊晶鰭片的生長材料在生長期間進行原位摻雜(in situ doped),如此可以避免佈植步驟,雖然原位摻雜和佈植摻雜也可以一起進行。
在第5圖中,在鰭片54和奈米結構56上形成一虛置介電層(dummy dielectric layer)62。虛置介電層62可以是例如氧化矽、氮化矽、上述之組合、或其類似材料,並且可以根據可接受的技術而被沉積或熱生長。在虛置介電層62上方形成一虛置閘極層(dummy gate layer)64,並在虛置閘極層64上方形成一遮罩層(mask layer)66。虛置閘極層64可以沉積在虛置介電層62的上方,然後例如藉由一化學機械研磨法(CMP)將虛置閘極層64平坦化。遮罩層66可以沉積在虛置閘極層64的上方。虛置閘極層64可以是一導電材料或非導電材料,並且可以選自由非晶矽(amorphous silicon)、多晶矽(polysilicon)、多晶矽鍺(poly-SiGe)、金屬氮化物(metallic nitrides)、金屬矽化物(metallic silicides)、金屬氧化物和金屬所組成之群組。可以通過物理氣相沉積(physical vapor deposition,PVD)、化學氣相沉積(CVD)、濺鍍、或其他用來沉積所選的材料的技術,以形成虛置閘極層64。虛 置閘極層64可以由相較於絕緣材料的蝕刻具有高蝕刻選擇性的材料製成,例如相較於淺溝槽隔離區60以及/或虛置介電層62的材料具有高蝕刻選擇性。遮罩層66可以包括一層或多層例如氮化矽、氮氧化矽、或類似物的材料層。在此示例中,單一個虛置閘極層64和單一個遮罩層66係跨越n型區域50N和p型區域50P而形成。雖然虛置介電層62在圖式中被繪示為覆蓋淺溝槽隔離區60,但應可理解的是,虛置介電層62可以通過其他方式而形成。在一些實施例中,例如當熱生長上述之虛置介電層62時,虛置介電層62係形成為僅覆蓋鰭片54和奈米結構56。
在第6圖中,使用可接受的光學微影和蝕刻技術對遮罩層66進行圖案化,以形成遮罩(masks)76。然後,通過一可接受的蝕刻技術將遮罩76的圖案轉移到虛置閘極層64,以形成虛置閘極(dummy gates)74。遮罩76的圖案可以較佳地通過可接受的蝕刻技術而進一步轉移到虛置介電層62,以形成虛置介電質(dummy dielectrics)72。虛置閘極74覆蓋奈米結構56的部分將在後續製程中被暴露出來,以形成通道區。具體而言,虛置閘極74沿著將用於形成通道區58的第二奈米結構56B的部分延伸(參見第7A圖)。遮罩76的圖案可用於使各個虛置閘極74與相鄰的虛置閘極74物理性地分隔開來。虛置閘極74也可具有與各個磊晶的鰭片54的長度方向(lengthwise direction)基本上垂直的長度方向。在圖案化步驟之後,遮罩76可以選擇性的被去除,例如藉由一可接受的蝕刻技術選擇性的去除遮罩76。
第7A圖至第20C圖是根據一些實施例的奈米場效電晶體(nano-FET)在製造過程中進一步的多個中間階段的剖面圖。第7A、8A、9A、10A、11A、12A、13A、14A、15A、16A、17A、18A、19A和20A圖係沿著第1圖中的參考剖面A-A而繪示。第7B、8B、9B、10B、11B、12B、13B、14B、15B、16B、 17B、18B、19B和20B圖係沿著第1圖中的參考剖面B-BA而繪示,除了此些圖式是示出了兩個鰭片。第7C、8C、9C、10C、11C、12C、13C、14C、15C、16C、17C、18C、19C和20C圖係沿著第1圖中的參考剖面C-C而繪示,除了此些圖式是示出了兩個鰭片。第7A圖至第20C圖可適用於n型區域50N和p型區域50P兩者。n型區域50N和p型區域50P在結構上的差異(如果有的話)則在每個圖式所相應的文字中描述。
在第7A圖、第7B圖和第7C圖中,在奈米結構56和鰭片54的上方,且在遮罩76、虛置閘極74和虛置介電質72的暴露側壁上形成閘極間隔物(gate spacers)80。閘極間隔物80可以通過順應性(conformally)的形成一絕緣材料並隨後對絕緣材料進行蝕刻而形成。閘極間隔物80的絕緣材料可以是氮化矽、碳氮化矽(silicon carbonitride)、碳氮氧化矽(silicon oxycarbonitride)、前述之組合、或其類似物,並且可以通過熱氧化、沉積、前述方式之組合、或其類似方式而形成閘極間隔物80。閘極間隔物80可由單層的絕緣材料或是多層的絕緣材料而形成。在一些實施例中,閘極間隔物80包括多層的碳氮氧化矽,其中每層可以具有不同成分的碳氮氧化矽。在一些實施例中,閘極間隔物80包括設置在兩層氮化矽之間的一氧化矽層。還可以形成其他的間隔結構(spacer structures)。絕緣材料的蝕刻可以是非等向性的(anisotropic)。例如,蝕刻製程可以是例如RIE、NBE、或其類似方式的乾式蝕刻。在蝕刻之後,閘極間隔物80可以具有直的側壁或是彎曲的側壁。進行乾式蝕刻,以去除奈米結構56(以及可選擇性的鰭片54)的側壁上的絕緣材料。例如,前述之乾式蝕刻可以進行大約1秒至大約15秒範圍內的持續時間,以從奈米結構56的側壁去除此絕緣材料。在所示的實施例中,絕緣材料也從鰭片54的側壁去除,使得沒有閘極間隔物80的材料留在淺溝槽隔離區60 的上方。在另一個實施例中,一些絕緣材料可以留在鰭片54的側壁之上,但不在奈米結構56的側壁之上。
在形成閘極間隔物80之前,可以進行輕摻雜源極/汲極(lightly doped source/drain,LDD)區82的佈植。在具有不同裝置類型的實施例中,類似於上面討論的佈植,可以在n型區域50N的上方形成一遮罩,例如光阻,其同時暴露出p型區域50P,並且可以將適當導電類型的雜質(例如,p型雜質)植入於暴露在p型區域50P的奈米結構56和鰭片54中。然後,可以去除遮罩。隨後,可在p型區域50P的上方形成一遮罩,例如光阻,其同時暴露出n型區域50N,並將可以將適當導電類型的雜質(例如,n型雜質)植入於暴露在n型區域50N的奈米結構56和鰭片54中。然後,可以去除遮罩。n型雜質可以是之前討論的n型雜質中的任何一種,並且p型雜質可以是之前討論的p型雜質中的任何一種。輕摻雜源極/汲極區可具有在大約1015cm-3至大約1019cm-3範圍內的雜質濃度。一退火製程可以用於修復佈植造成的損壞,並活化植入的雜質。在佈植期間,通道區58保持被虛置閘極74所覆蓋,使得通道區58維持實質上沒有植入到輕摻雜源極/汲極區82中的雜質。
需要說明的是,上述揭露內容係概括地描述了形成間隔物和輕摻雜源極/汲極區的製程。也可以使用其他的製程和製作順序。例如,可以使用更少的間隔物或額外的間隔物、可以使用不同順序的步驟(例如,可以形成和去除額外的間隔物等),以及/或類似部件和步驟。此外,可以使用不同的結構和步驟形成n型裝置和p型裝置。
在第8A圖、第8B圖和第8C圖中,去除部分的第一奈米結構56A以形成源極/汲極開口(source/drain openings)84。具體而言,去除第一奈米結構56A 的橫向上未被閘極間隔物80和虛置閘極74覆蓋的部分,以暴露出第二奈米結構56B的頂面和底面,例如輕摻雜源極/汲極區(LDD regions)82的頂面和底面。因此,源極/汲極開口84在鰭片54的側壁之間橫向的延伸,如第8C圖所示。第一奈米結構56A的部分可以通過可接受的蝕刻製程而被去除,此製程是以比第二奈米結構56B和鰭片54的材料還要快的速率選擇性的蝕刻第一奈米結構56A的材料。上述的蝕刻製程可以是非等向性的。例如,當鰭片54和第二奈米結構56B由矽形成並且第一奈米結構56A由矽鍺形成時,上述的蝕刻製程可以是一濕式蝕刻,其使用四甲基氫氧化銨(tetramethylammonium hydroxide,TMAH)、氫氧化銨(NH4OH)、或類似物。由於閘極間隔物80並沒有沿著奈米結構56的側壁延伸,因此可以在第8C圖所示的剖面中完全的去除第一奈米結構56A。
在第9A圖、第9B圖和第9C圖中,內部間隔物(inner spacers)86可以選擇性的形成在第一奈米結構56A的留下部分的側壁上,例如由源極/汲極開口84暴露出的第一奈米結構56A的那些側壁。下文將有詳細敘述,隨後將在源極/汲極開口84中形成源極/汲極區(source/drain regions),並隨後將第一奈米結構56A替換為對應的閘極結構。內部間隔物86可做為隨後形成的源極/汲極區和隨後形成的閘極結構之間的隔離部件(isolation features)。此外,內部間隔物86可用於避免後續進行蝕刻製程時對於後續形成的源極/汲極區造成損壞,例如避免後續形成閘極結構的蝕刻製程對於後續形成的源極/汲極區造成損壞。
在形成內部間隔物86的一個例子中,可以擴大源極/汲極開口84。具體而言,可以下凹(recessed)第一奈米結構56A的被源極/汲極開口84暴露出的部分側壁。儘管第一奈米結構56A的側壁被繪示為是直的,但是此些側壁也可以是內凹的(concave)或是外凸的(convex)。此些側壁可以通過可接受的蝕刻製 程進行凹陷,此蝕刻製程是以比第二奈米結構56B和鰭片54的材料更快的速率而選擇性的蝕刻第一奈米結構56A的材料。上述之蝕刻製程可以是非等向性的。例如,當鰭片54和第二奈米結構56B由矽形成並且第一奈米結構56A由矽鍺形成時,蝕刻製程可以是一濕式蝕刻,其使用四甲基氫氧化銨(tetramethylammonium hydroxide,TMAH)、氫氧化銨(NH4OH)、或類似物。在另一個實施例中,蝕刻製程可以是一乾式蝕刻,其使用一含氟氣體(fluorine-based gas)例如氟化氫(hydrogen fluoride)進行乾式蝕刻。在一些實施例中,可連續的進行相同的蝕刻製程以形成源極/汲極開口84,並使得第一奈米結構56A的側壁凹陷。然後,可以通過順應性的形成一絕緣材料且隨後對絕緣材料進行蝕刻,而形成上述之內部間隔物86。絕緣材料可以是例如氮化矽、氮氧化矽或其類似物,但也可以使用任何合適的材料,例如具有介電常數值小於約3.5的低介電常數(low-k)材料。絕緣材料可以通過例如原子層沉積(ALD)、化學氣相沉積(CVD)、或類似方式的共形沉積製程(conformal deposition process)來沉積。絕緣材料的蝕刻可以是非等向性的。例如,蝕刻製程可以是例如RIE、NBE、或類似物的乾式蝕刻。雖然內部間隔物86的外側壁被圖示為與閘極間隔物80的側壁齊平,但是內部間隔物86的外側壁可以延伸超過閘極間隔物80的側壁,或是從閘極間隔物80的側壁凹陷。例如,內部間隔物86可以部分填充、完全填充、或是過量填充側壁的凹陷處。此外,雖然內部間隔物86的側壁被圖示為直的,但是內部間隔物86的側壁可以是內凹的(concave)或是外凸的(convex)的。
在第10A圖、第10B圖和第10C圖中,第二奈米結構56B和鰭片54被源極/汲極開口84暴露的部分可以選擇性的被修整(trimmed)。上述修整可以減小第二奈米結構56B(例如,輕摻雜源極/汲極區82)的暴露部分的尺寸(例如,厚 度和寬度),而第二奈米結構56B(例如,通道區域58)的未暴露部分則保留了它們的原始尺寸。第二奈米結構56B的未暴露部分是被閘極間隔物80和虛置閘極74覆蓋的那些部分。鰭片54的未暴露部分是在淺溝槽隔離區60的上方延伸的那些部分。例如,上述修整(trimming)可以減少第二奈米結構56B的暴露部分的厚度,從第二厚度T2(如上面關於第2圖所討論的)減少到第三厚度T3,第三厚度T3在大約3nm到大約15nm的範圍內,並且第三厚度T3比第二厚度T2小大約25%至大約40%。類似地,上述修整(trimming)可以將鰭片54和第二奈米結構56B的暴露部分的寬度從第一寬度W1減少到第二寬度W2,其中第一寬度W1在大約5nm至大約20nm的範圍內,第二寬度W2在大約3nm至大約15nm的範圍內,並且第二寬度W2比第一寬度W1小大約25%至大約50%。在修整(trimming)之後,第二奈米結構56B在第10B圖所示的剖面中具有第一周長(例如,第二厚度T2和第一寬度W1的總和的兩倍),並且在第10C圖所示的剖面中具有第二周長(例如,第三厚度T3和第二寬度W2的總和的兩倍),前述第二周長是小於前述第一周長。上述修整(trimming)擴大了源極/汲極開口84,使得它們可以為奈米場效電晶體(nano-FET)容納更大的源極/汲極區。第二奈米結構56B和鰭片54的暴露部分可以通過可接受的蝕刻製程進行上述修整,此蝕刻製程是以比起對第一奈米結構56A、內部間隔物86和閘極間隔物80的材料更快的蝕刻速率而選擇性的蝕刻第二奈米結構56B和鰭片54的材料。上述蝕刻製程可以是非等向性的。例如,當鰭片54和第二奈米結構56B是由矽形成並且第一奈米結構56A是由矽鍺形成時,蝕刻製程可以是一濕式蝕刻製程,其使用稀釋的氫氧化銨-過氧化氫混合物(diluted ammonium hydroxide-hydrogen peroxide mixture,APM)、硫酸-過氧化氫混合物(sulfuric acid-hydrogen peroxide mixture,SPM)等。當省略修整製程時,通道區58和輕摻 雜源極/汲極區82均可以具有相同的厚度。
在第11A圖、第11B圖和第11C圖中,在源極/汲極開口84中和第二奈米結構56B(例如,輕摻雜源極/汲極區82)的暴露/修整部分(exposed/trimmed portions)的周圍形成磊晶源極/汲極區88。在形成磊晶源極/汲極區88之後,磊晶源極/汲極區88包裹在第二奈米結構56B的四個側面(例如,頂面、側壁和底面)的周圍。因此,磊晶源極/汲極區88是完全圍繞第11C圖所示的剖面中的第二奈米結構56B。磊晶源極/汲極區88也可以選擇性的形成在鰭片54的暴露/修整部分上,使得磊晶源極/汲極區88的第一子集(first subset)88A包裹在第二奈米結構56B的周圍,而磊晶源極/汲極區88的第二子集88B則沿著鰭片54延伸。磊晶源極/汲極區88形成於源極/汲極開口84中,使得各個磊晶源極/汲極區88設置在相鄰的一對虛置閘極74之間。在一些實施例中,閘極間隔物80和內部間隔物86是用於將磊晶源極/汲極區88與虛置閘極74和第一奈米結構56A隔開一適當的橫向距離(lateral distance),使得磊晶源極/汲極區88不會造成隨後形成的奈米場效電晶體(nano-FET)的閘極的短路。磊晶源極/汲極區88可以形成為與內部間隔物86(如果存在)接觸。當奈米結構56B被修整時(trimmed),磊晶源極/汲極區88可以對通道區58施加應力(stress),從而提高性能表現。
n型區域50N中的磊晶源極/汲極區88可以通過遮蔽p型區域50P來形成。然後,在n型區域50N中的源極/汲極開口84中磊晶生長形成磊晶源極/汲極區88。磊晶源極/汲極區88可以包括任何適用於n型奈米場效電晶體(nano-FET)的可接受的材料。例如,n型區域50N中的磊晶源極/汲極區88可以包括在通道區58上施加拉伸應變(tensile strain)的材料,例如矽、碳化矽(silicon carbide)、摻雜磷的碳化矽(phosphorous doped silicon carbide)、磷化矽(silicon phosphide)、或類似 物。n型區域50N中的磊晶源極/汲極區88可以具有從第二奈米結構56B和鰭片54的相應表面凸起的表面,並且磊晶源極/汲極區88可以具有刻面(facets)。
p型區域50P中的磊晶源極/汲極區88可以通過遮蔽n型區域50N來形成。然後,在p型區域50P中的源極/汲極開口84中磊晶生長磊晶源極/汲極區88。磊晶源極/汲極區88可以包括任何適用於p型奈米場效電晶體(nano-FET)的可接受的材料。例如,p型區域50P中的磊晶源極/汲極區88可以包括在通道區58上施加壓縮應變(compressive strain)的材料,例如矽鍺(silicon germanium)、硼摻雜的矽鍺(boron doped silicon germanium)、鍺、鍺錫(germanium tin)、或類似物。p型區域50P中的磊晶源極/汲極區88也可以具有從第二奈米結構56B和鰭片54的相應表面凸起的表面,並且磊晶源極/汲極區88可以具有刻面(facets)。
磊晶源極/汲極區88、第二奈米結構56B、以及/或鰭片54可以植入摻雜物以形成源極/汲極區,類似於前面討論的形成輕摻雜源極/汲極區(LDD regions)的製程,隨後進行退火(anneal)。源極/汲極區可具有在大約1019cm-3至大約1021cm-3範圍內的雜質濃度。源極/汲極區的n型雜質以及/或p型雜質可以是先前討論的任何雜質。在一些實施例中,磊晶源極/汲極區88可以在生長期間原位摻雜。
由於用來形成磊晶源極/汲極區88的磊晶製程,磊晶源極/汲極區88的上表面是具有刻面(facets),這些刻面橫向的向外擴展到超出第二奈米結構56B和鰭片54的表面。在淺溝槽隔離區60的上方沒有留下閘極間隔物80的材料的實施例中,磊晶源極/汲極區88B可以沿著淺溝槽隔離區60延伸並接觸淺溝槽隔離區60。磊晶源極/汲極區88形成為厚度T4,所選擇的此厚度使得磊晶源極/汲極區88在磊晶製程期間不合併(merge)。在一些實施例中,磊晶源極/汲極區88的厚 度T4高達第一奈米結構56A的原始第一厚度T1(上面關於第2圖討論)的大約四分之一。例如,厚度T4可以在大約5nm至大約15nm的範圍內。將磊晶源極/汲極區88形成到前述範圍內的厚度T4,以避免磊晶源極/汲極區88的合併。將磊晶源極/汲極區88形成為前述範圍之外的厚度T4,有可能無法避免磊晶源極/汲極區88的合併。避免磊晶源極/汲極區88的合併可以允許隨後形成的源極/汲極接觸件(source/drain contacts)圍繞磊晶源極/汲極區88A的所有側邊(例如,四個側邊),從而增加源極/汲極接觸件的接觸面積,並降低源極/汲極接觸件的接觸電阻(contact resistance,RC)。
磊晶源極/汲極區88可以包括一層或多層半導體材料層。例如,磊晶源極/汲極區88可以包括第一半導體材料層(first semiconductor material layers)、第二半導體材料層(second semiconductor material layers)以及第三半導體材料層(third semiconductor material layers)。任何數量的半導體材料層可以用於形成磊晶源極/汲極區88。第一半導體材料層、第二半導體材料層和第三半導體材料層中的每一個材料層可以由不同的半導體材料形成,以及/或是可以摻雜至不同的摻雜濃度。在一些實施例中,第一半導體材料層的摻雜物濃度可以小於第二半導體材料層的摻雜物濃度,且大於第三半導體材料層的摻雜物濃度。當磊晶源極/汲極區88包括三個半導體材料層時,第一半導體材料層可以從第二奈米結構56B和鰭片54開始生長,第二半導體材料層可以從第一半導體材料層開始生長,第三半導體材料層可以從第二半導體材料層開始生長。
在第12A圖、第12B圖和第12C圖中,在磊晶源極/汲極區88之上和周圍形成虛置層(dummy layers)92。虛置層92圍繞在磊晶源極/汲極區88A的四個側面(例如,頂面、側壁和底面)的周圍。且虛置層92圍繞在磊晶源極/汲極區 88B的三個側面(例如,頂面和側壁)的周圍。具體而言,在相鄰的虛置閘極74之間設置的每組磊晶源極/汲極區88的周圍形成此些虛置層92。此些虛置層92是填充源極/汲極開口84的未被磊晶源極/汲極區88A填充的留下部分。虛置層92可以由介電材料形成,例如碳氮化矽(silicon carbonitride)、氮氧化矽(silicon oxynitride)或碳氮氧化矽(silicon oxycarbonitride),但是也可以選用其他合適的介電材料。值得注意的是,虛置層92由介電材料形成,且此介電材料對隨後形成的層間介電質(ILD)的蝕刻係具有高蝕刻選擇性(high etching selectivity)。虛置層92如此命名是因為它們將在後續穿過層間介電質(ILD)而形成源極/汲極接觸件(source/drain contacts)的後續製程中被去除。虛置層92可以通過例如原子層沉積(ALD)、化學氣相沉積(CVD)、或類似方式的共形沉積製程來沉積。
作為形成虛置層92的一個示例,虛置層92的介電材料可以順應性的(conformally)沉積在磊晶源極/汲極區88周圍以及沉積在閘極間隔物80和遮罩76之上,例如是通過原子層沉積(ALD)進行前述沉積。然後,應用一去除製程,以去除閘極間隔物80和遮罩76上方的過量的介電材料。在一些實施例中,平坦化製程可以利用例如化學機械研磨(CMP)、回蝕製程、前述方式之組合、或類似方式來進行。平坦化製程可暴露出閘極間隔物80和遮罩76,使得在平坦化製程完成之後,介電材料的頂面、閘極間隔物80的頂面和遮罩76的頂面係為共平面(在製程變化範圍內)。然後,使介電材料凹陷,以形成虛置層92。虛置層92的頂面是下凹到遮罩76的頂面之下,並且可以下凹到虛置閘極74的頂面之下。
在第13A圖、第13B圖和第13C圖中,第一層間介電質(first ILD)94沉積在虛置層92、閘極間隔物80和遮罩76的上方。第一層間介電質94可以由一介電材料形成,並且可以通過任何合適的方法進行沉積,例如化學氣相沉積 (CVD)、電漿輔助化學氣相沉積(plasma-enhanced CVD,PECVD)或流動式化學氣相沉積(FCVD)。介電材料可包括磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、摻雜硼之磷矽酸鹽玻璃(boron-doped phosphosilicate glass,BPSG)、未摻雜矽玻璃(undoped silicate glass,USG)、或其類似物質。也可以是使用任何可接受的製程形成的其他的絕緣材料。在一些實施例中,在虛置層92和第一層間介電質94之間形成一蝕刻停止層(etch stop layer)。蝕刻停止層可以包括一介電材料,例如氮化矽、氧化矽、氮氧化矽、或類似材料,蝕刻停止層的介電材料是與第一層間介電質94的材料具有不同的蝕刻速率。
在第14A圖、第14B圖和第14C圖中,可以進行一平坦化製程,例如化學機械研磨(CMP),以使第一層間介電質94的頂面與虛置閘極74的頂面或遮罩76的頂面齊平。上述之平坦化製程還可以去除虛置閘極74上的遮罩76,以及去除沿著遮罩76側壁的部分的閘極間隔物80。在平坦化製程之後,第一層間介電質94的頂面、閘極間隔物80的頂面和遮罩76(如果存在)的頂面或虛置閘極74的頂面是共平面的(在製程變化範圍內)。因此,遮罩76(如果存在)的頂面或虛置閘極74的頂面是通過第一層間介電質94暴露出來。在所示實施例中,是留下了遮罩76,且平坦化製程是使第一層間介電質94的頂面與遮罩76的頂面齊平。
在第15A圖、第15B圖和第15C圖中,在蝕刻製程中去除遮罩76(如果存在)和虛置閘極74,從而形成凹槽(recesses)96。也可以去除位於凹槽96中的部分的虛置介電質72。在一些實施例中,可通過非等向性乾式蝕刻製程(anisotropic dry etch process)以去除虛置閘極74。例如,蝕刻製程可以包括使用反應氣體的乾式蝕刻製程,此乾式蝕刻製程是以比對於第一層間介電質94或閘極 間隔物80更快的蝕刻速率而選擇性的蝕刻虛置閘極74。在去除虛置閘極74期間,虛置介電質72可以做為蝕刻虛置閘極74時的蝕刻停止層。然後,可以在去除虛置閘極74之後,去除虛置介電質72。各個凹槽96係暴露出以及/或重疊於第二奈米結構56B中的通道區58的部分。做為通道區58的第二奈米結構56B的部分是設置在一對相鄰的磊晶源極/汲極區88之間。
然後,去除第一奈米結構56A的留下部分,以擴大凹槽96。第一奈米結構56A的留下部分可以通過可接受的蝕刻製程而去除,前述之蝕刻製程是以比起對於第二奈米結構56B、鰭部54和淺溝槽隔離區60的材料能有更快的蝕刻速率以選擇性的蝕刻第一奈米結構56A的材料。前述之蝕刻製程可以是非等向性的。例如,當鰭片54和第二奈米結構56B是由矽(silicon)形成並且第一奈米結構56A是由矽鍺(silicon germanium)形成時,蝕刻製程可以是一濕式蝕刻,其使用四甲基氫氧化銨(tetramethylammonium hydroxide,TMAH)、氫氧化銨(NH4OH)、或類似物。
在第16A圖、第16B圖和第16C圖中,形成閘極介電質(gate dielectrics)102和閘極電極(gate electrodes)104,以形成替換閘極(replacement gates)。閘極介電質102係順應性的沉積在凹槽96中,例如沉積在鰭片54的頂面和側壁上以及在第二奈米結構56B的頂面、側壁和底面上。閘極介電質102也可以沉積在第一層間介電質94、閘極間隔物80和淺溝槽隔離區60的頂面上。根據一些實施例,閘極介電質102包括氧化矽、氮化矽、或多層的前述材料。在一些實施例中,閘極介電質102包括高介電常數之介電材料(high-k dielectric material),並且在這些實施例中,閘極介電質102可以具有大於約7.0的k值,並且可以包括含有鉿(hafnium)、鋁(aluminum)、鋯(zirconium)、鑭(lanthanum)、錳(manganese)、 鉭(barium)、鈦(titanium)、鉛(lead)、及前述之組合的金屬氧化物或金屬矽化物。閘極介電質102的形成方法可以包括分子束沉積(MBD)、原子層沉積(ALD)、電漿輔助化學氣相沉積(PECVD)、或類似方式。
閘極電極104分別沉積在閘極介電質102的上方,並填充凹槽96的剩餘部分。閘極電極104可以包括一含有金屬之材料(metal-containing material),例如氮化鈦(titanium nitride)、氧化鈦(titanium oxide)、氮化鉭(tantalum nitride)、碳化鉭(tantalum carbide)、鈷、釕、鋁、鎢、前述之組合、或多層前述的材料。例如,雖然圖中示出了單層的閘極電極104,但是閘極電極104可以包括任意數量的襯墊層、任意數量的功函數諧調層(work function tuning layers)和填充材料。構成閘極電極104的層的任何組合可以沉積在每個第二奈米結構56B之間以及沉積在鰭片54和第二奈米結構56B之間的區域中。在填充凹槽96之後,可以進行平坦化製程,例如化學機械研磨(CMP),以去除閘極介電質102和閘極電極104的材料的過量部分,這些過量部分係位於第一層間介電質94和閘極間隔物80的頂面上方。閘極介電質102和閘極電極104的材料的留下部分因而形成所製得之奈米場效電晶體(nano-FET)的替換閘極(replacement gates)。閘極介電質102和閘極電極104可以共同稱為閘極結構100或是閘極堆疊(gate stacks)。
在n型區域50N和p型區域50P中的閘極介電質102的形成可以是同時進行的,使得每個區域中的閘極介電質102是由相同的材料形成,並且閘極電極104的形成也可以是同時進行的,使得每個區域中的閘極電極104是由相同的材料形成。在一些實施例中,每個區域中的閘極介電質102可以通過不同的製程形成,使得閘極介電質102可以是不同的材料,以及/或每個區域中的閘極電極104可以通過不同的製程形成,使得閘極電極104可以是不同的材料。當使用不 同的製程時,可以使用各種遮蔽步驟來遮住和暴露出適當的區域。
在第17A、17B和17C圖中,通過第一層間介電質94形成源極/汲極接觸開口(source/drain contact openings)106。源極/汲極接觸開口106可以使用可接受的光學微影技術和蝕刻技術而形成,例如使用對於第一層間介電質94是具有選擇性的蝕刻製程(例如,以比起對於虛置層92的材料有更快的蝕刻速率以蝕刻第一層間介電質94的材料)。在蝕刻期間,虛置層92可以做為蝕刻停止層(etch stop layers),使得源極/汲極接觸開口106暴露出虛置層92。
在第18A、18B和18C圖中,去除虛置層92以擴大源極/汲極接觸開口106,並暴露出磊晶源極/汲極區88。去除虛置層92可以暴露出磊晶源極/汲極區88的所有外表面(例如,磊晶源極/汲極區88的頂面、側壁和底面)。可以使用可接受的蝕刻製程以去除虛置層92,例如,使用對虛置層92有選擇性的蝕刻製程進行去除(例如,以比起對於第一層間介電質94的材料有更快的蝕刻速率蝕刻虛置層92的材料)。
在第19A圖、第19B圖和第19C圖中,在源極/汲極接觸開口106中和在磊晶源極/汲極區88上形成矽化物(silicides)108。矽化物108包裹磊晶源極/汲極區88的周圍。可以通過在源極/汲極接觸開口106中沉積一金屬層(metal layer),並進行一退火製程來形成矽化物108。金屬層可以順應性的形成在第一層間介電質94的頂面上、第一層間介電質94的側壁上、以及磊晶源極/汲極區88的所有表面(例如,頂面、側壁和底面)上。金屬層可以由鈦、鈷、鎢、或類似物而形成,並且可以通過任何合適的方法沉積,例如原子層沉積(ALD)、物理氣相沉積(PVD)、化學氣相沉積(CVD)和電漿輔助化學氣相沉積(PECVD)。在一些實施例中,還可以在源極/汲極接觸開口106中形成一襯層(liner)。前述之襯層可以是 一擴散阻擋層(diffusion barrier layer)、一黏結層(adhesion layer)、或類似層,並且可以有助於防止金屬層在退火期間擴散到第一層間介電質94中。襯層可以包括鈦、氮化鈦、鉭、氮化鉭、或類似物。然後,對金屬層和選擇性形成的襯墊進行退火以形成矽化物108。此些矽化物108可物理性接觸磊晶源極/汲極區88並且電性耦接至磊晶源極/汲極區88。然後,可以通過可接受的蝕刻製程,以去除金屬層以及/或襯層的過量部分。
然後,在源極/汲極接觸開口106中形成下部源極/汲極接觸件112A(Lower source/drain contacts)。在源極/汲極接觸開口106中形成一襯層,例如一擴散阻擋層、一黏結層(adhesion layer)、或類似層,以及在源極/汲極接觸開口106中形成一導電材料。襯層可以包括鈦、氮化鈦、鉭、氮化鉭、或其類似物。襯層可以通過一共形沉積製程(conformal deposition process)進行沉積,例如原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、或其類似方式。在一些實施例中,襯層可以包括一黏結層,並且可以對粘附層的至少一部分進行處理以形成一擴散阻擋層。導電材料可以是銅、銅合金、銀、金、鎢、鈷、鋁、鎳、或其類似物。導電材料可以通過原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、或其類似方式進行沉積。可以進行一平坦化製程,例如化學機械研磨(CMP),以從第一層間介電質的表面去除多餘的材料。源極/汲極接觸開口106中留下的襯層和導電材料係形成下部源極/汲極接觸件112A。下部源極/汲極接觸件112A是物理性的接觸矽化物108和電性耦合至矽化物108。
在第20A圖、第20B圖和第20C圖中,在第一層間介電質94的上方沉積第二層間介電質114。第二層間介電質114可以由一介電材料形成,並且可以通過任何合適的方法進行沉積,例如化學氣相沉積(CVD)、電漿輔助化學氣相 沉積(PECVD)或流動式化學氣相沉積(FCVD)。第二層間介電質114的介電材料可以包括氧化物,例如氧化矽、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、摻雜硼之磷矽酸鹽玻璃(boron-doped phosphosilicate glass,BPSG)、未摻雜矽玻璃(undoped silicate glass,USG)、或其類似物;可以包括氮化物,例如氮化矽;或是前述之類似物。在形成第二層間介電質114之後,可以對第二層間介電質114進行平坦化,例如通過化學機械研磨(CMP)進行平坦化。在一些實施例中,一蝕刻停止層(etch stop layer)形成在第一層間介電質94和第二層間介電質114之間。前述之蝕刻停止層可以包括介電材料,例如氮化矽、氧化矽、氮氧化矽、或其類似物,蝕刻停止層的介電材料是與第二層間介電質114的材料具有不同的蝕刻速率。
然後,形成上部源極/汲極接觸件(upper source/drain contacts)112B和閘極接觸件(gate contacts)116,上部源極/汲極接觸件112B和閘極接觸件116係延伸穿過第二層間介電質114。用於設置上部源極/汲極接觸件112B和閘極接觸件116的開口係穿過第二層間介電質114。可以使用可接受的光學微影技術和蝕刻技術來形成這些開口。可在開口中形成一襯層(liner)例如一擴散阻擋層(diffusion barrier layer)、黏結層(adhesion layer)或類似材料層,以及在開口中形成一導電材料。襯層可以包括鈦、氮化鈦、鉭、氮化鉭、或類似物。襯層可以通過一共形沉積製程(conformal deposition process)而沉積,例如原子層沉積(ALD)、化學氣相沉積(CVD)、物理氣相沉積(PVD)、或類似方式而沉積。在一些實施例中,襯層可以包括一黏結層,並且可以對黏結層的至少一部分進行處理,以形成一擴散阻擋層。導電材料可以是銅、銅合金、銀、金、鎢、鈷、鋁、鎳、或其類似物。導電材料可以通過原子層沉積(ALD)、化學氣相沉積(CVD)、 物理氣相沉積(PVD)、或類似方式而沉積。可以進行平坦化製程,例如通過化學機械研磨(CMP)以從第二層間介電質114的表面去除過量的材料。源極/汲極接觸開口106中留下的襯層和導電材料則形成上部源極/汲極接觸件112B和閘極接觸件116。上部源極/汲極接觸件112B係物理性的接觸和電性耦合至下部源極/汲極接觸件112A,閘極接觸件116係物理性的接觸和電性耦合至閘極電極104。上部源極/汲極接觸件112B和下部源極/汲極接觸件112A可以共同稱為源極/汲極接觸件(source/drain contacts)112。形成源極/汲極接觸件112之後,下部源極/汲極接觸件112A係物理性的接觸閘極間隔物80和內部間隔物86,並且下部源極/汲極接觸件112A具有一部份設置在同一行(same column)的磊晶源極/汲極區88之間。在此實施例中,源極/汲極接觸件112包括延伸穿過第一層間介電質94的第一導電部件(例如,下部源極/汲極接觸件112A),並且包括延伸穿過第二層間介電質114的第二導電部件(例如,上部源極/汲極接觸件112B)。
源極/汲極接觸件112和閘極接觸件116可以在不同的製程中形成,也可以在相同的製程中形成。儘管源極/汲極接觸件112和閘極接觸件116在相同的剖面中示出,但是接觸件可以形成在不同的剖面中,如此可以避免接觸件的短路。
第21圖至第23圖是根據一些實施例的製造奈米場效電晶體(nano-FET)的中間階段的剖面圖。如下文將更詳細討論的,第21圖至第23圖示出了接觸件切割製程(contact cut process),其中通過在相鄰的下部源極/汲極接觸112A之間形成一介電部件(dielectric feature),使得相鄰的下部源極/汲極接觸112A彼此分離。第21圖至第23圖係沿著第1圖中的參考剖面C-C繪示,除了顯示了四個鰭片。第7A圖至第20C圖可適用於n型區域50N和p型區域50P兩者。n型區 域50N和p型區域50P的結構的差異(如果有的話)係在每個圖式所相應的文字中描述。
在第21圖中,所提出的結構是處於與關於第12C圖描述的製程狀態相類似的製程狀態。第21圖係示出了在基底50上方的第一組鰭片54(例如,在第21圖的左側)和第二組鰭片54(例如,在第21圖的右側)。各組鰭片54可用於形成一奈米場效電晶體(nano-FET)。在虛置層92中形成一切割開口(cut opening)98。可以使用可接受的光學微影和蝕刻技術形成上述之切割開口98。在形成切割開口98之後,切割開口98係暴露出下方的絕緣材料,例如暴露出淺溝槽隔離區60。切割開口98形成在第一組鰭片54和第二組鰭片54之間,並且定義出隨後在源極/汲極接觸件之間形成的一介電部件(dielectric feature)的位置,其中源極/汲極接觸件係連接至奈米場效電晶體。
在第22圖中,係使用與關於第13A圖至第14C圖描述的製程相類似的製程,以形成第一層間介電質94並寫平坦化第一層間介電質94。第一層間介電質94係形成在切割開口98中和形成在虛置層92的上方。因此,第一層間介電質94包括一下部區域94A(例如,位於切割開口98中)和一上部區域94B(例如,位於虛置層92的上方)。
在第23圖中,係使用與關於第17A圖至第20C圖所描述的製程相類似的製程,而形成下部源極/汲極接觸件112A、第二層間介電質114以及上部源極/汲極接觸件112B。在形成前述之下部源極/汲極接觸件112A、第二層間介電質114以及上部源極/汲極接觸件112B之後,第一層間介電質94的下部區域94A因而可作為能分隔相鄰的下部源極/汲極接觸件112A的一介電部件。
應當理解的是,第21圖至第23圖示出了一示例性的接觸件切割製 程(contact cut process)。也可以形成其他介電部件,以分隔相鄰的下部源極/汲極接觸件112A。例如,可以在相鄰的下部源極/汲極接觸件112A之間形成一介電部件,且形成此介電部件的材料係與第一層間介電質94和虛置層92的材料不同。
在上述實施例中,相鄰的磊晶源極/汲極區88(例如,設置在不同鰭片54上方的磊晶源極/汲極區88)係與相同的源極/汲極接觸件112電性耦合。換言之,各個下部源極/汲極接觸112A係耦合到多行的磊晶源極/汲極區(multiple columns of epitaxial source/drain regions)88。在另一個實施例中(下面更詳細地討論),相鄰的磊晶源極/汲極區88可以各自耦合到不同的相應的源極/汲極接觸件112。
第24圖是根據一些其他實施例的奈米場效電晶體(nano-FET)的剖面圖。此些實施例係類似於關於第23圖所描述的實施例,除了相鄰的磊晶源極/汲極區88各自耦合到不同的下部源極/汲極接觸件112A。換言之,各個下部源極/汲極接觸112A係耦合到一行的磊晶源極/汲極區(one column of epitaxial source/drain regions)88。
第25A圖、第25B圖和第25C圖是根據一些其他實施例的奈米場效電晶體(nano-FET)的剖面圖。此實施例類似於關於第20A圖、第20B圖和第20C圖所描述的實施例,除了源極/汲極接觸件112是延伸穿過第一層間介電層94和第二層間介電層114兩者的連續導電部件(continuous conductive features)。可以通過在與關於第16A圖、第16B圖和第16C圖描述的製程狀態相類似的製程狀態下而獲得實施例的結構,然後,在形成源極/汲極接觸開口106之前,先在第一層間介電層94之上形成第二層間介電層114。在形成第二層間介電層114之後,可以形成穿過第二層間介電層114和第一層間介電層94兩者的源極/汲極接觸開口106, 並且可以使用如關於第17A圖到第18C圖所描述的相類似的製程以去除虛置層92。然後,可以使用與關於第19A圖、第19B圖和第19C圖描述的製程相類似的製程,以在源極/汲極接觸開口106中形成源極/汲極接觸件112。
應當理解的是,關於第25A圖、第25B圖和第25C圖所描述的實施例,可以與關於第21圖到第24圖所描述的實施例的部件互相組合。例如,第25A圖、第25B圖和第25C圖所示的源極/汲極接觸件112可以耦合到一行的磊晶源極/汲極區88、或者耦合到多行的磊晶源極/汲極區88。相類似的,可以在第25A圖、第25B圖和第25C圖所示的源極/汲極接觸件112上進行一接觸件切割製程(contact cut process)。
實施例可以實現許多優點。通過形成和去除虛置層92來形成源極/汲極接觸件112,可使得源極/汲極接觸件112延伸而圍繞磊晶源極/汲極區88的所有側面(例如,四個側面)。源極/汲極接觸件112的接觸面積也因此可以增加,從而降低源極/汲極接觸件112的接觸電阻(contact resistance RC),並提高奈米場效電晶體(nano-FET)的性能表現。具體而言,源極/汲極接觸件112對於靠近基底50設置的磊晶源極/汲極區88和對於遠離基底50設置的磊晶源極/汲極區88,可以具有相似的接觸電阻。
在一個實施例中,一種半導體裝置的製造方法,包括:圖案化複數個半導體層,以形成一第一奈米結構(first nanostructure)、一第二奈米結構(second nanostructure)和第三奈米結構(third nanostructure),前述第二奈米結構係設置在前述第一奈米結構和前述第三奈米結構之間;在覆蓋前述第二奈米結構的一第二區域(second region)的同時,係摻雜一雜質於前述第二奈米結構的一第一區域(first region);去除前述第一奈米結構和前述第三奈米結構的部分,以暴 露出前述第二奈米結構的前述第一區域的頂部和底部;在前述第二奈米結構的前述第一區域的頂部和底部的周圍生長一磊晶源極/汲極區(epitaxial source/drain region);以及在前述第二奈米結構的前述第二區域的頂部和底部的周圍形成一閘極堆疊(gate stack)。
一些實施例中,前述之半導體裝置的製造方法還包括:在生長前述磊晶源極/汲極區之前,修整(trimming)前述第二奈米結構的前述第一區域,以減少前述第二奈米結構的前述第一區域的一厚度。在前述之半導體裝置的製造方法的一些實施例中,在修整前述第二奈米結構的前述第一區域之後,前述第二奈米結構的前述第一區域的厚度係小於前述第二奈米結構的前述第二區域的厚度。在一些實施例中,前述之半導體裝置的製造方法還包括:在生長前述磊晶源極/汲極區之後,在前述磊晶源極/汲極區的頂部和底部的周圍沉積一虛置層(dummy layer);在前述虛置層上沉積一層間介電(interlayer dielectric,ILD)層;蝕刻前述層間介電層,以形成暴露出前述虛置層的一第一開口(first opening);以及蝕刻前述虛置層,以擴大前述第一開口以及暴露出磊晶源極/汲極區。在一些實施例中,前述之半導體裝置的製造方法還包括:在前述第一開口中和前述磊晶源極/汲極區的周圍沉積一金屬層(metal layer);對前述金屬層進行退火,以在前述磊晶源極/汲極區的周圍形成一矽化物;以及在前述第一開口中沉積一導電材料,以在前述矽化物的周圍形成一源極/汲極接觸件(source/drain contact)。在前述之半導體裝置的製造方法的一些實施例中,前述虛置層包括一第一介電材料(first dielectric material),前述層間介電層包括一第二介電材料(second dielectric material),蝕刻前述層間介電層係包括以比前述第一介電材料一更快的速率蝕刻前述第二介電材料,以及蝕刻前述虛置層係包括以比前述第二介電材料一更快 的速率蝕刻前述第一介電材料。在前述之半導體裝置的製造方法的一些實施例中,前述第一介電材料是碳氮化矽(silicon carbonitride),並且前述第二介電材料是氧化矽(silicon oxide)。在一些實施例中,前述半導體裝置的製造方法還包括:在沉積前述層間介電層之前,在前述虛置層中蝕刻一第二開口(second opening),其中沉積前述層間介電層包括沉積前述層間介電層的一部分於前述第二開口中。在一些實施例中,前述之半導體裝置的製造方法還包括:在一基底上方形成前述半導體層;圖案化前述基底以形成一鰭片,前述第二奈米結構係設置在前述鰭片之上;以及在生長前述磊晶源極/汲極區之前,修整前述鰭片的一上方部分(upper portion)。在前述之半導體裝置的製造方法的一些實施例中,形成前述閘極堆疊包括:去除前述第一奈米結構和前述第三奈米結構的留下部分,以暴露出前述第二奈米結構的前述第二區域的頂部和底部;在前述第二奈米結構的前述第二區域的頂部和底部周圍沉積一閘極介電質(gate dielectric);以及在前述閘極介電質上形成一閘極電極(gate electrode)。
在一個實施例中,一種半導體裝置包括:一第一奈米結構(first nanostructure)位於一基底的上方,前述第一奈米結構包括一通道區(channel region)和一第一輕摻雜源極/汲極(lightly doped source/drain,LDD)區,前述第一輕摻雜源極/汲極區與前述通道區相鄰;一第一磊晶源極/汲極區(first epitaxial source/drain region)係圍繞前述第一輕摻雜源極/汲極區的四個側面;一層間介電層(ILD layer),位於前述第一磊晶源極/汲極區的上方;一源極/汲極接觸件(source/drain contact)係延伸貫穿前述層間介電層,前述源極/汲極接觸件係圍繞前述第一磊晶源極/汲極區的四個側面;以及一閘極堆疊(gate stack),鄰近前述源極/汲極接觸件以及前述第一磊晶源極/汲極區,前述閘極堆疊係圍繞前述通道區 的四個側面。
在前述之半導體裝置的一些實施例中,前述第一輕摻雜源極/汲極區具有一第一厚度(first thickness),前述通道區具有一第二厚度(second thickness),並且前述第二厚度大於前述第一厚度。在前述之半導體裝置的一些實施例中,前述第一輕摻雜源極/汲極區和前述通道區具有一相同厚度。在一些實施例中,半導體裝置更包括:一第二奈米結構(second nanostructure)位於前述基底的上方,前述第二奈米結構包括一第二輕摻雜源極/汲極區(second LDD region);以及一第二磊晶源極/汲極區(second epitaxial source/drain region)圍繞前述第二輕摻雜源極/汲極區的四個側面,前述源極/汲極接觸件係圍繞前述第二磊晶源極/汲極區的四個側面。在一些實施例中,前述之半導體裝置更包括:一第一間隔物(first spacer),設置在前述閘極堆疊和前述第一磊晶源極/汲極區之間,前述源極/汲極接觸件係物理性接觸前述第一間隔物;以及一第二間隔物(first spacer),設置在前述閘極堆疊和前述第二磊晶源極/汲極區之間,前述源極/汲極接觸件係物理性接觸前述第二間隔物。在前述之半導體裝置的一些實施例中,前述源極/汲極接觸件具有一第一部分(first portion)和一第二部分(second portion),前述第一部分係延伸穿過前述層間介電層,前述第二部分係設置在前述第一磊晶源極/汲極區和前述第二磊晶源極/汲極區之間,前述第二部分具有比前述第一部分更大的寬度。
在一個實施例中,一種半導體裝置包括:一奈米結構(nanostructure)位於一基底的上方,前述奈米結構包括一通道區(channel region)和一輕摻雜源極/汲極區(LDD region),前述輕摻雜源極/汲極區係與前述通道區相鄰,前述通道區係在一第一剖面(first cross-section)中具有一第一寬度以及一第 一厚度,前述輕摻雜源極/汲極區係在一第二剖面(second cross-section)中具有一第二寬度和一第二厚度,前述第二寬度小於前述第一寬度,前述第二厚度小於前述第一厚度,前述第一剖面和前述第二剖面均垂直於前述奈米結構的一縱軸(longitudinal axis);一閘極堆疊(gate stack),前述閘極堆疊在前述第一剖面中係完全圍繞前述通道區;以及一磊晶源極/汲極區(epitaxial source/drain region),前述磊晶源極/汲極區在前述第二剖面中係完全圍繞前述輕摻雜源極/汲極區。
在一些實施例中,前述之半導體裝置還包括:一層間介電層(interlayer dielectric(ILD)layer),位於前述磊晶源極/汲極區的上方;以及一源極/汲極接觸件(source/drain contact),係延伸貫穿前述層間介電層,前述源極/汲極接觸件係完全圍繞在前述第二剖面中的前述磊晶源極/汲極區。在一些實施例中,前述之半導體裝置還包括:一矽化物(silicide),位於前述源極/汲極接觸件與前述磊晶源極/汲極區之間,前述矽化物在前述第二剖面中完全包圍前述磊晶源極/汲極區。在一些實施例中,前述之半導體裝置還包括:一隔離區(isolation region),位於前述基底的上方;以及一鰭片,具有一第一部分(first portion)和一第二部分(second portion),前述第一部分延伸穿過前述隔離區,前述第二部分延伸到前述隔離區的上方,前述奈米結構設置在前述鰭片的上方,前述鰭片的前述第一部分具有一第三寬度(third width),前述鰭片的前述第二部分具有一第四寬度(fourth width),前述第二寬度和前述第四寬度係小於前述第三寬度。
以上概述數個實施例之部件,以便在本發明所屬技術領域中具有通常知識者可以更加理解本發明實施例的觀點。在本發明所屬技術領域中具有通常知識者應理解,他們能輕易地以本發明實施例為基礎,設計或修改其他製程和結構,以達到與在此介紹的實施例相同之目的及/或優勢。在本發明所屬技 術領域中具有通常知識者也應理解,此類等效的結構並無悖離本發明的精神與範圍,且他們能在不違背本發明之精神和範圍下,做各式各樣的改變、取代和替換。因此,本發明之保護範圍當視後附之申請專利範圍所界定為準。
50:基底
50N:n型區域
50P:p型區域
54:鰭片
56B:第二奈米結構
58:通道區
80:閘極間隔物
82:輕摻雜源極/汲極區
86:內部間隔物
88:磊晶源極/汲極區
88A:磊晶源極/汲極區的第一子集
88B:磊晶源極/汲極區的第二子集
94:第一層間介電質(第一層間介電層)
102:閘極介電質
104:閘極電極
108:矽化物
112:源極/汲極接觸件
112A:下部源極/汲極接觸件
112B:上部源極/汲極接觸件
114:第二層間介電質(第二層間介電層)
116:閘極接觸件

Claims (13)

  1. 一種半導體裝置的製造方法,包括:圖案化複數個半導體層,以形成一第一奈米結構(first nanostructure)、一第二奈米結構(second nanostructure)和第三奈米結構(third nanostructure),該第二奈米結構係設置在該第一奈米結構和該第三奈米結構之間;在覆蓋該第二奈米結構的一第二區域(second region)的同時,係摻雜一雜質於該第二奈米結構的一第一區域(first region);去除該第一奈米結構和該第三奈米結構的部分,以暴露出該第二奈米結構的該第一區域的一頂部和一底部;在該第二奈米結構的該第一區域的該頂部和該底部的周圍生長一磊晶源極/汲極區(epitaxial source/drain region);在該磊晶源極/汲極區的一頂部和一底部沉積一虛置層(dummy layer),該虛置層包括一第一介電材料(first dielectric material);在該虛置層上沉積一層間介電(interlayer dielectric,ILD)層,該層間介電層包括一第二介電材料(second dielectric material),該第二介電材料不同於該第一介電材料;以及在該第二奈米結構的該第二區域的頂部和底部的周圍形成一閘極堆疊(gate stack)。
  2. 如請求項1所述的半導體裝置的製造方法,更包括:在生長該磊晶源極/汲極區之前,修整(trimming)該第二奈米結構的該第一區域,以減少該第二奈米結構的該第一區域的一厚度。
  3. 如請求項2所述的半導體裝置的製造方法,其中在修整該第 二奈米結構的該第一區域之後,該第二奈米結構的該第一區域的該厚度係小於該第二奈米結構的該第二區域的厚度。
  4. 如請求項1-3任一項所述的半導體裝置的製造方法,更包括:蝕刻該層間介電層,以形成暴露出該虛置層的一第一開口(first opening);蝕刻該虛置層,以擴大該第一開口以及暴露出磊晶源極/汲極區;在該第一開口中和該磊晶源極/汲極區的周圍沉積一金屬層(metal layer);對該金屬層進行退火,以在該磊晶源極/汲極區的周圍形成一矽化物;以及在該第一開口中沉積一導電材料,以在該矽化物的周圍形成一源極/汲極接觸件(source/drain contact)。
  5. 如請求項4所述的半導體裝置的製造方法,其中蝕刻該層間介電層係包括以比該第一介電材料一更快的速率蝕刻該第二介電材料,以及蝕刻該虛置層係包括以比該第二介電材料一更快的速率蝕刻該第一介電材料。
  6. 如請求項4所述的半導體裝置的製造方法,更包括:在沉積該層間介電層之前,在該虛置層中蝕刻一第二開口(second opening),其中沉積該層間介電層包括沉積該層間介電層的一部分於該第二開口中。
  7. 如請求項1-3任一項所述的半導體裝置的製造方法,更包括:在一基底上方形成該些半導體層;圖案化該基底以形成一鰭片,該第二奈米結構係設置在該鰭片之上;以及在生長該磊晶源極/汲極區之前,修整該鰭片的一上方部分(upper portion)。
  8. 如請求項1-3任一項所述的半導體裝置的製造方法,其中形成該閘極堆疊包括:去除該第一奈米結構和該第三奈米結構的留下部分,以暴露出該第二奈米結 構的該第二區域的該頂部和該底部;在該第二奈米結構的該第二區域的該頂部和該底部周圍沉積一閘極介電質(gate dielectric);以及在該閘極介電質上形成一閘極電極(gate electrode)。
  9. 一種半導體裝置,包括:一第一奈米結構(first nanostructure)位於一基底的上方,該第一奈米結構包括一通道區(channel region)和一第一輕摻雜源極/汲極(lightly doped source/drain,LDD)區,該第一輕摻雜源極/汲極區與該通道區相鄰,其中該第一輕摻雜源極/汲極區具有一第一厚度(first thickness),該通道區具有一第二厚度(second thickness),且該第二厚度大於該第一厚度;一第一磊晶源極/汲極區(first epitaxial source/drain region)係圍繞該第一輕摻雜源極/汲極區的四個側面;一層間介電層(ILD layer),位於該第一磊晶源極/汲極區的上方;一源極/汲極接觸件係延伸貫穿該層間介電層,該源極/汲極接觸件係圍繞該第一磊晶源極/汲極區的四個側面;以及一閘極堆疊(gate stack),鄰近該源極/汲極接觸件以及該第一磊晶源極/汲極區,該閘極堆疊係圍繞該通道區的四個側面。
  10. 如請求項9所述的半導體裝置,更包括:一第二奈米結構(second nanostructure)位於該基底的上方,該第二奈米結構包括一第二輕摻雜源極/汲極區(second LDD region);一第二磊晶源極/汲極區(second epitaxial source/drain region)圍繞該第二輕摻雜源極/汲極區的四個側面,該源極/汲極接觸件係圍繞該第二磊晶源極/汲極區的 四個側面;一第一間隔物(first spacer),設置在該閘極堆疊和該第一磊晶源極/汲極區之間,該源極/汲極接觸件係物理性接觸該第一間隔物;以及一第二間隔物(first spacer),設置在該閘極堆疊和該第二磊晶源極/汲極區之間,該源極/汲極接觸件係物理性接觸該第二間隔物。
  11. 如請求項10所述的半導體裝置,其中該源極/汲極接觸件具有一第一部分(first portion)和一第二部分(second portion),該第一部分係延伸穿過該層間介電層,該第二部分係設置在該第一磊晶源極/汲極區和該第二磊晶源極/汲極區之間,該第二部分具有比該第一部分更大的寬度。
  12. 一種半導體裝置,包括:一奈米結構(nanostructure)位於一基底的上方,該奈米結構包括一通道區(channel region)和一輕摻雜源極/汲極區(lightly doped source/drain(LDD)region),該輕摻雜源極/汲極區係與該通道區相鄰,該通道區係在一第一剖面(first cross-section)中具有一第一寬度以及一第一厚度,該輕摻雜源極/汲極區係在一第二剖面(second cross-section)中具有一第二寬度和一第二厚度,該第二寬度小於該第一寬度,該第二厚度小於該第一厚度,該第一剖面和該第二剖面均垂直於該奈米結構的一縱軸(longitudinal axis);一閘極堆疊(gate stack),該閘極堆疊在該第一剖面中係完全圍繞該通道區;以及一磊晶源極/汲極區(epitaxial source/drain region),該磊晶源極/汲極區在該第二剖面中係完全圍繞該輕摻雜源極/汲極區。
  13. 如請求項12所述的半導體裝置,更包括: 一層間介電層(interlayer dielectric(ILD)layer),位於該磊晶源極/汲極區的上方;一源極/汲極接觸件(source/drain contact),係延伸貫穿該層間介電層,該源極/汲極接觸件係完全圍繞在該第二剖面中的該磊晶源極/汲極區;以及一矽化物(silicide),位於該源極/汲極接觸件與該磊晶源極/汲極區之間,該矽化物在該第二剖面中完全包圍該磊晶源極/汲極區。
TW111100637A 2021-02-12 2022-01-07 半導體裝置及其製造方法 TWI831110B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/174,793 US11581410B2 (en) 2021-02-12 2021-02-12 Semiconductor device and method
US17/174,793 2021-02-12

Publications (2)

Publication Number Publication Date
TW202232582A TW202232582A (zh) 2022-08-16
TWI831110B true TWI831110B (zh) 2024-02-01

Family

ID=81992153

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111100637A TWI831110B (zh) 2021-02-12 2022-01-07 半導體裝置及其製造方法

Country Status (5)

Country Link
US (3) US11581410B2 (zh)
KR (1) KR102538269B1 (zh)
CN (1) CN114649268A (zh)
DE (1) DE102021103538A1 (zh)
TW (1) TWI831110B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9136343B2 (en) * 2013-01-24 2015-09-15 Intel Corporation Deep gate-all-around semiconductor device having germanium or group III-V active layer
US11581410B2 (en) * 2021-02-12 2023-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140001520A1 (en) * 2012-06-29 2014-01-02 Glenn A. Glass Contact resistance reduced p-mos transistors employing ge-rich contact layer
US20180323259A1 (en) * 2017-05-08 2018-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of fabricating the same
US20190371888A1 (en) * 2018-06-05 2019-12-05 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure and fabrication method
US20200091288A1 (en) * 2018-09-18 2020-03-19 International Business Machines Corporation Inner spacer formation and contact resistance reduction in nanosheet transistors

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9236267B2 (en) 2012-02-09 2016-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Cut-mask patterning process for fin-like field effect transistor (FinFET) device
WO2014018201A1 (en) * 2012-07-27 2014-01-30 Intel Corporation Nanowire transistor devices and forming techniques
US9006829B2 (en) 2012-08-24 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Aligned gate-all-around structure
US9209247B2 (en) 2013-05-10 2015-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned wrapped-around structure
CN106030810B (zh) * 2013-09-27 2019-07-16 英特尔公司 经由用于硅上异质集成的模板工程的改进的包覆层外延
US9136332B2 (en) 2013-12-10 2015-09-15 Taiwan Semiconductor Manufacturing Company Limited Method for forming a nanowire field effect transistor device having a replacement gate
US9136106B2 (en) 2013-12-19 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Method for integrated circuit patterning
KR102168475B1 (ko) * 2014-03-24 2020-10-21 인텔 코포레이션 나노와이어 디바이스들을 위한 내부 스페이서들을 제조하는 집적 방법들
US9608116B2 (en) 2014-06-27 2017-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. FINFETs with wrap-around silicide and method forming the same
US9412817B2 (en) 2014-12-19 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Silicide regions in vertical gate all around (VGAA) devices and methods of forming same
US9536738B2 (en) 2015-02-13 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical gate all around (VGAA) devices and methods of manufacturing the same
US9502265B1 (en) 2015-11-04 2016-11-22 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical gate all around (VGAA) transistors and methods of forming the same
US9520482B1 (en) 2015-11-13 2016-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cutting metal gate
US10290548B2 (en) 2017-08-31 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with semiconductor wire
US11101360B2 (en) * 2018-11-29 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
US11581410B2 (en) * 2021-02-12 2023-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140001520A1 (en) * 2012-06-29 2014-01-02 Glenn A. Glass Contact resistance reduced p-mos transistors employing ge-rich contact layer
US20180323259A1 (en) * 2017-05-08 2018-11-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of fabricating the same
US20190371888A1 (en) * 2018-06-05 2019-12-05 Semiconductor Manufacturing International (Shanghai) Corporation Semiconductor structure and fabrication method
US20200091288A1 (en) * 2018-09-18 2020-03-19 International Business Machines Corporation Inner spacer formation and contact resistance reduction in nanosheet transistors

Also Published As

Publication number Publication date
DE102021103538A1 (de) 2022-08-18
KR20220115841A (ko) 2022-08-19
US20220262911A1 (en) 2022-08-18
CN114649268A (zh) 2022-06-21
US20230197801A1 (en) 2023-06-22
US20240194749A1 (en) 2024-06-13
TW202232582A (zh) 2022-08-16
US11942523B2 (en) 2024-03-26
US11581410B2 (en) 2023-02-14
KR102538269B1 (ko) 2023-05-30

Similar Documents

Publication Publication Date Title
US11532519B2 (en) Semiconductor device and method
US11942523B2 (en) Semiconductor devices and methods of forming the same
US20220352371A1 (en) Semiconductor Device and Method
TW202147433A (zh) 半導體裝置及其形成方法
US20230378001A1 (en) Semiconductor device and method
US20220238649A1 (en) Transistor Gate Structures and Methods of Forming the Same
US11450743B2 (en) Method of forming a semiconductor device with implantation of impurities at high temperature
US11652155B2 (en) Air spacer and method of forming same
TWI807706B (zh) 半導體裝置及其製造方法
US11557518B2 (en) Gapfill structure and manufacturing methods thereof
KR102454025B1 (ko) 게이트 전극 퇴적 및 게이트 전극 퇴적에 의해 형성되는 구조체
US20230033289A1 (en) Gate structures in transistor devices and methods of forming same
US20230163075A1 (en) Semiconductor Device and Method
US20230155005A1 (en) Semiconductor device and method
US20220384436A1 (en) Semiconductor Device and Method of Forming Same
US20230369129A1 (en) Semiconductor Device and Method
US20220359066A1 (en) Semiconductor Device and Method
TW202230606A (zh) 半導體裝置
TW202410163A (zh) 奈米結構場效電晶體及其製造方法