JP2008263168A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2008263168A JP2008263168A JP2008018513A JP2008018513A JP2008263168A JP 2008263168 A JP2008263168 A JP 2008263168A JP 2008018513 A JP2008018513 A JP 2008018513A JP 2008018513 A JP2008018513 A JP 2008018513A JP 2008263168 A JP2008263168 A JP 2008263168A
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Abstract
【解決手段】ダミーゲートを除去することで形成された溝39、59を有して半導体基板11上に形成された側壁絶縁膜33、53と、前記溝39、59内にゲート絶縁膜41を介して形成されたゲート電極43、63と、前記側壁絶縁膜33、53上から前記半導体基板11上にかけてそれぞれに形成された第1、第2応力印加膜21、22と、前記ゲート電極43、63の両側に前記半導体基板11に形成されたソース・ドレイン領域35、36、55、56とを有し、前記応力印加膜21、22は前記第1溝39、第2溝59が形成される前に成膜されていることを特徴とする。
【選択図】図1
Description
上記ゲート絶縁膜41は、例えば2nm〜3nm程度の厚さの高誘電率(High‐k)絶縁膜である酸化ハフニウム(HfO2)膜で形成されている。本実施例ではHfO2を使っているが、HfSiO、酸化タンタル(Ta2O5)、酸化アルミニウムハフニウム(HfAlOx)などのHigh‐k材料を用いたり、もしくは単純に半導体基板11表面、すなわち、シリコン表面を酸化することでゲート絶縁膜41としても構わない。また、あらかじめ半導体基板11表面上に高誘電率(High−k)絶縁膜を形成しておいてそのまま利用しても構わない。
また、上記ゲート電極43、63は、例えば、金属化合物層もしくは金属層を用いる。ここでは、一例として窒化チタン(TiN)を用いている。また、上記金属層としてはタングステン(W)、チタン(Ti)、窒化チタン(TiN)、ハフニウム(Hf)、ハフニウムシリサイド(HfSi)、ルテニウム(Ru)、イリジウム(Ir)、コバルト(Co)などを選択することができる。本実施例では単層の膜を使っているが、抵抗を下げるためや、しきい値電圧を調整するために複数の金属膜を積層しても構わない。
また、上記第2応力印加膜22は、例えば膜厚が40nm程度の圧縮応力を有する窒化シリコン膜で形成する。本実施例では1.2GPaの圧縮応力をもつ膜を形成しているが、応力についてはこの値に限定されるものではない。また膜厚についても本実施例の膜厚に限定されるものではない。
その後、上記イオン注入マスクを除去する。
次いで、n型トランジスタの形成領域12を覆うイオン注入マスク(図示せず)を形成した後、イオン注入法によって、p型トランジスタの形成領域13の半導体基板11中にn型不純物を導入して、n型ウェル領域16を形成する。
その後、上記イオン注入マスクを除去する。さらに、上記保護膜80を除去する。
なお、上記p型ウェル領域15、n型ウェル領域16は、どちらを先に形成してもよい。
上記ダミーゲート絶縁膜81は、例えば1nm〜3nm程度の酸化膜で形成する。その形成方法は、例えば熱酸化プロセスを用いる。
上記ダミーゲート形成膜82は、例えば100nm〜150nm程度の厚さのポリシリコン膜で形成する。その形成方法は、例えばCVD法などを用いる。本実施例ではダミーゲート絶縁膜を後の工程で除去するが、この時点で、例えばゲート絶縁膜を形成する場合もある。例えばゲート絶縁膜には、酸化ハフニウム(HfO2)等の高誘電率(High‐k)絶縁膜を用いることができる。また、上記ダミーゲート形成膜82には、アモルファスシリコン膜を用いることもできる。
上記ハードマスク層83は、例えば、30nm〜100nm程度の厚さの窒化シリコン膜を用いる。その成膜方法は、例えばCVD法による。
なお、上記ドライエッチングではハードマスク層83をほとんどエッチングしないような選択比で行われることがこの好ましい。
また、p型トランジスタの形成領域13において、上記ダミーゲート85の両側のp型トランジスタの形成領域13の半導体基板11にエクステンション領域51、52を形成する。
次いで、n型トランジスタの形成領域12を覆うイオン注入マスク(図示せず)を形成した後、イオン注入法によって、ダミーゲート85の両側におけるp型トランジスタの形成領域13の半導体基板11中にp型不純物を導入して、上記エクステンション領域51、52を形成する。このイオン注入では、n型不純物に例えばホウ素(B)、インジウム(In)等を用いる。また、上記p型不純物のイオン注入マスクには例えばレジスト膜を用いる。
その後、上記イオン注入マスクを除去する。
また、上記各エクステンション領域31、32、51、52の不純物注入をする前に、ダミーゲート84、85の各側壁を窒化シリコン膜や酸化シリコン膜などの側壁保護膜で保護しておいても良い。
同様に、上記ダミーゲート85の両側における半導体基板11に上記エクステンション領域51、52をそれぞれに介してソース・ドレイン領域55、56を形成する。
上記ソース・ドレイン領域35、36の形成には、p型トランジスタの形成領域上にイオン注入マスク(図示せず)を形成した後、例えばn型不純物を上記半導体基板11にイオン注入して形成する。
次いで、上記イオン注入マスクを除去する。
次いで、上記イオン注入マスクを除去する。
その後、活性化アニールを行って、上記エクステンション領域31、32、51、52およびソース・ドレイン領域35、36、55、56に注入された不純物を活性化する。この活性化アニールは、例えば1000℃〜1100℃程度の急速熱処理(RTA)による。
なお、第2応力印加膜22は、水素(H2)ガス(1000cm3/min〜5000cm3/min)、窒素(N2)ガス(500cm3/min〜2500cm3/min)、アルゴン(Ar)ガス(1000cm3/min〜5000cm3/min)、アンモニア(NH3)ガス(50cm3/min〜200cm3/min)、トリメチルシランガス(10cm3/min〜50cm3/min)を供給し、基板温度が400℃〜600℃、圧力が0.13kPa〜0.67kPa、RFパワーが50W〜500Wの条件で化学反応させて形成される。
本実施例では、1.2GPaの圧縮応力をもつ膜を形成しているが、応力についてはこの値に限定されるものではない。また膜厚についても本実施例の膜厚に限定されるものではない。
その後、光リソグラフィー技術およびドライエッチング技術を用いて、p型トランジスタの形成領域13上のみに上記第2応力印加膜22を残すよう加工する。
なお、第1応力印加膜21は、窒素(N2)ガス(500cm3/min〜2000cm3/min)、アンモニア(NH3)ガス(500cm3/min〜1500cm3/min)、モノシラン(SiH4)ガス(50cm3/min〜300cm3/min)を供給し、基板温度が200℃〜400℃、圧力が0.67kPa〜2.0kPa、RFパワーが50W〜500Wの条件で化学反応させる。さらに成膜後、ヘリウム(He)ガス(10L/min〜20L/min)を供給し、温度400℃〜600℃、圧力0.67kPa〜2.0kPa、紫外線(UV)ランプパワーが1kW〜10kWの条件で紫外線(UV)照射処理を行い形成する。
本実施例では1.2GPaの引張応力をもつ膜を形成しているが、応力についてはこの値に限定されるものではない。また膜厚についても本実施例の膜厚に限定されるものではない。
その後、光リソグラフィー技術およびドライエッチング技術を用いて、n型トランジスタの形成領域12上のみに上記第1応力印加膜21を残すよう加工する。なお、上記第1、第2応力印加膜21、22の形成順序はどちらが先に形成されてもよい。
上記ゲート絶縁膜41は、例えば2nm〜3nm程度の厚さの高誘電率(High‐k)絶縁膜である酸化ハフニウム(HfO2)膜で形成されている。本実施例ではHfO2を使っているが、HfSiO、酸化タンタル(Ta2O5)、酸化アルミニウムハフニウム(HfAlOx)などのHigh‐k材料を用いることもでき、また単純に半導体基板11表面、すなわち、シリコン表面を酸化することや、予め半導体基板11表面に形成しておいた高誘電率膜をゲート絶縁膜41としても構わない。
また、上記ゲート電極43、63は、例えば、金属化合物層もしくは金属層を用いる。ここでは、一例として窒化チタン(TiN)を用いている。また、上記金属層としてはタングステン(W)、チタン(Ti)、窒化チタン(TiN)、ハフニウム(Hf)、ハフニウムシリサイド(HfSi)、ルテニウム(Ru)、イリジウム(Ir)、コバルト(Co)などを選択することができる。本実施例では単層の膜を使っているが、抵抗を下げるためや、しきい値電圧を調整するために複数の金属膜を積層しても構わない。
また、上記第4応力印加膜24は、例えば膜厚が40nm程度の圧縮応力を有する窒化シリコン膜で形成する。本実施例では1.2GPaの圧縮応力をもつ膜を形成しているが、応力についてはこの値に限定されるものではない。また膜厚についても本実施例の膜厚に限定されるものではない。
Claims (23)
- ダミーゲートを除去することで形成された溝を有して半導体基板上に形成された側壁絶縁膜と、
前記溝内の半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記側壁絶縁膜上から前記半導体基板上にかけて形成された応力印加膜と、
前記ゲート電極の両側に前記半導体基板に形成されたソース・ドレイン領域とを有し、
前記応力印加膜は前記溝が形成される前に成膜されている
ことを特徴とする半導体装置。 - 前記応力印加膜は、前記半導体装置がn型トランジスタでは引張応力を有するものであり、前記半導体装置がp型トランジスタでは圧縮応力を有するものである
ことを特徴とする請求項1記載の半導体装置。 - 前記ゲート電極上を含む前記応力印加膜上に第2応力印加膜を有する
ことを特徴とする請求項1記載の半導体装置。 - 前記応力印加膜は窒化シリコンで形成されている
ことを特徴とする請求項1記載の半導体装置。 - 前記半導体基板のn型トランジスタの形成領域に、
第1ダミーゲートを除去することで形成された第1溝を有して前記半導体基板上に形成された側壁絶縁膜と、
前記第1溝内の半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記側壁絶縁膜上から前記半導体基板上にかけて形成された引張応力を有する第1応力印加膜と、
前記ゲート電極の両側の前記半導体基板に形成されたソース・ドレイン領域とを有するn型トランジスタを有し、
半導体基板のp型トランジスタの形成領域に、
第2ダミーゲートを除去することで形成された第2溝を有して前記半導体基板上に形成された側壁絶縁膜と、
前記第2溝内の半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記側壁絶縁膜上から前記半導体基板上にかけて形成された圧縮応力を有する第2応力印加膜と、
前記ゲート電極の両側の前記半導体基板に形成されたソース・ドレイン領域とを有するp型トランジスタを備え、
前記第1応力印加膜は前記第1溝が形成される前に成膜されていて、
前記第2応力印加膜は前記第2溝が形成される前に成膜されている
ことを特徴とする半導体装置。 - 前記半導体基板のn型トランジスタの形成領域に、
前記ゲート電極上を含む前記応力印加膜上に第3応力印加膜を有し、
前記半導体基板のp型トランジスタの形成領域に、
前記ゲート電極上を含む前記応力印加膜上に第4応力印加膜を有する
ことを特徴とする請求項5記載の半導体装置。 - 前記第3応力印加膜は引張応力を有するものであり、前記第4応力印加膜は圧縮応力を有するものである
ことを特徴とする請求項6記載の半導体装置。 - 前記第3応力印加膜および前記第4応力印加膜は共通である
ことを特徴とする請求項6記載の半導体装置。 - 前記第1応力印加膜は窒化シリコンで形成されていて、
前記第2応力印加膜は窒化シリコンで形成されている
ことを特徴とする請求項5記載の半導体装置。 - 前記第3応力印加膜は窒化シリコンで形成されていて、
前記第4応力印加膜は窒化シリコンで形成されている
ことを特徴とする請求項6記載の半導体装置。 - 前記p型トランジスタのソース・ドレイン領域に応力印加源を有する
ことを特徴とする請求項5もしくは6記載の半導体装置。 - 前記n型トランジスタのソース・ドレイン領域に第1応力印加源を有し、
前記p型トランジスタのソース・ドレイン領域に第2応力印加源を有する
ことを特徴とする請求項5記載の半導体装置。 - 前記第1応力印加源は引張応力を有するものであり、
前記第2応力印加源は圧縮応力を有するものである
ことを特徴とする請求項12記載の半導体装置。 - 前記半導体基板に、第1導電型の第1トランジスタと第1導電型とは逆の第2導電型の第2トランジスタとが形成され、
前記第1トランジスタは、
ダミーゲートを除去することで形成された溝を有して前記半導体基板上に形成された側壁絶縁膜と、
前記溝内の半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、
前記側壁絶縁膜上から前記半導体基板上にかけて形成された応力印加膜と、
前記ゲート電極の両側に前記半導体基板に形成されたソース・ドレイン領域とを有し、
前記応力印加膜は前記溝が形成される前に成膜されていて、
前記第2トランジスタは、そのソース・ドレイン領域に応力印加源を有する
ことを特徴とする請求項1記載の半導体装置。 - 前記応力印加源は、前記第2トランジスタが、n型トランジスタでは引張応力を有するものであり、p型トランジスタでは圧縮応力を有するものである
ことを特徴とする請求項14記載の半導体装置。 - 前記第1トランジスタ上および前記第2トランジスタ上に共通の第2応力印加膜を有する
ことを特徴とする請求項14記載の半導体装置。 - 半導体基板上にダミーゲートを形成した後、該ダミーゲートの側壁に側壁絶縁膜を形成し、該ダミーゲートの両側の前記半導体基板にソース・ドレイン領域を形成する工程と、
前記側壁絶縁膜上から前記半導体基板上にかけて応力印加膜を形成する工程と、
前記ダミーゲートを除去して溝を形成する工程と、
前記溝内の半導体基板上にゲート絶縁膜を介してゲート電極を形成する工程と
を備えたことを特徴とする半導体装置の製造方法。 - 前記ダミーゲートを、前記半導体基板上にダミーゲート絶縁膜とダミーゲート形成膜を順に積層して形成した後、該ダミーゲート形成膜をパターニングして形成し、
前記ダミーゲートを除去するときに前記ダミーゲートの下部に形成されている前記ダミーゲート絶縁膜を除去する
ことを特徴とする請求項17記載の半導体装置の製造方法。 - 半導体基板上のn型トランジスタの形成領域とp型トランジスタの形成領域とにダミーゲートを形成した後、各ダミーゲートの側壁に側壁絶縁膜を形成し、各ダミーゲートの両側の前記半導体基板にソース・ドレイン領域をそれぞれに形成する工程と、
前記n型トランジスタの形成領域の前記側壁絶縁膜上から前記半導体基板上にかけて第1応力印加膜を形成する工程と、
前記p型トランジスタの形成領域の前記側壁絶縁膜上から前記半導体基板上にかけて第2応力印加膜を形成する工程と、
前記各ダミーゲートを除去して溝を形成する工程と、
前記各溝内の半導体基板上にゲート絶縁膜を介してゲート電極を形成する工程と
を備えたことを特徴とする半導体装置の製造方法。 - 前記ダミーゲートを、前記半導体基板上にダミーゲート絶縁膜とダミーゲート形成膜を順に積層して形成した後、該ダミーゲート形成膜をパターニングして形成し、
前記ダミーゲートを除去するときに前記ダミーゲートの下部に形成されている前記ダミーゲート絶縁膜を除去する
ことを特徴とする請求項19記載の半導体装置の製造方法。 - 前記ゲート電極を形成した後、前記n型トランジスタ上、もしくはn型トランジスタおよびp型トランジスタ上に第3応力印加膜を形成する
ことを特徴とする請求項19記載の半導体装置の製造方法。 - 前記p型トランジスタのソース・ドレイン領域を応力印加源で形成する
ことを特徴とする請求項19記載の半導体装置の製造方法。 - 前記応力印加源を、
前記半導体基板のソース・ドレイン領域を形成する領域に溝を形成した後、
前記溝にシリコンゲルマニウム層をエピタキシャル成長させて形成する
ことを特徴とする請求項22記載の半導体装置の製造方法。
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US10269801B2 (en) | 2019-04-23 |
KR20100014343A (ko) | 2010-02-10 |
US20200144262A1 (en) | 2020-05-07 |
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TW200847300A (en) | 2008-12-01 |
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CN101641780B (zh) | 2011-12-21 |
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TW201230209A (en) | 2012-07-16 |
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CN102136429A (zh) | 2011-07-27 |
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TWI392029B (zh) | 2013-04-01 |
US11011518B2 (en) | 2021-05-18 |
US20230246032A1 (en) | 2023-08-03 |
US11664376B2 (en) | 2023-05-30 |
US20190157271A1 (en) | 2019-05-23 |
JP5003515B2 (ja) | 2012-08-15 |
US20100102394A1 (en) | 2010-04-29 |
US20210265347A1 (en) | 2021-08-26 |
US9070783B2 (en) | 2015-06-30 |
TWI416635B (zh) | 2013-11-21 |
CN101641780A (zh) | 2010-02-03 |
CN102136429B (zh) | 2013-10-30 |
US9881920B2 (en) | 2018-01-30 |
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US9449974B2 (en) | 2016-09-20 |
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